Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the Thumb2 ISA. */ |
| 18 | |
| 19 | #include "arm_lir.h" |
| 20 | #include "codegen_arm.h" |
| 21 | #include "dex/quick/mir_to_lir-inl.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 22 | #include "entrypoints/quick/quick_entrypoints.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 23 | |
| 24 | namespace art { |
| 25 | |
| 26 | |
| 27 | /* Return the position of an ssa name within the argument list */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 28 | int ArmMir2Lir::InPosition(int s_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 30 | return v_reg - cu_->num_regs; |
| 31 | } |
| 32 | |
| 33 | /* |
| 34 | * Describe an argument. If it's already in an arg register, just leave it |
| 35 | * there. NOTE: all live arg registers must be locked prior to this call |
| 36 | * to avoid having them allocated as a temp by downstream utilities. |
| 37 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 38 | RegLocation ArmMir2Lir::ArgLoc(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 39 | int arg_num = InPosition(loc.s_reg_low); |
| 40 | if (loc.wide) { |
| 41 | if (arg_num == 2) { |
| 42 | // Bad case - half in register, half in frame. Just punt |
| 43 | loc.location = kLocInvalid; |
| 44 | } else if (arg_num < 2) { |
| 45 | loc.low_reg = rARM_ARG1 + arg_num; |
| 46 | loc.high_reg = loc.low_reg + 1; |
| 47 | loc.location = kLocPhysReg; |
| 48 | } else { |
| 49 | loc.location = kLocDalvikFrame; |
| 50 | } |
| 51 | } else { |
| 52 | if (arg_num < 3) { |
| 53 | loc.low_reg = rARM_ARG1 + arg_num; |
| 54 | loc.location = kLocPhysReg; |
| 55 | } else { |
| 56 | loc.location = kLocDalvikFrame; |
| 57 | } |
| 58 | } |
| 59 | return loc; |
| 60 | } |
| 61 | |
| 62 | /* |
| 63 | * Load an argument. If already in a register, just return. If in |
| 64 | * the frame, we can't use the normal LoadValue() because it assumed |
| 65 | * a proper frame - and we're frameless. |
| 66 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 67 | RegLocation ArmMir2Lir::LoadArg(RegLocation loc) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 68 | if (loc.location == kLocDalvikFrame) { |
| 69 | int start = (InPosition(loc.s_reg_low) + 1) * sizeof(uint32_t); |
| 70 | loc.low_reg = AllocTemp(); |
| 71 | LoadWordDisp(rARM_SP, start, loc.low_reg); |
| 72 | if (loc.wide) { |
| 73 | loc.high_reg = AllocTemp(); |
| 74 | LoadWordDisp(rARM_SP, start + sizeof(uint32_t), loc.high_reg); |
| 75 | } |
| 76 | loc.location = kLocPhysReg; |
| 77 | } |
| 78 | return loc; |
| 79 | } |
| 80 | |
| 81 | /* Lock any referenced arguments that arrive in registers */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 82 | void ArmMir2Lir::LockLiveArgs(MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 83 | int first_in = cu_->num_regs; |
| 84 | const int num_arg_regs = 3; // TODO: generalize & move to RegUtil.cc |
| 85 | for (int i = 0; i < mir->ssa_rep->num_uses; i++) { |
| 86 | int v_reg = mir_graph_->SRegToVReg(mir->ssa_rep->uses[i]); |
| 87 | int InPosition = v_reg - first_in; |
| 88 | if (InPosition < num_arg_regs) { |
| 89 | LockTemp(rARM_ARG1 + InPosition); |
| 90 | } |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | /* Find the next MIR, which may be in a following basic block */ |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 95 | // TODO: make this a utility in mir_graph. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 96 | MIR* ArmMir2Lir::GetNextMir(BasicBlock** p_bb, MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 97 | BasicBlock* bb = *p_bb; |
| 98 | MIR* orig_mir = mir; |
| 99 | while (bb != NULL) { |
| 100 | if (mir != NULL) { |
| 101 | mir = mir->next; |
| 102 | } |
| 103 | if (mir != NULL) { |
| 104 | return mir; |
| 105 | } else { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 106 | bb = mir_graph_->GetBasicBlock(bb->fall_through); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | *p_bb = bb; |
| 108 | if (bb) { |
| 109 | mir = bb->first_mir_insn; |
| 110 | if (mir != NULL) { |
| 111 | return mir; |
| 112 | } |
| 113 | } |
| 114 | } |
| 115 | } |
| 116 | return orig_mir; |
| 117 | } |
| 118 | |
| 119 | /* Used for the "verbose" listing */ |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 120 | // TODO: move to common code |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 121 | void ArmMir2Lir::GenPrintLabel(MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 122 | /* Mark the beginning of a Dalvik instruction for line tracking */ |
buzbee | 252254b | 2013-09-08 16:20:53 -0700 | [diff] [blame] | 123 | if (cu_->verbose) { |
| 124 | char* inst_str = mir_graph_->GetDalvikDisassembly(mir); |
| 125 | MarkBoundary(mir->offset, inst_str); |
| 126 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | MIR* ArmMir2Lir::SpecialIGet(BasicBlock** bb, MIR* mir, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 130 | OpSize size, bool long_or_double, bool is_object) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 131 | int32_t field_offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 132 | bool is_volatile; |
| 133 | uint32_t field_idx = mir->dalvikInsn.vC; |
Ian Rogers | 9b297bf | 2013-09-06 11:11:25 -0700 | [diff] [blame] | 134 | bool fast_path = FastInstance(field_idx, false, &field_offset, &is_volatile); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 135 | if (!fast_path || !(mir->optimization_flags & MIR_IGNORE_NULL_CHECK)) { |
| 136 | return NULL; |
| 137 | } |
| 138 | RegLocation rl_obj = mir_graph_->GetSrc(mir, 0); |
| 139 | LockLiveArgs(mir); |
| 140 | rl_obj = ArmMir2Lir::ArgLoc(rl_obj); |
| 141 | RegLocation rl_dest; |
| 142 | if (long_or_double) { |
| 143 | rl_dest = GetReturnWide(false); |
| 144 | } else { |
| 145 | rl_dest = GetReturn(false); |
| 146 | } |
| 147 | // Point of no return - no aborts after this |
| 148 | ArmMir2Lir::GenPrintLabel(mir); |
| 149 | rl_obj = LoadArg(rl_obj); |
| 150 | GenIGet(field_idx, mir->optimization_flags, size, rl_dest, rl_obj, long_or_double, is_object); |
| 151 | return GetNextMir(bb, mir); |
| 152 | } |
| 153 | |
| 154 | MIR* ArmMir2Lir::SpecialIPut(BasicBlock** bb, MIR* mir, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 155 | OpSize size, bool long_or_double, bool is_object) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 156 | int32_t field_offset; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 157 | bool is_volatile; |
| 158 | uint32_t field_idx = mir->dalvikInsn.vC; |
Ian Rogers | 9b297bf | 2013-09-06 11:11:25 -0700 | [diff] [blame] | 159 | bool fast_path = FastInstance(field_idx, false, &field_offset, &is_volatile); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 160 | if (!fast_path || !(mir->optimization_flags & MIR_IGNORE_NULL_CHECK)) { |
| 161 | return NULL; |
| 162 | } |
| 163 | RegLocation rl_src; |
| 164 | RegLocation rl_obj; |
| 165 | LockLiveArgs(mir); |
| 166 | if (long_or_double) { |
| 167 | rl_src = mir_graph_->GetSrcWide(mir, 0); |
| 168 | rl_obj = mir_graph_->GetSrc(mir, 2); |
| 169 | } else { |
| 170 | rl_src = mir_graph_->GetSrc(mir, 0); |
| 171 | rl_obj = mir_graph_->GetSrc(mir, 1); |
| 172 | } |
| 173 | rl_src = ArmMir2Lir::ArgLoc(rl_src); |
| 174 | rl_obj = ArmMir2Lir::ArgLoc(rl_obj); |
| 175 | // Reject if source is split across registers & frame |
| 176 | if (rl_obj.location == kLocInvalid) { |
| 177 | ResetRegPool(); |
| 178 | return NULL; |
| 179 | } |
| 180 | // Point of no return - no aborts after this |
| 181 | ArmMir2Lir::GenPrintLabel(mir); |
| 182 | rl_obj = LoadArg(rl_obj); |
| 183 | rl_src = LoadArg(rl_src); |
| 184 | GenIPut(field_idx, mir->optimization_flags, size, rl_src, rl_obj, long_or_double, is_object); |
| 185 | return GetNextMir(bb, mir); |
| 186 | } |
| 187 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 188 | MIR* ArmMir2Lir::SpecialIdentity(MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 189 | RegLocation rl_src; |
| 190 | RegLocation rl_dest; |
| 191 | bool wide = (mir->ssa_rep->num_uses == 2); |
| 192 | if (wide) { |
| 193 | rl_src = mir_graph_->GetSrcWide(mir, 0); |
| 194 | rl_dest = GetReturnWide(false); |
| 195 | } else { |
| 196 | rl_src = mir_graph_->GetSrc(mir, 0); |
| 197 | rl_dest = GetReturn(false); |
| 198 | } |
| 199 | LockLiveArgs(mir); |
| 200 | rl_src = ArmMir2Lir::ArgLoc(rl_src); |
| 201 | if (rl_src.location == kLocInvalid) { |
| 202 | ResetRegPool(); |
| 203 | return NULL; |
| 204 | } |
| 205 | // Point of no return - no aborts after this |
| 206 | ArmMir2Lir::GenPrintLabel(mir); |
| 207 | rl_src = LoadArg(rl_src); |
| 208 | if (wide) { |
| 209 | StoreValueWide(rl_dest, rl_src); |
| 210 | } else { |
| 211 | StoreValue(rl_dest, rl_src); |
| 212 | } |
| 213 | return mir; |
| 214 | } |
| 215 | |
| 216 | /* |
| 217 | * Special-case code genration for simple non-throwing leaf methods. |
| 218 | */ |
| 219 | void ArmMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 220 | SpecialCaseHandler special_case) { |
Brian Carlstrom | 6f485c6 | 2013-07-18 15:35:35 -0700 | [diff] [blame] | 221 | current_dalvik_offset_ = mir->offset; |
| 222 | MIR* next_mir = NULL; |
| 223 | switch (special_case) { |
| 224 | case kNullMethod: |
| 225 | DCHECK(mir->dalvikInsn.opcode == Instruction::RETURN_VOID); |
| 226 | next_mir = mir; |
| 227 | break; |
| 228 | case kConstFunction: |
| 229 | ArmMir2Lir::GenPrintLabel(mir); |
| 230 | LoadConstant(rARM_RET0, mir->dalvikInsn.vB); |
| 231 | next_mir = GetNextMir(&bb, mir); |
| 232 | break; |
| 233 | case kIGet: |
| 234 | next_mir = SpecialIGet(&bb, mir, kWord, false, false); |
| 235 | break; |
| 236 | case kIGetBoolean: |
| 237 | case kIGetByte: |
| 238 | next_mir = SpecialIGet(&bb, mir, kUnsignedByte, false, false); |
| 239 | break; |
| 240 | case kIGetObject: |
| 241 | next_mir = SpecialIGet(&bb, mir, kWord, false, true); |
| 242 | break; |
| 243 | case kIGetChar: |
| 244 | next_mir = SpecialIGet(&bb, mir, kUnsignedHalf, false, false); |
| 245 | break; |
| 246 | case kIGetShort: |
| 247 | next_mir = SpecialIGet(&bb, mir, kSignedHalf, false, false); |
| 248 | break; |
| 249 | case kIGetWide: |
| 250 | next_mir = SpecialIGet(&bb, mir, kLong, true, false); |
| 251 | break; |
| 252 | case kIPut: |
| 253 | next_mir = SpecialIPut(&bb, mir, kWord, false, false); |
| 254 | break; |
| 255 | case kIPutBoolean: |
| 256 | case kIPutByte: |
| 257 | next_mir = SpecialIPut(&bb, mir, kUnsignedByte, false, false); |
| 258 | break; |
| 259 | case kIPutObject: |
| 260 | next_mir = SpecialIPut(&bb, mir, kWord, false, true); |
| 261 | break; |
| 262 | case kIPutChar: |
| 263 | next_mir = SpecialIPut(&bb, mir, kUnsignedHalf, false, false); |
| 264 | break; |
| 265 | case kIPutShort: |
| 266 | next_mir = SpecialIPut(&bb, mir, kSignedHalf, false, false); |
| 267 | break; |
| 268 | case kIPutWide: |
| 269 | next_mir = SpecialIPut(&bb, mir, kLong, true, false); |
| 270 | break; |
| 271 | case kIdentity: |
| 272 | next_mir = SpecialIdentity(mir); |
| 273 | break; |
| 274 | default: |
| 275 | return; |
| 276 | } |
| 277 | if (next_mir != NULL) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 278 | current_dalvik_offset_ = next_mir->offset; |
| 279 | if (special_case != kIdentity) { |
| 280 | ArmMir2Lir::GenPrintLabel(next_mir); |
| 281 | } |
| 282 | NewLIR1(kThumbBx, rARM_LR); |
| 283 | core_spill_mask_ = 0; |
| 284 | num_core_spills_ = 0; |
| 285 | fp_spill_mask_ = 0; |
| 286 | num_fp_spills_ = 0; |
| 287 | frame_size_ = 0; |
| 288 | core_vmap_table_.clear(); |
| 289 | fp_vmap_table_.clear(); |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | /* |
| 294 | * The sparse table in the literal pool is an array of <key,displacement> |
| 295 | * pairs. For each set, we'll load them as a pair using ldmia. |
| 296 | * This means that the register number of the temp we use for the key |
| 297 | * must be lower than the reg for the displacement. |
| 298 | * |
| 299 | * The test loop will look something like: |
| 300 | * |
| 301 | * adr rBase, <table> |
| 302 | * ldr r_val, [rARM_SP, v_reg_off] |
| 303 | * mov r_idx, #table_size |
| 304 | * lp: |
| 305 | * ldmia rBase!, {r_key, r_disp} |
| 306 | * sub r_idx, #1 |
| 307 | * cmp r_val, r_key |
| 308 | * ifeq |
| 309 | * add rARM_PC, r_disp ; This is the branch from which we compute displacement |
| 310 | * cbnz r_idx, lp |
| 311 | */ |
| 312 | void ArmMir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 313 | RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 314 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 315 | if (cu_->verbose) { |
| 316 | DumpSparseSwitchTable(table); |
| 317 | } |
| 318 | // Add the table to the list - we'll process it later |
| 319 | SwitchTable *tab_rec = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 320 | static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 321 | tab_rec->table = table; |
| 322 | tab_rec->vaddr = current_dalvik_offset_; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 323 | uint32_t size = table[1]; |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 324 | tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 325 | ArenaAllocator::kAllocLIR)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 326 | switch_tables_.Insert(tab_rec); |
| 327 | |
| 328 | // Get the switch value |
| 329 | rl_src = LoadValue(rl_src, kCoreReg); |
| 330 | int rBase = AllocTemp(); |
| 331 | /* Allocate key and disp temps */ |
| 332 | int r_key = AllocTemp(); |
| 333 | int r_disp = AllocTemp(); |
| 334 | // Make sure r_key's register number is less than r_disp's number for ldmia |
| 335 | if (r_key > r_disp) { |
| 336 | int tmp = r_disp; |
| 337 | r_disp = r_key; |
| 338 | r_key = tmp; |
| 339 | } |
| 340 | // Materialize a pointer to the switch table |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 341 | NewLIR3(kThumb2Adr, rBase, 0, WrapPointer(tab_rec)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 342 | // Set up r_idx |
| 343 | int r_idx = AllocTemp(); |
| 344 | LoadConstant(r_idx, size); |
| 345 | // Establish loop branch target |
| 346 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 347 | // Load next key/disp |
| 348 | NewLIR2(kThumb2LdmiaWB, rBase, (1 << r_key) | (1 << r_disp)); |
| 349 | OpRegReg(kOpCmp, r_key, rl_src.low_reg); |
| 350 | // Go if match. NOTE: No instruction set switch here - must stay Thumb2 |
| 351 | OpIT(kCondEq, ""); |
| 352 | LIR* switch_branch = NewLIR1(kThumb2AddPCR, r_disp); |
| 353 | tab_rec->anchor = switch_branch; |
| 354 | // Needs to use setflags encoding here |
| 355 | NewLIR3(kThumb2SubsRRI12, r_idx, r_idx, 1); |
| 356 | OpCondBranch(kCondNe, target); |
| 357 | } |
| 358 | |
| 359 | |
| 360 | void ArmMir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 361 | RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 362 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 363 | if (cu_->verbose) { |
| 364 | DumpPackedSwitchTable(table); |
| 365 | } |
| 366 | // Add the table to the list - we'll process it later |
| 367 | SwitchTable *tab_rec = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 368 | static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 369 | tab_rec->table = table; |
| 370 | tab_rec->vaddr = current_dalvik_offset_; |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 371 | uint32_t size = table[1]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 372 | tab_rec->targets = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 373 | static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), ArenaAllocator::kAllocLIR)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 374 | switch_tables_.Insert(tab_rec); |
| 375 | |
| 376 | // Get the switch value |
| 377 | rl_src = LoadValue(rl_src, kCoreReg); |
| 378 | int table_base = AllocTemp(); |
| 379 | // Materialize a pointer to the switch table |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 380 | NewLIR3(kThumb2Adr, table_base, 0, WrapPointer(tab_rec)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 381 | int low_key = s4FromSwitchData(&table[2]); |
| 382 | int keyReg; |
| 383 | // Remove the bias, if necessary |
| 384 | if (low_key == 0) { |
| 385 | keyReg = rl_src.low_reg; |
| 386 | } else { |
| 387 | keyReg = AllocTemp(); |
| 388 | OpRegRegImm(kOpSub, keyReg, rl_src.low_reg, low_key); |
| 389 | } |
| 390 | // Bounds check - if < 0 or >= size continue following switch |
| 391 | OpRegImm(kOpCmp, keyReg, size-1); |
| 392 | LIR* branch_over = OpCondBranch(kCondHi, NULL); |
| 393 | |
| 394 | // Load the displacement from the switch table |
| 395 | int disp_reg = AllocTemp(); |
| 396 | LoadBaseIndexed(table_base, keyReg, disp_reg, 2, kWord); |
| 397 | |
| 398 | // ..and go! NOTE: No instruction set switch here - must stay Thumb2 |
| 399 | LIR* switch_branch = NewLIR1(kThumb2AddPCR, disp_reg); |
| 400 | tab_rec->anchor = switch_branch; |
| 401 | |
| 402 | /* branch_over target here */ |
| 403 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 404 | branch_over->target = target; |
| 405 | } |
| 406 | |
| 407 | /* |
| 408 | * Array data table format: |
| 409 | * ushort ident = 0x0300 magic value |
| 410 | * ushort width width of each element in the table |
| 411 | * uint size number of elements in the table |
| 412 | * ubyte data[size*width] table of data values (may contain a single-byte |
| 413 | * padding at the end) |
| 414 | * |
| 415 | * Total size is 4+(width * size + 1)/2 16-bit code units. |
| 416 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 417 | void ArmMir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 418 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 419 | // Add the table to the list - we'll process it later |
| 420 | FillArrayData *tab_rec = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 421 | static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), ArenaAllocator::kAllocData)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 422 | tab_rec->table = table; |
| 423 | tab_rec->vaddr = current_dalvik_offset_; |
| 424 | uint16_t width = tab_rec->table[1]; |
| 425 | uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); |
| 426 | tab_rec->size = (size * width) + 8; |
| 427 | |
| 428 | fill_array_data_.Insert(tab_rec); |
| 429 | |
| 430 | // Making a call - use explicit registers |
| 431 | FlushAllRegs(); /* Everything to home location */ |
| 432 | LoadValueDirectFixed(rl_src, r0); |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 433 | LoadWordDisp(rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData).Int32Value(), |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 434 | rARM_LR); |
| 435 | // Materialize a pointer to the fill data image |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame^] | 436 | NewLIR3(kThumb2Adr, r1, 0, WrapPointer(tab_rec)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 437 | ClobberCalleeSave(); |
| 438 | LIR* call_inst = OpReg(kOpBlx, rARM_LR); |
| 439 | MarkSafepointPC(call_inst); |
| 440 | } |
| 441 | |
| 442 | /* |
Ian Rogers | d9c4fc9 | 2013-10-01 19:45:43 -0700 | [diff] [blame] | 443 | * Handle unlocked -> thin locked transition inline or else call out to quick entrypoint. For more |
| 444 | * details see monitor.cc. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 445 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 446 | void ArmMir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 447 | FlushAllRegs(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 448 | LoadValueDirectFixed(rl_src, r0); // Get obj |
| 449 | LockCallTemps(); // Prepare for explicit register usage |
Ian Rogers | d9c4fc9 | 2013-10-01 19:45:43 -0700 | [diff] [blame] | 450 | constexpr bool kArchVariantHasGoodBranchPredictor = false; // TODO: true if cortex-A15. |
| 451 | if (kArchVariantHasGoodBranchPredictor) { |
| 452 | LIR* null_check_branch; |
| 453 | if ((opt_flags & MIR_IGNORE_NULL_CHECK) && !(cu_->disable_opt & (1 << kNullCheckElimination))) { |
| 454 | null_check_branch = nullptr; // No null check. |
| 455 | } else { |
| 456 | // If the null-check fails its handled by the slow-path to reduce exception related meta-data. |
| 457 | null_check_branch = OpCmpImmBranch(kCondEq, r0, 0, NULL); |
| 458 | } |
| 459 | LoadWordDisp(rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2); |
| 460 | NewLIR3(kThumb2Ldrex, r1, r0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 461 | LIR* not_unlocked_branch = OpCmpImmBranch(kCondNe, r1, 0, NULL); |
| 462 | NewLIR4(kThumb2Strex, r1, r2, r0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 463 | LIR* lock_success_branch = OpCmpImmBranch(kCondEq, r1, 0, NULL); |
| 464 | |
| 465 | |
| 466 | LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); |
| 467 | not_unlocked_branch->target = slow_path_target; |
| 468 | if (null_check_branch != nullptr) { |
| 469 | null_check_branch->target = slow_path_target; |
| 470 | } |
| 471 | // TODO: move to a slow path. |
| 472 | // Go expensive route - artLockObjectFromCode(obj); |
| 473 | LoadWordDisp(rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pLockObject).Int32Value(), rARM_LR); |
| 474 | ClobberCalleeSave(); |
| 475 | LIR* call_inst = OpReg(kOpBlx, rARM_LR); |
| 476 | MarkSafepointPC(call_inst); |
| 477 | |
| 478 | LIR* success_target = NewLIR0(kPseudoTargetLabel); |
| 479 | lock_success_branch->target = success_target; |
| 480 | GenMemBarrier(kLoadLoad); |
| 481 | } else { |
| 482 | // Explicit null-check as slow-path is entered using an IT. |
| 483 | GenNullCheck(rl_src.s_reg_low, r0, opt_flags); |
| 484 | LoadWordDisp(rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2); |
| 485 | NewLIR3(kThumb2Ldrex, r1, r0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 486 | OpRegImm(kOpCmp, r1, 0); |
| 487 | OpIT(kCondEq, ""); |
| 488 | NewLIR4(kThumb2Strex/*eq*/, r1, r2, r0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 489 | OpRegImm(kOpCmp, r1, 0); |
| 490 | OpIT(kCondNe, "T"); |
| 491 | // Go expensive route - artLockObjectFromCode(self, obj); |
| 492 | LoadWordDisp/*ne*/(rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pLockObject).Int32Value(), rARM_LR); |
| 493 | ClobberCalleeSave(); |
| 494 | LIR* call_inst = OpReg(kOpBlx/*ne*/, rARM_LR); |
| 495 | MarkSafepointPC(call_inst); |
| 496 | GenMemBarrier(kLoadLoad); |
| 497 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 498 | } |
| 499 | |
| 500 | /* |
Ian Rogers | d9c4fc9 | 2013-10-01 19:45:43 -0700 | [diff] [blame] | 501 | * Handle thin locked -> unlocked transition inline or else call out to quick entrypoint. For more |
| 502 | * details see monitor.cc. Note the code below doesn't use ldrex/strex as the code holds the lock |
| 503 | * and can only give away ownership if its suspended. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 504 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 505 | void ArmMir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 506 | FlushAllRegs(); |
| 507 | LoadValueDirectFixed(rl_src, r0); // Get obj |
| 508 | LockCallTemps(); // Prepare for explicit register usage |
Ian Rogers | d9c4fc9 | 2013-10-01 19:45:43 -0700 | [diff] [blame] | 509 | LIR* null_check_branch; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 510 | LoadWordDisp(rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2); |
Ian Rogers | d9c4fc9 | 2013-10-01 19:45:43 -0700 | [diff] [blame] | 511 | constexpr bool kArchVariantHasGoodBranchPredictor = false; // TODO: true if cortex-A15. |
| 512 | if (kArchVariantHasGoodBranchPredictor) { |
| 513 | if ((opt_flags & MIR_IGNORE_NULL_CHECK) && !(cu_->disable_opt & (1 << kNullCheckElimination))) { |
| 514 | null_check_branch = nullptr; // No null check. |
| 515 | } else { |
| 516 | // If the null-check fails its handled by the slow-path to reduce exception related meta-data. |
| 517 | null_check_branch = OpCmpImmBranch(kCondEq, r0, 0, NULL); |
| 518 | } |
| 519 | LoadWordDisp(r0, mirror::Object::MonitorOffset().Int32Value(), r1); |
| 520 | LoadConstantNoClobber(r3, 0); |
| 521 | LIR* slow_unlock_branch = OpCmpBranch(kCondNe, r1, r2, NULL); |
| 522 | StoreWordDisp(r0, mirror::Object::MonitorOffset().Int32Value(), r3); |
| 523 | LIR* unlock_success_branch = OpUnconditionalBranch(NULL); |
| 524 | |
| 525 | LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); |
| 526 | slow_unlock_branch->target = slow_path_target; |
| 527 | if (null_check_branch != nullptr) { |
| 528 | null_check_branch->target = slow_path_target; |
| 529 | } |
| 530 | // TODO: move to a slow path. |
| 531 | // Go expensive route - artUnlockObjectFromCode(obj); |
| 532 | LoadWordDisp(rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pUnlockObject).Int32Value(), rARM_LR); |
| 533 | ClobberCalleeSave(); |
| 534 | LIR* call_inst = OpReg(kOpBlx, rARM_LR); |
| 535 | MarkSafepointPC(call_inst); |
| 536 | |
| 537 | LIR* success_target = NewLIR0(kPseudoTargetLabel); |
| 538 | unlock_success_branch->target = success_target; |
| 539 | GenMemBarrier(kStoreLoad); |
| 540 | } else { |
| 541 | // Explicit null-check as slow-path is entered using an IT. |
| 542 | GenNullCheck(rl_src.s_reg_low, r0, opt_flags); |
| 543 | LoadWordDisp(r0, mirror::Object::MonitorOffset().Int32Value(), r1); // Get lock |
| 544 | LoadWordDisp(rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2); |
| 545 | LoadConstantNoClobber(r3, 0); |
| 546 | // Is lock unheld on lock or held by us (==thread_id) on unlock? |
| 547 | OpRegReg(kOpCmp, r1, r2); |
| 548 | OpIT(kCondEq, "EE"); |
| 549 | StoreWordDisp/*eq*/(r0, mirror::Object::MonitorOffset().Int32Value(), r3); |
| 550 | // Go expensive route - UnlockObjectFromCode(obj); |
| 551 | LoadWordDisp/*ne*/(rARM_SELF, QUICK_ENTRYPOINT_OFFSET(pUnlockObject).Int32Value(), rARM_LR); |
| 552 | ClobberCalleeSave(); |
| 553 | LIR* call_inst = OpReg(kOpBlx/*ne*/, rARM_LR); |
| 554 | MarkSafepointPC(call_inst); |
| 555 | GenMemBarrier(kStoreLoad); |
| 556 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 557 | } |
| 558 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 559 | void ArmMir2Lir::GenMoveException(RegLocation rl_dest) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 560 | int ex_offset = Thread::ExceptionOffset().Int32Value(); |
| 561 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 562 | int reset_reg = AllocTemp(); |
| 563 | LoadWordDisp(rARM_SELF, ex_offset, rl_result.low_reg); |
| 564 | LoadConstant(reset_reg, 0); |
| 565 | StoreWordDisp(rARM_SELF, ex_offset, reset_reg); |
| 566 | FreeTemp(reset_reg); |
| 567 | StoreValue(rl_dest, rl_result); |
| 568 | } |
| 569 | |
| 570 | /* |
| 571 | * Mark garbage collection card. Skip if the value we're storing is null. |
| 572 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 573 | void ArmMir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 574 | int reg_card_base = AllocTemp(); |
| 575 | int reg_card_no = AllocTemp(); |
| 576 | LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); |
| 577 | LoadWordDisp(rARM_SELF, Thread::CardTableOffset().Int32Value(), reg_card_base); |
| 578 | OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); |
| 579 | StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, |
| 580 | kUnsignedByte); |
| 581 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 582 | branch_over->target = target; |
| 583 | FreeTemp(reg_card_base); |
| 584 | FreeTemp(reg_card_no); |
| 585 | } |
| 586 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 587 | void ArmMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 588 | int spill_count = num_core_spills_ + num_fp_spills_; |
| 589 | /* |
| 590 | * On entry, r0, r1, r2 & r3 are live. Let the register allocation |
| 591 | * mechanism know so it doesn't try to use any of them when |
| 592 | * expanding the frame or flushing. This leaves the utility |
| 593 | * code with a single temp: r12. This should be enough. |
| 594 | */ |
| 595 | LockTemp(r0); |
| 596 | LockTemp(r1); |
| 597 | LockTemp(r2); |
| 598 | LockTemp(r3); |
| 599 | |
| 600 | /* |
| 601 | * We can safely skip the stack overflow check if we're |
| 602 | * a leaf *and* our frame size < fudge factor. |
| 603 | */ |
| 604 | bool skip_overflow_check = (mir_graph_->MethodIsLeaf() && |
| 605 | (static_cast<size_t>(frame_size_) < |
| 606 | Thread::kStackOverflowReservedBytes)); |
| 607 | NewLIR0(kPseudoMethodEntry); |
| 608 | if (!skip_overflow_check) { |
| 609 | /* Load stack limit */ |
| 610 | LoadWordDisp(rARM_SELF, Thread::StackEndOffset().Int32Value(), r12); |
| 611 | } |
| 612 | /* Spill core callee saves */ |
| 613 | NewLIR1(kThumb2Push, core_spill_mask_); |
| 614 | /* Need to spill any FP regs? */ |
| 615 | if (num_fp_spills_) { |
| 616 | /* |
| 617 | * NOTE: fp spills are a little different from core spills in that |
| 618 | * they are pushed as a contiguous block. When promoting from |
| 619 | * the fp set, we must allocate all singles from s16..highest-promoted |
| 620 | */ |
| 621 | NewLIR1(kThumb2VPushCS, num_fp_spills_); |
| 622 | } |
| 623 | if (!skip_overflow_check) { |
| 624 | OpRegRegImm(kOpSub, rARM_LR, rARM_SP, frame_size_ - (spill_count * 4)); |
| 625 | GenRegRegCheck(kCondCc, rARM_LR, r12, kThrowStackOverflow); |
| 626 | OpRegCopy(rARM_SP, rARM_LR); // Establish stack |
| 627 | } else { |
| 628 | OpRegImm(kOpSub, rARM_SP, frame_size_ - (spill_count * 4)); |
| 629 | } |
| 630 | |
| 631 | FlushIns(ArgLocs, rl_method); |
| 632 | |
| 633 | FreeTemp(r0); |
| 634 | FreeTemp(r1); |
| 635 | FreeTemp(r2); |
| 636 | FreeTemp(r3); |
| 637 | } |
| 638 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 639 | void ArmMir2Lir::GenExitSequence() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 640 | int spill_count = num_core_spills_ + num_fp_spills_; |
| 641 | /* |
| 642 | * In the exit path, r0/r1 are live - make sure they aren't |
| 643 | * allocated by the register utilities as temps. |
| 644 | */ |
| 645 | LockTemp(r0); |
| 646 | LockTemp(r1); |
| 647 | |
| 648 | NewLIR0(kPseudoMethodExit); |
| 649 | OpRegImm(kOpAdd, rARM_SP, frame_size_ - (spill_count * 4)); |
| 650 | /* Need to restore any FP callee saves? */ |
| 651 | if (num_fp_spills_) { |
| 652 | NewLIR1(kThumb2VPopCS, num_fp_spills_); |
| 653 | } |
| 654 | if (core_spill_mask_ & (1 << rARM_LR)) { |
| 655 | /* Unspill rARM_LR to rARM_PC */ |
| 656 | core_spill_mask_ &= ~(1 << rARM_LR); |
| 657 | core_spill_mask_ |= (1 << rARM_PC); |
| 658 | } |
| 659 | NewLIR1(kThumb2Pop, core_spill_mask_); |
| 660 | if (!(core_spill_mask_ & (1 << rARM_PC))) { |
| 661 | /* We didn't pop to rARM_PC, so must do a bv rARM_LR */ |
| 662 | NewLIR1(kThumbBx, rARM_LR); |
| 663 | } |
| 664 | } |
| 665 | |
| 666 | } // namespace art |