jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1 | /* |
jeffhao | c0228b8 | 2012-08-29 18:15:05 -0700 | [diff] [blame] | 2 | * Copyright (C) 2012 The Android Open Source Project |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_SRC_CONSTANTS_MIPS_H_ |
| 18 | #define ART_SRC_CONSTANTS_MIPS_H_ |
| 19 | |
| 20 | #include <iosfwd> |
| 21 | #include "globals.h" |
| 22 | #include "logging.h" |
| 23 | #include "macros.h" |
| 24 | |
| 25 | namespace art { |
| 26 | namespace mips { |
| 27 | |
| 28 | enum Register { |
| 29 | ZERO = 0, |
| 30 | AT = 1, |
| 31 | V0 = 2, |
| 32 | V1 = 3, |
| 33 | A0 = 4, |
| 34 | A1 = 5, |
| 35 | A2 = 6, |
| 36 | A3 = 7, |
| 37 | T0 = 8, |
| 38 | T1 = 9, |
| 39 | T2 = 10, |
| 40 | T3 = 11, |
| 41 | T4 = 12, |
| 42 | T5 = 13, |
| 43 | T6 = 14, |
| 44 | T7 = 15, |
| 45 | S0 = 16, |
| 46 | S1 = 17, |
| 47 | S2 = 18, |
| 48 | S3 = 19, |
| 49 | S4 = 20, |
| 50 | S5 = 21, |
| 51 | S6 = 22, |
| 52 | S7 = 23, |
| 53 | T8 = 24, |
| 54 | T9 = 25, |
| 55 | K0 = 26, |
| 56 | K1 = 27, |
| 57 | GP = 28, |
| 58 | SP = 29, |
| 59 | FP = 30, |
| 60 | RA = 31, |
| 61 | kNumberOfCoreRegisters = 32, |
| 62 | kNoRegister = -1 // Signals an illegal register. |
| 63 | }; |
| 64 | std::ostream& operator<<(std::ostream& os, const Register& rhs); |
| 65 | |
| 66 | // Values for single-precision floating point registers. |
| 67 | enum FRegister { |
| 68 | F0 = 0, |
| 69 | F1 = 1, |
| 70 | F2 = 2, |
| 71 | F3 = 3, |
| 72 | F4 = 4, |
| 73 | F5 = 5, |
| 74 | F6 = 6, |
| 75 | F7 = 7, |
| 76 | F8 = 8, |
| 77 | F9 = 9, |
| 78 | F10 = 10, |
| 79 | F11 = 11, |
| 80 | F12 = 12, |
| 81 | F13 = 13, |
| 82 | F14 = 14, |
| 83 | F15 = 15, |
| 84 | F16 = 16, |
| 85 | F17 = 17, |
| 86 | F18 = 18, |
| 87 | F19 = 19, |
| 88 | F20 = 20, |
| 89 | F21 = 21, |
| 90 | F22 = 22, |
| 91 | F23 = 23, |
| 92 | F24 = 24, |
| 93 | F25 = 25, |
| 94 | F26 = 26, |
| 95 | F27 = 27, |
| 96 | F28 = 28, |
| 97 | F29 = 29, |
| 98 | F30 = 30, |
| 99 | F31 = 31, |
| 100 | kNumberOfFRegisters = 32, |
| 101 | kNoFRegister = -1, |
| 102 | }; |
| 103 | std::ostream& operator<<(std::ostream& os, const FRegister& rhs); |
| 104 | |
| 105 | // Values for double-precision floating point registers. |
| 106 | enum DRegister { |
| 107 | D0 = 0, |
| 108 | D1 = 1, |
| 109 | D2 = 2, |
| 110 | D3 = 3, |
| 111 | D4 = 4, |
| 112 | D5 = 5, |
| 113 | D6 = 6, |
| 114 | D7 = 7, |
| 115 | D8 = 8, |
| 116 | D9 = 9, |
| 117 | D10 = 10, |
| 118 | D11 = 11, |
| 119 | D12 = 12, |
| 120 | D13 = 13, |
| 121 | D14 = 14, |
| 122 | D15 = 15, |
| 123 | kNumberOfDRegisters = 16, |
| 124 | kNumberOfOverlappingDRegisters = 16, |
| 125 | kNoDRegister = -1, |
| 126 | }; |
| 127 | std::ostream& operator<<(std::ostream& os, const DRegister& rhs); |
| 128 | |
| 129 | // Constants used for the decoding or encoding of the individual fields of instructions. |
| 130 | enum InstructionFields { |
| 131 | kOpcodeShift = 26, |
| 132 | kOpcodeBits = 6, |
| 133 | kRsShift = 21, |
| 134 | kRsBits = 5, |
| 135 | kRtShift = 16, |
| 136 | kRtBits = 5, |
| 137 | kRdShift = 11, |
| 138 | kRdBits = 5, |
| 139 | kShamtShift = 6, |
| 140 | kShamtBits = 5, |
| 141 | kFunctShift = 0, |
| 142 | kFunctBits = 6, |
| 143 | |
| 144 | kFmtShift = 21, |
| 145 | kFmtBits = 5, |
| 146 | kFtShift = 16, |
| 147 | kFtBits = 5, |
| 148 | kFsShift = 11, |
| 149 | kFsBits = 5, |
| 150 | kFdShift = 6, |
| 151 | kFdBits = 5, |
| 152 | |
| 153 | kBranchOffsetMask = 0x0000ffff, |
| 154 | kJumpOffsetMask = 0x03ffffff, |
| 155 | }; |
| 156 | |
| 157 | enum ScaleFactor { |
| 158 | TIMES_1 = 0, |
| 159 | TIMES_2 = 1, |
| 160 | TIMES_4 = 2, |
| 161 | TIMES_8 = 3 |
| 162 | }; |
| 163 | |
| 164 | class Instr { |
| 165 | public: |
| 166 | static const uint32_t kBreakPointInstruction = 0x0000000D; |
| 167 | |
| 168 | bool IsBreakPoint() { |
| 169 | return ((*reinterpret_cast<const uint32_t*>(this)) & 0xFC0000CF) == kBreakPointInstruction; |
| 170 | } |
| 171 | |
| 172 | // Instructions are read out of a code stream. The only way to get a |
| 173 | // reference to an instruction is to convert a pointer. There is no way |
| 174 | // to allocate or create instances of class Instr. |
| 175 | // Use the At(pc) function to create references to Instr. |
| 176 | static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); } |
| 177 | |
| 178 | private: |
| 179 | DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
| 180 | }; |
| 181 | |
| 182 | } // namespace mips |
| 183 | } // namespace art |
| 184 | |
| 185 | #endif // ART_SRC_CONSTANTS_MIPS_H_ |