Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
| 21 | #include "x86_lir.h" |
| 22 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 23 | #include <map> |
| 24 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 25 | namespace art { |
| 26 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 27 | class X86Mir2Lir : public Mir2Lir { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 28 | protected: |
| 29 | class InToRegStorageMapper { |
| 30 | public: |
| 31 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide) = 0; |
| 32 | virtual ~InToRegStorageMapper() {} |
| 33 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 34 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 35 | class InToRegStorageX86_64Mapper : public InToRegStorageMapper { |
| 36 | public: |
| 37 | InToRegStorageX86_64Mapper() : cur_core_reg_(0), cur_fp_reg_(0) {} |
| 38 | virtual ~InToRegStorageX86_64Mapper() {} |
| 39 | virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide); |
| 40 | private: |
| 41 | int cur_core_reg_; |
| 42 | int cur_fp_reg_; |
| 43 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 44 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 45 | class InToRegStorageMapping { |
| 46 | public: |
| 47 | InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), |
| 48 | initialized_(false) {} |
| 49 | void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); |
| 50 | int GetMaxMappedIn() { return max_mapped_in_; } |
| 51 | bool IsThereStackMapped() { return is_there_stack_mapped_; } |
| 52 | RegStorage Get(int in_position); |
| 53 | bool IsInitialized() { return initialized_; } |
| 54 | private: |
| 55 | std::map<int, RegStorage> mapping_; |
| 56 | int max_mapped_in_; |
| 57 | bool is_there_stack_mapped_; |
| 58 | bool initialized_; |
| 59 | }; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 60 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 61 | public: |
| 62 | X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena, bool gen64bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 63 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 64 | // Required for target - codegen helpers. |
| 65 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
| 66 | RegLocation rl_dest, int lit); |
| 67 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
| 68 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
| 69 | RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; |
| 70 | RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; |
| 71 | LIR* LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, |
| 72 | OpSize size) OVERRIDE; |
| 73 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 74 | OpSize size) OVERRIDE; |
| 75 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 76 | OpSize size) OVERRIDE; |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 77 | LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
| 78 | RegStorage r_dest, OpSize size) OVERRIDE; |
| 79 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 80 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
| 81 | LIR* StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src, |
| 82 | OpSize size) OVERRIDE; |
| 83 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
| 84 | OpSize size) OVERRIDE; |
| 85 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
| 86 | OpSize size) OVERRIDE; |
| 87 | LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, |
| 88 | RegStorage r_src, OpSize size) OVERRIDE; |
| 89 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 90 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 91 | // Required for target - register utilities. |
| 92 | RegStorage TargetReg(SpecialTargetRegister reg); |
| 93 | RegStorage GetArgMappingToPhysicalReg(int arg_num); |
| 94 | RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); |
| 95 | RegLocation GetReturnAlt(); |
| 96 | RegLocation GetReturnWideAlt(); |
| 97 | RegLocation LocCReturn(); |
| 98 | RegLocation LocCReturnRef(); |
| 99 | RegLocation LocCReturnDouble(); |
| 100 | RegLocation LocCReturnFloat(); |
| 101 | RegLocation LocCReturnWide(); |
| 102 | uint64_t GetRegMaskCommon(RegStorage reg); |
| 103 | void AdjustSpillMask(); |
| 104 | void ClobberCallerSave(); |
| 105 | void FreeCallTemps(); |
| 106 | void LockCallTemps(); |
| 107 | void MarkPreservedSingle(int v_reg, RegStorage reg); |
| 108 | void MarkPreservedDouble(int v_reg, RegStorage reg); |
| 109 | void CompilerInitializeRegAlloc(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 111 | // Required for target - miscellaneous. |
| 112 | void AssembleLIR(); |
| 113 | int AssignInsnOffsets(); |
| 114 | void AssignOffsets(); |
| 115 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
| 116 | void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); |
| 117 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags); |
| 118 | const char* GetTargetInstFmt(int opcode); |
| 119 | const char* GetTargetInstName(int opcode); |
| 120 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
| 121 | uint64_t GetPCUseDefEncoding(); |
| 122 | uint64_t GetTargetInstFlags(int opcode); |
| 123 | int GetInsnSize(LIR* lir); |
| 124 | bool IsUnconditionalBranch(LIR* lir); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 125 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 126 | // Check support for volatile load/store of a given size. |
| 127 | bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; |
| 128 | // Get the register class for load/store of a field. |
| 129 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 130 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 131 | // Required for target - Dalvik-level generators. |
| 132 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 133 | RegLocation rl_src2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 134 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, |
| 135 | RegLocation rl_dest, int scale); |
| 136 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
| 137 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); |
| 138 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 139 | RegLocation rl_src1, RegLocation rl_shift); |
| 140 | void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 141 | RegLocation rl_src2); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 142 | void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 143 | RegLocation rl_src2); |
| 144 | void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 145 | RegLocation rl_src2); |
| 146 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 147 | RegLocation rl_src2); |
| 148 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 149 | RegLocation rl_src2); |
| 150 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 151 | RegLocation rl_src2); |
| 152 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
| 153 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); |
| 154 | bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); |
| 155 | bool GenInlinedSqrt(CallInfo* info); |
| 156 | bool GenInlinedPeek(CallInfo* info, OpSize size); |
| 157 | bool GenInlinedPoke(CallInfo* info, OpSize size); |
| 158 | void GenNotLong(RegLocation rl_dest, RegLocation rl_src); |
| 159 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 160 | void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 161 | RegLocation rl_src2); |
| 162 | void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 163 | RegLocation rl_src2); |
| 164 | void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 165 | RegLocation rl_src2); |
| 166 | void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
| 167 | RegLocation rl_src2, bool is_div); |
| 168 | // TODO: collapse reg_lo, reg_hi |
| 169 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); |
| 170 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); |
| 171 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
| 172 | void GenDivZeroCheckWide(RegStorage reg); |
| 173 | void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); |
| 174 | void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); |
| 175 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); |
| 176 | void GenExitSequence(); |
| 177 | void GenSpecialExitSequence(); |
| 178 | void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); |
| 179 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| 180 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); |
| 181 | void GenSelect(BasicBlock* bb, MIR* mir); |
| 182 | bool GenMemBarrier(MemBarrierKind barrier_kind); |
| 183 | void GenMoveException(RegLocation rl_dest); |
| 184 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
| 185 | int first_bit, int second_bit); |
| 186 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); |
| 187 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); |
| 188 | void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
| 189 | void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); |
| 190 | void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 191 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 192 | /* |
| 193 | * @brief Generate a two address long operation with a constant value |
| 194 | * @param rl_dest location of result |
| 195 | * @param rl_src constant source operand |
| 196 | * @param op Opcode to be generated |
| 197 | * @return success or not |
| 198 | */ |
| 199 | bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
| 200 | /* |
| 201 | * @brief Generate a three address long operation with a constant value |
| 202 | * @param rl_dest location of result |
| 203 | * @param rl_src1 source operand |
| 204 | * @param rl_src2 constant source operand |
| 205 | * @param op Opcode to be generated |
| 206 | * @return success or not |
| 207 | */ |
| 208 | bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 209 | Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 210 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 211 | /** |
| 212 | * @brief Generate a long arithmetic operation. |
| 213 | * @param rl_dest The destination. |
| 214 | * @param rl_src1 First operand. |
| 215 | * @param rl_src2 Second operand. |
| 216 | * @param op The DEX opcode for the operation. |
| 217 | * @param is_commutative The sources can be swapped if needed. |
| 218 | */ |
| 219 | virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 220 | Instruction::Code op, bool is_commutative); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 221 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 222 | /** |
| 223 | * @brief Generate a two operand long arithmetic operation. |
| 224 | * @param rl_dest The destination. |
| 225 | * @param rl_src Second operand. |
| 226 | * @param op The DEX opcode for the operation. |
| 227 | */ |
| 228 | void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 229 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 230 | /** |
| 231 | * @brief Generate a long operation. |
| 232 | * @param rl_dest The destination. Must be in a register |
| 233 | * @param rl_src The other operand. May be in a register or in memory. |
| 234 | * @param op The DEX opcode for the operation. |
| 235 | */ |
| 236 | virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 237 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 238 | /** |
| 239 | * @brief Implement instanceof a final class with x86 specific code. |
| 240 | * @param use_declaring_class 'true' if we can use the class itself. |
| 241 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 242 | * @param rl_dest Result to be set to 0 or 1. |
| 243 | * @param rl_src Object to be tested. |
| 244 | */ |
| 245 | void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, |
| 246 | RegLocation rl_src); |
| 247 | /* |
| 248 | * |
| 249 | * @brief Implement Set up instanceof a class with x86 specific code. |
| 250 | * @param needs_access_check 'true' if we must check the access. |
| 251 | * @param type_known_final 'true' if the type is known to be a final class. |
| 252 | * @param type_known_abstract 'true' if the type is known to be an abstract class. |
| 253 | * @param use_declaring_class 'true' if the type can be loaded off the current Method*. |
| 254 | * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. |
| 255 | * @param type_idx Type index to use if use_declaring_class is 'false'. |
| 256 | * @param rl_dest Result to be set to 0 or 1. |
| 257 | * @param rl_src Object to be tested. |
| 258 | */ |
| 259 | void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, |
| 260 | bool type_known_abstract, bool use_declaring_class, |
| 261 | bool can_assume_type_is_in_dex_cache, |
| 262 | uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 263 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 264 | void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 265 | RegLocation rl_src1, RegLocation rl_shift); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 266 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 267 | // Single operation generators. |
| 268 | LIR* OpUnconditionalBranch(LIR* target); |
| 269 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); |
| 270 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); |
| 271 | LIR* OpCondBranch(ConditionCode cc, LIR* target); |
| 272 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); |
| 273 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 274 | LIR* OpIT(ConditionCode cond, const char* guide); |
| 275 | void OpEndIT(LIR* it); |
| 276 | LIR* OpMem(OpKind op, RegStorage r_base, int disp); |
| 277 | LIR* OpPcRelLoad(RegStorage reg, LIR* target); |
| 278 | LIR* OpReg(OpKind op, RegStorage r_dest_src); |
| 279 | void OpRegCopy(RegStorage r_dest, RegStorage r_src); |
| 280 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); |
| 281 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); |
| 282 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); |
| 283 | LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); |
| 284 | LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); |
| 285 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); |
| 286 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); |
| 287 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); |
| 288 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); |
| 289 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); |
| 290 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); |
| 291 | LIR* OpTestSuspend(LIR* target); |
| 292 | LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; |
| 293 | LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; |
| 294 | LIR* OpVldm(RegStorage r_base, int count); |
| 295 | LIR* OpVstm(RegStorage r_base, int count); |
| 296 | void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); |
| 297 | void OpRegCopyWide(RegStorage dest, RegStorage src); |
| 298 | void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; |
| 299 | void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 300 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 301 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); |
| 302 | void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); |
| 303 | void SpillCoreRegs(); |
| 304 | void UnSpillCoreRegs(); |
| 305 | static const X86EncodingMap EncodingMap[kX86Last]; |
| 306 | bool InexpensiveConstantInt(int32_t value); |
| 307 | bool InexpensiveConstantFloat(int32_t value); |
| 308 | bool InexpensiveConstantLong(int64_t value); |
| 309 | bool InexpensiveConstantDouble(int64_t value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 310 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 311 | /* |
| 312 | * @brief Should try to optimize for two address instructions? |
| 313 | * @return true if we try to avoid generating three operand instructions. |
| 314 | */ |
| 315 | virtual bool GenerateTwoOperandInstructions() const { return true; } |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 316 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 317 | /* |
| 318 | * @brief x86 specific codegen for int operations. |
| 319 | * @param opcode Operation to perform. |
| 320 | * @param rl_dest Destination for the result. |
| 321 | * @param rl_lhs Left hand operand. |
| 322 | * @param rl_rhs Right hand operand. |
| 323 | */ |
| 324 | void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, |
| 325 | RegLocation rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 326 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 327 | /* |
| 328 | * @brief Dump a RegLocation using printf |
| 329 | * @param loc Register location to dump |
| 330 | */ |
| 331 | static void DumpRegLocation(RegLocation loc); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 332 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 333 | /* |
| 334 | * @brief Load the Method* of a dex method into the register. |
| 335 | * @param target_method The MethodReference of the method to be invoked. |
| 336 | * @param type How the method will be invoked. |
| 337 | * @param register that will contain the code address. |
| 338 | * @note register will be passed to TargetReg to get physical register. |
| 339 | */ |
| 340 | void LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
| 341 | SpecialTargetRegister symbolic_reg); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 342 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 343 | /* |
| 344 | * @brief Load the Class* of a Dex Class type into the register. |
| 345 | * @param type How the method will be invoked. |
| 346 | * @param register that will contain the code address. |
| 347 | * @note register will be passed to TargetReg to get physical register. |
| 348 | */ |
| 349 | void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 350 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 351 | void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 352 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 353 | int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 354 | NextCallInsn next_call_insn, |
| 355 | const MethodReference& target_method, |
| 356 | uint32_t vtable_idx, |
| 357 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 358 | bool skip_this); |
| 359 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 360 | int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, |
| 361 | NextCallInsn next_call_insn, |
| 362 | const MethodReference& target_method, |
| 363 | uint32_t vtable_idx, |
| 364 | uintptr_t direct_code, uintptr_t direct_method, InvokeType type, |
| 365 | bool skip_this); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 366 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 367 | /* |
| 368 | * @brief Generate a relative call to the method that will be patched at link time. |
| 369 | * @param target_method The MethodReference of the method to be invoked. |
| 370 | * @param type How the method will be invoked. |
| 371 | * @returns Call instruction |
| 372 | */ |
| 373 | virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 374 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 375 | /* |
| 376 | * @brief Handle x86 specific literals |
| 377 | */ |
| 378 | void InstallLiteralPools(); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 379 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 380 | /* |
| 381 | * @brief Generate the debug_frame CFI information. |
| 382 | * @returns pointer to vector containing CFE information |
| 383 | */ |
| 384 | static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 385 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 386 | /* |
| 387 | * @brief Generate the debug_frame FDE information. |
| 388 | * @returns pointer to vector containing CFE information |
| 389 | */ |
| 390 | std::vector<uint8_t>* ReturnCallFrameInformation(); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 391 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 392 | protected: |
| 393 | size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, |
| 394 | int32_t raw_base, bool has_sib, bool r8_form, bool r8_reg_reg_form, |
| 395 | int32_t displacement); |
| 396 | void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); |
| 397 | void EmitPrefix(const X86EncodingMap* entry, |
| 398 | int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b, |
| 399 | bool r8_form); |
| 400 | void EmitOpcode(const X86EncodingMap* entry); |
| 401 | void EmitPrefixAndOpcode(const X86EncodingMap* entry, |
| 402 | int32_t reg_r, int32_t reg_x, int32_t reg_b, bool r8_form); |
| 403 | void EmitDisp(uint8_t base, int32_t disp); |
| 404 | void EmitModrmThread(uint8_t reg_or_opcode); |
| 405 | void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); |
| 406 | void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, |
| 407 | int32_t disp); |
| 408 | void EmitImm(const X86EncodingMap* entry, int64_t imm); |
| 409 | void EmitNullary(const X86EncodingMap* entry); |
| 410 | void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); |
| 411 | void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); |
| 412 | void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 413 | void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 414 | int32_t disp); |
| 415 | void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); |
| 416 | void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); |
| 417 | void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, |
| 418 | int32_t raw_index, int scale, int32_t disp); |
| 419 | void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 420 | int32_t disp, int32_t raw_reg); |
| 421 | void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 422 | void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, |
| 423 | int32_t raw_disp, int32_t imm); |
| 424 | void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); |
| 425 | void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); |
| 426 | void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); |
| 427 | void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 428 | int32_t imm); |
| 429 | void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, |
| 430 | int32_t imm); |
| 431 | void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 432 | void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); |
| 433 | void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); |
| 434 | void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); |
| 435 | void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); |
| 436 | void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); |
| 437 | void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); |
| 438 | void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); |
| 439 | void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); |
| 440 | void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); |
| 441 | void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, |
| 442 | int32_t cc); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 443 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 444 | void EmitJmp(const X86EncodingMap* entry, int32_t rel); |
| 445 | void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); |
| 446 | void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); |
| 447 | void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); |
| 448 | void EmitCallThread(const X86EncodingMap* entry, int32_t disp); |
| 449 | void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, |
| 450 | int32_t raw_index, int scale, int32_t table_or_disp); |
| 451 | void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); |
| 452 | void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); |
| 453 | void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 454 | int64_t val, ConditionCode ccode); |
| 455 | void GenConstWide(RegLocation rl_dest, int64_t value); |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 456 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 457 | static bool ProvidesFullMemoryBarrier(X86OpCode opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 458 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 459 | /* |
| 460 | * @brief Ensure that a temporary register is byte addressable. |
| 461 | * @returns a temporary guarenteed to be byte addressable. |
| 462 | */ |
| 463 | virtual RegStorage AllocateByteRegister(); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 464 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 465 | /* |
| 466 | * @brief generate inline code for fast case of Strng.indexOf. |
| 467 | * @param info Call parameters |
| 468 | * @param zero_based 'true' if the index into the string is 0. |
| 469 | * @returns 'true' if the call was inlined, 'false' if a regular call needs to be |
| 470 | * generated. |
| 471 | */ |
| 472 | bool GenInlinedIndexOf(CallInfo* info, bool zero_based); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 473 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 474 | /* |
| 475 | * @brief Load 128 bit constant into vector register. |
| 476 | * @param bb The basic block in which the MIR is from. |
| 477 | * @param mir The MIR whose opcode is kMirConstVector |
| 478 | * @note vA is the TypeSize for the register. |
| 479 | * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. |
| 480 | */ |
| 481 | void GenConst128(BasicBlock* bb, MIR* mir); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 482 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 483 | /* |
| 484 | * @brief MIR to move a vectorized register to another. |
| 485 | * @param bb The basic block in which the MIR is from. |
| 486 | * @param mir The MIR whose opcode is kMirConstVector. |
| 487 | * @note vA: TypeSize |
| 488 | * @note vB: destination |
| 489 | * @note vC: source |
| 490 | */ |
| 491 | void GenMoveVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 492 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 493 | /* |
| 494 | * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. |
| 495 | * @param bb The basic block in which the MIR is from. |
| 496 | * @param mir The MIR whose opcode is kMirConstVector. |
| 497 | * @note vA: TypeSize |
| 498 | * @note vB: destination and source |
| 499 | * @note vC: source |
| 500 | */ |
| 501 | void GenMultiplyVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 502 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 503 | /* |
| 504 | * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. |
| 505 | * @param bb The basic block in which the MIR is from. |
| 506 | * @param mir The MIR whose opcode is kMirConstVector. |
| 507 | * @note vA: TypeSize |
| 508 | * @note vB: destination and source |
| 509 | * @note vC: source |
| 510 | */ |
| 511 | void GenAddVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 512 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 513 | /* |
| 514 | * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. |
| 515 | * @param bb The basic block in which the MIR is from. |
| 516 | * @param mir The MIR whose opcode is kMirConstVector. |
| 517 | * @note vA: TypeSize |
| 518 | * @note vB: destination and source |
| 519 | * @note vC: source |
| 520 | */ |
| 521 | void GenSubtractVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 522 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 523 | /* |
| 524 | * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. |
| 525 | * @param bb The basic block in which the MIR is from. |
| 526 | * @param mir The MIR whose opcode is kMirConstVector. |
| 527 | * @note vA: TypeSize |
| 528 | * @note vB: destination and source |
| 529 | * @note vC: immediate |
| 530 | */ |
| 531 | void GenShiftLeftVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 532 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 533 | /* |
| 534 | * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. |
| 535 | * @param bb The basic block in which the MIR is from. |
| 536 | * @param mir The MIR whose opcode is kMirConstVector. |
| 537 | * @note vA: TypeSize |
| 538 | * @note vB: destination and source |
| 539 | * @note vC: immediate |
| 540 | */ |
| 541 | void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 542 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 543 | /* |
| 544 | * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. |
| 545 | * @param bb The basic block in which the MIR is from.. |
| 546 | * @param mir The MIR whose opcode is kMirConstVector. |
| 547 | * @note vA: TypeSize |
| 548 | * @note vB: destination and source |
| 549 | * @note vC: immediate |
| 550 | */ |
| 551 | void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 552 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 553 | /* |
| 554 | * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. |
| 555 | * @note vA: TypeSize |
| 556 | * @note vB: destination and source |
| 557 | * @note vC: source |
| 558 | */ |
| 559 | void GenAndVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 560 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 561 | /* |
| 562 | * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. |
| 563 | * @param bb The basic block in which the MIR is from. |
| 564 | * @param mir The MIR whose opcode is kMirConstVector. |
| 565 | * @note vA: TypeSize |
| 566 | * @note vB: destination and source |
| 567 | * @note vC: source |
| 568 | */ |
| 569 | void GenOrVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 570 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 571 | /* |
| 572 | * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. |
| 573 | * @param bb The basic block in which the MIR is from. |
| 574 | * @param mir The MIR whose opcode is kMirConstVector. |
| 575 | * @note vA: TypeSize |
| 576 | * @note vB: destination and source |
| 577 | * @note vC: source |
| 578 | */ |
| 579 | void GenXorVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 580 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 581 | /* |
| 582 | * @brief Reduce a 128-bit packed element into a single VR by taking lower bits |
| 583 | * @param bb The basic block in which the MIR is from. |
| 584 | * @param mir The MIR whose opcode is kMirConstVector. |
| 585 | * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. |
| 586 | * @note vA: TypeSize |
| 587 | * @note vB: destination and source VR (not vector register) |
| 588 | * @note vC: source (vector register) |
| 589 | */ |
| 590 | void GenAddReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 591 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 592 | /* |
| 593 | * @brief Extract a packed element into a single VR. |
| 594 | * @param bb The basic block in which the MIR is from. |
| 595 | * @param mir The MIR whose opcode is kMirConstVector. |
| 596 | * @note vA: TypeSize |
| 597 | * @note vB: destination VR (not vector register) |
| 598 | * @note vC: source (vector register) |
| 599 | * @note arg[0]: The index to use for extraction from vector register (which packed element). |
| 600 | */ |
| 601 | void GenReduceVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 602 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 603 | /* |
| 604 | * @brief Create a vector value, with all TypeSize values equal to vC |
| 605 | * @param bb The basic block in which the MIR is from. |
| 606 | * @param mir The MIR whose opcode is kMirConstVector. |
| 607 | * @note vA: TypeSize. |
| 608 | * @note vB: destination vector register. |
| 609 | * @note vC: source VR (not vector register). |
| 610 | */ |
| 611 | void GenSetVector(BasicBlock *bb, MIR *mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 612 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 613 | /* |
| 614 | * @brief Generate code for a vector opcode. |
| 615 | * @param bb The basic block in which the MIR is from. |
| 616 | * @param mir The MIR whose opcode is a non-standard opcode. |
| 617 | */ |
| 618 | void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 619 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 620 | /* |
| 621 | * @brief Return the correct x86 opcode for the Dex operation |
| 622 | * @param op Dex opcode for the operation |
| 623 | * @param loc Register location of the operand |
| 624 | * @param is_high_op 'true' if this is an operation on the high word |
| 625 | * @param value Immediate value for the operation. Used for byte variants |
| 626 | * @returns the correct x86 opcode to perform the operation |
| 627 | */ |
| 628 | X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 629 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 630 | /* |
| 631 | * @brief Return the correct x86 opcode for the Dex operation |
| 632 | * @param op Dex opcode for the operation |
| 633 | * @param dest location of the destination. May be register or memory. |
| 634 | * @param rhs Location for the rhs of the operation. May be in register or memory. |
| 635 | * @param is_high_op 'true' if this is an operation on the high word |
| 636 | * @returns the correct x86 opcode to perform the operation |
| 637 | * @note at most one location may refer to memory |
| 638 | */ |
| 639 | X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 640 | bool is_high_op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 641 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 642 | /* |
| 643 | * @brief Is this operation a no-op for this opcode and value |
| 644 | * @param op Dex opcode for the operation |
| 645 | * @param value Immediate value for the operation. |
| 646 | * @returns 'true' if the operation will have no effect |
| 647 | */ |
| 648 | bool IsNoOp(Instruction::Code op, int32_t value); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 649 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 650 | /** |
| 651 | * @brief Calculate magic number and shift for a given divisor |
| 652 | * @param divisor divisor number for calculation |
| 653 | * @param magic hold calculated magic number |
| 654 | * @param shift hold calculated shift |
| 655 | */ |
| 656 | void CalculateMagicAndShift(int divisor, int& magic, int& shift); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 657 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 658 | /* |
| 659 | * @brief Generate an integer div or rem operation. |
| 660 | * @param rl_dest Destination Location. |
| 661 | * @param rl_src1 Numerator Location. |
| 662 | * @param rl_src2 Divisor Location. |
| 663 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 664 | * @param check_zero 'true' if an exception should be generated if the divisor is 0. |
| 665 | */ |
| 666 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, |
| 667 | bool is_div, bool check_zero); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 668 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 669 | /* |
| 670 | * @brief Generate an integer div or rem operation by a literal. |
| 671 | * @param rl_dest Destination Location. |
| 672 | * @param rl_src Numerator Location. |
| 673 | * @param lit Divisor. |
| 674 | * @param is_div 'true' if this is a division, 'false' for a remainder. |
| 675 | */ |
| 676 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 677 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 678 | /* |
| 679 | * Generate code to implement long shift operations. |
| 680 | * @param opcode The DEX opcode to specify the shift type. |
| 681 | * @param rl_dest The destination. |
| 682 | * @param rl_src The value to be shifted. |
| 683 | * @param shift_amount How much to shift. |
| 684 | * @returns the RegLocation of the result. |
| 685 | */ |
| 686 | RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 687 | RegLocation rl_src, int shift_amount); |
| 688 | /* |
| 689 | * Generate an imul of a register by a constant or a better sequence. |
| 690 | * @param dest Destination Register. |
| 691 | * @param src Source Register. |
| 692 | * @param val Constant multiplier. |
| 693 | */ |
| 694 | void GenImulRegImm(RegStorage dest, RegStorage src, int val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 695 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 696 | /* |
| 697 | * Generate an imul of a memory location by a constant or a better sequence. |
| 698 | * @param dest Destination Register. |
| 699 | * @param sreg Symbolic register. |
| 700 | * @param displacement Displacement on stack of Symbolic Register. |
| 701 | * @param val Constant multiplier. |
| 702 | */ |
| 703 | void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 704 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 705 | /* |
| 706 | * @brief Compare memory to immediate, and branch if condition true. |
| 707 | * @param cond The condition code that when true will branch to the target. |
| 708 | * @param temp_reg A temporary register that can be used if compare memory is not |
| 709 | * supported by the architecture. |
| 710 | * @param base_reg The register holding the base address. |
| 711 | * @param offset The offset from the base. |
| 712 | * @param check_value The immediate to compare to. |
| 713 | */ |
| 714 | LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, |
| 715 | int offset, int check_value, LIR* target); |
Mark Mendell | 766e929 | 2014-01-27 07:55:47 -0800 | [diff] [blame] | 716 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 717 | /* |
| 718 | * Can this operation be using core registers without temporaries? |
| 719 | * @param rl_lhs Left hand operand. |
| 720 | * @param rl_rhs Right hand operand. |
| 721 | * @returns 'true' if the operation can proceed without needing temporary regs. |
| 722 | */ |
| 723 | bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 724 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 725 | /** |
| 726 | * @brief Generates inline code for conversion of long to FP by using x87/ |
| 727 | * @param rl_dest The destination of the FP. |
| 728 | * @param rl_src The source of the long. |
| 729 | * @param is_double 'true' if dealing with double, 'false' for float. |
| 730 | */ |
| 731 | virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 732 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 733 | /* |
| 734 | * @brief Perform MIR analysis before compiling method. |
| 735 | * @note Invokes Mir2LiR::Materialize after analysis. |
| 736 | */ |
| 737 | void Materialize(); |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 738 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 739 | /* |
| 740 | * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register |
| 741 | * without regard to data type. In practice, this can result in UpdateLoc returning a |
| 742 | * location record for a Dalvik float value in a core register, and vis-versa. For targets |
| 743 | * which can inexpensively move data between core and float registers, this can often be a win. |
| 744 | * However, for x86 this is generally not a win. These variants of UpdateLoc() |
| 745 | * take a register class argument - and will return an in-register location record only if |
| 746 | * the value is live in a temp register of the correct class. Additionally, if the value is in |
| 747 | * a temp register of the wrong register class, it will be clobbered. |
| 748 | */ |
| 749 | RegLocation UpdateLocTyped(RegLocation loc, int reg_class); |
| 750 | RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 751 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 752 | /* |
| 753 | * @brief Analyze MIR before generating code, to prepare for the code generation. |
| 754 | */ |
| 755 | void AnalyzeMIR(); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 756 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 757 | /* |
| 758 | * @brief Analyze one basic block. |
| 759 | * @param bb Basic block to analyze. |
| 760 | */ |
| 761 | void AnalyzeBB(BasicBlock * bb); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 762 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 763 | /* |
| 764 | * @brief Analyze one extended MIR instruction |
| 765 | * @param opcode MIR instruction opcode. |
| 766 | * @param bb Basic block containing instruction. |
| 767 | * @param mir Extended instruction to analyze. |
| 768 | */ |
| 769 | void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 770 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 771 | /* |
| 772 | * @brief Analyze one MIR instruction |
| 773 | * @param opcode MIR instruction opcode. |
| 774 | * @param bb Basic block containing instruction. |
| 775 | * @param mir Instruction to analyze. |
| 776 | */ |
| 777 | virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 778 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 779 | /* |
| 780 | * @brief Analyze one MIR float/double instruction |
| 781 | * @param opcode MIR instruction opcode. |
| 782 | * @param bb Basic block containing instruction. |
| 783 | * @param mir Instruction to analyze. |
| 784 | */ |
| 785 | void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 786 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 787 | /* |
| 788 | * @brief Analyze one use of a double operand. |
| 789 | * @param rl_use Double RegLocation for the operand. |
| 790 | */ |
| 791 | void AnalyzeDoubleUse(RegLocation rl_use); |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 792 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 793 | bool Gen64Bit() const { return gen64bit_; } |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 794 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 795 | // Information derived from analysis of MIR |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 796 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 797 | // The compiler temporary for the code address of the method. |
| 798 | CompilerTemp *base_of_code_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 799 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 800 | // Have we decided to compute a ptr to code and store in temporary VR? |
| 801 | bool store_method_addr_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 802 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 803 | // Have we used the stored method address? |
| 804 | bool store_method_addr_used_; |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 805 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 806 | // Instructions to remove if we didn't use the stored method address. |
| 807 | LIR* setup_method_address_[2]; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 808 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 809 | // Instructions needing patching with Method* values. |
| 810 | GrowableArray<LIR*> method_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 811 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 812 | // Instructions needing patching with Class Type* values. |
| 813 | GrowableArray<LIR*> class_type_address_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 814 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 815 | // Instructions needing patching with PC relative code addresses. |
| 816 | GrowableArray<LIR*> call_method_insns_; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 817 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 818 | // Prologue decrement of stack pointer. |
| 819 | LIR* stack_decrement_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 820 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 821 | // Epilogue increment of stack pointer. |
| 822 | LIR* stack_increment_; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 823 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 824 | // 64-bit mode |
| 825 | bool gen64bit_; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 826 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 827 | // The list of const vector literals. |
| 828 | LIR *const_vectors_; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 829 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 830 | /* |
| 831 | * @brief Search for a matching vector literal |
| 832 | * @param mir A kMirOpConst128b MIR instruction to match. |
| 833 | * @returns pointer to matching LIR constant, or nullptr if not found. |
| 834 | */ |
| 835 | LIR *ScanVectorLiteral(MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 836 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 837 | /* |
| 838 | * @brief Add a constant vector literal |
| 839 | * @param mir A kMirOpConst128b MIR instruction to match. |
| 840 | */ |
| 841 | LIR *AddVectorLiteral(MIR *mir); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 842 | |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame^] | 843 | InToRegStorageMapping in_to_reg_storage_mapping_; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 844 | }; |
| 845 | |
| 846 | } // namespace art |
| 847 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 848 | #endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ |