Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_x86.h" |
| 18 | #include "dex/compiler_internals.h" |
| 19 | #include "dex/quick/mir_to_lir-inl.h" |
| 20 | #include "x86_lir.h" |
| 21 | |
| 22 | #include <string> |
| 23 | |
| 24 | namespace art { |
| 25 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 26 | // FIXME: restore "static" when usage uncovered |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | /*static*/ int core_regs[] = { |
| 28 | rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI |
| 29 | #ifdef TARGET_REX_SUPPORT |
| 30 | r8, r9, r10, r11, r12, r13, r14, 15 |
| 31 | #endif |
| 32 | }; |
| 33 | /*static*/ int ReservedRegs[] = {rX86_SP}; |
| 34 | /*static*/ int core_temps[] = {rAX, rCX, rDX, rBX}; |
| 35 | /*static*/ int FpRegs[] = { |
| 36 | fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, |
| 37 | #ifdef TARGET_REX_SUPPORT |
| 38 | fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 |
| 39 | #endif |
| 40 | }; |
| 41 | /*static*/ int fp_temps[] = { |
| 42 | fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, |
| 43 | #ifdef TARGET_REX_SUPPORT |
| 44 | fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 |
| 45 | #endif |
| 46 | }; |
| 47 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 48 | RegLocation X86Mir2Lir::LocCReturn() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | RegLocation res = X86_LOC_C_RETURN; |
| 50 | return res; |
| 51 | } |
| 52 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 53 | RegLocation X86Mir2Lir::LocCReturnWide() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 54 | RegLocation res = X86_LOC_C_RETURN_WIDE; |
| 55 | return res; |
| 56 | } |
| 57 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 58 | RegLocation X86Mir2Lir::LocCReturnFloat() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 59 | RegLocation res = X86_LOC_C_RETURN_FLOAT; |
| 60 | return res; |
| 61 | } |
| 62 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 63 | RegLocation X86Mir2Lir::LocCReturnDouble() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 64 | RegLocation res = X86_LOC_C_RETURN_DOUBLE; |
| 65 | return res; |
| 66 | } |
| 67 | |
| 68 | // Return a target-dependent special register. |
| 69 | int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { |
| 70 | int res = INVALID_REG; |
| 71 | switch (reg) { |
| 72 | case kSelf: res = rX86_SELF; break; |
| 73 | case kSuspend: res = rX86_SUSPEND; break; |
| 74 | case kLr: res = rX86_LR; break; |
| 75 | case kPc: res = rX86_PC; break; |
| 76 | case kSp: res = rX86_SP; break; |
| 77 | case kArg0: res = rX86_ARG0; break; |
| 78 | case kArg1: res = rX86_ARG1; break; |
| 79 | case kArg2: res = rX86_ARG2; break; |
| 80 | case kArg3: res = rX86_ARG3; break; |
| 81 | case kFArg0: res = rX86_FARG0; break; |
| 82 | case kFArg1: res = rX86_FARG1; break; |
| 83 | case kFArg2: res = rX86_FARG2; break; |
| 84 | case kFArg3: res = rX86_FARG3; break; |
| 85 | case kRet0: res = rX86_RET0; break; |
| 86 | case kRet1: res = rX86_RET1; break; |
| 87 | case kInvokeTgt: res = rX86_INVOKE_TGT; break; |
Jeff Hao | 88474b4 | 2013-10-23 16:24:40 -0700 | [diff] [blame] | 88 | case kHiddenArg: res = rAX; break; |
| 89 | case kHiddenFpArg: res = fr0; break; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 90 | case kCount: res = rX86_COUNT; break; |
| 91 | } |
| 92 | return res; |
| 93 | } |
| 94 | |
| 95 | // Create a double from a pair of singles. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 96 | int X86Mir2Lir::S2d(int low_reg, int high_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 97 | return X86_S2D(low_reg, high_reg); |
| 98 | } |
| 99 | |
| 100 | // Return mask to strip off fp reg flags and bias. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 101 | uint32_t X86Mir2Lir::FpRegMask() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 102 | return X86_FP_REG_MASK; |
| 103 | } |
| 104 | |
| 105 | // True if both regs single, both core or both double. |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 106 | bool X86Mir2Lir::SameRegType(int reg1, int reg2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2)); |
| 108 | } |
| 109 | |
| 110 | /* |
| 111 | * Decode the register id. |
| 112 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 113 | uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 114 | uint64_t seed; |
| 115 | int shift; |
| 116 | int reg_id; |
| 117 | |
| 118 | reg_id = reg & 0xf; |
| 119 | /* Double registers in x86 are just a single FP register */ |
| 120 | seed = 1; |
| 121 | /* FP register starts at bit position 16 */ |
| 122 | shift = X86_FPREG(reg) ? kX86FPReg0 : 0; |
| 123 | /* Expand the double register id into single offset */ |
| 124 | shift += reg_id; |
| 125 | return (seed << shift); |
| 126 | } |
| 127 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 128 | uint64_t X86Mir2Lir::GetPCUseDefEncoding() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 129 | /* |
| 130 | * FIXME: might make sense to use a virtual resource encoding bit for pc. Might be |
| 131 | * able to clean up some of the x86/Arm_Mips differences |
| 132 | */ |
| 133 | LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for x86"; |
| 134 | return 0ULL; |
| 135 | } |
| 136 | |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 137 | void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 138 | DCHECK_EQ(cu_->instruction_set, kX86); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 139 | DCHECK(!lir->flags.use_def_invalid); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 140 | |
| 141 | // X86-specific resource map setup here. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 142 | if (flags & REG_USE_SP) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 143 | lir->u.m.use_mask |= ENCODE_X86_REG_SP; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | if (flags & REG_DEF_SP) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 147 | lir->u.m.def_mask |= ENCODE_X86_REG_SP; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | if (flags & REG_DEFA) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 151 | SetupRegMask(&lir->u.m.def_mask, rAX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | if (flags & REG_DEFD) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 155 | SetupRegMask(&lir->u.m.def_mask, rDX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 156 | } |
| 157 | if (flags & REG_USEA) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 158 | SetupRegMask(&lir->u.m.use_mask, rAX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | if (flags & REG_USEC) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 162 | SetupRegMask(&lir->u.m.use_mask, rCX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | if (flags & REG_USED) { |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 166 | SetupRegMask(&lir->u.m.use_mask, rDX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 167 | } |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 168 | |
| 169 | if (flags & REG_USEB) { |
| 170 | SetupRegMask(&lir->u.m.use_mask, rBX); |
| 171 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | /* For dumping instructions */ |
| 175 | static const char* x86RegName[] = { |
| 176 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", |
| 177 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
| 178 | }; |
| 179 | |
| 180 | static const char* x86CondName[] = { |
| 181 | "O", |
| 182 | "NO", |
| 183 | "B/NAE/C", |
| 184 | "NB/AE/NC", |
| 185 | "Z/EQ", |
| 186 | "NZ/NE", |
| 187 | "BE/NA", |
| 188 | "NBE/A", |
| 189 | "S", |
| 190 | "NS", |
| 191 | "P/PE", |
| 192 | "NP/PO", |
| 193 | "L/NGE", |
| 194 | "NL/GE", |
| 195 | "LE/NG", |
| 196 | "NLE/G" |
| 197 | }; |
| 198 | |
| 199 | /* |
| 200 | * Interpret a format string and build a string no longer than size |
| 201 | * See format key in Assemble.cc. |
| 202 | */ |
| 203 | std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { |
| 204 | std::string buf; |
| 205 | size_t i = 0; |
| 206 | size_t fmt_len = strlen(fmt); |
| 207 | while (i < fmt_len) { |
| 208 | if (fmt[i] != '!') { |
| 209 | buf += fmt[i]; |
| 210 | i++; |
| 211 | } else { |
| 212 | i++; |
| 213 | DCHECK_LT(i, fmt_len); |
| 214 | char operand_number_ch = fmt[i]; |
| 215 | i++; |
| 216 | if (operand_number_ch == '!') { |
| 217 | buf += "!"; |
| 218 | } else { |
| 219 | int operand_number = operand_number_ch - '0'; |
| 220 | DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. |
| 221 | DCHECK_LT(i, fmt_len); |
| 222 | int operand = lir->operands[operand_number]; |
| 223 | switch (fmt[i]) { |
| 224 | case 'c': |
| 225 | DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); |
| 226 | buf += x86CondName[operand]; |
| 227 | break; |
| 228 | case 'd': |
| 229 | buf += StringPrintf("%d", operand); |
| 230 | break; |
| 231 | case 'p': { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 232 | EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 233 | buf += StringPrintf("0x%08x", tab_rec->offset); |
| 234 | break; |
| 235 | } |
| 236 | case 'r': |
| 237 | if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) { |
| 238 | int fp_reg = operand & X86_FP_REG_MASK; |
| 239 | buf += StringPrintf("xmm%d", fp_reg); |
| 240 | } else { |
| 241 | DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName)); |
| 242 | buf += x86RegName[operand]; |
| 243 | } |
| 244 | break; |
| 245 | case 't': |
Ian Rogers | 107c31e | 2014-01-23 20:55:29 -0800 | [diff] [blame^] | 246 | buf += StringPrintf("0x%08" PRIxPTR " (L%p)", |
| 247 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, |
| 248 | lir->target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 249 | break; |
| 250 | default: |
| 251 | buf += StringPrintf("DecodeError '%c'", fmt[i]); |
| 252 | break; |
| 253 | } |
| 254 | i++; |
| 255 | } |
| 256 | } |
| 257 | } |
| 258 | return buf; |
| 259 | } |
| 260 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 261 | void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 262 | char buf[256]; |
| 263 | buf[0] = 0; |
| 264 | |
| 265 | if (mask == ENCODE_ALL) { |
| 266 | strcpy(buf, "all"); |
| 267 | } else { |
| 268 | char num[8]; |
| 269 | int i; |
| 270 | |
| 271 | for (i = 0; i < kX86RegEnd; i++) { |
| 272 | if (mask & (1ULL << i)) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 273 | snprintf(num, arraysize(num), "%d ", i); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 274 | strcat(buf, num); |
| 275 | } |
| 276 | } |
| 277 | |
| 278 | if (mask & ENCODE_CCODE) { |
| 279 | strcat(buf, "cc "); |
| 280 | } |
| 281 | /* Memory bits */ |
| 282 | if (x86LIR && (mask & ENCODE_DALVIK_REG)) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 283 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 284 | DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), |
| 285 | (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 286 | } |
| 287 | if (mask & ENCODE_LITERAL) { |
| 288 | strcat(buf, "lit "); |
| 289 | } |
| 290 | |
| 291 | if (mask & ENCODE_HEAP_REF) { |
| 292 | strcat(buf, "heap "); |
| 293 | } |
| 294 | if (mask & ENCODE_MUST_NOT_ALIAS) { |
| 295 | strcat(buf, "noalias "); |
| 296 | } |
| 297 | } |
| 298 | if (buf[0]) { |
| 299 | LOG(INFO) << prefix << ": " << buf; |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | void X86Mir2Lir::AdjustSpillMask() { |
| 304 | // Adjustment for LR spilling, x86 has no LR so nothing to do here |
| 305 | core_spill_mask_ |= (1 << rRET); |
| 306 | num_core_spills_++; |
| 307 | } |
| 308 | |
| 309 | /* |
| 310 | * Mark a callee-save fp register as promoted. Note that |
| 311 | * vpush/vpop uses contiguous register lists so we must |
| 312 | * include any holes in the mask. Associate holes with |
| 313 | * Dalvik register INVALID_VREG (0xFFFFU). |
| 314 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 315 | void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 316 | UNIMPLEMENTED(WARNING) << "MarkPreservedSingle"; |
| 317 | #if 0 |
| 318 | LOG(FATAL) << "No support yet for promoted FP regs"; |
| 319 | #endif |
| 320 | } |
| 321 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 322 | void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 323 | RegisterInfo* info1 = GetRegInfo(reg1); |
| 324 | RegisterInfo* info2 = GetRegInfo(reg2); |
| 325 | DCHECK(info1 && info2 && info1->pair && info2->pair && |
| 326 | (info1->partner == info2->reg) && |
| 327 | (info2->partner == info1->reg)); |
| 328 | if ((info1->live && info1->dirty) || (info2->live && info2->dirty)) { |
| 329 | if (!(info1->is_temp && info2->is_temp)) { |
| 330 | /* Should not happen. If it does, there's a problem in eval_loc */ |
| 331 | LOG(FATAL) << "Long half-temp, half-promoted"; |
| 332 | } |
| 333 | |
| 334 | info1->dirty = false; |
| 335 | info2->dirty = false; |
| 336 | if (mir_graph_->SRegToVReg(info2->s_reg) < mir_graph_->SRegToVReg(info1->s_reg)) |
| 337 | info1 = info2; |
| 338 | int v_reg = mir_graph_->SRegToVReg(info1->s_reg); |
| 339 | StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info1->partner); |
| 340 | } |
| 341 | } |
| 342 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 343 | void X86Mir2Lir::FlushReg(int reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 344 | RegisterInfo* info = GetRegInfo(reg); |
| 345 | if (info->live && info->dirty) { |
| 346 | info->dirty = false; |
| 347 | int v_reg = mir_graph_->SRegToVReg(info->s_reg); |
| 348 | StoreBaseDisp(rX86_SP, VRegOffset(v_reg), reg, kWord); |
| 349 | } |
| 350 | } |
| 351 | |
| 352 | /* Give access to the target-dependent FP register encoding to common code */ |
| 353 | bool X86Mir2Lir::IsFpReg(int reg) { |
| 354 | return X86_FPREG(reg); |
| 355 | } |
| 356 | |
| 357 | /* Clobber all regs that might be used by an external C call */ |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 358 | void X86Mir2Lir::ClobberCallerSave() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 359 | Clobber(rAX); |
| 360 | Clobber(rCX); |
| 361 | Clobber(rDX); |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 362 | Clobber(rBX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | RegLocation X86Mir2Lir::GetReturnWideAlt() { |
| 366 | RegLocation res = LocCReturnWide(); |
| 367 | CHECK(res.low_reg == rAX); |
| 368 | CHECK(res.high_reg == rDX); |
| 369 | Clobber(rAX); |
| 370 | Clobber(rDX); |
| 371 | MarkInUse(rAX); |
| 372 | MarkInUse(rDX); |
| 373 | MarkPair(res.low_reg, res.high_reg); |
| 374 | return res; |
| 375 | } |
| 376 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 377 | RegLocation X86Mir2Lir::GetReturnAlt() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 378 | RegLocation res = LocCReturn(); |
| 379 | res.low_reg = rDX; |
| 380 | Clobber(rDX); |
| 381 | MarkInUse(rDX); |
| 382 | return res; |
| 383 | } |
| 384 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 385 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 386 | void X86Mir2Lir::LockCallTemps() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 387 | LockTemp(rX86_ARG0); |
| 388 | LockTemp(rX86_ARG1); |
| 389 | LockTemp(rX86_ARG2); |
| 390 | LockTemp(rX86_ARG3); |
| 391 | } |
| 392 | |
| 393 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 394 | void X86Mir2Lir::FreeCallTemps() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 395 | FreeTemp(rX86_ARG0); |
| 396 | FreeTemp(rX86_ARG1); |
| 397 | FreeTemp(rX86_ARG2); |
| 398 | FreeTemp(rX86_ARG3); |
| 399 | } |
| 400 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 401 | void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 402 | #if ANDROID_SMP != 0 |
| 403 | // TODO: optimize fences |
| 404 | NewLIR0(kX86Mfence); |
| 405 | #endif |
| 406 | } |
| 407 | /* |
| 408 | * Alloc a pair of core registers, or a double. Low reg in low byte, |
| 409 | * high reg in next byte. |
| 410 | */ |
| 411 | int X86Mir2Lir::AllocTypedTempPair(bool fp_hint, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 412 | int reg_class) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 413 | int high_reg; |
| 414 | int low_reg; |
| 415 | int res = 0; |
| 416 | |
| 417 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { |
| 418 | low_reg = AllocTempDouble(); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 419 | high_reg = low_reg; // only one allocated! |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 420 | res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); |
| 421 | return res; |
| 422 | } |
| 423 | |
| 424 | low_reg = AllocTemp(); |
| 425 | high_reg = AllocTemp(); |
| 426 | res = (low_reg & 0xff) | ((high_reg & 0xff) << 8); |
| 427 | return res; |
| 428 | } |
| 429 | |
| 430 | int X86Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { |
| 431 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { |
| 432 | return AllocTempFloat(); |
| 433 | } |
| 434 | return AllocTemp(); |
| 435 | } |
| 436 | |
| 437 | void X86Mir2Lir::CompilerInitializeRegAlloc() { |
| 438 | int num_regs = sizeof(core_regs)/sizeof(*core_regs); |
| 439 | int num_reserved = sizeof(ReservedRegs)/sizeof(*ReservedRegs); |
| 440 | int num_temps = sizeof(core_temps)/sizeof(*core_temps); |
| 441 | int num_fp_regs = sizeof(FpRegs)/sizeof(*FpRegs); |
| 442 | int num_fp_temps = sizeof(fp_temps)/sizeof(*fp_temps); |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 443 | reg_pool_ = static_cast<RegisterPool*>(arena_->Alloc(sizeof(*reg_pool_), |
| 444 | ArenaAllocator::kAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 445 | reg_pool_->num_core_regs = num_regs; |
| 446 | reg_pool_->core_regs = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 447 | static_cast<RegisterInfo*>(arena_->Alloc(num_regs * sizeof(*reg_pool_->core_regs), |
| 448 | ArenaAllocator::kAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 449 | reg_pool_->num_fp_regs = num_fp_regs; |
| 450 | reg_pool_->FPRegs = |
Mathieu Chartier | f6c4b3b | 2013-08-24 16:11:37 -0700 | [diff] [blame] | 451 | static_cast<RegisterInfo *>(arena_->Alloc(num_fp_regs * sizeof(*reg_pool_->FPRegs), |
| 452 | ArenaAllocator::kAllocRegAlloc)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 453 | CompilerInitPool(reg_pool_->core_regs, core_regs, reg_pool_->num_core_regs); |
| 454 | CompilerInitPool(reg_pool_->FPRegs, FpRegs, reg_pool_->num_fp_regs); |
| 455 | // Keep special registers from being allocated |
| 456 | for (int i = 0; i < num_reserved; i++) { |
| 457 | MarkInUse(ReservedRegs[i]); |
| 458 | } |
| 459 | // Mark temp regs - all others not in use can be used for promotion |
| 460 | for (int i = 0; i < num_temps; i++) { |
| 461 | MarkTemp(core_temps[i]); |
| 462 | } |
| 463 | for (int i = 0; i < num_fp_temps; i++) { |
| 464 | MarkTemp(fp_temps[i]); |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 469 | RegLocation rl_free) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 470 | if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) && |
| 471 | (rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) { |
| 472 | // No overlap, free both |
| 473 | FreeTemp(rl_free.low_reg); |
| 474 | FreeTemp(rl_free.high_reg); |
| 475 | } |
| 476 | } |
| 477 | |
| 478 | void X86Mir2Lir::SpillCoreRegs() { |
| 479 | if (num_core_spills_ == 0) { |
| 480 | return; |
| 481 | } |
| 482 | // Spill mask not including fake return address register |
| 483 | uint32_t mask = core_spill_mask_ & ~(1 << rRET); |
| 484 | int offset = frame_size_ - (4 * num_core_spills_); |
| 485 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 486 | if (mask & 0x1) { |
| 487 | StoreWordDisp(rX86_SP, offset, reg); |
| 488 | offset += 4; |
| 489 | } |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | void X86Mir2Lir::UnSpillCoreRegs() { |
| 494 | if (num_core_spills_ == 0) { |
| 495 | return; |
| 496 | } |
| 497 | // Spill mask not including fake return address register |
| 498 | uint32_t mask = core_spill_mask_ & ~(1 << rRET); |
| 499 | int offset = frame_size_ - (4 * num_core_spills_); |
| 500 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 501 | if (mask & 0x1) { |
| 502 | LoadWordDisp(rX86_SP, offset, reg); |
| 503 | offset += 4; |
| 504 | } |
| 505 | } |
| 506 | } |
| 507 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 508 | bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 509 | return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); |
| 510 | } |
| 511 | |
| 512 | X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
| 513 | : Mir2Lir(cu, mir_graph, arena) { |
| 514 | for (int i = 0; i < kX86Last; i++) { |
| 515 | if (X86Mir2Lir::EncodingMap[i].opcode != i) { |
| 516 | LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name |
| 517 | << " is wrong: expecting " << i << ", seeing " |
| 518 | << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); |
| 519 | } |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 524 | ArenaAllocator* const arena) { |
| 525 | return new X86Mir2Lir(cu, mir_graph, arena); |
| 526 | } |
| 527 | |
| 528 | // Not used in x86 |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 529 | int X86Mir2Lir::LoadHelper(ThreadOffset offset) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 530 | LOG(FATAL) << "Unexpected use of LoadHelper in x86"; |
| 531 | return INVALID_REG; |
| 532 | } |
| 533 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 534 | uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 535 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 536 | return X86Mir2Lir::EncodingMap[opcode].flags; |
| 537 | } |
| 538 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 539 | const char* X86Mir2Lir::GetTargetInstName(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 540 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 541 | return X86Mir2Lir::EncodingMap[opcode].name; |
| 542 | } |
| 543 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 544 | const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 545 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 546 | return X86Mir2Lir::EncodingMap[opcode].fmt; |
| 547 | } |
| 548 | |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 549 | /* |
| 550 | * Return an updated location record with current in-register status. |
| 551 | * If the value lives in live temps, reflect that fact. No code |
| 552 | * is generated. If the live value is part of an older pair, |
| 553 | * clobber both low and high. |
| 554 | */ |
| 555 | // TODO: Reunify with common code after 'pair mess' has been fixed |
| 556 | RegLocation X86Mir2Lir::UpdateLocWide(RegLocation loc) { |
| 557 | DCHECK(loc.wide); |
| 558 | DCHECK(CheckCorePoolSanity()); |
| 559 | if (loc.location != kLocPhysReg) { |
| 560 | DCHECK((loc.location == kLocDalvikFrame) || |
| 561 | (loc.location == kLocCompilerTemp)); |
| 562 | // Are the dalvik regs already live in physical registers? |
| 563 | RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); |
| 564 | |
| 565 | // Handle FP registers specially on x86. |
| 566 | if (info_lo && IsFpReg(info_lo->reg)) { |
| 567 | bool match = true; |
| 568 | |
| 569 | // We can't match a FP register with a pair of Core registers. |
| 570 | match = match && (info_lo->pair == 0); |
| 571 | |
| 572 | if (match) { |
| 573 | // We can reuse;update the register usage info. |
| 574 | loc.low_reg = info_lo->reg; |
| 575 | loc.high_reg = info_lo->reg; // Play nice with existing code. |
| 576 | loc.location = kLocPhysReg; |
| 577 | loc.vec_len = kVectorLength8; |
| 578 | DCHECK(IsFpReg(loc.low_reg)); |
| 579 | return loc; |
| 580 | } |
| 581 | // We can't easily reuse; clobber and free any overlaps. |
| 582 | if (info_lo) { |
| 583 | Clobber(info_lo->reg); |
| 584 | FreeTemp(info_lo->reg); |
| 585 | if (info_lo->pair) |
| 586 | Clobber(info_lo->partner); |
| 587 | } |
| 588 | } else { |
| 589 | RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); |
| 590 | bool match = true; |
| 591 | match = match && (info_lo != NULL); |
| 592 | match = match && (info_hi != NULL); |
| 593 | // Are they both core or both FP? |
| 594 | match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); |
| 595 | // If a pair of floating point singles, are they properly aligned? |
| 596 | if (match && IsFpReg(info_lo->reg)) { |
| 597 | match &= ((info_lo->reg & 0x1) == 0); |
| 598 | match &= ((info_hi->reg - info_lo->reg) == 1); |
| 599 | } |
| 600 | // If previously used as a pair, it is the same pair? |
| 601 | if (match && (info_lo->pair || info_hi->pair)) { |
| 602 | match = (info_lo->pair == info_hi->pair); |
| 603 | match &= ((info_lo->reg == info_hi->partner) && |
| 604 | (info_hi->reg == info_lo->partner)); |
| 605 | } |
| 606 | if (match) { |
| 607 | // Can reuse - update the register usage info |
| 608 | loc.low_reg = info_lo->reg; |
| 609 | loc.high_reg = info_hi->reg; |
| 610 | loc.location = kLocPhysReg; |
| 611 | MarkPair(loc.low_reg, loc.high_reg); |
| 612 | DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); |
| 613 | return loc; |
| 614 | } |
| 615 | // Can't easily reuse - clobber and free any overlaps |
| 616 | if (info_lo) { |
| 617 | Clobber(info_lo->reg); |
| 618 | FreeTemp(info_lo->reg); |
| 619 | if (info_lo->pair) |
| 620 | Clobber(info_lo->partner); |
| 621 | } |
| 622 | if (info_hi) { |
| 623 | Clobber(info_hi->reg); |
| 624 | FreeTemp(info_hi->reg); |
| 625 | if (info_hi->pair) |
| 626 | Clobber(info_hi->partner); |
| 627 | } |
| 628 | } |
| 629 | } |
| 630 | return loc; |
| 631 | } |
| 632 | |
| 633 | // TODO: Reunify with common code after 'pair mess' has been fixed |
| 634 | RegLocation X86Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) { |
| 635 | DCHECK(loc.wide); |
| 636 | int32_t new_regs; |
| 637 | int32_t low_reg; |
| 638 | int32_t high_reg; |
| 639 | |
| 640 | loc = UpdateLocWide(loc); |
| 641 | |
| 642 | /* If it is already in a register, we can assume proper form. Is it the right reg class? */ |
| 643 | if (loc.location == kLocPhysReg) { |
| 644 | DCHECK_EQ(IsFpReg(loc.low_reg), loc.IsVectorScalar()); |
| 645 | if (!RegClassMatches(reg_class, loc.low_reg)) { |
| 646 | /* It is the wrong register class. Reallocate and copy. */ |
| 647 | if (!IsFpReg(loc.low_reg)) { |
| 648 | // We want this in a FP reg, and it is in core registers. |
| 649 | DCHECK(reg_class != kCoreReg); |
| 650 | // Allocate this into any FP reg, and mark it with the right size. |
| 651 | low_reg = AllocTypedTemp(true, reg_class); |
| 652 | OpVectorRegCopyWide(low_reg, loc.low_reg, loc.high_reg); |
| 653 | CopyRegInfo(low_reg, loc.low_reg); |
| 654 | Clobber(loc.low_reg); |
| 655 | Clobber(loc.high_reg); |
| 656 | loc.low_reg = low_reg; |
| 657 | loc.high_reg = low_reg; // Play nice with existing code. |
| 658 | loc.vec_len = kVectorLength8; |
| 659 | } else { |
| 660 | // The value is in a FP register, and we want it in a pair of core registers. |
| 661 | DCHECK_EQ(reg_class, kCoreReg); |
| 662 | DCHECK_EQ(loc.low_reg, loc.high_reg); |
| 663 | new_regs = AllocTypedTempPair(false, kCoreReg); // Force to core registers. |
| 664 | low_reg = new_regs & 0xff; |
| 665 | high_reg = (new_regs >> 8) & 0xff; |
| 666 | DCHECK_NE(low_reg, high_reg); |
| 667 | OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg); |
| 668 | CopyRegInfo(low_reg, loc.low_reg); |
| 669 | CopyRegInfo(high_reg, loc.high_reg); |
| 670 | Clobber(loc.low_reg); |
| 671 | Clobber(loc.high_reg); |
| 672 | loc.low_reg = low_reg; |
| 673 | loc.high_reg = high_reg; |
| 674 | MarkPair(loc.low_reg, loc.high_reg); |
| 675 | DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); |
| 676 | } |
| 677 | } |
| 678 | return loc; |
| 679 | } |
| 680 | |
| 681 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 682 | if (IsFpReg(loc.low_reg) && reg_class != kCoreReg) { |
| 683 | // Need a wide vector register. |
| 684 | low_reg = AllocTypedTemp(true, reg_class); |
| 685 | loc.low_reg = low_reg; |
| 686 | loc.high_reg = low_reg; // Play nice with existing code. |
| 687 | loc.vec_len = kVectorLength8; |
| 688 | if (update) { |
| 689 | loc.location = kLocPhysReg; |
| 690 | MarkLive(loc.low_reg, loc.s_reg_low); |
| 691 | } |
| 692 | DCHECK(IsFpReg(loc.low_reg)); |
| 693 | } else { |
| 694 | DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); |
| 695 | |
| 696 | new_regs = AllocTypedTempPair(loc.fp, reg_class); |
| 697 | loc.low_reg = new_regs & 0xff; |
| 698 | loc.high_reg = (new_regs >> 8) & 0xff; |
| 699 | |
| 700 | MarkPair(loc.low_reg, loc.high_reg); |
| 701 | if (update) { |
| 702 | loc.location = kLocPhysReg; |
| 703 | MarkLive(loc.low_reg, loc.s_reg_low); |
| 704 | MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low)); |
| 705 | } |
| 706 | DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); |
| 707 | } |
| 708 | return loc; |
| 709 | } |
| 710 | |
| 711 | // TODO: Reunify with common code after 'pair mess' has been fixed |
| 712 | RegLocation X86Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) { |
| 713 | int new_reg; |
| 714 | |
| 715 | if (loc.wide) |
| 716 | return EvalLocWide(loc, reg_class, update); |
| 717 | |
| 718 | loc = UpdateLoc(loc); |
| 719 | |
| 720 | if (loc.location == kLocPhysReg) { |
| 721 | if (!RegClassMatches(reg_class, loc.low_reg)) { |
| 722 | /* Wrong register class. Realloc, copy and transfer ownership. */ |
| 723 | new_reg = AllocTypedTemp(loc.fp, reg_class); |
| 724 | OpRegCopy(new_reg, loc.low_reg); |
| 725 | CopyRegInfo(new_reg, loc.low_reg); |
| 726 | Clobber(loc.low_reg); |
| 727 | loc.low_reg = new_reg; |
| 728 | if (IsFpReg(loc.low_reg) && reg_class != kCoreReg) |
| 729 | loc.vec_len = kVectorLength4; |
| 730 | } |
| 731 | return loc; |
| 732 | } |
| 733 | |
| 734 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 735 | |
| 736 | new_reg = AllocTypedTemp(loc.fp, reg_class); |
| 737 | loc.low_reg = new_reg; |
| 738 | if (IsFpReg(loc.low_reg) && reg_class != kCoreReg) |
| 739 | loc.vec_len = kVectorLength4; |
| 740 | |
| 741 | if (update) { |
| 742 | loc.location = kLocPhysReg; |
| 743 | MarkLive(loc.low_reg, loc.s_reg_low); |
| 744 | } |
| 745 | return loc; |
| 746 | } |
| 747 | |
| 748 | int X86Mir2Lir::AllocTempDouble() { |
| 749 | // We really don't need a pair of registers. |
| 750 | return AllocTempFloat(); |
| 751 | } |
| 752 | |
| 753 | // TODO: Reunify with common code after 'pair mess' has been fixed |
| 754 | void X86Mir2Lir::ResetDefLocWide(RegLocation rl) { |
| 755 | DCHECK(rl.wide); |
| 756 | RegisterInfo* p_low = IsTemp(rl.low_reg); |
| 757 | if (IsFpReg(rl.low_reg)) { |
| 758 | // We are using only the low register. |
| 759 | if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 760 | NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); |
| 761 | } |
| 762 | ResetDef(rl.low_reg); |
| 763 | } else { |
| 764 | RegisterInfo* p_high = IsTemp(rl.high_reg); |
| 765 | if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 766 | DCHECK(p_low->pair); |
| 767 | NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); |
| 768 | } |
| 769 | if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
| 770 | DCHECK(p_high->pair); |
| 771 | } |
| 772 | ResetDef(rl.low_reg); |
| 773 | ResetDef(rl.high_reg); |
| 774 | } |
| 775 | } |
| 776 | |
| 777 | void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { |
| 778 | // Can we do this directly to memory? |
| 779 | rl_dest = UpdateLocWide(rl_dest); |
| 780 | if ((rl_dest.location == kLocDalvikFrame) || |
| 781 | (rl_dest.location == kLocCompilerTemp)) { |
| 782 | int32_t val_lo = Low32Bits(value); |
| 783 | int32_t val_hi = High32Bits(value); |
| 784 | int rBase = TargetReg(kSp); |
| 785 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 786 | |
| 787 | LIR * store = NewLIR3(kX86Mov32MI, rBase, displacement + LOWORD_OFFSET, val_lo); |
| 788 | AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, |
| 789 | false /* is_load */, true /* is64bit */); |
| 790 | store = NewLIR3(kX86Mov32MI, rBase, displacement + HIWORD_OFFSET, val_hi); |
| 791 | AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, |
| 792 | false /* is_load */, true /* is64bit */); |
| 793 | return; |
| 794 | } |
| 795 | |
| 796 | // Just use the standard code to do the generation. |
| 797 | Mir2Lir::GenConstWide(rl_dest, value); |
| 798 | } |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 799 | } // namespace art |