| buzbee | 1452bee | 2015-03-06 14:43:04 -0800 | [diff] [blame^] | 1 | %default {"preinstr":"", "result":"r0", "chkzero":"0"} |
| 2 | /* |
| 3 | * Generic 32-bit binary operation. Provide an "instr" line that |
| 4 | * specifies an instruction that performs "result = r0 op r1". |
| 5 | * This could be an ARM instruction or a function call. (If the result |
| 6 | * comes back in a register other than r0, you can override "result".) |
| 7 | * |
| 8 | * If "chkzero" is set to 1, we perform a divide-by-zero check on |
| 9 | * vCC (r1). Useful for integer division and modulus. Note that we |
| 10 | * *don't* check for (INT_MIN / -1) here, because the ARM math lib |
| 11 | * handles it correctly. |
| 12 | * |
| 13 | * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, |
| 14 | * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, |
| 15 | * mul-float, div-float, rem-float |
| 16 | */ |
| 17 | /* binop vAA, vBB, vCC */ |
| 18 | FETCH r0, 1 @ r0<- CCBB |
| 19 | mov r9, rINST, lsr #8 @ r9<- AA |
| 20 | mov r3, r0, lsr #8 @ r3<- CC |
| 21 | and r2, r0, #255 @ r2<- BB |
| 22 | GET_VREG r1, r3 @ r1<- vCC |
| 23 | GET_VREG r0, r2 @ r0<- vBB |
| 24 | .if $chkzero |
| 25 | cmp r1, #0 @ is second operand zero? |
| 26 | beq common_errDivideByZero |
| 27 | .endif |
| 28 | |
| 29 | FETCH_ADVANCE_INST 2 @ advance rPC, load rINST |
| 30 | $preinstr @ optional op; may set condition codes |
| 31 | $instr @ $result<- op, r0-r3 changed |
| 32 | GET_INST_OPCODE ip @ extract opcode from rINST |
| 33 | SET_VREG $result, r9 @ vAA<- $result |
| 34 | GOTO_OPCODE ip @ jump to next instruction |
| 35 | /* 11-14 instructions */ |