Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the X86 ISA */ |
| 18 | |
| 19 | #include "codegen_x86.h" |
| 20 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 21 | #include "dex/reg_storage_eq.h" |
Mingyao Yang | 98d1cc8 | 2014-05-15 17:02:16 -0700 | [diff] [blame] | 22 | #include "mirror/art_method.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 23 | #include "mirror/array.h" |
| 24 | #include "x86_lir.h" |
| 25 | |
| 26 | namespace art { |
| 27 | |
| 28 | /* |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | * Compare two 64-bit values |
| 30 | * x = y return 0 |
| 31 | * x < y return -1 |
| 32 | * x > y return 1 |
| 33 | */ |
| 34 | void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 35 | RegLocation rl_src2) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 36 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 37 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 38 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 39 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 40 | RegStorage temp_reg = AllocTemp(); |
Serguei Katkov | 1c55703 | 2014-06-23 13:23:38 +0700 | [diff] [blame] | 41 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 42 | NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0 |
| 43 | NewLIR2(kX86Set8R, temp_reg.GetReg(), kX86CondL); // temp = (src1 >= src2) ? 0 : 1 |
| 44 | NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg()); |
| 45 | NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
Serguei Katkov | 0498223 | 2014-06-20 18:17:16 +0700 | [diff] [blame] | 46 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 47 | StoreValue(rl_dest, rl_result); |
| 48 | FreeTemp(temp_reg); |
| 49 | return; |
| 50 | } |
| 51 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 52 | FlushAllRegs(); |
| 53 | LockCallTemps(); // Prepare for explicit register usage |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 54 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 55 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 56 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 57 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 58 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 59 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 60 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 61 | NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 |
| 62 | NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 63 | OpReg(kOpNeg, rs_r2); // r2 = -r2 |
| 64 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 65 | NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | NewLIR2(kX86Movzx8RR, r0, r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 67 | OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 68 | RegLocation rl_result = LocCReturn(); |
| 69 | StoreValue(rl_dest, rl_result); |
| 70 | } |
| 71 | |
| 72 | X86ConditionCode X86ConditionEncoding(ConditionCode cond) { |
| 73 | switch (cond) { |
| 74 | case kCondEq: return kX86CondEq; |
| 75 | case kCondNe: return kX86CondNe; |
| 76 | case kCondCs: return kX86CondC; |
| 77 | case kCondCc: return kX86CondNc; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 78 | case kCondUlt: return kX86CondC; |
| 79 | case kCondUge: return kX86CondNc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 80 | case kCondMi: return kX86CondS; |
| 81 | case kCondPl: return kX86CondNs; |
| 82 | case kCondVs: return kX86CondO; |
| 83 | case kCondVc: return kX86CondNo; |
| 84 | case kCondHi: return kX86CondA; |
| 85 | case kCondLs: return kX86CondBe; |
| 86 | case kCondGe: return kX86CondGe; |
| 87 | case kCondLt: return kX86CondL; |
| 88 | case kCondGt: return kX86CondG; |
| 89 | case kCondLe: return kX86CondLe; |
| 90 | case kCondAl: |
| 91 | case kCondNv: LOG(FATAL) << "Should not reach here"; |
| 92 | } |
| 93 | return kX86CondO; |
| 94 | } |
| 95 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 96 | LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 97 | NewLIR2(src1.Is64Bit() ? kX86Cmp64RR : kX86Cmp32RR, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 98 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 99 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , |
| 100 | cc); |
| 101 | branch->target = target; |
| 102 | return branch; |
| 103 | } |
| 104 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 105 | LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 106 | int check_value, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { |
| 108 | // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 109 | NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg.GetReg(), reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 111 | if (reg.Is64Bit()) { |
| 112 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp64RI8 : kX86Cmp64RI, reg.GetReg(), check_value); |
| 113 | } else { |
| 114 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); |
| 115 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 116 | } |
| 117 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 118 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); |
| 119 | branch->target = target; |
| 120 | return branch; |
| 121 | } |
| 122 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 123 | LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
| 124 | // If src or dest is a pair, we'll be using low reg. |
| 125 | if (r_dest.IsPair()) { |
| 126 | r_dest = r_dest.GetLow(); |
| 127 | } |
| 128 | if (r_src.IsPair()) { |
| 129 | r_src = r_src.GetLow(); |
| 130 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 131 | if (r_dest.IsFloat() || r_src.IsFloat()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 132 | return OpFpRegCopy(r_dest, r_src); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 133 | LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 134 | r_dest.GetReg(), r_src.GetReg()); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 135 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 136 | res->flags.is_nop = true; |
| 137 | } |
| 138 | return res; |
| 139 | } |
| 140 | |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 141 | void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
| 142 | if (r_dest != r_src) { |
| 143 | LIR *res = OpRegCopyNoInsert(r_dest, r_src); |
| 144 | AppendLIR(res); |
| 145 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 146 | } |
| 147 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 148 | void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 149 | if (r_dest != r_src) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 150 | bool dest_fp = r_dest.IsFloat(); |
| 151 | bool src_fp = r_src.IsFloat(); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 152 | if (dest_fp) { |
| 153 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 154 | OpRegCopy(r_dest, r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 155 | } else { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 156 | // TODO: Prevent this from happening in the code. The result is often |
| 157 | // unused or could have been loaded more easily from memory. |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 158 | if (!r_src.IsPair()) { |
| 159 | DCHECK(!r_dest.IsPair()); |
| 160 | NewLIR2(kX86MovqxrRR, r_dest.GetReg(), r_src.GetReg()); |
| 161 | } else { |
| 162 | NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); |
| 163 | RegStorage r_tmp = AllocTempDouble(); |
| 164 | NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); |
| 165 | NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); |
| 166 | FreeTemp(r_tmp); |
| 167 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 168 | } |
| 169 | } else { |
| 170 | if (src_fp) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 171 | if (!r_dest.IsPair()) { |
| 172 | DCHECK(!r_src.IsPair()); |
| 173 | NewLIR2(kX86MovqrxRR, r_dest.GetReg(), r_src.GetReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 174 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 175 | NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); |
| 176 | RegStorage temp_reg = AllocTempDouble(); |
| 177 | NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); |
| 178 | NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); |
| 179 | NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); |
| 180 | } |
| 181 | } else { |
| 182 | DCHECK_EQ(r_dest.IsPair(), r_src.IsPair()); |
| 183 | if (!r_src.IsPair()) { |
| 184 | // Just copy the register directly. |
| 185 | OpRegCopy(r_dest, r_src); |
| 186 | } else { |
| 187 | // Handle overlap |
| 188 | if (r_src.GetHighReg() == r_dest.GetLowReg() && |
| 189 | r_src.GetLowReg() == r_dest.GetHighReg()) { |
| 190 | // Deal with cycles. |
| 191 | RegStorage temp_reg = AllocTemp(); |
| 192 | OpRegCopy(temp_reg, r_dest.GetHigh()); |
| 193 | OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); |
| 194 | OpRegCopy(r_dest.GetLow(), temp_reg); |
| 195 | FreeTemp(temp_reg); |
| 196 | } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 197 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 198 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 199 | } else { |
| 200 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 201 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 202 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 203 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 204 | } |
| 205 | } |
| 206 | } |
| 207 | } |
| 208 | |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 209 | void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 210 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 211 | int dest_reg_class) { |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 212 | DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); |
| 213 | DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); |
| 214 | |
| 215 | // We really need this check for correctness, otherwise we will need to do more checks in |
| 216 | // non zero/one case |
| 217 | if (true_val == false_val) { |
| 218 | LoadConstantNoClobber(rs_dest, true_val); |
| 219 | return; |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 220 | } |
| 221 | |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 222 | const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); |
| 223 | |
| 224 | const bool zero_one_case = (true_val == 0 && false_val == 1) || (true_val == 1 && false_val == 0); |
| 225 | if (zero_one_case && IsByteRegister(rs_dest)) { |
| 226 | if (!dest_intersect) { |
| 227 | LoadConstantNoClobber(rs_dest, 0); |
| 228 | } |
| 229 | OpRegReg(kOpCmp, left_op, right_op); |
| 230 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
| 231 | NewLIR2(kX86Set8R, rs_dest.GetReg(), |
| 232 | X86ConditionEncoding(true_val == 1 ? code : FlipComparisonOrder(code))); |
| 233 | if (dest_intersect) { |
| 234 | NewLIR2(rs_dest.Is64Bit() ? kX86Movzx8qRR : kX86Movzx8RR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 235 | } |
| 236 | } else { |
| 237 | // Be careful rs_dest can be changed only after cmp because it can be the same as one of ops |
| 238 | // and it cannot use xor because it makes cc flags to be dirty |
| 239 | RegStorage temp_reg = AllocTypedTemp(false, dest_reg_class, false); |
| 240 | if (temp_reg.Valid()) { |
| 241 | if (false_val == 0 && dest_intersect) { |
| 242 | code = FlipComparisonOrder(code); |
| 243 | std::swap(true_val, false_val); |
| 244 | } |
| 245 | if (!dest_intersect) { |
| 246 | LoadConstantNoClobber(rs_dest, false_val); |
| 247 | } |
| 248 | LoadConstantNoClobber(temp_reg, true_val); |
| 249 | OpRegReg(kOpCmp, left_op, right_op); |
| 250 | if (dest_intersect) { |
| 251 | LoadConstantNoClobber(rs_dest, false_val); |
| 252 | DCHECK(!last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
| 253 | } |
| 254 | OpCondRegReg(kOpCmov, code, rs_dest, temp_reg); |
| 255 | FreeTemp(temp_reg); |
| 256 | } else { |
| 257 | // slow path |
| 258 | LIR* cmp_branch = OpCmpBranch(code, left_op, right_op, nullptr); |
| 259 | LoadConstantNoClobber(rs_dest, false_val); |
| 260 | LIR* that_is_it = NewLIR1(kX86Jmp8, 0); |
| 261 | LIR* true_case = NewLIR0(kPseudoTargetLabel); |
| 262 | cmp_branch->target = true_case; |
| 263 | LoadConstantNoClobber(rs_dest, true_val); |
| 264 | LIR* end = NewLIR0(kPseudoTargetLabel); |
| 265 | that_is_it->target = end; |
| 266 | } |
| 267 | } |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 268 | } |
| 269 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 270 | void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 271 | RegLocation rl_result; |
| 272 | RegLocation rl_src = mir_graph_->GetSrc(mir, 0); |
| 273 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 274 | // Avoid using float regs here. |
| 275 | RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; |
| 276 | RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; |
| 277 | rl_src = LoadValue(rl_src, src_reg_class); |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 278 | ConditionCode ccode = mir->meta.ccode; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 279 | |
| 280 | // The kMirOpSelect has two variants, one for constants and one for moves. |
| 281 | const bool is_constant_case = (mir->ssa_rep->num_uses == 1); |
| 282 | |
| 283 | if (is_constant_case) { |
| 284 | int true_val = mir->dalvikInsn.vB; |
| 285 | int false_val = mir->dalvikInsn.vC; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 286 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 287 | |
| 288 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 289 | * For ccode == kCondEq: |
| 290 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 291 | * 1) When the true case is zero and result_reg is not same as src_reg: |
| 292 | * xor result_reg, result_reg |
| 293 | * cmp $0, src_reg |
| 294 | * mov t1, $false_case |
| 295 | * cmovnz result_reg, t1 |
| 296 | * 2) When the false case is zero and result_reg is not same as src_reg: |
| 297 | * xor result_reg, result_reg |
| 298 | * cmp $0, src_reg |
| 299 | * mov t1, $true_case |
| 300 | * cmovz result_reg, t1 |
| 301 | * 3) All other cases (we do compare first to set eflags): |
| 302 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 303 | * mov result_reg, $false_case |
| 304 | * mov t1, $true_case |
| 305 | * cmovz result_reg, t1 |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 306 | */ |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 307 | // FIXME: depending on how you use registers you could get a false != mismatch when dealing |
| 308 | // with different views of the same underlying physical resource (i.e. solo32 vs. solo64). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 309 | const bool result_reg_same_as_src = |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 310 | (rl_src.location == kLocPhysReg && rl_src.reg.GetRegNum() == rl_result.reg.GetRegNum()); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 311 | const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); |
| 312 | const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); |
| 313 | const bool catch_all_case = !(true_zero_case || false_zero_case); |
| 314 | |
| 315 | if (true_zero_case || false_zero_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 316 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | if (true_zero_case || false_zero_case || catch_all_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 320 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | if (catch_all_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 324 | OpRegImm(kOpMov, rl_result.reg, false_val); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | if (true_zero_case || false_zero_case || catch_all_case) { |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 328 | ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; |
| 329 | int immediateForTemp = true_zero_case ? false_val : true_val; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 330 | RegStorage temp1_reg = AllocTypedTemp(false, result_reg_class); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 331 | OpRegImm(kOpMov, temp1_reg, immediateForTemp); |
| 332 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 333 | OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 334 | |
| 335 | FreeTemp(temp1_reg); |
| 336 | } |
| 337 | } else { |
| 338 | RegLocation rl_true = mir_graph_->GetSrc(mir, 1); |
| 339 | RegLocation rl_false = mir_graph_->GetSrc(mir, 2); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 340 | rl_true = LoadValue(rl_true, result_reg_class); |
| 341 | rl_false = LoadValue(rl_false, result_reg_class); |
| 342 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 343 | |
| 344 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 345 | * For ccode == kCondEq: |
| 346 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 347 | * 1) When true case is already in place: |
| 348 | * cmp $0, src_reg |
| 349 | * cmovnz result_reg, false_reg |
| 350 | * 2) When false case is already in place: |
| 351 | * cmp $0, src_reg |
| 352 | * cmovz result_reg, true_reg |
| 353 | * 3) When neither cases are in place: |
| 354 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 355 | * mov result_reg, false_reg |
| 356 | * cmovz result_reg, true_reg |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 357 | */ |
| 358 | |
| 359 | // kMirOpSelect is generated just for conditional cases when comparison is done with zero. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 360 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 361 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 362 | if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 363 | OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 364 | } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 365 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 366 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 367 | OpRegCopy(rl_result.reg, rl_false.reg); |
| 368 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 369 | } |
| 370 | } |
| 371 | |
| 372 | StoreValue(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 376 | LIR* taken = &block_label_list_[bb->taken]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 377 | RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 378 | RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
Vladimir Marko | a894607 | 2014-01-22 10:30:44 +0000 | [diff] [blame] | 379 | ConditionCode ccode = mir->meta.ccode; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 380 | |
| 381 | if (rl_src1.is_const) { |
| 382 | std::swap(rl_src1, rl_src2); |
| 383 | ccode = FlipComparisonOrder(ccode); |
| 384 | } |
| 385 | if (rl_src2.is_const) { |
| 386 | // Do special compare/branch against simple const operand |
| 387 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 388 | GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); |
| 389 | return; |
| 390 | } |
| 391 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 392 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 393 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 394 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 395 | |
| 396 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 397 | OpCondBranch(ccode, taken); |
| 398 | return; |
| 399 | } |
| 400 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 401 | FlushAllRegs(); |
| 402 | LockCallTemps(); // Prepare for explicit register usage |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 403 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 404 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 405 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 406 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 407 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 408 | // Swap operands and condition code to prevent use of zero flag. |
| 409 | if (ccode == kCondLe || ccode == kCondGt) { |
| 410 | // Compute (r3:r2) = (r3:r2) - (r1:r0) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 411 | OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 |
| 412 | OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 413 | } else { |
| 414 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 415 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 416 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 417 | } |
| 418 | switch (ccode) { |
| 419 | case kCondEq: |
| 420 | case kCondNe: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 421 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 422 | break; |
| 423 | case kCondLe: |
| 424 | ccode = kCondGe; |
| 425 | break; |
| 426 | case kCondGt: |
| 427 | ccode = kCondLt; |
| 428 | break; |
| 429 | case kCondLt: |
| 430 | case kCondGe: |
| 431 | break; |
| 432 | default: |
| 433 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 434 | } |
| 435 | OpCondBranch(ccode, taken); |
| 436 | } |
| 437 | |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 438 | void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 439 | int64_t val, ConditionCode ccode) { |
| 440 | int32_t val_lo = Low32Bits(val); |
| 441 | int32_t val_hi = High32Bits(val); |
| 442 | LIR* taken = &block_label_list_[bb->taken]; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 443 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 444 | bool is_equality_test = ccode == kCondEq || ccode == kCondNe; |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 445 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 446 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 447 | if (is_equality_test && val == 0) { |
| 448 | // We can simplify of comparing for ==, != to 0. |
| 449 | NewLIR2(kX86Test64RR, rl_src1.reg.GetReg(), rl_src1.reg.GetReg()); |
| 450 | } else if (is_equality_test && val_hi == 0 && val_lo > 0) { |
| 451 | OpRegImm(kOpCmp, rl_src1.reg, val_lo); |
| 452 | } else { |
| 453 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 454 | LoadConstantWide(tmp, val); |
| 455 | OpRegReg(kOpCmp, rl_src1.reg, tmp); |
| 456 | FreeTemp(tmp); |
| 457 | } |
| 458 | OpCondBranch(ccode, taken); |
| 459 | return; |
| 460 | } |
| 461 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 462 | if (is_equality_test && val != 0) { |
| 463 | rl_src1 = ForceTempWide(rl_src1); |
| 464 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 465 | RegStorage low_reg = rl_src1.reg.GetLow(); |
| 466 | RegStorage high_reg = rl_src1.reg.GetHigh(); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 467 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 468 | if (is_equality_test) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 469 | // We can simplify of comparing for ==, != to 0. |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 470 | if (val == 0) { |
| 471 | if (IsTemp(low_reg)) { |
| 472 | OpRegReg(kOpOr, low_reg, high_reg); |
| 473 | // We have now changed it; ignore the old values. |
| 474 | Clobber(rl_src1.reg); |
| 475 | } else { |
| 476 | RegStorage t_reg = AllocTemp(); |
| 477 | OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); |
| 478 | FreeTemp(t_reg); |
| 479 | } |
| 480 | OpCondBranch(ccode, taken); |
| 481 | return; |
| 482 | } |
| 483 | |
| 484 | // Need to compute the actual value for ==, !=. |
| 485 | OpRegImm(kOpSub, low_reg, val_lo); |
| 486 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 487 | OpRegReg(kOpOr, high_reg, low_reg); |
| 488 | Clobber(rl_src1.reg); |
| 489 | } else if (ccode == kCondLe || ccode == kCondGt) { |
| 490 | // Swap operands and condition code to prevent use of zero flag. |
| 491 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 492 | LoadConstantWide(tmp, val); |
| 493 | OpRegReg(kOpSub, tmp.GetLow(), low_reg); |
| 494 | OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); |
| 495 | ccode = (ccode == kCondLe) ? kCondGe : kCondLt; |
| 496 | FreeTemp(tmp); |
| 497 | } else { |
| 498 | // We can use a compare for the low word to set CF. |
| 499 | OpRegImm(kOpCmp, low_reg, val_lo); |
| 500 | if (IsTemp(high_reg)) { |
| 501 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 502 | // We have now changed it; ignore the old values. |
| 503 | Clobber(rl_src1.reg); |
| 504 | } else { |
| 505 | // mov temp_reg, high_reg; sbb temp_reg, high_constant |
| 506 | RegStorage t_reg = AllocTemp(); |
| 507 | OpRegCopy(t_reg, high_reg); |
| 508 | NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); |
| 509 | FreeTemp(t_reg); |
| 510 | } |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 511 | } |
| 512 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 513 | OpCondBranch(ccode, taken); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 514 | } |
| 515 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 516 | void X86Mir2Lir::CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 517 | // It does not make sense to calculate magic and shift for zero divisor. |
| 518 | DCHECK_NE(divisor, 0); |
| 519 | |
| 520 | /* According to H.S.Warren's Hacker's Delight Chapter 10 and |
| 521 | * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 522 | * The magic number M and shift S can be calculated in the following way: |
| 523 | * Let nc be the most positive value of numerator(n) such that nc = kd - 1, |
| 524 | * where divisor(d) >=2. |
| 525 | * Let nc be the most negative value of numerator(n) such that nc = kd + 1, |
| 526 | * where divisor(d) <= -2. |
| 527 | * Thus nc can be calculated like: |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 528 | * nc = exp + exp % d - 1, where d >= 2 and exp = 2^31 for int or 2^63 for long |
| 529 | * nc = -exp + (exp + 1) % d, where d >= 2 and exp = 2^31 for int or 2^63 for long |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 530 | * |
| 531 | * So the shift p is the smallest p satisfying |
| 532 | * 2^p > nc * (d - 2^p % d), where d >= 2 |
| 533 | * 2^p > nc * (d + 2^p % d), where d <= -2. |
| 534 | * |
| 535 | * the magic number M is calcuated by |
| 536 | * M = (2^p + d - 2^p % d) / d, where d >= 2 |
| 537 | * M = (2^p - d - 2^p % d) / d, where d <= -2. |
| 538 | * |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 539 | * Notice that p is always bigger than or equal to 32/64, so we just return 32-p/64-p as |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 540 | * the shift number S. |
| 541 | */ |
| 542 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 543 | int64_t p = (is_long) ? 63 : 31; |
| 544 | const uint64_t exp = (is_long) ? 0x8000000000000000ULL : 0x80000000U; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 545 | |
| 546 | // Initialize the computations. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 547 | uint64_t abs_d = (divisor >= 0) ? divisor : -divisor; |
| 548 | uint64_t tmp = exp + ((is_long) ? static_cast<uint64_t>(divisor) >> 63 : |
| 549 | static_cast<uint32_t>(divisor) >> 31); |
| 550 | uint64_t abs_nc = tmp - 1 - tmp % abs_d; |
| 551 | uint64_t quotient1 = exp / abs_nc; |
| 552 | uint64_t remainder1 = exp % abs_nc; |
| 553 | uint64_t quotient2 = exp / abs_d; |
| 554 | uint64_t remainder2 = exp % abs_d; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 555 | |
| 556 | /* |
| 557 | * To avoid handling both positive and negative divisor, Hacker's Delight |
| 558 | * introduces a method to handle these 2 cases together to avoid duplication. |
| 559 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 560 | uint64_t delta; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 561 | do { |
| 562 | p++; |
| 563 | quotient1 = 2 * quotient1; |
| 564 | remainder1 = 2 * remainder1; |
| 565 | if (remainder1 >= abs_nc) { |
| 566 | quotient1++; |
| 567 | remainder1 = remainder1 - abs_nc; |
| 568 | } |
| 569 | quotient2 = 2 * quotient2; |
| 570 | remainder2 = 2 * remainder2; |
| 571 | if (remainder2 >= abs_d) { |
| 572 | quotient2++; |
| 573 | remainder2 = remainder2 - abs_d; |
| 574 | } |
| 575 | delta = abs_d - remainder2; |
| 576 | } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); |
| 577 | |
| 578 | magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 579 | |
| 580 | if (!is_long) { |
| 581 | magic = static_cast<int>(magic); |
| 582 | } |
| 583 | |
| 584 | shift = (is_long) ? p - 64 : p - 32; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 585 | } |
| 586 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 587 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 588 | LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; |
| 589 | return rl_dest; |
| 590 | } |
| 591 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 592 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, |
| 593 | int imm, bool is_div) { |
| 594 | // Use a multiply (and fixup) to perform an int div/rem by a constant. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 595 | RegLocation rl_result; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 596 | |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 597 | if (imm == 1) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 598 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 599 | if (is_div) { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 600 | // x / 1 == x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 601 | LoadValueDirectFixed(rl_src, rl_result.reg); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 602 | } else { |
| 603 | // x % 1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 604 | LoadConstantNoClobber(rl_result.reg, 0); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 605 | } |
| 606 | } else if (imm == -1) { // handle 0x80000000 / -1 special case. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 607 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 608 | if (is_div) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 609 | LoadValueDirectFixed(rl_src, rl_result.reg); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 610 | |
| 611 | // Check if numerator is 0 |
| 612 | OpRegImm(kOpCmp, rl_result.reg, 0); |
| 613 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 614 | |
| 615 | // handle 0x80000000 / -1 |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 616 | OpRegImm(kOpCmp, rl_result.reg, 0x80000000); |
| 617 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 618 | |
| 619 | // for x != MIN_INT, x / -1 == -x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 620 | NewLIR1(kX86Neg32R, rl_result.reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 621 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 622 | // EAX already contains the right value (0x80000000), |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 623 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 624 | branch->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 625 | } else { |
| 626 | // x % -1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 627 | LoadConstantNoClobber(rl_result.reg, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 628 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 629 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 630 | // Division using shifting. |
| 631 | rl_src = LoadValue(rl_src, kCoreReg); |
| 632 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 633 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 634 | RegStorage rs_temp = AllocTypedTemp(false, kCoreReg); |
| 635 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 636 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 637 | |
| 638 | // Check if numerator is 0 |
| 639 | OpRegImm(kOpCmp, rl_src.reg, 0); |
| 640 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 641 | LoadConstantNoClobber(rl_result.reg, 0); |
| 642 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 643 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 644 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 645 | NewLIR3(kX86Lea32RM, rl_result.reg.GetReg(), rl_src.reg.GetReg(), std::abs(imm) - 1); |
| 646 | NewLIR2(kX86Test32RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 647 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
| 648 | int shift_amount = LowestSetBit(imm); |
| 649 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 650 | if (imm < 0) { |
| 651 | OpReg(kOpNeg, rl_result.reg); |
| 652 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 653 | done->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 654 | } else { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 655 | CHECK(imm <= -2 || imm >= 2); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 656 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 657 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 658 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 659 | int64_t magic; |
| 660 | int shift; |
| 661 | CalculateMagicAndShift((int64_t)imm, magic, shift, false /* is_long */); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 662 | |
| 663 | /* |
| 664 | * For imm >= 2, |
| 665 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 666 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 667 | * For imm <= -2, |
| 668 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 669 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 670 | * We implement this algorithm in the following way: |
| 671 | * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX |
| 672 | * 2. if imm > 0 and magic < 0, add numerator to EDX |
| 673 | * if imm < 0 and magic > 0, sub numerator from EDX |
| 674 | * 3. if S !=0, SAR S bits for EDX |
| 675 | * 4. add 1 to EDX if EDX < 0 |
| 676 | * 5. Thus, EDX is the quotient |
| 677 | */ |
| 678 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 679 | FlushReg(rs_r0); |
| 680 | Clobber(rs_r0); |
| 681 | LockTemp(rs_r0); |
| 682 | FlushReg(rs_r2); |
| 683 | Clobber(rs_r2); |
| 684 | LockTemp(rs_r2); |
| 685 | |
| 686 | // Assume that the result will be in EDX. |
| 687 | rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r2, INVALID_SREG, INVALID_SREG}; |
| 688 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 689 | // Numerator into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 690 | RegStorage numerator_reg; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 691 | if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { |
| 692 | // We will need the value later. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 693 | rl_src = LoadValue(rl_src, kCoreReg); |
| 694 | numerator_reg = rl_src.reg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 695 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 696 | } else { |
| 697 | // Only need this once. Just put it into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 698 | LoadValueDirectFixed(rl_src, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 699 | } |
| 700 | |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 701 | // Check if numerator is 0 |
| 702 | OpRegImm(kOpCmp, rs_r0, 0); |
| 703 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 704 | LoadConstantNoClobber(rs_r2, 0); |
| 705 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 706 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 707 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 708 | // EDX = magic. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 709 | LoadConstantNoClobber(rs_r2, magic); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 710 | |
| 711 | // EDX:EAX = magic & dividend. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 712 | NewLIR1(kX86Imul32DaR, rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 713 | |
| 714 | if (imm > 0 && magic < 0) { |
| 715 | // Add numerator to EDX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 716 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 717 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 718 | } else if (imm < 0 && magic > 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 719 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 720 | NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | // Do we need the shift? |
| 724 | if (shift != 0) { |
| 725 | // Shift EDX by 'shift' bits. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 726 | NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 727 | } |
| 728 | |
| 729 | // Add 1 to EDX if EDX < 0. |
| 730 | |
| 731 | // Move EDX to EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 732 | OpRegCopy(rs_r0, rs_r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 733 | |
| 734 | // Move sign bit to bit 0, zeroing the rest. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 735 | NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 736 | |
| 737 | // EDX = EDX + EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 738 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 739 | |
| 740 | // Quotient is in EDX. |
| 741 | if (!is_div) { |
| 742 | // We need to compute the remainder. |
| 743 | // Remainder is divisor - (quotient * imm). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 744 | DCHECK(numerator_reg.Valid()); |
| 745 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 746 | |
| 747 | // EAX = numerator * imm. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 748 | OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 749 | |
| 750 | // EDX -= EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 751 | NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 752 | |
| 753 | // For this case, return the result in EAX. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 754 | rl_result.reg.SetReg(r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 755 | } |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 756 | done->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 757 | } |
| 758 | |
| 759 | return rl_result; |
| 760 | } |
| 761 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 762 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, |
| 763 | bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 764 | LOG(FATAL) << "Unexpected use of GenDivRem for x86"; |
| 765 | return rl_dest; |
| 766 | } |
| 767 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 768 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
| 769 | RegLocation rl_src2, bool is_div, bool check_zero) { |
| 770 | // We have to use fixed registers, so flush all the temps. |
| 771 | FlushAllRegs(); |
| 772 | LockCallTemps(); // Prepare for explicit register usage. |
| 773 | |
| 774 | // Load LHS into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 775 | LoadValueDirectFixed(rl_src1, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 776 | |
| 777 | // Load RHS into EBX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 778 | LoadValueDirectFixed(rl_src2, rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 779 | |
| 780 | // Copy LHS sign bit into EDX. |
| 781 | NewLIR0(kx86Cdq32Da); |
| 782 | |
| 783 | if (check_zero) { |
| 784 | // Handle division by zero case. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 785 | GenDivZeroCheck(rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 786 | } |
| 787 | |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 788 | // Check if numerator is 0 |
| 789 | OpRegImm(kOpCmp, rs_r0, 0); |
| 790 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 791 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 792 | // Have to catch 0x80000000/-1 case, or we will get an exception! |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 793 | OpRegImm(kOpCmp, rs_r1, -1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 794 | LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 795 | |
| 796 | // RHS is -1. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 797 | OpRegImm(kOpCmp, rs_r0, 0x80000000); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 798 | LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 799 | |
Yixin Shou | 2ddd175 | 2014-08-26 15:15:13 -0400 | [diff] [blame^] | 800 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 801 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 802 | // In 0x80000000/-1 case. |
| 803 | if (!is_div) { |
| 804 | // For DIV, EAX is already right. For REM, we need EDX 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 805 | LoadConstantNoClobber(rs_r2, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 806 | } |
| 807 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 808 | |
| 809 | // Expected case. |
| 810 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 811 | minint_branch->target = minus_one_branch->target; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 812 | NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 813 | done->target = NewLIR0(kPseudoTargetLabel); |
| 814 | |
| 815 | // Result is in EAX for div and EDX for rem. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 816 | RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 817 | if (!is_div) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 818 | rl_result.reg.SetReg(r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 819 | } |
| 820 | return rl_result; |
| 821 | } |
| 822 | |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 823 | bool X86Mir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 824 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 825 | |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 826 | if (is_long && !cu_->target64) { |
| 827 | /* |
| 828 | * We want to implement the following algorithm |
| 829 | * mov eax, low part of arg1 |
| 830 | * mov edx, high part of arg1 |
| 831 | * mov ebx, low part of arg2 |
| 832 | * mov ecx, high part of arg2 |
| 833 | * mov edi, eax |
| 834 | * sub edi, ebx |
| 835 | * mov edi, edx |
| 836 | * sbb edi, ecx |
| 837 | * is_min ? "cmovgel eax, ebx" : "cmovll eax, ebx" |
| 838 | * is_min ? "cmovgel edx, ecx" : "cmovll edx, ecx" |
| 839 | * |
| 840 | * The algorithm above needs 5 registers: a pair for the first operand |
| 841 | * (which later will be used as result), a pair for the second operand |
| 842 | * and a temp register (e.g. 'edi') for intermediate calculations. |
| 843 | * Ideally we have 6 GP caller-save registers in 32-bit mode. They are: |
| 844 | * 'eax', 'ebx', 'ecx', 'edx', 'esi' and 'edi'. So there should be |
| 845 | * always enough registers to operate on. Practically, there is a pair |
| 846 | * of registers 'edi' and 'esi' which holds promoted values and |
| 847 | * sometimes should be treated as 'callee save'. If one of the operands |
| 848 | * is in the promoted registers then we have enough register to |
| 849 | * operate on. Otherwise there is lack of resources and we have to |
| 850 | * save 'edi' before calculations and restore after. |
| 851 | */ |
| 852 | |
| 853 | RegLocation rl_src1 = info->args[0]; |
| 854 | RegLocation rl_src2 = info->args[2]; |
| 855 | RegLocation rl_dest = InlineTargetWide(info); |
| 856 | int res_vreg, src1_vreg, src2_vreg; |
| 857 | |
| 858 | /* |
| 859 | * If the result register is the same as the second element, then we |
| 860 | * need to be careful. The reason is that the first copy will |
| 861 | * inadvertently clobber the second element with the first one thus |
| 862 | * yielding the wrong result. Thus we do a swap in that case. |
| 863 | */ |
| 864 | res_vreg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); |
| 865 | src2_vreg = mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 866 | if (res_vreg == src2_vreg) { |
| 867 | std::swap(rl_src1, rl_src2); |
| 868 | } |
| 869 | |
| 870 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 871 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 872 | |
| 873 | // Pick the first integer as min/max. |
| 874 | OpRegCopyWide(rl_result.reg, rl_src1.reg); |
| 875 | |
| 876 | /* |
| 877 | * If the integers are both in the same register, then there is |
| 878 | * nothing else to do because they are equal and we have already |
| 879 | * moved one into the result. |
| 880 | */ |
| 881 | src1_vreg = mir_graph_->SRegToVReg(rl_src1.s_reg_low); |
| 882 | src2_vreg = mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 883 | if (src1_vreg == src2_vreg) { |
| 884 | StoreValueWide(rl_dest, rl_result); |
| 885 | return true; |
| 886 | } |
| 887 | |
| 888 | // Free registers to make some room for the second operand. |
| 889 | // But don't try to free ourselves or promoted registers. |
| 890 | if (res_vreg != src1_vreg && |
| 891 | IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
| 892 | FreeTemp(rl_src1.reg); |
| 893 | } |
| 894 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 895 | |
| 896 | // Do we have a free register for intermediate calculations? |
| 897 | RegStorage tmp = AllocTemp(false); |
| 898 | if (tmp == RegStorage::InvalidReg()) { |
| 899 | /* |
| 900 | * No, will use 'edi'. |
| 901 | * |
| 902 | * As mentioned above we have 4 temporary and 2 promotable |
| 903 | * caller-save registers. Therefore, we assume that a free |
| 904 | * register can be allocated only if 'esi' and 'edi' are |
| 905 | * already used as operands. If number of promotable registers |
| 906 | * increases from 2 to 4 then our assumption fails and operand |
| 907 | * data is corrupted. |
| 908 | * Let's DCHECK it. |
| 909 | */ |
| 910 | DCHECK(IsTemp(rl_src2.reg.GetLow()) && |
| 911 | IsTemp(rl_src2.reg.GetHigh()) && |
| 912 | IsTemp(rl_result.reg.GetLow()) && |
| 913 | IsTemp(rl_result.reg.GetHigh())); |
| 914 | tmp = rs_rDI; |
| 915 | NewLIR1(kX86Push32R, tmp.GetReg()); |
| 916 | } |
| 917 | |
| 918 | // Now we are ready to do calculations. |
| 919 | OpRegReg(kOpMov, tmp, rl_result.reg.GetLow()); |
| 920 | OpRegReg(kOpSub, tmp, rl_src2.reg.GetLow()); |
| 921 | OpRegReg(kOpMov, tmp, rl_result.reg.GetHigh()); |
| 922 | OpRegReg(kOpSbc, tmp, rl_src2.reg.GetHigh()); |
| 923 | |
| 924 | // Let's put pop 'edi' here to break a bit the dependency chain. |
| 925 | if (tmp == rs_rDI) { |
| 926 | NewLIR1(kX86Pop32R, tmp.GetReg()); |
| 927 | } |
| 928 | |
| 929 | // Conditionally move the other integer into the destination register. |
| 930 | ConditionCode cc = is_min ? kCondGe : kCondLt; |
| 931 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); |
| 932 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); |
| 933 | StoreValueWide(rl_dest, rl_result); |
| 934 | return true; |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 935 | } |
| 936 | |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 937 | // Get the two arguments to the invoke and place them in GP registers. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 938 | RegLocation rl_src1 = info->args[0]; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 939 | RegLocation rl_src2 = (is_long) ? info->args[2] : info->args[1]; |
| 940 | rl_src1 = (is_long) ? LoadValueWide(rl_src1, kCoreReg) : LoadValue(rl_src1, kCoreReg); |
| 941 | rl_src2 = (is_long) ? LoadValueWide(rl_src2, kCoreReg) : LoadValue(rl_src2, kCoreReg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 942 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 943 | RegLocation rl_dest = (is_long) ? InlineTargetWide(info) : InlineTarget(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 944 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 945 | |
| 946 | /* |
| 947 | * If the result register is the same as the second element, then we need to be careful. |
| 948 | * The reason is that the first copy will inadvertently clobber the second element with |
| 949 | * the first one thus yielding the wrong result. Thus we do a swap in that case. |
| 950 | */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 951 | if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 952 | std::swap(rl_src1, rl_src2); |
| 953 | } |
| 954 | |
| 955 | // Pick the first integer as min/max. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 956 | OpRegCopy(rl_result.reg, rl_src1.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 957 | |
| 958 | // If the integers are both in the same register, then there is nothing else to do |
| 959 | // because they are equal and we have already moved one into the result. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 960 | if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 961 | // It is possible we didn't pick correctly so do the actual comparison now. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 962 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 963 | |
| 964 | // Conditionally move the other integer into the destination register. |
| 965 | ConditionCode condition_code = is_min ? kCondGt : kCondLt; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 966 | OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 967 | } |
| 968 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 969 | if (is_long) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 970 | StoreValueWide(rl_dest, rl_result); |
| 971 | } else { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 972 | StoreValue(rl_dest, rl_result); |
| 973 | } |
| 974 | return true; |
| 975 | } |
| 976 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 977 | bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 978 | RegLocation rl_src_address = info->args[0]; // long address |
| 979 | RegLocation rl_address; |
| 980 | if (!cu_->target64) { |
| 981 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 982 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 983 | } else { |
| 984 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 985 | } |
| 986 | RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); |
| 987 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 988 | // Unaligned access is allowed on x86. |
| 989 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile); |
| 990 | if (size == k64) { |
| 991 | StoreValueWide(rl_dest, rl_result); |
| 992 | } else { |
| 993 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 994 | StoreValue(rl_dest, rl_result); |
| 995 | } |
| 996 | return true; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 997 | } |
| 998 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 999 | bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 1000 | RegLocation rl_src_address = info->args[0]; // long address |
| 1001 | RegLocation rl_address; |
| 1002 | if (!cu_->target64) { |
| 1003 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 1004 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 1005 | } else { |
| 1006 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 1007 | } |
| 1008 | RegLocation rl_src_value = info->args[2]; // [size] value |
| 1009 | RegLocation rl_value; |
| 1010 | if (size == k64) { |
| 1011 | // Unaligned access is allowed on x86. |
| 1012 | rl_value = LoadValueWide(rl_src_value, kCoreReg); |
| 1013 | } else { |
| 1014 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 1015 | // In 32-bit mode the only EAX..EDX registers can be used with Mov8MR. |
| 1016 | if (!cu_->target64 && size == kSignedByte) { |
| 1017 | rl_src_value = UpdateLocTyped(rl_src_value, kCoreReg); |
| 1018 | if (rl_src_value.location == kLocPhysReg && !IsByteRegister(rl_src_value.reg)) { |
| 1019 | RegStorage temp = AllocateByteRegister(); |
| 1020 | OpRegCopy(temp, rl_src_value.reg); |
| 1021 | rl_value.reg = temp; |
| 1022 | } else { |
| 1023 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 1024 | } |
| 1025 | } else { |
| 1026 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 1027 | } |
| 1028 | } |
| 1029 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile); |
| 1030 | return true; |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1031 | } |
| 1032 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1033 | void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { |
| 1034 | NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1035 | } |
| 1036 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1037 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1038 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 1039 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
| 1040 | } |
| 1041 | |
| 1042 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { |
| 1043 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 1044 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1045 | } |
| 1046 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1047 | static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { |
| 1048 | return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1049 | } |
| 1050 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 1051 | bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 1052 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1053 | // Unused - RegLocation rl_src_unsafe = info->args[0]; |
| 1054 | RegLocation rl_src_obj = info->args[1]; // Object - known non-null |
| 1055 | RegLocation rl_src_offset = info->args[2]; // long low |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1056 | if (!cu_->target64) { |
| 1057 | rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] |
| 1058 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1059 | RegLocation rl_src_expected = info->args[4]; // int, long or Object |
| 1060 | // If is_long, high half is in info->args[5] |
| 1061 | RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object |
| 1062 | // If is_long, high half is in info->args[7] |
| 1063 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1064 | if (is_long && cu_->target64) { |
| 1065 | // RAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in RAX. |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1066 | FlushReg(rs_r0q); |
| 1067 | Clobber(rs_r0q); |
| 1068 | LockTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1069 | |
| 1070 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
| 1071 | RegLocation rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg); |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1072 | RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1073 | LoadValueDirectWide(rl_src_expected, rs_r0q); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1074 | NewLIR5(kX86LockCmpxchg64AR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1075 | rl_new_value.reg.GetReg()); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1076 | |
| 1077 | // After a store we need to insert barrier in case of potential load. Since the |
| 1078 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1079 | GenMemBarrier(kAnyAny); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1080 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1081 | FreeTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1082 | } else if (is_long) { |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1083 | // TODO: avoid unnecessary loads of SI and DI when the values are in registers. |
| 1084 | // TODO: CFI support. |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1085 | FlushAllRegs(); |
| 1086 | LockCallTemps(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1087 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 1088 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1089 | LoadValueDirectWideFixed(rl_src_expected, r_tmp1); |
| 1090 | LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1091 | // FIXME: needs 64-bit update. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1092 | const bool obj_in_di = IsInReg(this, rl_src_obj, rs_rDI); |
| 1093 | const bool obj_in_si = IsInReg(this, rl_src_obj, rs_rSI); |
| 1094 | DCHECK(!obj_in_si || !obj_in_di); |
| 1095 | const bool off_in_di = IsInReg(this, rl_src_offset, rs_rDI); |
| 1096 | const bool off_in_si = IsInReg(this, rl_src_offset, rs_rSI); |
| 1097 | DCHECK(!off_in_si || !off_in_di); |
| 1098 | // If obj/offset is in a reg, use that reg. Otherwise, use the empty reg. |
| 1099 | RegStorage rs_obj = obj_in_di ? rs_rDI : obj_in_si ? rs_rSI : !off_in_di ? rs_rDI : rs_rSI; |
| 1100 | RegStorage rs_off = off_in_si ? rs_rSI : off_in_di ? rs_rDI : !obj_in_si ? rs_rSI : rs_rDI; |
| 1101 | bool push_di = (!obj_in_di && !off_in_di) && (rs_obj == rs_rDI || rs_off == rs_rDI); |
| 1102 | bool push_si = (!obj_in_si && !off_in_si) && (rs_obj == rs_rSI || rs_off == rs_rSI); |
| 1103 | if (push_di) { |
| 1104 | NewLIR1(kX86Push32R, rs_rDI.GetReg()); |
| 1105 | MarkTemp(rs_rDI); |
| 1106 | LockTemp(rs_rDI); |
| 1107 | } |
| 1108 | if (push_si) { |
| 1109 | NewLIR1(kX86Push32R, rs_rSI.GetReg()); |
| 1110 | MarkTemp(rs_rSI); |
| 1111 | LockTemp(rs_rSI); |
| 1112 | } |
| 1113 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1114 | const size_t push_offset = (push_si ? 4u : 0u) + (push_di ? 4u : 0u); |
| 1115 | if (!obj_in_si && !obj_in_di) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1116 | LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_obj.s_reg_low) + push_offset, rs_obj); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1117 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1118 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1119 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1120 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1121 | } |
| 1122 | if (!off_in_si && !off_in_di) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1123 | LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1124 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1125 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1126 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1127 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1128 | } |
| 1129 | NewLIR4(kX86LockCmpxchg64A, rs_obj.GetReg(), rs_off.GetReg(), 0, 0); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1130 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1131 | // After a store we need to insert barrier to prevent reordering with either |
| 1132 | // earlier or later memory accesses. Since |
| 1133 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1134 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1135 | GenMemBarrier(kAnyAny); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1136 | |
| 1137 | if (push_si) { |
| 1138 | FreeTemp(rs_rSI); |
| 1139 | UnmarkTemp(rs_rSI); |
| 1140 | NewLIR1(kX86Pop32R, rs_rSI.GetReg()); |
| 1141 | } |
| 1142 | if (push_di) { |
| 1143 | FreeTemp(rs_rDI); |
| 1144 | UnmarkTemp(rs_rDI); |
| 1145 | NewLIR1(kX86Pop32R, rs_rDI.GetReg()); |
| 1146 | } |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1147 | FreeCallTemps(); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1148 | } else { |
| 1149 | // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1150 | FlushReg(rs_r0); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1151 | Clobber(rs_r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1152 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1153 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1154 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
| 1155 | RegLocation rl_new_value = LoadValue(rl_src_new_value); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1156 | |
| 1157 | if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { |
| 1158 | // Mark card for object assuming new value is stored. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1159 | FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1160 | MarkGCCard(rl_new_value.reg, rl_object.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1161 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1162 | } |
| 1163 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1164 | RegLocation rl_offset; |
| 1165 | if (cu_->target64) { |
| 1166 | rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1167 | } else { |
| 1168 | rl_offset = LoadValue(rl_src_offset, kCoreReg); |
| 1169 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1170 | LoadValueDirect(rl_src_expected, rs_r0); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1171 | NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1172 | rl_new_value.reg.GetReg()); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1173 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1174 | // After a store we need to insert barrier to prevent reordering with either |
| 1175 | // earlier or later memory accesses. Since |
| 1176 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1177 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1178 | GenMemBarrier(kAnyAny); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1179 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1180 | FreeTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | // Convert ZF to boolean |
| 1184 | RegLocation rl_dest = InlineTarget(info); // boolean place for result |
| 1185 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1186 | RegStorage result_reg = rl_result.reg; |
| 1187 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1188 | // For 32-bit, SETcc only works with EAX..EDX. |
| 1189 | if (!IsByteRegister(result_reg)) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1190 | result_reg = AllocateByteRegister(); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1191 | } |
| 1192 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondZ); |
| 1193 | NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), result_reg.GetReg()); |
| 1194 | if (IsTemp(result_reg)) { |
| 1195 | FreeTemp(result_reg); |
| 1196 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1197 | StoreValue(rl_dest, rl_result); |
| 1198 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1199 | } |
| 1200 | |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 1201 | void X86Mir2Lir::SwapBits(RegStorage result_reg, int shift, int32_t value) { |
| 1202 | RegStorage r_temp = AllocTemp(); |
| 1203 | OpRegCopy(r_temp, result_reg); |
| 1204 | OpRegImm(kOpLsr, result_reg, shift); |
| 1205 | OpRegImm(kOpAnd, r_temp, value); |
| 1206 | OpRegImm(kOpAnd, result_reg, value); |
| 1207 | OpRegImm(kOpLsl, r_temp, shift); |
| 1208 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1209 | FreeTemp(r_temp); |
| 1210 | } |
| 1211 | |
| 1212 | void X86Mir2Lir::SwapBits64(RegStorage result_reg, int shift, int64_t value) { |
| 1213 | RegStorage r_temp = AllocTempWide(); |
| 1214 | OpRegCopy(r_temp, result_reg); |
| 1215 | OpRegImm(kOpLsr, result_reg, shift); |
| 1216 | RegStorage r_value = AllocTempWide(); |
| 1217 | LoadConstantWide(r_value, value); |
| 1218 | OpRegReg(kOpAnd, r_temp, r_value); |
| 1219 | OpRegReg(kOpAnd, result_reg, r_value); |
| 1220 | OpRegImm(kOpLsl, r_temp, shift); |
| 1221 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1222 | FreeTemp(r_temp); |
| 1223 | FreeTemp(r_value); |
| 1224 | } |
| 1225 | |
| 1226 | bool X86Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { |
| 1227 | RegLocation rl_src_i = info->args[0]; |
| 1228 | RegLocation rl_i = (size == k64) ? LoadValueWide(rl_src_i, kCoreReg) |
| 1229 | : LoadValue(rl_src_i, kCoreReg); |
| 1230 | RegLocation rl_dest = (size == k64) ? InlineTargetWide(info) : InlineTarget(info); |
| 1231 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1232 | if (size == k64) { |
| 1233 | if (cu_->instruction_set == kX86_64) { |
| 1234 | /* Use one bswap instruction to reverse byte order first and then use 3 rounds of |
| 1235 | swapping bits to reverse bits in a long number x. Using bswap to save instructions |
| 1236 | compared to generic luni implementation which has 5 rounds of swapping bits. |
| 1237 | x = bswap x |
| 1238 | x = (x & 0x5555555555555555) << 1 | (x >> 1) & 0x5555555555555555; |
| 1239 | x = (x & 0x3333333333333333) << 2 | (x >> 2) & 0x3333333333333333; |
| 1240 | x = (x & 0x0F0F0F0F0F0F0F0F) << 4 | (x >> 4) & 0x0F0F0F0F0F0F0F0F; |
| 1241 | */ |
| 1242 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1243 | SwapBits64(rl_result.reg, 1, 0x5555555555555555); |
| 1244 | SwapBits64(rl_result.reg, 2, 0x3333333333333333); |
| 1245 | SwapBits64(rl_result.reg, 4, 0x0f0f0f0f0f0f0f0f); |
| 1246 | StoreValueWide(rl_dest, rl_result); |
| 1247 | return true; |
| 1248 | } |
| 1249 | RegStorage r_i_low = rl_i.reg.GetLow(); |
| 1250 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1251 | // First REV shall clobber rl_result.reg.GetLowReg(), save the value in a temp for the second |
| 1252 | // REV. |
| 1253 | r_i_low = AllocTemp(); |
| 1254 | OpRegCopy(r_i_low, rl_i.reg); |
| 1255 | } |
| 1256 | OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh()); |
| 1257 | OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low); |
| 1258 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1259 | FreeTemp(r_i_low); |
| 1260 | } |
| 1261 | SwapBits(rl_result.reg.GetLow(), 1, 0x55555555); |
| 1262 | SwapBits(rl_result.reg.GetLow(), 2, 0x33333333); |
| 1263 | SwapBits(rl_result.reg.GetLow(), 4, 0x0f0f0f0f); |
| 1264 | SwapBits(rl_result.reg.GetHigh(), 1, 0x55555555); |
| 1265 | SwapBits(rl_result.reg.GetHigh(), 2, 0x33333333); |
| 1266 | SwapBits(rl_result.reg.GetHigh(), 4, 0x0f0f0f0f); |
| 1267 | StoreValueWide(rl_dest, rl_result); |
| 1268 | } else { |
| 1269 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1270 | SwapBits(rl_result.reg, 1, 0x55555555); |
| 1271 | SwapBits(rl_result.reg, 2, 0x33333333); |
| 1272 | SwapBits(rl_result.reg, 4, 0x0f0f0f0f); |
| 1273 | StoreValue(rl_dest, rl_result); |
| 1274 | } |
| 1275 | return true; |
| 1276 | } |
| 1277 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1278 | LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1279 | CHECK(base_of_code_ != nullptr); |
| 1280 | |
| 1281 | // Address the start of the method |
| 1282 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 1283 | if (rl_method.wide) { |
| 1284 | LoadValueDirectWideFixed(rl_method, reg); |
| 1285 | } else { |
| 1286 | LoadValueDirectFixed(rl_method, reg); |
| 1287 | } |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1288 | store_method_addr_used_ = true; |
| 1289 | |
| 1290 | // Load the proper value from the literal area. |
| 1291 | // We don't know the proper offset for the value, so pick one that will force |
| 1292 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 1293 | // value. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1294 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1295 | LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256, |
| 1296 | 0, 0, target); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1297 | res->target = target; |
| 1298 | res->flags.fixup = kFixupLoad; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1299 | store_method_addr_used_ = true; |
| 1300 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1301 | } |
| 1302 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1303 | LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1304 | LOG(FATAL) << "Unexpected use of OpVldm for x86"; |
| 1305 | return NULL; |
| 1306 | } |
| 1307 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1308 | LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1309 | LOG(FATAL) << "Unexpected use of OpVstm for x86"; |
| 1310 | return NULL; |
| 1311 | } |
| 1312 | |
| 1313 | void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 1314 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1315 | int first_bit, int second_bit) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1316 | RegStorage t_reg = AllocTemp(); |
| 1317 | OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); |
| 1318 | OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1319 | FreeTemp(t_reg); |
| 1320 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1321 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1322 | } |
| 1323 | } |
| 1324 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1325 | void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1326 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1327 | DCHECK(reg.Is64Bit()); |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1328 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1329 | NewLIR2(kX86Cmp64RI8, reg.GetReg(), 0); |
| 1330 | } else { |
| 1331 | DCHECK(reg.IsPair()); |
| 1332 | |
| 1333 | // We are not supposed to clobber the incoming storage, so allocate a temporary. |
| 1334 | RegStorage t_reg = AllocTemp(); |
| 1335 | // Doing an OR is a quick way to check if both registers are zero. This will set the flags. |
| 1336 | OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); |
| 1337 | // The temp is no longer needed so free it at this time. |
| 1338 | FreeTemp(t_reg); |
| 1339 | } |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1340 | |
| 1341 | // In case of zero, throw ArithmeticException. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1342 | GenDivZeroCheck(kCondEq); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1343 | } |
| 1344 | |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1345 | void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, |
| 1346 | RegStorage array_base, |
| 1347 | int len_offset) { |
| 1348 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1349 | public: |
| 1350 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 1351 | RegStorage index, RegStorage array_base, int32_t len_offset) |
| 1352 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 1353 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 1354 | } |
| 1355 | |
| 1356 | void Compile() OVERRIDE { |
| 1357 | m2l_->ResetRegPool(); |
| 1358 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1359 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1360 | |
| 1361 | RegStorage new_index = index_; |
| 1362 | // Move index out of kArg1, either directly to kArg0, or to kArg2. |
Serguei Katkov | 4c7cc15 | 2014-06-24 00:50:02 +0700 | [diff] [blame] | 1363 | // TODO: clean-up to check not a number but with type |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1364 | if (index_ == m2l_->TargetReg(kArg1, kNotWide)) { |
| 1365 | if (array_base_ == m2l_->TargetReg(kArg0, kRef)) { |
| 1366 | m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kNotWide), index_); |
| 1367 | new_index = m2l_->TargetReg(kArg2, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1368 | } else { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1369 | m2l_->OpRegCopy(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1370 | new_index = m2l_->TargetReg(kArg0, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1371 | } |
| 1372 | } |
| 1373 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1374 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1375 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1376 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, new_index, |
| 1377 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1378 | } |
| 1379 | |
| 1380 | private: |
| 1381 | const RegStorage index_; |
| 1382 | const RegStorage array_base_; |
| 1383 | const int32_t len_offset_; |
| 1384 | }; |
| 1385 | |
| 1386 | OpRegMem(kOpCmp, index, array_base, len_offset); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1387 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1388 | LIR* branch = OpCondBranch(kCondUge, nullptr); |
| 1389 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1390 | index, array_base, len_offset)); |
| 1391 | } |
| 1392 | |
| 1393 | void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, |
| 1394 | RegStorage array_base, |
| 1395 | int32_t len_offset) { |
| 1396 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1397 | public: |
| 1398 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 1399 | int32_t index, RegStorage array_base, int32_t len_offset) |
| 1400 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 1401 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 1402 | } |
| 1403 | |
| 1404 | void Compile() OVERRIDE { |
| 1405 | m2l_->ResetRegPool(); |
| 1406 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1407 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1408 | |
| 1409 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1410 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1411 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1412 | x86_m2l->LoadConstant(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1413 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, m2l_->TargetReg(kArg0, kNotWide), |
| 1414 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1415 | } |
| 1416 | |
| 1417 | private: |
| 1418 | const int32_t index_; |
| 1419 | const RegStorage array_base_; |
| 1420 | const int32_t len_offset_; |
| 1421 | }; |
| 1422 | |
| 1423 | NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1424 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1425 | LIR* branch = OpCondBranch(kCondLs, nullptr); |
| 1426 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1427 | index, array_base, len_offset)); |
| 1428 | } |
| 1429 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1430 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1431 | LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 1432 | if (cu_->target64) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1433 | OpTlsCmp(Thread::ThreadFlagsOffset<8>(), 0); |
| 1434 | } else { |
| 1435 | OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); |
| 1436 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1437 | return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); |
| 1438 | } |
| 1439 | |
| 1440 | // Decrement register and branch on condition |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1441 | LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1442 | OpRegImm(kOpSub, reg, 1); |
Yixin Shou | a0dac3e | 2014-01-23 05:01:22 -0800 | [diff] [blame] | 1443 | return OpCondBranch(c_code, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1444 | } |
| 1445 | |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 1446 | bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1447 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1448 | LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; |
| 1449 | return false; |
| 1450 | } |
| 1451 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1452 | bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
| 1453 | LOG(FATAL) << "Unexpected use of easyMultiply in x86"; |
| 1454 | return false; |
| 1455 | } |
| 1456 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1457 | LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1458 | LOG(FATAL) << "Unexpected use of OpIT in x86"; |
| 1459 | return NULL; |
| 1460 | } |
| 1461 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 1462 | void X86Mir2Lir::OpEndIT(LIR* it) { |
| 1463 | LOG(FATAL) << "Unexpected use of OpEndIT in x86"; |
| 1464 | } |
| 1465 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1466 | void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1467 | switch (val) { |
| 1468 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1469 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1470 | break; |
| 1471 | case 1: |
| 1472 | OpRegCopy(dest, src); |
| 1473 | break; |
| 1474 | default: |
| 1475 | OpRegRegImm(kOpMul, dest, src, val); |
| 1476 | break; |
| 1477 | } |
| 1478 | } |
| 1479 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1480 | void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1481 | // All memory accesses below reference dalvik regs. |
| 1482 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1483 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1484 | LIR *m; |
| 1485 | switch (val) { |
| 1486 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1487 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1488 | break; |
| 1489 | case 1: |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1490 | LoadBaseDisp(rs_rX86_SP, displacement, dest, k32, kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1491 | break; |
| 1492 | default: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1493 | m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), |
| 1494 | rs_rX86_SP.GetReg(), displacement, val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1495 | AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); |
| 1496 | break; |
| 1497 | } |
| 1498 | } |
| 1499 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1500 | void X86Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 1501 | RegLocation rl_src2) { |
| 1502 | if (!cu_->target64) { |
| 1503 | // Some x86 32b ops are fallback. |
| 1504 | switch (opcode) { |
| 1505 | case Instruction::NOT_LONG: |
| 1506 | case Instruction::DIV_LONG: |
| 1507 | case Instruction::DIV_LONG_2ADDR: |
| 1508 | case Instruction::REM_LONG: |
| 1509 | case Instruction::REM_LONG_2ADDR: |
| 1510 | Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1511 | return; |
| 1512 | |
| 1513 | default: |
| 1514 | // Everything else we can handle. |
| 1515 | break; |
| 1516 | } |
| 1517 | } |
| 1518 | |
| 1519 | switch (opcode) { |
| 1520 | case Instruction::NOT_LONG: |
| 1521 | GenNotLong(rl_dest, rl_src2); |
| 1522 | return; |
| 1523 | |
| 1524 | case Instruction::ADD_LONG: |
| 1525 | case Instruction::ADD_LONG_2ADDR: |
| 1526 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1527 | return; |
| 1528 | |
| 1529 | case Instruction::SUB_LONG: |
| 1530 | case Instruction::SUB_LONG_2ADDR: |
| 1531 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); |
| 1532 | return; |
| 1533 | |
| 1534 | case Instruction::MUL_LONG: |
| 1535 | case Instruction::MUL_LONG_2ADDR: |
| 1536 | GenMulLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1537 | return; |
| 1538 | |
| 1539 | case Instruction::DIV_LONG: |
| 1540 | case Instruction::DIV_LONG_2ADDR: |
| 1541 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); |
| 1542 | return; |
| 1543 | |
| 1544 | case Instruction::REM_LONG: |
| 1545 | case Instruction::REM_LONG_2ADDR: |
| 1546 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); |
| 1547 | return; |
| 1548 | |
| 1549 | case Instruction::AND_LONG_2ADDR: |
| 1550 | case Instruction::AND_LONG: |
| 1551 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1552 | return; |
| 1553 | |
| 1554 | case Instruction::OR_LONG: |
| 1555 | case Instruction::OR_LONG_2ADDR: |
| 1556 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1557 | return; |
| 1558 | |
| 1559 | case Instruction::XOR_LONG: |
| 1560 | case Instruction::XOR_LONG_2ADDR: |
| 1561 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1562 | return; |
| 1563 | |
| 1564 | case Instruction::NEG_LONG: |
| 1565 | GenNegLong(rl_dest, rl_src2); |
| 1566 | return; |
| 1567 | |
| 1568 | default: |
| 1569 | LOG(FATAL) << "Invalid long arith op"; |
| 1570 | return; |
| 1571 | } |
| 1572 | } |
| 1573 | |
| 1574 | bool X86Mir2Lir::GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1575 | // All memory accesses below reference dalvik regs. |
| 1576 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1577 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1578 | if (val == 0) { |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1579 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1580 | if (cu_->target64) { |
| 1581 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1582 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1583 | OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); |
| 1584 | OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1585 | } |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1586 | StoreValueWide(rl_dest, rl_result); |
| 1587 | return true; |
| 1588 | } else if (val == 1) { |
| 1589 | StoreValueWide(rl_dest, rl_src1); |
| 1590 | return true; |
| 1591 | } else if (val == 2) { |
| 1592 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); |
| 1593 | return true; |
| 1594 | } else if (IsPowerOfTwo(val)) { |
| 1595 | int shift_amount = LowestSetBit(val); |
| 1596 | if (!BadOverlap(rl_src1, rl_dest)) { |
| 1597 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1598 | RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, rl_src1, |
| 1599 | shift_amount); |
| 1600 | StoreValueWide(rl_dest, rl_result); |
| 1601 | return true; |
| 1602 | } |
| 1603 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1604 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1605 | // Okay, on 32b just bite the bullet and do it, still better than the general case. |
| 1606 | if (!cu_->target64) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1607 | int32_t val_lo = Low32Bits(val); |
| 1608 | int32_t val_hi = High32Bits(val); |
| 1609 | FlushAllRegs(); |
| 1610 | LockCallTemps(); // Prepare for explicit register usage. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1611 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1612 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1613 | int displacement = SRegOffset(rl_src1.s_reg_low); |
| 1614 | |
| 1615 | // ECX <- 1H * 2L |
| 1616 | // EAX <- 1L * 2H |
| 1617 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1618 | GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); |
| 1619 | GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1620 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1621 | GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); |
| 1622 | GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1623 | } |
| 1624 | |
| 1625 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1626 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1627 | |
| 1628 | // EAX <- 2L |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1629 | LoadConstantNoClobber(rs_r0, val_lo); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1630 | |
| 1631 | // EDX:EAX <- 2L * 1L (double precision) |
| 1632 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1633 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1634 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1635 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1636 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1637 | true /* is_load */, true /* is_64bit */); |
| 1638 | } |
| 1639 | |
| 1640 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1641 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1642 | |
| 1643 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1644 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
| 1645 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1646 | StoreValueWide(rl_dest, rl_result); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1647 | return true; |
| 1648 | } |
| 1649 | return false; |
| 1650 | } |
| 1651 | |
| 1652 | void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
| 1653 | RegLocation rl_src2) { |
| 1654 | if (rl_src1.is_const) { |
| 1655 | std::swap(rl_src1, rl_src2); |
| 1656 | } |
| 1657 | |
| 1658 | if (rl_src2.is_const) { |
| 1659 | if (GenMulLongConst(rl_dest, rl_src1, mir_graph_->ConstantValueWide(rl_src2))) { |
| 1660 | return; |
| 1661 | } |
| 1662 | } |
| 1663 | |
| 1664 | // All memory accesses below reference dalvik regs. |
| 1665 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1666 | |
| 1667 | if (cu_->target64) { |
| 1668 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1669 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1670 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1671 | if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1672 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1673 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
| 1674 | } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() && |
| 1675 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1676 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); |
| 1677 | } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1678 | rl_result.reg.GetReg() != rl_src2.reg.GetReg()) { |
| 1679 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1680 | } else { |
| 1681 | OpRegCopy(rl_result.reg, rl_src1.reg); |
| 1682 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1683 | } |
| 1684 | StoreValueWide(rl_dest, rl_result); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1685 | return; |
| 1686 | } |
| 1687 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1688 | // Not multiplying by a constant. Do it the hard way |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1689 | // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. |
| 1690 | bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == |
| 1691 | mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 1692 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1693 | FlushAllRegs(); |
| 1694 | LockCallTemps(); // Prepare for explicit register usage. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1695 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
| 1696 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1697 | |
| 1698 | // At this point, the VRs are in their home locations. |
| 1699 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1700 | bool src2_in_reg = rl_src2.location == kLocPhysReg; |
| 1701 | |
| 1702 | // ECX <- 1H |
| 1703 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1704 | NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1705 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1706 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32, |
| 1707 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1708 | } |
| 1709 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1710 | if (is_square) { |
| 1711 | // Take advantage of the fact that the values are the same. |
| 1712 | // ECX <- ECX * 2L (1H * 2L) |
| 1713 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1714 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1715 | } else { |
| 1716 | int displacement = SRegOffset(rl_src2.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1717 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
| 1718 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1719 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1720 | true /* is_load */, true /* is_64bit */); |
| 1721 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1722 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1723 | // ECX <- 2*ECX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1724 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1725 | } else { |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1726 | // EAX <- 2H |
| 1727 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1728 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1729 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1730 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32, |
| 1731 | kNotVolatile); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1732 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1733 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1734 | // EAX <- EAX * 1L (2H * 1L) |
| 1735 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1736 | NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1737 | } else { |
| 1738 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1739 | LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP.GetReg(), |
| 1740 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1741 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1742 | true /* is_load */, true /* is_64bit */); |
| 1743 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1744 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1745 | // ECX <- ECX * 2L (1H * 2L) |
| 1746 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1747 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1748 | } else { |
| 1749 | int displacement = SRegOffset(rl_src2.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1750 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
| 1751 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1752 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1753 | true /* is_load */, true /* is_64bit */); |
| 1754 | } |
| 1755 | |
| 1756 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1757 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1758 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1759 | |
| 1760 | // EAX <- 2L |
| 1761 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1762 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1763 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1764 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32, |
| 1765 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1766 | } |
| 1767 | |
| 1768 | // EDX:EAX <- 2L * 1L (double precision) |
| 1769 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1770 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1771 | } else { |
| 1772 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1773 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1774 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1775 | true /* is_load */, true /* is_64bit */); |
| 1776 | } |
| 1777 | |
| 1778 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1779 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1780 | |
| 1781 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1782 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1783 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1784 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1785 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1786 | |
| 1787 | void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, |
| 1788 | Instruction::Code op) { |
| 1789 | DCHECK_EQ(rl_dest.location, kLocPhysReg); |
| 1790 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
| 1791 | if (rl_src.location == kLocPhysReg) { |
| 1792 | // Both operands are in registers. |
Serguei Katkov | ab5545f | 2014-03-25 10:51:15 +0700 | [diff] [blame] | 1793 | // But we must ensure that rl_src is in pair |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1794 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1795 | NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg()); |
| 1796 | } else { |
| 1797 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1798 | if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { |
| 1799 | // The registers are the same, so we would clobber it before the use. |
| 1800 | RegStorage temp_reg = AllocTemp(); |
| 1801 | OpRegCopy(temp_reg, rl_dest.reg); |
| 1802 | rl_src.reg.SetHighReg(temp_reg.GetReg()); |
| 1803 | } |
| 1804 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1805 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1806 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1807 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); |
| 1808 | FreeTemp(rl_src.reg); // ??? |
| 1809 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1810 | return; |
| 1811 | } |
| 1812 | |
| 1813 | // RHS is in memory. |
| 1814 | DCHECK((rl_src.location == kLocDalvikFrame) || |
| 1815 | (rl_src.location == kLocCompilerTemp)); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1816 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1817 | int displacement = SRegOffset(rl_src.s_reg_low); |
| 1818 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1819 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1820 | LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), |
| 1821 | r_base, displacement + LOWORD_OFFSET); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1822 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 1823 | true /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1824 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1825 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1826 | lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1827 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1828 | true /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1829 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1830 | } |
| 1831 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1832 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1833 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1834 | if (rl_dest.location == kLocPhysReg) { |
| 1835 | // Ensure we are in a register pair |
| 1836 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1837 | |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1838 | rl_src = UpdateLocWideTyped(rl_src, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1839 | GenLongRegOrMemOp(rl_result, rl_src, op); |
| 1840 | StoreFinalValueWide(rl_dest, rl_result); |
| 1841 | return; |
| 1842 | } |
| 1843 | |
| 1844 | // It wasn't in registers, so it better be in memory. |
| 1845 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1846 | (rl_dest.location == kLocCompilerTemp)); |
| 1847 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1848 | |
| 1849 | // Operate directly into memory. |
| 1850 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1851 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1852 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 1853 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1854 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1855 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1856 | cu_->target64 ? rl_src.reg.GetReg() : rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1857 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1858 | true /* is_load */, true /* is64bit */); |
| 1859 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1860 | false /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1861 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1862 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1863 | lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1864 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1865 | true /* is_load */, true /* is64bit */); |
| 1866 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1867 | false /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1868 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1869 | FreeTemp(rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1870 | } |
| 1871 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1872 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, |
| 1873 | RegLocation rl_src2, Instruction::Code op, |
| 1874 | bool is_commutative) { |
| 1875 | // Is this really a 2 operand operation? |
| 1876 | switch (op) { |
| 1877 | case Instruction::ADD_LONG_2ADDR: |
| 1878 | case Instruction::SUB_LONG_2ADDR: |
| 1879 | case Instruction::AND_LONG_2ADDR: |
| 1880 | case Instruction::OR_LONG_2ADDR: |
| 1881 | case Instruction::XOR_LONG_2ADDR: |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 1882 | if (GenerateTwoOperandInstructions()) { |
| 1883 | GenLongArith(rl_dest, rl_src2, op); |
| 1884 | return; |
| 1885 | } |
| 1886 | break; |
| 1887 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1888 | default: |
| 1889 | break; |
| 1890 | } |
| 1891 | |
| 1892 | if (rl_dest.location == kLocPhysReg) { |
| 1893 | RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); |
| 1894 | |
| 1895 | // We are about to clobber the LHS, so it needs to be a temp. |
| 1896 | rl_result = ForceTempWide(rl_result); |
| 1897 | |
| 1898 | // Perform the operation using the RHS. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1899 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1900 | GenLongRegOrMemOp(rl_result, rl_src2, op); |
| 1901 | |
| 1902 | // And now record that the result is in the temp. |
| 1903 | StoreFinalValueWide(rl_dest, rl_result); |
| 1904 | return; |
| 1905 | } |
| 1906 | |
| 1907 | // It wasn't in registers, so it better be in memory. |
| 1908 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1909 | (rl_dest.location == kLocCompilerTemp)); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1910 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
| 1911 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1912 | |
| 1913 | // Get one of the source operands into temporary register. |
| 1914 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1915 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1916 | if (IsTemp(rl_src1.reg)) { |
| 1917 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1918 | } else if (is_commutative) { |
| 1919 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1920 | // We need at least one of them to be a temporary. |
| 1921 | if (!IsTemp(rl_src2.reg)) { |
| 1922 | rl_src1 = ForceTempWide(rl_src1); |
| 1923 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1924 | } else { |
| 1925 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 1926 | StoreFinalValueWide(rl_dest, rl_src2); |
| 1927 | return; |
| 1928 | } |
| 1929 | } else { |
| 1930 | // Need LHS to be the temp. |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1931 | rl_src1 = ForceTempWide(rl_src1); |
Yevgeny Rouban | 91b6ffa | 2014-03-07 14:35:44 +0700 | [diff] [blame] | 1932 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1933 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1934 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1935 | if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
| 1936 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1937 | } else if (is_commutative) { |
| 1938 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1939 | // We need at least one of them to be a temporary. |
| 1940 | if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { |
| 1941 | rl_src1 = ForceTempWide(rl_src1); |
| 1942 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1943 | } else { |
| 1944 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 1945 | StoreFinalValueWide(rl_dest, rl_src2); |
| 1946 | return; |
| 1947 | } |
| 1948 | } else { |
| 1949 | // Need LHS to be the temp. |
| 1950 | rl_src1 = ForceTempWide(rl_src1); |
| 1951 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1952 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1953 | } |
| 1954 | |
| 1955 | StoreFinalValueWide(rl_dest, rl_src1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1956 | } |
| 1957 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 1958 | void X86Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1959 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1960 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1961 | RegLocation rl_result; |
| 1962 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1963 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1964 | OpReg(kOpNot, rl_result.reg); |
| 1965 | StoreValueWide(rl_dest, rl_result); |
| 1966 | } else { |
| 1967 | LOG(FATAL) << "Unexpected use GenNotLong()"; |
| 1968 | } |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 1969 | } |
| 1970 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 1971 | void X86Mir2Lir::GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, |
| 1972 | int64_t imm, bool is_div) { |
| 1973 | if (imm == 0) { |
| 1974 | GenDivZeroException(); |
| 1975 | } else if (imm == 1) { |
| 1976 | if (is_div) { |
| 1977 | // x / 1 == x. |
| 1978 | StoreValueWide(rl_dest, rl_src); |
| 1979 | } else { |
| 1980 | // x % 1 == 0. |
| 1981 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1982 | LoadConstantWide(rl_result.reg, 0); |
| 1983 | StoreValueWide(rl_dest, rl_result); |
| 1984 | } |
| 1985 | } else if (imm == -1) { // handle 0x8000000000000000 / -1 special case. |
| 1986 | if (is_div) { |
| 1987 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1988 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1989 | RegStorage rs_temp = AllocTempWide(); |
| 1990 | |
| 1991 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1992 | LoadConstantWide(rs_temp, 0x8000000000000000); |
| 1993 | |
| 1994 | // If x == MIN_LONG, return MIN_LONG. |
| 1995 | OpRegReg(kOpCmp, rl_src.reg, rs_temp); |
| 1996 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 1997 | |
| 1998 | // For x != MIN_LONG, x / -1 == -x. |
| 1999 | OpReg(kOpNeg, rl_result.reg); |
| 2000 | |
| 2001 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
| 2002 | FreeTemp(rs_temp); |
| 2003 | StoreValueWide(rl_dest, rl_result); |
| 2004 | } else { |
| 2005 | // x % -1 == 0. |
| 2006 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2007 | LoadConstantWide(rl_result.reg, 0); |
| 2008 | StoreValueWide(rl_dest, rl_result); |
| 2009 | } |
| 2010 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 2011 | // Division using shifting. |
| 2012 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2013 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2014 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 2015 | RegStorage rs_temp = AllocTypedTempWide(false, kCoreReg); |
| 2016 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 2017 | } |
| 2018 | LoadConstantWide(rl_result.reg, std::abs(imm) - 1); |
| 2019 | OpRegReg(kOpAdd, rl_result.reg, rl_src.reg); |
| 2020 | NewLIR2(kX86Test64RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 2021 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
| 2022 | int shift_amount = LowestSetBit(imm); |
| 2023 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 2024 | if (imm < 0) { |
| 2025 | OpReg(kOpNeg, rl_result.reg); |
| 2026 | } |
| 2027 | StoreValueWide(rl_dest, rl_result); |
| 2028 | } else { |
| 2029 | CHECK(imm <= -2 || imm >= 2); |
| 2030 | |
| 2031 | FlushReg(rs_r0q); |
| 2032 | Clobber(rs_r0q); |
| 2033 | LockTemp(rs_r0q); |
| 2034 | FlushReg(rs_r2q); |
| 2035 | Clobber(rs_r2q); |
| 2036 | LockTemp(rs_r2q); |
| 2037 | |
| 2038 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r2q, INVALID_SREG, INVALID_SREG}; |
| 2039 | |
| 2040 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 2041 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 2042 | int64_t magic; |
| 2043 | int shift; |
| 2044 | CalculateMagicAndShift(imm, magic, shift, true /* is_long */); |
| 2045 | |
| 2046 | /* |
| 2047 | * For imm >= 2, |
| 2048 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 2049 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 2050 | * For imm <= -2, |
| 2051 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 2052 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 2053 | * We implement this algorithm in the following way: |
| 2054 | * 1. multiply magic number m and numerator n, get the higher 64bit result in RDX |
| 2055 | * 2. if imm > 0 and magic < 0, add numerator to RDX |
| 2056 | * if imm < 0 and magic > 0, sub numerator from RDX |
| 2057 | * 3. if S !=0, SAR S bits for RDX |
| 2058 | * 4. add 1 to RDX if RDX < 0 |
| 2059 | * 5. Thus, RDX is the quotient |
| 2060 | */ |
| 2061 | |
| 2062 | // Numerator into RAX. |
| 2063 | RegStorage numerator_reg; |
| 2064 | if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { |
| 2065 | // We will need the value later. |
| 2066 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2067 | numerator_reg = rl_src.reg; |
| 2068 | OpRegCopyWide(rs_r0q, numerator_reg); |
| 2069 | } else { |
| 2070 | // Only need this once. Just put it into RAX. |
| 2071 | LoadValueDirectWideFixed(rl_src, rs_r0q); |
| 2072 | } |
| 2073 | |
| 2074 | // RDX = magic. |
| 2075 | LoadConstantWide(rs_r2q, magic); |
| 2076 | |
| 2077 | // RDX:RAX = magic & dividend. |
| 2078 | NewLIR1(kX86Imul64DaR, rs_r2q.GetReg()); |
| 2079 | |
| 2080 | if (imm > 0 && magic < 0) { |
| 2081 | // Add numerator to RDX. |
| 2082 | DCHECK(numerator_reg.Valid()); |
| 2083 | OpRegReg(kOpAdd, rs_r2q, numerator_reg); |
| 2084 | } else if (imm < 0 && magic > 0) { |
| 2085 | DCHECK(numerator_reg.Valid()); |
| 2086 | OpRegReg(kOpSub, rs_r2q, numerator_reg); |
| 2087 | } |
| 2088 | |
| 2089 | // Do we need the shift? |
| 2090 | if (shift != 0) { |
| 2091 | // Shift RDX by 'shift' bits. |
| 2092 | OpRegImm(kOpAsr, rs_r2q, shift); |
| 2093 | } |
| 2094 | |
| 2095 | // Move RDX to RAX. |
| 2096 | OpRegCopyWide(rs_r0q, rs_r2q); |
| 2097 | |
| 2098 | // Move sign bit to bit 0, zeroing the rest. |
| 2099 | OpRegImm(kOpLsr, rs_r2q, 63); |
| 2100 | |
| 2101 | // RDX = RDX + RAX. |
| 2102 | OpRegReg(kOpAdd, rs_r2q, rs_r0q); |
| 2103 | |
| 2104 | // Quotient is in RDX. |
| 2105 | if (!is_div) { |
| 2106 | // We need to compute the remainder. |
| 2107 | // Remainder is divisor - (quotient * imm). |
| 2108 | DCHECK(numerator_reg.Valid()); |
| 2109 | OpRegCopyWide(rs_r0q, numerator_reg); |
| 2110 | |
| 2111 | // Imul doesn't support 64-bit imms. |
| 2112 | if (imm > std::numeric_limits<int32_t>::max() || |
| 2113 | imm < std::numeric_limits<int32_t>::min()) { |
| 2114 | RegStorage rs_temp = AllocTempWide(); |
| 2115 | LoadConstantWide(rs_temp, imm); |
| 2116 | |
| 2117 | // RAX = numerator * imm. |
| 2118 | NewLIR2(kX86Imul64RR, rs_r2q.GetReg(), rs_temp.GetReg()); |
| 2119 | |
| 2120 | FreeTemp(rs_temp); |
| 2121 | } else { |
| 2122 | // RAX = numerator * imm. |
| 2123 | int short_imm = static_cast<int>(imm); |
| 2124 | NewLIR3(kX86Imul64RRI, rs_r2q.GetReg(), rs_r2q.GetReg(), short_imm); |
| 2125 | } |
| 2126 | |
| 2127 | // RDX -= RAX. |
| 2128 | OpRegReg(kOpSub, rs_r0q, rs_r2q); |
| 2129 | |
| 2130 | // Store result. |
| 2131 | OpRegCopyWide(rl_result.reg, rs_r0q); |
| 2132 | } else { |
| 2133 | // Store result. |
| 2134 | OpRegCopyWide(rl_result.reg, rs_r2q); |
| 2135 | } |
| 2136 | StoreValueWide(rl_dest, rl_result); |
| 2137 | FreeTemp(rs_r0q); |
| 2138 | FreeTemp(rs_r2q); |
| 2139 | } |
| 2140 | } |
| 2141 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2142 | void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2143 | RegLocation rl_src2, bool is_div) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2144 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2145 | LOG(FATAL) << "Unexpected use GenDivRemLong()"; |
| 2146 | return; |
| 2147 | } |
| 2148 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2149 | if (rl_src2.is_const) { |
| 2150 | DCHECK(rl_src2.wide); |
| 2151 | int64_t imm = mir_graph_->ConstantValueWide(rl_src2); |
| 2152 | GenDivRemLongLit(rl_dest, rl_src1, imm, is_div); |
| 2153 | return; |
| 2154 | } |
| 2155 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2156 | // We have to use fixed registers, so flush all the temps. |
| 2157 | FlushAllRegs(); |
| 2158 | LockCallTemps(); // Prepare for explicit register usage. |
| 2159 | |
| 2160 | // Load LHS into RAX. |
| 2161 | LoadValueDirectWideFixed(rl_src1, rs_r0q); |
| 2162 | |
| 2163 | // Load RHS into RCX. |
| 2164 | LoadValueDirectWideFixed(rl_src2, rs_r1q); |
| 2165 | |
| 2166 | // Copy LHS sign bit into RDX. |
| 2167 | NewLIR0(kx86Cqo64Da); |
| 2168 | |
| 2169 | // Handle division by zero case. |
| 2170 | GenDivZeroCheckWide(rs_r1q); |
| 2171 | |
| 2172 | // Have to catch 0x8000000000000000/-1 case, or we will get an exception! |
| 2173 | NewLIR2(kX86Cmp64RI8, rs_r1q.GetReg(), -1); |
| 2174 | LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 2175 | |
| 2176 | // RHS is -1. |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2177 | LoadConstantWide(rs_r6q, 0x8000000000000000); |
| 2178 | NewLIR2(kX86Cmp64RR, rs_r0q.GetReg(), rs_r6q.GetReg()); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2179 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2180 | |
| 2181 | // In 0x8000000000000000/-1 case. |
| 2182 | if (!is_div) { |
| 2183 | // For DIV, RAX is already right. For REM, we need RDX 0. |
| 2184 | NewLIR2(kX86Xor64RR, rs_r2q.GetReg(), rs_r2q.GetReg()); |
| 2185 | } |
| 2186 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 2187 | |
| 2188 | // Expected case. |
| 2189 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 2190 | minint_branch->target = minus_one_branch->target; |
| 2191 | NewLIR1(kX86Idivmod64DaR, rs_r1q.GetReg()); |
| 2192 | done->target = NewLIR0(kPseudoTargetLabel); |
| 2193 | |
| 2194 | // Result is in RAX for div and RDX for rem. |
| 2195 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r0q, INVALID_SREG, INVALID_SREG}; |
| 2196 | if (!is_div) { |
| 2197 | rl_result.reg.SetReg(r2q); |
| 2198 | } |
| 2199 | |
| 2200 | StoreValueWide(rl_dest, rl_result); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2201 | } |
| 2202 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 2203 | void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2204 | rl_src = LoadValueWide(rl_src, kCoreReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2205 | RegLocation rl_result; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2206 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2207 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2208 | OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); |
| 2209 | } else { |
| 2210 | rl_result = ForceTempWide(rl_src); |
| 2211 | if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) && |
| 2212 | ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) { |
| 2213 | // The registers are the same, so we would clobber it before the use. |
| 2214 | RegStorage temp_reg = AllocTemp(); |
| 2215 | OpRegCopy(temp_reg, rl_result.reg); |
| 2216 | rl_result.reg.SetHighReg(temp_reg.GetReg()); |
| 2217 | } |
| 2218 | OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow |
| 2219 | OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF |
| 2220 | OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2221 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2222 | StoreValueWide(rl_dest, rl_result); |
| 2223 | } |
| 2224 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2225 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 2226 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 2227 | X86OpCode opcode = kX86Bkpt; |
| 2228 | switch (op) { |
| 2229 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2230 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2231 | default: |
| 2232 | LOG(FATAL) << "Bad opcode: " << op; |
| 2233 | break; |
| 2234 | } |
| 2235 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
| 2236 | } |
| 2237 | |
| 2238 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { |
| 2239 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2240 | X86OpCode opcode = kX86Bkpt; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2241 | if (cu_->target64 && r_dest.Is64BitSolo()) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 2242 | switch (op) { |
| 2243 | case kOpCmp: opcode = kX86Cmp64RT; break; |
| 2244 | case kOpMov: opcode = kX86Mov64RT; break; |
| 2245 | default: |
| 2246 | LOG(FATAL) << "Bad opcode(OpRegThreadMem 64): " << op; |
| 2247 | break; |
| 2248 | } |
| 2249 | } else { |
| 2250 | switch (op) { |
| 2251 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2252 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2253 | default: |
| 2254 | LOG(FATAL) << "Bad opcode: " << op; |
| 2255 | break; |
| 2256 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2257 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2258 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2259 | } |
| 2260 | |
| 2261 | /* |
| 2262 | * Generate array load |
| 2263 | */ |
| 2264 | void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2265 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2266 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2267 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2268 | RegLocation rl_result; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2269 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2270 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2271 | int data_offset; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2272 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2273 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2274 | } else { |
| 2275 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2276 | } |
| 2277 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2278 | bool constant_index = rl_index.is_const; |
| 2279 | int32_t constant_index_value = 0; |
| 2280 | if (!constant_index) { |
| 2281 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2282 | } else { |
| 2283 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2284 | // If index is constant, just fold it into the data offset |
| 2285 | data_offset += constant_index_value << scale; |
| 2286 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2287 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2288 | } |
| 2289 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2290 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2291 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2292 | |
| 2293 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2294 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2295 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2296 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2297 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2298 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2299 | } |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2300 | rl_result = EvalLoc(rl_dest, reg_class, true); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 2301 | LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2302 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2303 | StoreValueWide(rl_dest, rl_result); |
| 2304 | } else { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2305 | StoreValue(rl_dest, rl_result); |
| 2306 | } |
| 2307 | } |
| 2308 | |
| 2309 | /* |
| 2310 | * Generate array store |
| 2311 | * |
| 2312 | */ |
| 2313 | void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2314 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2315 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2316 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 2317 | int data_offset; |
| 2318 | |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2319 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2320 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2321 | } else { |
| 2322 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2323 | } |
| 2324 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2325 | rl_array = LoadValue(rl_array, kRefReg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2326 | bool constant_index = rl_index.is_const; |
| 2327 | int32_t constant_index_value = 0; |
| 2328 | if (!constant_index) { |
| 2329 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2330 | } else { |
| 2331 | // If index is constant, just fold it into the data offset |
| 2332 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2333 | data_offset += constant_index_value << scale; |
| 2334 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2335 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2336 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2337 | |
| 2338 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2339 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2340 | |
| 2341 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2342 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2343 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2344 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2345 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2346 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2347 | } |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2348 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2349 | rl_src = LoadValueWide(rl_src, reg_class); |
| 2350 | } else { |
| 2351 | rl_src = LoadValue(rl_src, reg_class); |
| 2352 | } |
| 2353 | // If the src reg can't be byte accessed, move it to a temp first. |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2354 | if ((size == kSignedByte || size == kUnsignedByte) && !IsByteRegister(rl_src.reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2355 | RegStorage temp = AllocTemp(); |
| 2356 | OpRegCopy(temp, rl_src.reg); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 2357 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2358 | } else { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 2359 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2360 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2361 | if (card_mark) { |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 2362 | // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2363 | if (!constant_index) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2364 | FreeTemp(rl_index.reg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2365 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2366 | MarkGCCard(rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2367 | } |
| 2368 | } |
| 2369 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2370 | RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 2371 | RegLocation rl_src, int shift_amount) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2372 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2373 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2374 | OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ |
| 2375 | switch (opcode) { |
| 2376 | case Instruction::SHL_LONG: |
| 2377 | case Instruction::SHL_LONG_2ADDR: |
| 2378 | op = kOpLsl; |
| 2379 | break; |
| 2380 | case Instruction::SHR_LONG: |
| 2381 | case Instruction::SHR_LONG_2ADDR: |
| 2382 | op = kOpAsr; |
| 2383 | break; |
| 2384 | case Instruction::USHR_LONG: |
| 2385 | case Instruction::USHR_LONG_2ADDR: |
| 2386 | op = kOpLsr; |
| 2387 | break; |
| 2388 | default: |
| 2389 | LOG(FATAL) << "Unexpected case"; |
| 2390 | } |
| 2391 | OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount); |
| 2392 | } else { |
| 2393 | switch (opcode) { |
| 2394 | case Instruction::SHL_LONG: |
| 2395 | case Instruction::SHL_LONG_2ADDR: |
| 2396 | DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. |
| 2397 | if (shift_amount == 32) { |
| 2398 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2399 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2400 | } else if (shift_amount > 31) { |
| 2401 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2402 | NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); |
| 2403 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2404 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2405 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2406 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2407 | NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), |
| 2408 | shift_amount); |
| 2409 | NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); |
| 2410 | } |
| 2411 | break; |
| 2412 | case Instruction::SHR_LONG: |
| 2413 | case Instruction::SHR_LONG_2ADDR: |
| 2414 | if (shift_amount == 32) { |
| 2415 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2416 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2417 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2418 | } else if (shift_amount > 31) { |
| 2419 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2420 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2421 | NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2422 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2423 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2424 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2425 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2426 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2427 | shift_amount); |
| 2428 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2429 | } |
| 2430 | break; |
| 2431 | case Instruction::USHR_LONG: |
| 2432 | case Instruction::USHR_LONG_2ADDR: |
| 2433 | if (shift_amount == 32) { |
| 2434 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2435 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2436 | } else if (shift_amount > 31) { |
| 2437 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2438 | NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2439 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2440 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2441 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2442 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2443 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2444 | shift_amount); |
| 2445 | NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2446 | } |
| 2447 | break; |
| 2448 | default: |
| 2449 | LOG(FATAL) << "Unexpected case"; |
| 2450 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2451 | } |
| 2452 | return rl_result; |
| 2453 | } |
| 2454 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2455 | void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2456 | RegLocation rl_src, RegLocation rl_shift) { |
| 2457 | // Per spec, we only care about low 6 bits of shift amount. |
| 2458 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 2459 | if (shift_amount == 0) { |
| 2460 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2461 | StoreValueWide(rl_dest, rl_src); |
| 2462 | return; |
| 2463 | } else if (shift_amount == 1 && |
| 2464 | (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { |
| 2465 | // Need to handle this here to avoid calling StoreValueWide twice. |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 2466 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2467 | return; |
| 2468 | } |
| 2469 | if (BadOverlap(rl_src, rl_dest)) { |
| 2470 | GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); |
| 2471 | return; |
| 2472 | } |
| 2473 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2474 | RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount); |
| 2475 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2476 | } |
| 2477 | |
| 2478 | void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 2479 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2480 | bool isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2481 | switch (opcode) { |
| 2482 | case Instruction::ADD_LONG: |
| 2483 | case Instruction::AND_LONG: |
| 2484 | case Instruction::OR_LONG: |
| 2485 | case Instruction::XOR_LONG: |
| 2486 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2487 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2488 | } else { |
| 2489 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2490 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2491 | } |
| 2492 | break; |
| 2493 | case Instruction::SUB_LONG: |
| 2494 | case Instruction::SUB_LONG_2ADDR: |
| 2495 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2496 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2497 | } else { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 2498 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2499 | isConstSuccess = true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2500 | } |
| 2501 | break; |
| 2502 | case Instruction::ADD_LONG_2ADDR: |
| 2503 | case Instruction::OR_LONG_2ADDR: |
| 2504 | case Instruction::XOR_LONG_2ADDR: |
| 2505 | case Instruction::AND_LONG_2ADDR: |
| 2506 | if (rl_src2.is_const) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2507 | if (GenerateTwoOperandInstructions()) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2508 | isConstSuccess = GenLongImm(rl_dest, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2509 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2510 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2511 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2512 | } else { |
| 2513 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2514 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2515 | } |
| 2516 | break; |
| 2517 | default: |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2518 | isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2519 | break; |
| 2520 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2521 | |
| 2522 | if (!isConstSuccess) { |
| 2523 | // Default - bail to non-const handler. |
| 2524 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 2525 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2526 | } |
| 2527 | |
| 2528 | bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { |
| 2529 | switch (op) { |
| 2530 | case Instruction::AND_LONG_2ADDR: |
| 2531 | case Instruction::AND_LONG: |
| 2532 | return value == -1; |
| 2533 | case Instruction::OR_LONG: |
| 2534 | case Instruction::OR_LONG_2ADDR: |
| 2535 | case Instruction::XOR_LONG: |
| 2536 | case Instruction::XOR_LONG_2ADDR: |
| 2537 | return value == 0; |
| 2538 | default: |
| 2539 | return false; |
| 2540 | } |
| 2541 | } |
| 2542 | |
| 2543 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 2544 | bool is_high_op) { |
| 2545 | bool rhs_in_mem = rhs.location != kLocPhysReg; |
| 2546 | bool dest_in_mem = dest.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2547 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2548 | DCHECK(!rhs_in_mem || !dest_in_mem); |
| 2549 | switch (op) { |
| 2550 | case Instruction::ADD_LONG: |
| 2551 | case Instruction::ADD_LONG_2ADDR: |
| 2552 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2553 | return is64Bit ? kX86Add64MR : is_high_op ? kX86Adc32MR : kX86Add32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2554 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2555 | return is64Bit ? kX86Add64RM : is_high_op ? kX86Adc32RM : kX86Add32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2556 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2557 | return is64Bit ? kX86Add64RR : is_high_op ? kX86Adc32RR : kX86Add32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2558 | case Instruction::SUB_LONG: |
| 2559 | case Instruction::SUB_LONG_2ADDR: |
| 2560 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2561 | return is64Bit ? kX86Sub64MR : is_high_op ? kX86Sbb32MR : kX86Sub32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2562 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2563 | return is64Bit ? kX86Sub64RM : is_high_op ? kX86Sbb32RM : kX86Sub32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2564 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2565 | return is64Bit ? kX86Sub64RR : is_high_op ? kX86Sbb32RR : kX86Sub32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2566 | case Instruction::AND_LONG_2ADDR: |
| 2567 | case Instruction::AND_LONG: |
| 2568 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2569 | return is64Bit ? kX86And64MR : kX86And32MR; |
| 2570 | } |
| 2571 | if (is64Bit) { |
| 2572 | return rhs_in_mem ? kX86And64RM : kX86And64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2573 | } |
| 2574 | return rhs_in_mem ? kX86And32RM : kX86And32RR; |
| 2575 | case Instruction::OR_LONG: |
| 2576 | case Instruction::OR_LONG_2ADDR: |
| 2577 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2578 | return is64Bit ? kX86Or64MR : kX86Or32MR; |
| 2579 | } |
| 2580 | if (is64Bit) { |
| 2581 | return rhs_in_mem ? kX86Or64RM : kX86Or64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2582 | } |
| 2583 | return rhs_in_mem ? kX86Or32RM : kX86Or32RR; |
| 2584 | case Instruction::XOR_LONG: |
| 2585 | case Instruction::XOR_LONG_2ADDR: |
| 2586 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2587 | return is64Bit ? kX86Xor64MR : kX86Xor32MR; |
| 2588 | } |
| 2589 | if (is64Bit) { |
| 2590 | return rhs_in_mem ? kX86Xor64RM : kX86Xor64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2591 | } |
| 2592 | return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; |
| 2593 | default: |
| 2594 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 2595 | return kX86Add32RR; |
| 2596 | } |
| 2597 | } |
| 2598 | |
| 2599 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, |
| 2600 | int32_t value) { |
| 2601 | bool in_mem = loc.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2602 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2603 | bool byte_imm = IS_SIMM8(value); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2604 | DCHECK(in_mem || !loc.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2605 | switch (op) { |
| 2606 | case Instruction::ADD_LONG: |
| 2607 | case Instruction::ADD_LONG_2ADDR: |
| 2608 | if (byte_imm) { |
| 2609 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2610 | return is64Bit ? kX86Add64MI8 : is_high_op ? kX86Adc32MI8 : kX86Add32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2611 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2612 | return is64Bit ? kX86Add64RI8 : is_high_op ? kX86Adc32RI8 : kX86Add32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2613 | } |
| 2614 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2615 | return is64Bit ? kX86Add64MI : is_high_op ? kX86Adc32MI : kX86Add32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2616 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2617 | return is64Bit ? kX86Add64RI : is_high_op ? kX86Adc32RI : kX86Add32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2618 | case Instruction::SUB_LONG: |
| 2619 | case Instruction::SUB_LONG_2ADDR: |
| 2620 | if (byte_imm) { |
| 2621 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2622 | return is64Bit ? kX86Sub64MI8 : is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2623 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2624 | return is64Bit ? kX86Sub64RI8 : is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2625 | } |
| 2626 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2627 | return is64Bit ? kX86Sub64MI : is_high_op ? kX86Sbb32MI : kX86Sub32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2628 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2629 | return is64Bit ? kX86Sub64RI : is_high_op ? kX86Sbb32RI : kX86Sub32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2630 | case Instruction::AND_LONG_2ADDR: |
| 2631 | case Instruction::AND_LONG: |
| 2632 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2633 | if (is64Bit) { |
| 2634 | return in_mem ? kX86And64MI8 : kX86And64RI8; |
| 2635 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2636 | return in_mem ? kX86And32MI8 : kX86And32RI8; |
| 2637 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2638 | if (is64Bit) { |
| 2639 | return in_mem ? kX86And64MI : kX86And64RI; |
| 2640 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2641 | return in_mem ? kX86And32MI : kX86And32RI; |
| 2642 | case Instruction::OR_LONG: |
| 2643 | case Instruction::OR_LONG_2ADDR: |
| 2644 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2645 | if (is64Bit) { |
| 2646 | return in_mem ? kX86Or64MI8 : kX86Or64RI8; |
| 2647 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2648 | return in_mem ? kX86Or32MI8 : kX86Or32RI8; |
| 2649 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2650 | if (is64Bit) { |
| 2651 | return in_mem ? kX86Or64MI : kX86Or64RI; |
| 2652 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2653 | return in_mem ? kX86Or32MI : kX86Or32RI; |
| 2654 | case Instruction::XOR_LONG: |
| 2655 | case Instruction::XOR_LONG_2ADDR: |
| 2656 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2657 | if (is64Bit) { |
| 2658 | return in_mem ? kX86Xor64MI8 : kX86Xor64RI8; |
| 2659 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2660 | return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; |
| 2661 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2662 | if (is64Bit) { |
| 2663 | return in_mem ? kX86Xor64MI : kX86Xor64RI; |
| 2664 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2665 | return in_mem ? kX86Xor32MI : kX86Xor32RI; |
| 2666 | default: |
| 2667 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 2668 | return kX86Add32MI; |
| 2669 | } |
| 2670 | } |
| 2671 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2672 | bool X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2673 | DCHECK(rl_src.is_const); |
| 2674 | int64_t val = mir_graph_->ConstantValueWide(rl_src); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2675 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2676 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2677 | // We can do with imm only if it fits 32 bit |
| 2678 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2679 | return false; |
| 2680 | } |
| 2681 | |
| 2682 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 2683 | |
| 2684 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2685 | (rl_dest.location == kLocCompilerTemp)) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2686 | int r_base = rs_rX86_SP.GetReg(); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2687 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2688 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2689 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2690 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
| 2691 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); |
| 2692 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2693 | true /* is_load */, true /* is64bit */); |
| 2694 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2695 | false /* is_load */, true /* is64bit */); |
| 2696 | return true; |
| 2697 | } |
| 2698 | |
| 2699 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2700 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
| 2701 | DCHECK(!rl_result.reg.IsFloat()); |
| 2702 | |
| 2703 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2704 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2705 | |
| 2706 | StoreValueWide(rl_dest, rl_result); |
| 2707 | return true; |
| 2708 | } |
| 2709 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2710 | int32_t val_lo = Low32Bits(val); |
| 2711 | int32_t val_hi = High32Bits(val); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2712 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2713 | |
| 2714 | // Can we just do this into memory? |
| 2715 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2716 | (rl_dest.location == kLocCompilerTemp)) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2717 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2718 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2719 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2720 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2721 | if (!IsNoOp(op, val_lo)) { |
| 2722 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2723 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2724 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2725 | true /* is_load */, true /* is64bit */); |
| 2726 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2727 | false /* is_load */, true /* is64bit */); |
| 2728 | } |
| 2729 | if (!IsNoOp(op, val_hi)) { |
| 2730 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2731 | LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2732 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2733 | true /* is_load */, true /* is64bit */); |
| 2734 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2735 | false /* is_load */, true /* is64bit */); |
| 2736 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2737 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2738 | } |
| 2739 | |
| 2740 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2741 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2742 | DCHECK(!rl_result.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2743 | |
| 2744 | if (!IsNoOp(op, val_lo)) { |
| 2745 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2746 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2747 | } |
| 2748 | if (!IsNoOp(op, val_hi)) { |
| 2749 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2750 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2751 | } |
| 2752 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2753 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2754 | } |
| 2755 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2756 | bool X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2757 | RegLocation rl_src2, Instruction::Code op) { |
| 2758 | DCHECK(rl_src2.is_const); |
| 2759 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2760 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2761 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2762 | // We can do with imm only if it fits 32 bit |
| 2763 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2764 | return false; |
| 2765 | } |
| 2766 | if (rl_dest.location == kLocPhysReg && |
| 2767 | rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) { |
| 2768 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2769 | OpRegCopy(rl_dest.reg, rl_src1.reg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2770 | NewLIR2(x86op, rl_dest.reg.GetReg(), val); |
| 2771 | StoreFinalValueWide(rl_dest, rl_dest); |
| 2772 | return true; |
| 2773 | } |
| 2774 | |
| 2775 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2776 | // We need the values to be in a temporary |
| 2777 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2778 | |
| 2779 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2780 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2781 | |
| 2782 | StoreFinalValueWide(rl_dest, rl_result); |
| 2783 | return true; |
| 2784 | } |
| 2785 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2786 | int32_t val_lo = Low32Bits(val); |
| 2787 | int32_t val_hi = High32Bits(val); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2788 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 2789 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2790 | |
| 2791 | // Can we do this directly into the destination registers? |
| 2792 | if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2793 | rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2794 | rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2795 | if (!IsNoOp(op, val_lo)) { |
| 2796 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2797 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2798 | } |
| 2799 | if (!IsNoOp(op, val_hi)) { |
| 2800 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2801 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2802 | } |
Maxim Kazantsev | 653f2bf | 2014-02-13 15:11:17 +0700 | [diff] [blame] | 2803 | |
| 2804 | StoreFinalValueWide(rl_dest, rl_dest); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2805 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2806 | } |
| 2807 | |
| 2808 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2809 | DCHECK_EQ(rl_src1.location, kLocPhysReg); |
| 2810 | |
| 2811 | // We need the values to be in a temporary |
| 2812 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2813 | if (!IsNoOp(op, val_lo)) { |
| 2814 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2815 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2816 | } |
| 2817 | if (!IsNoOp(op, val_hi)) { |
| 2818 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2819 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2820 | } |
| 2821 | |
| 2822 | StoreFinalValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2823 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2824 | } |
| 2825 | |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2826 | // For final classes there are no sub-classes to check and so we can answer the instance-of |
| 2827 | // question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. |
| 2828 | void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, |
| 2829 | RegLocation rl_dest, RegLocation rl_src) { |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2830 | RegLocation object = LoadValue(rl_src, kRefReg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2831 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2832 | RegStorage result_reg = rl_result.reg; |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2833 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2834 | // For 32-bit, SETcc only works with EAX..EDX. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2835 | RegStorage object_32reg = object.reg.Is64Bit() ? As32BitReg(object.reg) : object.reg; |
Dmitry Petrochenko | 407f5c1 | 2014-07-01 01:21:38 +0700 | [diff] [blame] | 2836 | if (result_reg.GetRegNum() == object_32reg.GetRegNum() || !IsByteRegister(result_reg)) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2837 | result_reg = AllocateByteRegister(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2838 | } |
| 2839 | |
| 2840 | // Assume that there is no match. |
| 2841 | LoadConstant(result_reg, 0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2842 | LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2843 | |
Mark Mendell | ade54a2 | 2014-06-09 12:49:55 -0400 | [diff] [blame] | 2844 | // We will use this register to compare to memory below. |
| 2845 | // References are 32 bit in memory, and 64 bit in registers (in 64 bit mode). |
| 2846 | // For this reason, force allocation of a 32 bit register to use, so that the |
| 2847 | // compare to memory will be done using a 32 bit comparision. |
| 2848 | // The LoadRefDisp(s) below will work normally, even in 64 bit mode. |
| 2849 | RegStorage check_class = AllocTemp(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2850 | |
| 2851 | // If Method* is already in a register, we can save a copy. |
| 2852 | RegLocation rl_method = mir_graph_->GetMethodLoc(); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2853 | int32_t offset_of_type = mirror::Array::DataOffset( |
| 2854 | sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + |
| 2855 | (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2856 | |
| 2857 | if (rl_method.location == kLocPhysReg) { |
| 2858 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2859 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2860 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2861 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2862 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2863 | check_class, kNotVolatile); |
| 2864 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2865 | } |
| 2866 | } else { |
| 2867 | LoadCurrMethodDirect(check_class); |
| 2868 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2869 | LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2870 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2871 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2872 | LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2873 | check_class, kNotVolatile); |
| 2874 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2875 | } |
| 2876 | } |
| 2877 | |
| 2878 | // Compare the computed class to the class in the object. |
| 2879 | DCHECK_EQ(object.location, kLocPhysReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2880 | OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2881 | |
| 2882 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2883 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2884 | |
| 2885 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 2886 | null_branchover->target = target; |
| 2887 | FreeTemp(check_class); |
| 2888 | if (IsTemp(result_reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2889 | OpRegCopy(rl_result.reg, result_reg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2890 | FreeTemp(result_reg); |
| 2891 | } |
| 2892 | StoreValue(rl_dest, rl_result); |
| 2893 | } |
| 2894 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2895 | void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, |
| 2896 | RegLocation rl_lhs, RegLocation rl_rhs) { |
| 2897 | OpKind op = kOpBkpt; |
| 2898 | bool is_div_rem = false; |
| 2899 | bool unary = false; |
| 2900 | bool shift_op = false; |
| 2901 | bool is_two_addr = false; |
| 2902 | RegLocation rl_result; |
| 2903 | switch (opcode) { |
| 2904 | case Instruction::NEG_INT: |
| 2905 | op = kOpNeg; |
| 2906 | unary = true; |
| 2907 | break; |
| 2908 | case Instruction::NOT_INT: |
| 2909 | op = kOpMvn; |
| 2910 | unary = true; |
| 2911 | break; |
| 2912 | case Instruction::ADD_INT_2ADDR: |
| 2913 | is_two_addr = true; |
| 2914 | // Fallthrough |
| 2915 | case Instruction::ADD_INT: |
| 2916 | op = kOpAdd; |
| 2917 | break; |
| 2918 | case Instruction::SUB_INT_2ADDR: |
| 2919 | is_two_addr = true; |
| 2920 | // Fallthrough |
| 2921 | case Instruction::SUB_INT: |
| 2922 | op = kOpSub; |
| 2923 | break; |
| 2924 | case Instruction::MUL_INT_2ADDR: |
| 2925 | is_two_addr = true; |
| 2926 | // Fallthrough |
| 2927 | case Instruction::MUL_INT: |
| 2928 | op = kOpMul; |
| 2929 | break; |
| 2930 | case Instruction::DIV_INT_2ADDR: |
| 2931 | is_two_addr = true; |
| 2932 | // Fallthrough |
| 2933 | case Instruction::DIV_INT: |
| 2934 | op = kOpDiv; |
| 2935 | is_div_rem = true; |
| 2936 | break; |
| 2937 | /* NOTE: returns in kArg1 */ |
| 2938 | case Instruction::REM_INT_2ADDR: |
| 2939 | is_two_addr = true; |
| 2940 | // Fallthrough |
| 2941 | case Instruction::REM_INT: |
| 2942 | op = kOpRem; |
| 2943 | is_div_rem = true; |
| 2944 | break; |
| 2945 | case Instruction::AND_INT_2ADDR: |
| 2946 | is_two_addr = true; |
| 2947 | // Fallthrough |
| 2948 | case Instruction::AND_INT: |
| 2949 | op = kOpAnd; |
| 2950 | break; |
| 2951 | case Instruction::OR_INT_2ADDR: |
| 2952 | is_two_addr = true; |
| 2953 | // Fallthrough |
| 2954 | case Instruction::OR_INT: |
| 2955 | op = kOpOr; |
| 2956 | break; |
| 2957 | case Instruction::XOR_INT_2ADDR: |
| 2958 | is_two_addr = true; |
| 2959 | // Fallthrough |
| 2960 | case Instruction::XOR_INT: |
| 2961 | op = kOpXor; |
| 2962 | break; |
| 2963 | case Instruction::SHL_INT_2ADDR: |
| 2964 | is_two_addr = true; |
| 2965 | // Fallthrough |
| 2966 | case Instruction::SHL_INT: |
| 2967 | shift_op = true; |
| 2968 | op = kOpLsl; |
| 2969 | break; |
| 2970 | case Instruction::SHR_INT_2ADDR: |
| 2971 | is_two_addr = true; |
| 2972 | // Fallthrough |
| 2973 | case Instruction::SHR_INT: |
| 2974 | shift_op = true; |
| 2975 | op = kOpAsr; |
| 2976 | break; |
| 2977 | case Instruction::USHR_INT_2ADDR: |
| 2978 | is_two_addr = true; |
| 2979 | // Fallthrough |
| 2980 | case Instruction::USHR_INT: |
| 2981 | shift_op = true; |
| 2982 | op = kOpLsr; |
| 2983 | break; |
| 2984 | default: |
| 2985 | LOG(FATAL) << "Invalid word arith op: " << opcode; |
| 2986 | } |
| 2987 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2988 | // Can we convert to a two address instruction? |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2989 | if (!is_two_addr && |
| 2990 | (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 2991 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2992 | is_two_addr = true; |
| 2993 | } |
| 2994 | |
| 2995 | if (!GenerateTwoOperandInstructions()) { |
| 2996 | is_two_addr = false; |
| 2997 | } |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2998 | |
| 2999 | // Get the div/rem stuff out of the way. |
| 3000 | if (is_div_rem) { |
| 3001 | rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, true); |
| 3002 | StoreValue(rl_dest, rl_result); |
| 3003 | return; |
| 3004 | } |
| 3005 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3006 | // If we generate any memory access below, it will reference a dalvik reg. |
| 3007 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 3008 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3009 | if (unary) { |
| 3010 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3011 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3012 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3013 | OpRegReg(op, rl_result.reg, rl_lhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3014 | } else { |
| 3015 | if (shift_op) { |
| 3016 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 3017 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3018 | LoadValueDirectFixed(rl_rhs, t_reg); |
| 3019 | if (is_two_addr) { |
| 3020 | // Can we do this directly into memory? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3021 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3022 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3023 | if (rl_result.location != kLocPhysReg) { |
| 3024 | // Okay, we can do this into memory |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3025 | OpMemReg(op, rl_result, t_reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3026 | FreeTemp(t_reg); |
| 3027 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3028 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3029 | // Can do this directly into the result register |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3030 | OpRegReg(op, rl_result.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3031 | FreeTemp(t_reg); |
| 3032 | StoreFinalValue(rl_dest, rl_result); |
| 3033 | return; |
| 3034 | } |
| 3035 | } |
| 3036 | // Three address form, or we can't do directly. |
| 3037 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3038 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3039 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3040 | FreeTemp(t_reg); |
| 3041 | } else { |
| 3042 | // Multiply is 3 operand only (sort of). |
| 3043 | if (is_two_addr && op != kOpMul) { |
| 3044 | // Can we do this directly into memory? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3045 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3046 | if (rl_result.location == kLocPhysReg) { |
Serguei Katkov | 366f8ae | 2014-04-15 16:55:26 +0700 | [diff] [blame] | 3047 | // Ensure res is in a core reg |
| 3048 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3049 | // Can we do this from memory directly? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3050 | rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3051 | if (rl_rhs.location != kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3052 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3053 | StoreFinalValue(rl_dest, rl_result); |
| 3054 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3055 | } else if (!rl_rhs.reg.IsFloat()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3056 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3057 | StoreFinalValue(rl_dest, rl_result); |
| 3058 | return; |
| 3059 | } |
| 3060 | } |
| 3061 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
Serguei Katkov | d293fb4 | 2014-05-19 15:45:42 +0700 | [diff] [blame] | 3062 | // It might happen rl_rhs and rl_dest are the same VR |
| 3063 | // in this case rl_dest is in reg after LoadValue while |
| 3064 | // rl_result is not updated yet, so do this |
| 3065 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3066 | if (rl_result.location != kLocPhysReg) { |
| 3067 | // Okay, we can do this into memory. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 3068 | OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3069 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3070 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3071 | // Can do this directly into the result register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3072 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3073 | StoreFinalValue(rl_dest, rl_result); |
| 3074 | return; |
| 3075 | } else { |
| 3076 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3077 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3078 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3079 | } |
| 3080 | } else { |
| 3081 | // Try to use reg/memory instructions. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3082 | rl_lhs = UpdateLocTyped(rl_lhs, kCoreReg); |
| 3083 | rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3084 | // We can't optimize with FP registers. |
| 3085 | if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { |
| 3086 | // Something is difficult, so fall back to the standard case. |
| 3087 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3088 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3089 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3090 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3091 | } else { |
| 3092 | // We can optimize by moving to result and using memory operands. |
| 3093 | if (rl_rhs.location != kLocPhysReg) { |
| 3094 | // Force LHS into result. |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3095 | // We should be careful with order here |
| 3096 | // If rl_dest and rl_lhs points to the same VR we should load first |
| 3097 | // If the are different we should find a register first for dest |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3098 | if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 3099 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3100 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3101 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3102 | // No-op if these are the same. |
| 3103 | OpRegCopy(rl_result.reg, rl_lhs.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3104 | } else { |
| 3105 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3106 | LoadValueDirect(rl_lhs, rl_result.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3107 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3108 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3109 | } else if (rl_lhs.location != kLocPhysReg) { |
| 3110 | // RHS is in a register; LHS is in memory. |
| 3111 | if (op != kOpSub) { |
| 3112 | // Force RHS into result and operate on memory. |
| 3113 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3114 | OpRegCopy(rl_result.reg, rl_rhs.reg); |
| 3115 | OpRegMem(op, rl_result.reg, rl_lhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3116 | } else { |
| 3117 | // Subtraction isn't commutative. |
| 3118 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3119 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3120 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3121 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3122 | } |
| 3123 | } else { |
| 3124 | // Both are in registers. |
| 3125 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3126 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3127 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3128 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3129 | } |
| 3130 | } |
| 3131 | } |
| 3132 | } |
| 3133 | } |
| 3134 | StoreValue(rl_dest, rl_result); |
| 3135 | } |
| 3136 | |
| 3137 | bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { |
| 3138 | // If we have non-core registers, then we can't do good things. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3139 | if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3140 | return false; |
| 3141 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3142 | if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3143 | return false; |
| 3144 | } |
| 3145 | |
| 3146 | // Everything will be fine :-). |
| 3147 | return true; |
| 3148 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3149 | |
| 3150 | void X86Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3151 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3152 | Mir2Lir::GenIntToLong(rl_dest, rl_src); |
| 3153 | return; |
| 3154 | } |
Serguei Katkov | e63d9d4 | 2014-06-25 00:25:35 +0700 | [diff] [blame] | 3155 | rl_src = UpdateLocTyped(rl_src, kCoreReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3156 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 3157 | if (rl_src.location == kLocPhysReg) { |
| 3158 | NewLIR2(kX86MovsxdRR, rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
| 3159 | } else { |
| 3160 | int displacement = SRegOffset(rl_src.s_reg_low); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3161 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3162 | LIR *m = NewLIR3(kX86MovsxdRM, rl_result.reg.GetReg(), rs_rX86_SP.GetReg(), |
| 3163 | displacement + LOWORD_OFFSET); |
| 3164 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 3165 | true /* is_load */, true /* is_64bit */); |
| 3166 | } |
| 3167 | StoreValueWide(rl_dest, rl_result); |
| 3168 | } |
| 3169 | |
| 3170 | void X86Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 3171 | RegLocation rl_src1, RegLocation rl_shift) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3172 | if (!cu_->target64) { |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 3173 | // Long shift operations in 32-bit. Use shld or shrd to create a 32-bit register filled from |
| 3174 | // the other half, shift the other half, if the shift amount is less than 32 we're done, |
| 3175 | // otherwise move one register to the other and place zero or sign bits in the other. |
| 3176 | LIR* branch; |
| 3177 | FlushAllRegs(); |
| 3178 | LockCallTemps(); |
| 3179 | LoadValueDirectFixed(rl_shift, rs_rCX); |
| 3180 | RegStorage r_tmp = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 3181 | LoadValueDirectWideFixed(rl_src1, r_tmp); |
| 3182 | switch (opcode) { |
| 3183 | case Instruction::SHL_LONG: |
| 3184 | case Instruction::SHL_LONG_2ADDR: |
| 3185 | NewLIR3(kX86Shld32RRC, r_tmp.GetHighReg(), r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3186 | NewLIR2(kX86Sal32RC, r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3187 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3188 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3189 | OpRegCopy(r_tmp.GetHigh(), r_tmp.GetLow()); |
| 3190 | LoadConstant(r_tmp.GetLow(), 0); |
| 3191 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3192 | break; |
| 3193 | case Instruction::SHR_LONG: |
| 3194 | case Instruction::SHR_LONG_2ADDR: |
| 3195 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3196 | NewLIR2(kX86Sar32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3197 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3198 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3199 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3200 | NewLIR2(kX86Sar32RI, r_tmp.GetHighReg(), 31); |
| 3201 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3202 | break; |
| 3203 | case Instruction::USHR_LONG: |
| 3204 | case Instruction::USHR_LONG_2ADDR: |
| 3205 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), |
| 3206 | rs_rCX.GetReg()); |
| 3207 | NewLIR2(kX86Shr32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3208 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3209 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3210 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3211 | LoadConstant(r_tmp.GetHigh(), 0); |
| 3212 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3213 | break; |
| 3214 | default: |
| 3215 | LOG(FATAL) << "Unexpected case: " << opcode; |
| 3216 | return; |
| 3217 | } |
| 3218 | RegLocation rl_result = LocCReturnWide(); |
| 3219 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3220 | return; |
| 3221 | } |
| 3222 | |
| 3223 | bool is_two_addr = false; |
| 3224 | OpKind op = kOpBkpt; |
| 3225 | RegLocation rl_result; |
| 3226 | |
| 3227 | switch (opcode) { |
| 3228 | case Instruction::SHL_LONG_2ADDR: |
| 3229 | is_two_addr = true; |
| 3230 | // Fallthrough |
| 3231 | case Instruction::SHL_LONG: |
| 3232 | op = kOpLsl; |
| 3233 | break; |
| 3234 | case Instruction::SHR_LONG_2ADDR: |
| 3235 | is_two_addr = true; |
| 3236 | // Fallthrough |
| 3237 | case Instruction::SHR_LONG: |
| 3238 | op = kOpAsr; |
| 3239 | break; |
| 3240 | case Instruction::USHR_LONG_2ADDR: |
| 3241 | is_two_addr = true; |
| 3242 | // Fallthrough |
| 3243 | case Instruction::USHR_LONG: |
| 3244 | op = kOpLsr; |
| 3245 | break; |
| 3246 | default: |
| 3247 | op = kOpBkpt; |
| 3248 | } |
| 3249 | |
| 3250 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 3251 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3252 | LoadValueDirectFixed(rl_shift, t_reg); |
| 3253 | if (is_two_addr) { |
| 3254 | // Can we do this directly into memory? |
| 3255 | rl_result = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 3256 | if (rl_result.location != kLocPhysReg) { |
| 3257 | // Okay, we can do this into memory |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3258 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3259 | OpMemReg(op, rl_result, t_reg.GetReg()); |
| 3260 | } else if (!rl_result.reg.IsFloat()) { |
| 3261 | // Can do this directly into the result register |
| 3262 | OpRegReg(op, rl_result.reg, t_reg); |
| 3263 | StoreFinalValueWide(rl_dest, rl_result); |
| 3264 | } |
| 3265 | } else { |
| 3266 | // Three address form, or we can't do directly. |
| 3267 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 3268 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 3269 | OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); |
| 3270 | StoreFinalValueWide(rl_dest, rl_result); |
| 3271 | } |
| 3272 | |
| 3273 | FreeTemp(t_reg); |
| 3274 | } |
| 3275 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 3276 | } // namespace art |