jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_UTILS_MIPS_ASSEMBLER_MIPS_H_ |
| 18 | #define ART_COMPILER_UTILS_MIPS_ASSEMBLER_MIPS_H_ |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 19 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 20 | #include <deque> |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 21 | #include <utility> |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 22 | #include <vector> |
Elliott Hughes | 7616005 | 2012-12-12 16:31:20 -0800 | [diff] [blame] | 23 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 24 | #include "arch/mips/instruction_set_features_mips.h" |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 25 | #include "base/arena_containers.h" |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 26 | #include "base/enums.h" |
David Sehr | 1979c64 | 2018-04-26 14:41:18 -0700 | [diff] [blame] | 27 | #include "base/globals.h" |
Elliott Hughes | 7616005 | 2012-12-12 16:31:20 -0800 | [diff] [blame] | 28 | #include "base/macros.h" |
Andreas Gampe | 5678db5 | 2017-06-08 14:11:18 -0700 | [diff] [blame] | 29 | #include "base/stl_util_identity.h" |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 30 | #include "constants_mips.h" |
Andreas Gampe | 09659c2 | 2017-09-18 18:23:32 -0700 | [diff] [blame] | 31 | #include "heap_poisoning.h" |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 32 | #include "managed_register_mips.h" |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 33 | #include "offsets.h" |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 34 | #include "utils/assembler.h" |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 35 | #include "utils/jni_macro_assembler.h" |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 36 | #include "utils/label.h" |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 37 | |
| 38 | namespace art { |
| 39 | namespace mips { |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 40 | |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 41 | static constexpr size_t kMipsHalfwordSize = 2; |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 42 | static constexpr size_t kMipsWordSize = 4; |
| 43 | static constexpr size_t kMipsDoublewordSize = 8; |
| 44 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 45 | enum LoadOperandType { |
| 46 | kLoadSignedByte, |
| 47 | kLoadUnsignedByte, |
| 48 | kLoadSignedHalfword, |
| 49 | kLoadUnsignedHalfword, |
| 50 | kLoadWord, |
Lena Djokic | 2e0a7e5 | 2017-07-06 11:55:24 +0200 | [diff] [blame] | 51 | kLoadDoubleword, |
| 52 | kLoadQuadword |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | enum StoreOperandType { |
| 56 | kStoreByte, |
| 57 | kStoreHalfword, |
| 58 | kStoreWord, |
Lena Djokic | 2e0a7e5 | 2017-07-06 11:55:24 +0200 | [diff] [blame] | 59 | kStoreDoubleword, |
| 60 | kStoreQuadword |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 61 | }; |
| 62 | |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 63 | // Used to test the values returned by ClassS/ClassD. |
| 64 | enum FPClassMaskType { |
| 65 | kSignalingNaN = 0x001, |
| 66 | kQuietNaN = 0x002, |
| 67 | kNegativeInfinity = 0x004, |
| 68 | kNegativeNormal = 0x008, |
| 69 | kNegativeSubnormal = 0x010, |
| 70 | kNegativeZero = 0x020, |
| 71 | kPositiveInfinity = 0x040, |
| 72 | kPositiveNormal = 0x080, |
| 73 | kPositiveSubnormal = 0x100, |
| 74 | kPositiveZero = 0x200, |
| 75 | }; |
| 76 | |
Alexey Frunze | a247dea | 2017-11-03 18:43:04 -0700 | [diff] [blame] | 77 | // Instruction description in terms of input and output registers. |
| 78 | // Used for instruction reordering. |
| 79 | struct InOutRegMasks { |
| 80 | InOutRegMasks() |
| 81 | : gpr_outs_(0), gpr_ins_(0), fpr_outs_(0), fpr_ins_(0), cc_outs_(0), cc_ins_(0) {} |
| 82 | |
| 83 | inline InOutRegMasks& GprOuts(Register reg) { |
| 84 | gpr_outs_ |= (1u << reg); |
| 85 | gpr_outs_ &= ~1u; // Ignore register ZERO. |
| 86 | return *this; |
| 87 | } |
| 88 | template<typename T, typename... Ts> |
| 89 | inline InOutRegMasks& GprOuts(T one, Ts... more) { GprOuts(one); GprOuts(more...); return *this; } |
| 90 | |
| 91 | inline InOutRegMasks& GprIns(Register reg) { |
| 92 | gpr_ins_ |= (1u << reg); |
| 93 | gpr_ins_ &= ~1u; // Ignore register ZERO. |
| 94 | return *this; |
| 95 | } |
| 96 | template<typename T, typename... Ts> |
| 97 | inline InOutRegMasks& GprIns(T one, Ts... more) { GprIns(one); GprIns(more...); return *this; } |
| 98 | |
| 99 | inline InOutRegMasks& GprInOuts(Register reg) { GprIns(reg); GprOuts(reg); return *this; } |
| 100 | template<typename T, typename... Ts> |
| 101 | inline InOutRegMasks& GprInOuts(T one, Ts... more) { |
| 102 | GprInOuts(one); |
| 103 | GprInOuts(more...); |
| 104 | return *this; |
| 105 | } |
| 106 | |
| 107 | inline InOutRegMasks& FprOuts(FRegister reg) { fpr_outs_ |= (1u << reg); return *this; } |
| 108 | inline InOutRegMasks& FprOuts(VectorRegister reg) { return FprOuts(static_cast<FRegister>(reg)); } |
| 109 | template<typename T, typename... Ts> |
| 110 | inline InOutRegMasks& FprOuts(T one, Ts... more) { FprOuts(one); FprOuts(more...); return *this; } |
| 111 | |
| 112 | inline InOutRegMasks& FprIns(FRegister reg) { fpr_ins_ |= (1u << reg); return *this; } |
| 113 | inline InOutRegMasks& FprIns(VectorRegister reg) { return FprIns(static_cast<FRegister>(reg)); } |
| 114 | template<typename T, typename... Ts> |
| 115 | inline InOutRegMasks& FprIns(T one, Ts... more) { FprIns(one); FprIns(more...); return *this; } |
| 116 | |
| 117 | inline InOutRegMasks& FprInOuts(FRegister reg) { FprIns(reg); FprOuts(reg); return *this; } |
| 118 | inline InOutRegMasks& FprInOuts(VectorRegister reg) { |
| 119 | return FprInOuts(static_cast<FRegister>(reg)); |
| 120 | } |
| 121 | template<typename T, typename... Ts> |
| 122 | inline InOutRegMasks& FprInOuts(T one, Ts... more) { |
| 123 | FprInOuts(one); |
| 124 | FprInOuts(more...); |
| 125 | return *this; |
| 126 | } |
| 127 | |
| 128 | inline InOutRegMasks& CcOuts(int cc) { cc_outs_ |= (1u << cc); return *this; } |
| 129 | template<typename T, typename... Ts> |
| 130 | inline InOutRegMasks& CcOuts(T one, Ts... more) { CcOuts(one); CcOuts(more...); return *this; } |
| 131 | |
| 132 | inline InOutRegMasks& CcIns(int cc) { cc_ins_ |= (1u << cc); return *this; } |
| 133 | template<typename T, typename... Ts> |
| 134 | inline InOutRegMasks& CcIns(T one, Ts... more) { CcIns(one); CcIns(more...); return *this; } |
| 135 | |
| 136 | // Mask of output GPRs for the instruction. |
| 137 | uint32_t gpr_outs_; |
| 138 | // Mask of input GPRs for the instruction. |
| 139 | uint32_t gpr_ins_; |
| 140 | // Mask of output FPRs for the instruction. |
| 141 | uint32_t fpr_outs_; |
| 142 | // Mask of input FPRs for the instruction. |
| 143 | uint32_t fpr_ins_; |
| 144 | // Mask of output FPU condition code flags for the instruction. |
| 145 | uint32_t cc_outs_; |
| 146 | // Mask of input FPU condition code flags for the instruction. |
| 147 | uint32_t cc_ins_; |
| 148 | |
| 149 | // TODO: add LO and HI. |
| 150 | }; |
| 151 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 152 | class MipsLabel : public Label { |
| 153 | public: |
| 154 | MipsLabel() : prev_branch_id_plus_one_(0) {} |
| 155 | |
| 156 | MipsLabel(MipsLabel&& src) |
| 157 | : Label(std::move(src)), prev_branch_id_plus_one_(src.prev_branch_id_plus_one_) {} |
| 158 | |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 159 | void AdjustBoundPosition(int delta) { |
| 160 | CHECK(IsBound()); |
| 161 | // Bound label's position is negative, hence decrementing it. |
| 162 | position_ -= delta; |
| 163 | } |
| 164 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 165 | private: |
| 166 | uint32_t prev_branch_id_plus_one_; // To get distance from preceding branch, if any. |
| 167 | |
| 168 | friend class MipsAssembler; |
| 169 | DISALLOW_COPY_AND_ASSIGN(MipsLabel); |
| 170 | }; |
| 171 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 172 | // Assembler literal is a value embedded in code, retrieved using a PC-relative load. |
| 173 | class Literal { |
| 174 | public: |
| 175 | static constexpr size_t kMaxSize = 8; |
| 176 | |
| 177 | Literal(uint32_t size, const uint8_t* data) |
| 178 | : label_(), size_(size) { |
| 179 | DCHECK_LE(size, Literal::kMaxSize); |
| 180 | memcpy(data_, data, size); |
| 181 | } |
| 182 | |
| 183 | template <typename T> |
| 184 | T GetValue() const { |
| 185 | DCHECK_EQ(size_, sizeof(T)); |
| 186 | T value; |
| 187 | memcpy(&value, data_, sizeof(T)); |
| 188 | return value; |
| 189 | } |
| 190 | |
| 191 | uint32_t GetSize() const { |
| 192 | return size_; |
| 193 | } |
| 194 | |
| 195 | const uint8_t* GetData() const { |
| 196 | return data_; |
| 197 | } |
| 198 | |
| 199 | MipsLabel* GetLabel() { |
| 200 | return &label_; |
| 201 | } |
| 202 | |
| 203 | const MipsLabel* GetLabel() const { |
| 204 | return &label_; |
| 205 | } |
| 206 | |
| 207 | private: |
| 208 | MipsLabel label_; |
| 209 | const uint32_t size_; |
| 210 | uint8_t data_[kMaxSize]; |
| 211 | |
| 212 | DISALLOW_COPY_AND_ASSIGN(Literal); |
| 213 | }; |
| 214 | |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 215 | // Jump table: table of labels emitted after the literals. Similar to literals. |
| 216 | class JumpTable { |
| 217 | public: |
| 218 | explicit JumpTable(std::vector<MipsLabel*>&& labels) |
| 219 | : label_(), labels_(std::move(labels)) { |
| 220 | } |
| 221 | |
| 222 | uint32_t GetSize() const { |
| 223 | return static_cast<uint32_t>(labels_.size()) * sizeof(uint32_t); |
| 224 | } |
| 225 | |
| 226 | const std::vector<MipsLabel*>& GetData() const { |
| 227 | return labels_; |
| 228 | } |
| 229 | |
| 230 | MipsLabel* GetLabel() { |
| 231 | return &label_; |
| 232 | } |
| 233 | |
| 234 | const MipsLabel* GetLabel() const { |
| 235 | return &label_; |
| 236 | } |
| 237 | |
| 238 | private: |
| 239 | MipsLabel label_; |
| 240 | std::vector<MipsLabel*> labels_; |
| 241 | |
| 242 | DISALLOW_COPY_AND_ASSIGN(JumpTable); |
| 243 | }; |
| 244 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 245 | // Slowpath entered when Thread::Current()->_exception is non-null. |
| 246 | class MipsExceptionSlowPath { |
| 247 | public: |
| 248 | explicit MipsExceptionSlowPath(MipsManagedRegister scratch, size_t stack_adjust) |
| 249 | : scratch_(scratch), stack_adjust_(stack_adjust) {} |
| 250 | |
| 251 | MipsExceptionSlowPath(MipsExceptionSlowPath&& src) |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 252 | : scratch_(src.scratch_), |
| 253 | stack_adjust_(src.stack_adjust_), |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 254 | exception_entry_(std::move(src.exception_entry_)) {} |
| 255 | |
| 256 | private: |
| 257 | MipsLabel* Entry() { return &exception_entry_; } |
| 258 | const MipsManagedRegister scratch_; |
| 259 | const size_t stack_adjust_; |
| 260 | MipsLabel exception_entry_; |
| 261 | |
| 262 | friend class MipsAssembler; |
| 263 | DISALLOW_COPY_AND_ASSIGN(MipsExceptionSlowPath); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 264 | }; |
| 265 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 266 | class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSize::k32> { |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 267 | public: |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 268 | using JNIBase = JNIMacroAssembler<PointerSize::k32>; |
| 269 | |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 270 | explicit MipsAssembler(ArenaAllocator* allocator, |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 271 | const MipsInstructionSetFeatures* instruction_set_features = nullptr) |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 272 | : Assembler(allocator), |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 273 | overwriting_(false), |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 274 | overwrite_location_(0), |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 275 | reordering_(true), |
| 276 | ds_fsm_state_(kExpectingLabel), |
| 277 | ds_fsm_target_pc_(0), |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 278 | literals_(allocator->Adapter(kArenaAllocAssembler)), |
| 279 | jump_tables_(allocator->Adapter(kArenaAllocAssembler)), |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 280 | last_position_adjustment_(0), |
| 281 | last_old_position_(0), |
| 282 | last_branch_id_(0), |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 283 | has_msa_(instruction_set_features != nullptr ? instruction_set_features->HasMsa() : false), |
Vladimir Marko | 10ef694 | 2015-10-22 15:25:54 +0100 | [diff] [blame] | 284 | isa_features_(instruction_set_features) { |
| 285 | cfi().DelayEmittingAdvancePCs(); |
| 286 | } |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 287 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 288 | size_t CodeSize() const override { return Assembler::CodeSize(); } |
| 289 | size_t CodePosition() override; |
Yi Kong | 3940254 | 2019-03-24 02:47:16 -0700 | [diff] [blame^] | 290 | DebugFrameOpCodeWriterForAssembler& cfi() override { return Assembler::cfi(); } |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 291 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 292 | virtual ~MipsAssembler() { |
| 293 | for (auto& branch : branches_) { |
| 294 | CHECK(branch.IsResolved()); |
| 295 | } |
| 296 | } |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 297 | |
| 298 | // Emit Machine Instructions. |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 299 | void Addu(Register rd, Register rs, Register rt); |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 300 | void Addiu(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 301 | void Addiu(Register rt, Register rs, uint16_t imm16); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 302 | void Subu(Register rd, Register rs, Register rt); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 303 | |
| 304 | void MultR2(Register rs, Register rt); // R2 |
| 305 | void MultuR2(Register rs, Register rt); // R2 |
| 306 | void DivR2(Register rs, Register rt); // R2 |
| 307 | void DivuR2(Register rs, Register rt); // R2 |
| 308 | void MulR2(Register rd, Register rs, Register rt); // R2 |
| 309 | void DivR2(Register rd, Register rs, Register rt); // R2 |
| 310 | void ModR2(Register rd, Register rs, Register rt); // R2 |
| 311 | void DivuR2(Register rd, Register rs, Register rt); // R2 |
| 312 | void ModuR2(Register rd, Register rs, Register rt); // R2 |
| 313 | void MulR6(Register rd, Register rs, Register rt); // R6 |
Alexey Frunze | 7e99e05 | 2015-11-24 19:28:01 -0800 | [diff] [blame] | 314 | void MuhR6(Register rd, Register rs, Register rt); // R6 |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 315 | void MuhuR6(Register rd, Register rs, Register rt); // R6 |
| 316 | void DivR6(Register rd, Register rs, Register rt); // R6 |
| 317 | void ModR6(Register rd, Register rs, Register rt); // R6 |
| 318 | void DivuR6(Register rd, Register rs, Register rt); // R6 |
| 319 | void ModuR6(Register rd, Register rs, Register rt); // R6 |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 320 | |
| 321 | void And(Register rd, Register rs, Register rt); |
| 322 | void Andi(Register rt, Register rs, uint16_t imm16); |
| 323 | void Or(Register rd, Register rs, Register rt); |
| 324 | void Ori(Register rt, Register rs, uint16_t imm16); |
| 325 | void Xor(Register rd, Register rs, Register rt); |
| 326 | void Xori(Register rt, Register rs, uint16_t imm16); |
| 327 | void Nor(Register rd, Register rs, Register rt); |
| 328 | |
Chris Larsen | e384547 | 2015-11-18 12:27:15 -0800 | [diff] [blame] | 329 | void Movz(Register rd, Register rs, Register rt); // R2 |
| 330 | void Movn(Register rd, Register rs, Register rt); // R2 |
| 331 | void Seleqz(Register rd, Register rs, Register rt); // R6 |
| 332 | void Selnez(Register rd, Register rs, Register rt); // R6 |
| 333 | void ClzR6(Register rd, Register rs); |
| 334 | void ClzR2(Register rd, Register rs); |
| 335 | void CloR6(Register rd, Register rs); |
| 336 | void CloR2(Register rd, Register rs); |
| 337 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 338 | void Seb(Register rd, Register rt); // R2+ |
| 339 | void Seh(Register rd, Register rt); // R2+ |
Chris Larsen | 3f8bf65 | 2015-10-28 10:08:56 -0700 | [diff] [blame] | 340 | void Wsbh(Register rd, Register rt); // R2+ |
Chris Larsen | 70014c8 | 2015-11-18 12:26:08 -0800 | [diff] [blame] | 341 | void Bitswap(Register rd, Register rt); // R6 |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 342 | |
| 343 | void Sll(Register rd, Register rt, int shamt); |
| 344 | void Srl(Register rd, Register rt, int shamt); |
Chris Larsen | 3f8bf65 | 2015-10-28 10:08:56 -0700 | [diff] [blame] | 345 | void Rotr(Register rd, Register rt, int shamt); // R2+ |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 346 | void Sra(Register rd, Register rt, int shamt); |
| 347 | void Sllv(Register rd, Register rt, Register rs); |
| 348 | void Srlv(Register rd, Register rt, Register rs); |
Chris Larsen | e16ce5a | 2015-11-18 12:30:20 -0800 | [diff] [blame] | 349 | void Rotrv(Register rd, Register rt, Register rs); // R2+ |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 350 | void Srav(Register rd, Register rt, Register rs); |
Alexey Frunze | 5c7aed3 | 2015-11-25 19:41:54 -0800 | [diff] [blame] | 351 | void Ext(Register rd, Register rt, int pos, int size); // R2+ |
| 352 | void Ins(Register rd, Register rt, int pos, int size); // R2+ |
Chris Larsen | 692235e | 2016-11-21 16:04:53 -0800 | [diff] [blame] | 353 | void Lsa(Register rd, Register rs, Register rt, int saPlusOne); // R6 |
Chris Larsen | cd0295d | 2017-03-31 15:26:54 -0700 | [diff] [blame] | 354 | void ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp = AT); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 355 | |
| 356 | void Lb(Register rt, Register rs, uint16_t imm16); |
| 357 | void Lh(Register rt, Register rs, uint16_t imm16); |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 358 | void Lw(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 359 | void Lw(Register rt, Register rs, uint16_t imm16); |
Chris Larsen | 3acee73 | 2015-11-18 13:31:08 -0800 | [diff] [blame] | 360 | void Lwl(Register rt, Register rs, uint16_t imm16); |
| 361 | void Lwr(Register rt, Register rs, uint16_t imm16); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 362 | void Lbu(Register rt, Register rs, uint16_t imm16); |
| 363 | void Lhu(Register rt, Register rs, uint16_t imm16); |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 364 | void Lwpc(Register rs, uint32_t imm19); // R6 |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 365 | void Lui(Register rt, uint16_t imm16); |
Alexey Frunze | cad3a4c | 2016-06-07 23:40:37 -0700 | [diff] [blame] | 366 | void Aui(Register rt, Register rs, uint16_t imm16); // R6 |
Alexey Frunze | 4147fcc | 2017-06-17 19:57:27 -0700 | [diff] [blame] | 367 | void AddUpper(Register rt, Register rs, uint16_t imm16, Register tmp = AT); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 368 | void Sync(uint32_t stype); |
| 369 | void Mfhi(Register rd); // R2 |
| 370 | void Mflo(Register rd); // R2 |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 371 | |
| 372 | void Sb(Register rt, Register rs, uint16_t imm16); |
| 373 | void Sh(Register rt, Register rs, uint16_t imm16); |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 374 | void Sw(Register rt, Register rs, uint16_t imm16, MipsLabel* patcher_label); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 375 | void Sw(Register rt, Register rs, uint16_t imm16); |
Chris Larsen | 3acee73 | 2015-11-18 13:31:08 -0800 | [diff] [blame] | 376 | void Swl(Register rt, Register rs, uint16_t imm16); |
| 377 | void Swr(Register rt, Register rs, uint16_t imm16); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 378 | |
Alexey Frunze | 51aff3a | 2016-03-17 17:21:45 -0700 | [diff] [blame] | 379 | void LlR2(Register rt, Register base, int16_t imm16 = 0); |
| 380 | void ScR2(Register rt, Register base, int16_t imm16 = 0); |
| 381 | void LlR6(Register rt, Register base, int16_t imm9 = 0); |
| 382 | void ScR6(Register rt, Register base, int16_t imm9 = 0); |
| 383 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 384 | void Slt(Register rd, Register rs, Register rt); |
| 385 | void Sltu(Register rd, Register rs, Register rt); |
| 386 | void Slti(Register rt, Register rs, uint16_t imm16); |
| 387 | void Sltiu(Register rt, Register rs, uint16_t imm16); |
| 388 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 389 | // Branches and jumps to immediate offsets/addresses do not take care of their |
| 390 | // delay/forbidden slots and generally should not be used directly. This applies |
| 391 | // to the following R2 and R6 branch/jump instructions with imm16, imm21, addr26 |
| 392 | // offsets/addresses. |
| 393 | // Use branches/jumps to labels instead. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 394 | void B(uint16_t imm16); |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 395 | void Bal(uint16_t imm16); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 396 | void Beq(Register rs, Register rt, uint16_t imm16); |
| 397 | void Bne(Register rs, Register rt, uint16_t imm16); |
| 398 | void Beqz(Register rt, uint16_t imm16); |
| 399 | void Bnez(Register rt, uint16_t imm16); |
| 400 | void Bltz(Register rt, uint16_t imm16); |
| 401 | void Bgez(Register rt, uint16_t imm16); |
| 402 | void Blez(Register rt, uint16_t imm16); |
| 403 | void Bgtz(Register rt, uint16_t imm16); |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 404 | void Bc1f(uint16_t imm16); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 405 | void Bc1f(int cc, uint16_t imm16); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 406 | void Bc1t(uint16_t imm16); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 407 | void Bc1t(int cc, uint16_t imm16); // R2 |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 408 | void J(uint32_t addr26); |
| 409 | void Jal(uint32_t addr26); |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 410 | // Jalr() and Jr() fill their delay slots when reordering is enabled. |
| 411 | // When reordering is disabled, the delay slots must be filled manually. |
| 412 | // You may use NopIfNoReordering() to fill them when reordering is disabled. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 413 | void Jalr(Register rd, Register rs); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 414 | void Jalr(Register rs); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 415 | void Jr(Register rs); |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 416 | // Nal() does not fill its delay slot. It must be filled manually. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 417 | void Nal(); |
| 418 | void Auipc(Register rs, uint16_t imm16); // R6 |
| 419 | void Addiupc(Register rs, uint32_t imm19); // R6 |
| 420 | void Bc(uint32_t imm26); // R6 |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 421 | void Balc(uint32_t imm26); // R6 |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 422 | void Jic(Register rt, uint16_t imm16); // R6 |
| 423 | void Jialc(Register rt, uint16_t imm16); // R6 |
| 424 | void Bltc(Register rs, Register rt, uint16_t imm16); // R6 |
| 425 | void Bltzc(Register rt, uint16_t imm16); // R6 |
| 426 | void Bgtzc(Register rt, uint16_t imm16); // R6 |
| 427 | void Bgec(Register rs, Register rt, uint16_t imm16); // R6 |
| 428 | void Bgezc(Register rt, uint16_t imm16); // R6 |
| 429 | void Blezc(Register rt, uint16_t imm16); // R6 |
| 430 | void Bltuc(Register rs, Register rt, uint16_t imm16); // R6 |
| 431 | void Bgeuc(Register rs, Register rt, uint16_t imm16); // R6 |
| 432 | void Beqc(Register rs, Register rt, uint16_t imm16); // R6 |
| 433 | void Bnec(Register rs, Register rt, uint16_t imm16); // R6 |
| 434 | void Beqzc(Register rs, uint32_t imm21); // R6 |
| 435 | void Bnezc(Register rs, uint32_t imm21); // R6 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 436 | void Bc1eqz(FRegister ft, uint16_t imm16); // R6 |
| 437 | void Bc1nez(FRegister ft, uint16_t imm16); // R6 |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 438 | |
| 439 | void AddS(FRegister fd, FRegister fs, FRegister ft); |
| 440 | void SubS(FRegister fd, FRegister fs, FRegister ft); |
| 441 | void MulS(FRegister fd, FRegister fs, FRegister ft); |
| 442 | void DivS(FRegister fd, FRegister fs, FRegister ft); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 443 | void AddD(FRegister fd, FRegister fs, FRegister ft); |
| 444 | void SubD(FRegister fd, FRegister fs, FRegister ft); |
| 445 | void MulD(FRegister fd, FRegister fs, FRegister ft); |
| 446 | void DivD(FRegister fd, FRegister fs, FRegister ft); |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 447 | void SqrtS(FRegister fd, FRegister fs); |
| 448 | void SqrtD(FRegister fd, FRegister fs); |
| 449 | void AbsS(FRegister fd, FRegister fs); |
| 450 | void AbsD(FRegister fd, FRegister fs); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 451 | void MovS(FRegister fd, FRegister fs); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 452 | void MovD(FRegister fd, FRegister fs); |
| 453 | void NegS(FRegister fd, FRegister fs); |
| 454 | void NegD(FRegister fd, FRegister fs); |
| 455 | |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 456 | void CunS(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 457 | void CunS(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 458 | void CeqS(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 459 | void CeqS(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 460 | void CueqS(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 461 | void CueqS(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 462 | void ColtS(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 463 | void ColtS(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 464 | void CultS(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 465 | void CultS(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 466 | void ColeS(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 467 | void ColeS(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 468 | void CuleS(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 469 | void CuleS(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 470 | void CunD(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 471 | void CunD(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 472 | void CeqD(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 473 | void CeqD(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 474 | void CueqD(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 475 | void CueqD(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 476 | void ColtD(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 477 | void ColtD(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 478 | void CultD(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 479 | void CultD(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 480 | void ColeD(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 481 | void ColeD(int cc, FRegister fs, FRegister ft); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 482 | void CuleD(FRegister fs, FRegister ft); // R2 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 483 | void CuleD(int cc, FRegister fs, FRegister ft); // R2 |
| 484 | void CmpUnS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 485 | void CmpEqS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 486 | void CmpUeqS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 487 | void CmpLtS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 488 | void CmpUltS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 489 | void CmpLeS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 490 | void CmpUleS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 491 | void CmpOrS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 492 | void CmpUneS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 493 | void CmpNeS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 494 | void CmpUnD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 495 | void CmpEqD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 496 | void CmpUeqD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 497 | void CmpLtD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 498 | void CmpUltD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 499 | void CmpLeD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 500 | void CmpUleD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 501 | void CmpOrD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 502 | void CmpUneD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 503 | void CmpNeD(FRegister fd, FRegister fs, FRegister ft); // R6 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 504 | void Movf(Register rd, Register rs, int cc = 0); // R2 |
| 505 | void Movt(Register rd, Register rs, int cc = 0); // R2 |
| 506 | void MovfS(FRegister fd, FRegister fs, int cc = 0); // R2 |
| 507 | void MovfD(FRegister fd, FRegister fs, int cc = 0); // R2 |
| 508 | void MovtS(FRegister fd, FRegister fs, int cc = 0); // R2 |
| 509 | void MovtD(FRegister fd, FRegister fs, int cc = 0); // R2 |
Alexey Frunze | 674b9ee | 2016-09-20 14:54:15 -0700 | [diff] [blame] | 510 | void MovzS(FRegister fd, FRegister fs, Register rt); // R2 |
| 511 | void MovzD(FRegister fd, FRegister fs, Register rt); // R2 |
| 512 | void MovnS(FRegister fd, FRegister fs, Register rt); // R2 |
| 513 | void MovnD(FRegister fd, FRegister fs, Register rt); // R2 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 514 | void SelS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 515 | void SelD(FRegister fd, FRegister fs, FRegister ft); // R6 |
Alexey Frunze | 674b9ee | 2016-09-20 14:54:15 -0700 | [diff] [blame] | 516 | void SeleqzS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 517 | void SeleqzD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 518 | void SelnezS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 519 | void SelnezD(FRegister fd, FRegister fs, FRegister ft); // R6 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 520 | void ClassS(FRegister fd, FRegister fs); // R6 |
| 521 | void ClassD(FRegister fd, FRegister fs); // R6 |
| 522 | void MinS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 523 | void MinD(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 524 | void MaxS(FRegister fd, FRegister fs, FRegister ft); // R6 |
| 525 | void MaxD(FRegister fd, FRegister fs, FRegister ft); // R6 |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 526 | |
Alexey Frunze | baf60b7 | 2015-12-22 15:15:03 -0800 | [diff] [blame] | 527 | void TruncLS(FRegister fd, FRegister fs); // R2+, FR=1 |
| 528 | void TruncLD(FRegister fd, FRegister fs); // R2+, FR=1 |
| 529 | void TruncWS(FRegister fd, FRegister fs); |
| 530 | void TruncWD(FRegister fd, FRegister fs); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 531 | void Cvtsw(FRegister fd, FRegister fs); |
| 532 | void Cvtdw(FRegister fd, FRegister fs); |
| 533 | void Cvtsd(FRegister fd, FRegister fs); |
| 534 | void Cvtds(FRegister fd, FRegister fs); |
Alexey Frunze | baf60b7 | 2015-12-22 15:15:03 -0800 | [diff] [blame] | 535 | void Cvtsl(FRegister fd, FRegister fs); // R2+, FR=1 |
| 536 | void Cvtdl(FRegister fd, FRegister fs); // R2+, FR=1 |
Chris Larsen | b74353a | 2015-11-20 09:07:09 -0800 | [diff] [blame] | 537 | void FloorWS(FRegister fd, FRegister fs); |
| 538 | void FloorWD(FRegister fd, FRegister fs); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 539 | |
Alexey Frunze | a247dea | 2017-11-03 18:43:04 -0700 | [diff] [blame] | 540 | // Note, the 32 LSBs of a 64-bit value must be loaded into an FPR before the 32 MSBs |
| 541 | // when loading the value as 32-bit halves. This applies to all 32-bit FPR loads: |
| 542 | // Mtc1(), Mthc1(), MoveToFpuHigh(), Lwc1(). Even if you need two Mtc1()'s or two |
| 543 | // Lwc1()'s to load a pair of 32-bit FPRs and these loads do not interfere with one |
| 544 | // another (unlike Mtc1() and Mthc1() with 64-bit FPRs), maintain the order: |
| 545 | // low then high. |
| 546 | // |
| 547 | // Also, prefer MoveFromFpuHigh()/MoveToFpuHigh() over Mfhc1()/Mthc1() and Mfc1()/Mtc1(). |
| 548 | // This will save you some if statements. |
| 549 | FRegister GetFpuRegLow(FRegister reg); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 550 | void Mfc1(Register rt, FRegister fs); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 551 | void Mtc1(Register rt, FRegister fs); |
| 552 | void Mfhc1(Register rt, FRegister fs); |
| 553 | void Mthc1(Register rt, FRegister fs); |
Alexey Frunze | bb9863a | 2016-01-11 15:51:16 -0800 | [diff] [blame] | 554 | void MoveFromFpuHigh(Register rt, FRegister fs); |
| 555 | void MoveToFpuHigh(Register rt, FRegister fs); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 556 | void Lwc1(FRegister ft, Register rs, uint16_t imm16); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 557 | void Ldc1(FRegister ft, Register rs, uint16_t imm16); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 558 | void Swc1(FRegister ft, Register rs, uint16_t imm16); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 559 | void Sdc1(FRegister ft, Register rs, uint16_t imm16); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 560 | |
| 561 | void Break(); |
jeffhao | 0703060 | 2012-09-26 14:33:14 -0700 | [diff] [blame] | 562 | void Nop(); |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 563 | void NopIfNoReordering(); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 564 | void Move(Register rd, Register rs); |
| 565 | void Clear(Register rd); |
| 566 | void Not(Register rd, Register rs); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 567 | |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 568 | // MSA instructions. |
| 569 | void AndV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 570 | void OrV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 571 | void NorV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 572 | void XorV(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 573 | |
| 574 | void AddvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 575 | void AddvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 576 | void AddvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 577 | void AddvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 578 | void SubvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 579 | void SubvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 580 | void SubvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 581 | void SubvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
Lena Djokic | 72aba71 | 2017-10-30 15:47:20 +0100 | [diff] [blame] | 582 | void Asub_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 583 | void Asub_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 584 | void Asub_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 585 | void Asub_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 586 | void Asub_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 587 | void Asub_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 588 | void Asub_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 589 | void Asub_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 590 | void MulvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 591 | void MulvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 592 | void MulvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 593 | void MulvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 594 | void Div_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 595 | void Div_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 596 | void Div_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 597 | void Div_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 598 | void Div_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 599 | void Div_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 600 | void Div_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 601 | void Div_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 602 | void Mod_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 603 | void Mod_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 604 | void Mod_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 605 | void Mod_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 606 | void Mod_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 607 | void Mod_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 608 | void Mod_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 609 | void Mod_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 610 | void Add_aB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 611 | void Add_aH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 612 | void Add_aW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 613 | void Add_aD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 614 | void Ave_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 615 | void Ave_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 616 | void Ave_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 617 | void Ave_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 618 | void Ave_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 619 | void Ave_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 620 | void Ave_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 621 | void Ave_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 622 | void Aver_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 623 | void Aver_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 624 | void Aver_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 625 | void Aver_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 626 | void Aver_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 627 | void Aver_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 628 | void Aver_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 629 | void Aver_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 630 | void Max_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 631 | void Max_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 632 | void Max_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 633 | void Max_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 634 | void Max_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 635 | void Max_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 636 | void Max_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 637 | void Max_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 638 | void Min_sB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 639 | void Min_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 640 | void Min_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 641 | void Min_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 642 | void Min_uB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 643 | void Min_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 644 | void Min_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 645 | void Min_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 646 | |
| 647 | void FaddW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 648 | void FaddD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 649 | void FsubW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 650 | void FsubD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 651 | void FmulW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 652 | void FmulD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 653 | void FdivW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 654 | void FdivD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 655 | void FmaxW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 656 | void FmaxD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 657 | void FminW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 658 | void FminD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 659 | |
| 660 | void Ffint_sW(VectorRegister wd, VectorRegister ws); |
| 661 | void Ffint_sD(VectorRegister wd, VectorRegister ws); |
| 662 | void Ftint_sW(VectorRegister wd, VectorRegister ws); |
| 663 | void Ftint_sD(VectorRegister wd, VectorRegister ws); |
| 664 | |
| 665 | void SllB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 666 | void SllH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 667 | void SllW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 668 | void SllD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 669 | void SraB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 670 | void SraH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 671 | void SraW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 672 | void SraD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 673 | void SrlB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 674 | void SrlH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 675 | void SrlW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 676 | void SrlD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 677 | |
| 678 | // Immediate shift instructions, where shamtN denotes shift amount (must be between 0 and 2^N-1). |
| 679 | void SlliB(VectorRegister wd, VectorRegister ws, int shamt3); |
| 680 | void SlliH(VectorRegister wd, VectorRegister ws, int shamt4); |
| 681 | void SlliW(VectorRegister wd, VectorRegister ws, int shamt5); |
| 682 | void SlliD(VectorRegister wd, VectorRegister ws, int shamt6); |
| 683 | void SraiB(VectorRegister wd, VectorRegister ws, int shamt3); |
| 684 | void SraiH(VectorRegister wd, VectorRegister ws, int shamt4); |
| 685 | void SraiW(VectorRegister wd, VectorRegister ws, int shamt5); |
| 686 | void SraiD(VectorRegister wd, VectorRegister ws, int shamt6); |
| 687 | void SrliB(VectorRegister wd, VectorRegister ws, int shamt3); |
| 688 | void SrliH(VectorRegister wd, VectorRegister ws, int shamt4); |
| 689 | void SrliW(VectorRegister wd, VectorRegister ws, int shamt5); |
| 690 | void SrliD(VectorRegister wd, VectorRegister ws, int shamt6); |
| 691 | |
| 692 | void MoveV(VectorRegister wd, VectorRegister ws); |
| 693 | void SplatiB(VectorRegister wd, VectorRegister ws, int n4); |
| 694 | void SplatiH(VectorRegister wd, VectorRegister ws, int n3); |
| 695 | void SplatiW(VectorRegister wd, VectorRegister ws, int n2); |
| 696 | void SplatiD(VectorRegister wd, VectorRegister ws, int n1); |
Lena Djokic | 3309c01 | 2017-10-13 14:34:32 +0200 | [diff] [blame] | 697 | void Copy_sB(Register rd, VectorRegister ws, int n4); |
| 698 | void Copy_sH(Register rd, VectorRegister ws, int n3); |
| 699 | void Copy_sW(Register rd, VectorRegister ws, int n2); |
| 700 | void Copy_uB(Register rd, VectorRegister ws, int n4); |
| 701 | void Copy_uH(Register rd, VectorRegister ws, int n3); |
| 702 | void InsertB(VectorRegister wd, Register rs, int n4); |
| 703 | void InsertH(VectorRegister wd, Register rs, int n3); |
| 704 | void InsertW(VectorRegister wd, Register rs, int n2); |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 705 | void FillB(VectorRegister wd, Register rs); |
| 706 | void FillH(VectorRegister wd, Register rs); |
| 707 | void FillW(VectorRegister wd, Register rs); |
| 708 | |
| 709 | void LdiB(VectorRegister wd, int imm8); |
| 710 | void LdiH(VectorRegister wd, int imm10); |
| 711 | void LdiW(VectorRegister wd, int imm10); |
| 712 | void LdiD(VectorRegister wd, int imm10); |
| 713 | void LdB(VectorRegister wd, Register rs, int offset); |
| 714 | void LdH(VectorRegister wd, Register rs, int offset); |
| 715 | void LdW(VectorRegister wd, Register rs, int offset); |
| 716 | void LdD(VectorRegister wd, Register rs, int offset); |
| 717 | void StB(VectorRegister wd, Register rs, int offset); |
| 718 | void StH(VectorRegister wd, Register rs, int offset); |
| 719 | void StW(VectorRegister wd, Register rs, int offset); |
| 720 | void StD(VectorRegister wd, Register rs, int offset); |
| 721 | |
Lena Djokic | 3309c01 | 2017-10-13 14:34:32 +0200 | [diff] [blame] | 722 | void IlvlB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 723 | void IlvlH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 724 | void IlvlW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 725 | void IlvlD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 726 | void IlvrB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 727 | void IlvrH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 728 | void IlvrW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 729 | void IlvrD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
Lena Djokic | 3309c01 | 2017-10-13 14:34:32 +0200 | [diff] [blame] | 730 | void IlvevB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 731 | void IlvevH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 732 | void IlvevW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 733 | void IlvevD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 734 | void IlvodB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 735 | void IlvodH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 736 | void IlvodW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 737 | void IlvodD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 738 | |
Lena Djokic | b3d79e4 | 2017-07-25 11:20:52 +0200 | [diff] [blame] | 739 | void MaddvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 740 | void MaddvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 741 | void MaddvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 742 | void MaddvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 743 | void MsubvB(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 744 | void MsubvH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 745 | void MsubvW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 746 | void MsubvD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 747 | void FmaddW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 748 | void FmaddD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 749 | void FmsubW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 750 | void FmsubD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 751 | |
Lena Djokic | 3309c01 | 2017-10-13 14:34:32 +0200 | [diff] [blame] | 752 | void Hadd_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 753 | void Hadd_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 754 | void Hadd_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 755 | void Hadd_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 756 | void Hadd_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 757 | void Hadd_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt); |
| 758 | |
Lena Djokic | 0d2cab5 | 2018-03-06 15:20:45 +0100 | [diff] [blame] | 759 | void PcntB(VectorRegister wd, VectorRegister ws); |
| 760 | void PcntH(VectorRegister wd, VectorRegister ws); |
| 761 | void PcntW(VectorRegister wd, VectorRegister ws); |
| 762 | void PcntD(VectorRegister wd, VectorRegister ws); |
| 763 | |
Lena Djokic | 51765b0 | 2017-06-22 13:49:59 +0200 | [diff] [blame] | 764 | // Helper for replicating floating point value in all destination elements. |
| 765 | void ReplicateFPToVectorRegister(VectorRegister dst, FRegister src, bool is_double); |
| 766 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 767 | // Higher level composite instructions. |
| 768 | void LoadConst32(Register rd, int32_t value); |
| 769 | void LoadConst64(Register reg_hi, Register reg_lo, int64_t value); |
| 770 | void LoadDConst64(FRegister rd, int64_t value, Register temp); |
| 771 | void LoadSConst32(FRegister r, int32_t value, Register temp); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 772 | void Addiu32(Register rt, Register rs, int32_t value, Register rtmp = AT); |
| 773 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 774 | void Bind(MipsLabel* label); |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 775 | // When `is_bare` is false, the branches will promote to long (if the range |
| 776 | // of the individual branch instruction is insufficient) and the delay/ |
| 777 | // forbidden slots will be taken care of. |
| 778 | // Use `is_bare = false` when the branch target may be out of reach of the |
| 779 | // individual branch instruction. IOW, this is for general purpose use. |
| 780 | // |
| 781 | // When `is_bare` is true, just the branch instructions will be generated |
| 782 | // leaving delay/forbidden slot filling up to the caller and the branches |
| 783 | // won't promote to long if the range is insufficient (you'll get a |
| 784 | // compilation error when the range is exceeded). |
| 785 | // Use `is_bare = true` when the branch target is known to be within reach |
| 786 | // of the individual branch instruction. This is intended for small local |
| 787 | // optimizations around delay/forbidden slots. |
| 788 | // Also prefer using `is_bare = true` if the code near the branch is to be |
| 789 | // patched or analyzed at run time (e.g. introspection) to |
| 790 | // - show the intent and |
| 791 | // - fail during compilation rather than during patching/execution if the |
| 792 | // bare branch range is insufficent but the code size and layout are |
| 793 | // expected to remain unchanged |
| 794 | // |
| 795 | // R2 branches with delay slots that are also available on R6. |
| 796 | // On R6 when `is_bare` is false these convert to equivalent R6 compact |
| 797 | // branches (to reduce code size). On R2 or when `is_bare` is true they |
| 798 | // remain R2 branches with delay slots. |
| 799 | void B(MipsLabel* label, bool is_bare = false); |
| 800 | void Bal(MipsLabel* label, bool is_bare = false); |
| 801 | void Beq(Register rs, Register rt, MipsLabel* label, bool is_bare = false); |
| 802 | void Bne(Register rs, Register rt, MipsLabel* label, bool is_bare = false); |
| 803 | void Beqz(Register rt, MipsLabel* label, bool is_bare = false); |
| 804 | void Bnez(Register rt, MipsLabel* label, bool is_bare = false); |
| 805 | void Bltz(Register rt, MipsLabel* label, bool is_bare = false); |
| 806 | void Bgez(Register rt, MipsLabel* label, bool is_bare = false); |
| 807 | void Blez(Register rt, MipsLabel* label, bool is_bare = false); |
| 808 | void Bgtz(Register rt, MipsLabel* label, bool is_bare = false); |
| 809 | void Blt(Register rs, Register rt, MipsLabel* label, bool is_bare = false); |
| 810 | void Bge(Register rs, Register rt, MipsLabel* label, bool is_bare = false); |
| 811 | void Bltu(Register rs, Register rt, MipsLabel* label, bool is_bare = false); |
| 812 | void Bgeu(Register rs, Register rt, MipsLabel* label, bool is_bare = false); |
| 813 | // R2-only branches with delay slots. |
| 814 | void Bc1f(MipsLabel* label, bool is_bare = false); // R2 |
| 815 | void Bc1f(int cc, MipsLabel* label, bool is_bare = false); // R2 |
| 816 | void Bc1t(MipsLabel* label, bool is_bare = false); // R2 |
| 817 | void Bc1t(int cc, MipsLabel* label, bool is_bare = false); // R2 |
| 818 | // R6-only compact branches without delay/forbidden slots. |
| 819 | void Bc(MipsLabel* label, bool is_bare = false); // R6 |
| 820 | void Balc(MipsLabel* label, bool is_bare = false); // R6 |
| 821 | // R6-only compact branches with forbidden slots. |
| 822 | void Beqc(Register rs, Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 823 | void Bnec(Register rs, Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 824 | void Beqzc(Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 825 | void Bnezc(Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 826 | void Bltzc(Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 827 | void Bgezc(Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 828 | void Blezc(Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 829 | void Bgtzc(Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 830 | void Bltc(Register rs, Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 831 | void Bgec(Register rs, Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 832 | void Bltuc(Register rs, Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 833 | void Bgeuc(Register rs, Register rt, MipsLabel* label, bool is_bare = false); // R6 |
| 834 | // R6-only branches with delay slots. |
| 835 | void Bc1eqz(FRegister ft, MipsLabel* label, bool is_bare = false); // R6 |
| 836 | void Bc1nez(FRegister ft, MipsLabel* label, bool is_bare = false); // R6 |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 837 | |
| 838 | void EmitLoad(ManagedRegister m_dst, Register src_register, int32_t src_offset, size_t size); |
Alexey Frunze | cad3a4c | 2016-06-07 23:40:37 -0700 | [diff] [blame] | 839 | void AdjustBaseAndOffset(Register& base, |
| 840 | int32_t& offset, |
| 841 | bool is_doubleword, |
| 842 | bool is_float = false); |
Lena Djokic | 2e0a7e5 | 2017-07-06 11:55:24 +0200 | [diff] [blame] | 843 | void AdjustBaseOffsetAndElementSizeShift(Register& base, |
| 844 | int32_t& offset, |
| 845 | int& element_size_shift); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 846 | |
| 847 | private: |
Tijana Jakovljevic | 5743386 | 2017-01-17 16:59:03 +0100 | [diff] [blame] | 848 | // This will be used as an argument for loads/stores |
| 849 | // when there is no need for implicit null checks. |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 850 | struct NoImplicitNullChecker { |
Tijana Jakovljevic | 5743386 | 2017-01-17 16:59:03 +0100 | [diff] [blame] | 851 | void operator()() const {} |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 852 | }; |
| 853 | |
| 854 | public: |
| 855 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
Alexey Frunze | f58b248 | 2016-09-02 22:14:06 -0700 | [diff] [blame] | 856 | void StoreConstToOffset(StoreOperandType type, |
| 857 | int64_t value, |
| 858 | Register base, |
| 859 | int32_t offset, |
| 860 | Register temp, |
| 861 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 862 | // We permit `base` and `temp` to coincide (however, we check that neither is AT), |
| 863 | // in which case the `base` register may be overwritten in the process. |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 864 | CHECK_NE(temp, AT); // Must not use AT as temp, so as not to overwrite the adjusted base. |
Andreas Gampe | 3db7068 | 2018-12-26 15:12:03 -0800 | [diff] [blame] | 865 | AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword)); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 866 | uint32_t low = Low32Bits(value); |
| 867 | uint32_t high = High32Bits(value); |
Alexey Frunze | f58b248 | 2016-09-02 22:14:06 -0700 | [diff] [blame] | 868 | Register reg; |
| 869 | // If the adjustment left `base` unchanged and equal to `temp`, we can't use `temp` |
| 870 | // to load and hold the value but we can use AT instead as AT hasn't been used yet. |
| 871 | // Otherwise, `temp` can be used for the value. And if `temp` is the same as the |
| 872 | // original `base` (that is, `base` prior to the adjustment), the original `base` |
| 873 | // register will be overwritten. |
| 874 | if (base == temp) { |
| 875 | temp = AT; |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 876 | } |
Alexey Frunze | f58b248 | 2016-09-02 22:14:06 -0700 | [diff] [blame] | 877 | if (low == 0) { |
| 878 | reg = ZERO; |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 879 | } else { |
Alexey Frunze | f58b248 | 2016-09-02 22:14:06 -0700 | [diff] [blame] | 880 | reg = temp; |
| 881 | LoadConst32(reg, low); |
| 882 | } |
| 883 | switch (type) { |
| 884 | case kStoreByte: |
| 885 | Sb(reg, base, offset); |
| 886 | break; |
| 887 | case kStoreHalfword: |
| 888 | Sh(reg, base, offset); |
| 889 | break; |
| 890 | case kStoreWord: |
| 891 | Sw(reg, base, offset); |
| 892 | break; |
| 893 | case kStoreDoubleword: |
| 894 | Sw(reg, base, offset); |
| 895 | null_checker(); |
| 896 | if (high == 0) { |
| 897 | reg = ZERO; |
| 898 | } else { |
| 899 | reg = temp; |
| 900 | if (high != low) { |
| 901 | LoadConst32(reg, high); |
| 902 | } |
| 903 | } |
| 904 | Sw(reg, base, offset + kMipsWordSize); |
| 905 | break; |
| 906 | default: |
| 907 | LOG(FATAL) << "UNREACHABLE"; |
| 908 | } |
| 909 | if (type != kStoreDoubleword) { |
| 910 | null_checker(); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 911 | } |
| 912 | } |
| 913 | |
| 914 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 915 | void LoadFromOffset(LoadOperandType type, |
| 916 | Register reg, |
| 917 | Register base, |
| 918 | int32_t offset, |
| 919 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
Andreas Gampe | 3db7068 | 2018-12-26 15:12:03 -0800 | [diff] [blame] | 920 | AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kLoadDoubleword)); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 921 | switch (type) { |
| 922 | case kLoadSignedByte: |
| 923 | Lb(reg, base, offset); |
| 924 | break; |
| 925 | case kLoadUnsignedByte: |
| 926 | Lbu(reg, base, offset); |
| 927 | break; |
| 928 | case kLoadSignedHalfword: |
| 929 | Lh(reg, base, offset); |
| 930 | break; |
| 931 | case kLoadUnsignedHalfword: |
| 932 | Lhu(reg, base, offset); |
| 933 | break; |
| 934 | case kLoadWord: |
| 935 | Lw(reg, base, offset); |
| 936 | break; |
| 937 | case kLoadDoubleword: |
| 938 | if (reg == base) { |
| 939 | // This will clobber the base when loading the lower register. Since we have to load the |
| 940 | // higher register as well, this will fail. Solution: reverse the order. |
| 941 | Lw(static_cast<Register>(reg + 1), base, offset + kMipsWordSize); |
| 942 | null_checker(); |
| 943 | Lw(reg, base, offset); |
| 944 | } else { |
| 945 | Lw(reg, base, offset); |
| 946 | null_checker(); |
| 947 | Lw(static_cast<Register>(reg + 1), base, offset + kMipsWordSize); |
| 948 | } |
| 949 | break; |
| 950 | default: |
| 951 | LOG(FATAL) << "UNREACHABLE"; |
| 952 | } |
| 953 | if (type != kLoadDoubleword) { |
| 954 | null_checker(); |
| 955 | } |
| 956 | } |
| 957 | |
| 958 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 959 | void LoadSFromOffset(FRegister reg, |
| 960 | Register base, |
| 961 | int32_t offset, |
| 962 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
Andreas Gampe | 3db7068 | 2018-12-26 15:12:03 -0800 | [diff] [blame] | 963 | AdjustBaseAndOffset(base, offset, /* is_doubleword= */ false, /* is_float= */ true); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 964 | Lwc1(reg, base, offset); |
| 965 | null_checker(); |
| 966 | } |
| 967 | |
| 968 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 969 | void LoadDFromOffset(FRegister reg, |
| 970 | Register base, |
| 971 | int32_t offset, |
| 972 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
Andreas Gampe | 3db7068 | 2018-12-26 15:12:03 -0800 | [diff] [blame] | 973 | AdjustBaseAndOffset(base, offset, /* is_doubleword= */ true, /* is_float= */ true); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 974 | if (IsAligned<kMipsDoublewordSize>(offset)) { |
| 975 | Ldc1(reg, base, offset); |
| 976 | null_checker(); |
| 977 | } else { |
| 978 | if (Is32BitFPU()) { |
| 979 | Lwc1(reg, base, offset); |
| 980 | null_checker(); |
| 981 | Lwc1(static_cast<FRegister>(reg + 1), base, offset + kMipsWordSize); |
| 982 | } else { |
| 983 | // 64-bit FPU. |
| 984 | Lwc1(reg, base, offset); |
| 985 | null_checker(); |
| 986 | Lw(T8, base, offset + kMipsWordSize); |
| 987 | Mthc1(T8, reg); |
| 988 | } |
| 989 | } |
| 990 | } |
| 991 | |
| 992 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
Lena Djokic | 2e0a7e5 | 2017-07-06 11:55:24 +0200 | [diff] [blame] | 993 | void LoadQFromOffset(FRegister reg, |
| 994 | Register base, |
| 995 | int32_t offset, |
| 996 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 997 | int element_size_shift = -1; |
| 998 | AdjustBaseOffsetAndElementSizeShift(base, offset, element_size_shift); |
| 999 | switch (element_size_shift) { |
| 1000 | case TIMES_1: LdB(static_cast<VectorRegister>(reg), base, offset); break; |
| 1001 | case TIMES_2: LdH(static_cast<VectorRegister>(reg), base, offset); break; |
| 1002 | case TIMES_4: LdW(static_cast<VectorRegister>(reg), base, offset); break; |
| 1003 | case TIMES_8: LdD(static_cast<VectorRegister>(reg), base, offset); break; |
| 1004 | default: |
| 1005 | LOG(FATAL) << "UNREACHABLE"; |
| 1006 | } |
| 1007 | null_checker(); |
| 1008 | } |
| 1009 | |
| 1010 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 1011 | void StoreToOffset(StoreOperandType type, |
| 1012 | Register reg, |
| 1013 | Register base, |
| 1014 | int32_t offset, |
| 1015 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 1016 | // Must not use AT as `reg`, so as not to overwrite the value being stored |
| 1017 | // with the adjusted `base`. |
| 1018 | CHECK_NE(reg, AT); |
Andreas Gampe | 3db7068 | 2018-12-26 15:12:03 -0800 | [diff] [blame] | 1019 | AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword)); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 1020 | switch (type) { |
| 1021 | case kStoreByte: |
| 1022 | Sb(reg, base, offset); |
| 1023 | break; |
| 1024 | case kStoreHalfword: |
| 1025 | Sh(reg, base, offset); |
| 1026 | break; |
| 1027 | case kStoreWord: |
| 1028 | Sw(reg, base, offset); |
| 1029 | break; |
| 1030 | case kStoreDoubleword: |
| 1031 | CHECK_NE(reg, base); |
| 1032 | CHECK_NE(static_cast<Register>(reg + 1), base); |
| 1033 | Sw(reg, base, offset); |
| 1034 | null_checker(); |
| 1035 | Sw(static_cast<Register>(reg + 1), base, offset + kMipsWordSize); |
| 1036 | break; |
| 1037 | default: |
| 1038 | LOG(FATAL) << "UNREACHABLE"; |
| 1039 | } |
| 1040 | if (type != kStoreDoubleword) { |
| 1041 | null_checker(); |
| 1042 | } |
| 1043 | } |
| 1044 | |
| 1045 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 1046 | void StoreSToOffset(FRegister reg, |
| 1047 | Register base, |
| 1048 | int32_t offset, |
| 1049 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
Andreas Gampe | 3db7068 | 2018-12-26 15:12:03 -0800 | [diff] [blame] | 1050 | AdjustBaseAndOffset(base, offset, /* is_doubleword= */ false, /* is_float= */ true); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 1051 | Swc1(reg, base, offset); |
| 1052 | null_checker(); |
| 1053 | } |
| 1054 | |
| 1055 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 1056 | void StoreDToOffset(FRegister reg, |
| 1057 | Register base, |
| 1058 | int32_t offset, |
| 1059 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
Andreas Gampe | 3db7068 | 2018-12-26 15:12:03 -0800 | [diff] [blame] | 1060 | AdjustBaseAndOffset(base, offset, /* is_doubleword= */ true, /* is_float= */ true); |
Alexey Frunze | 2923db7 | 2016-08-20 01:55:47 -0700 | [diff] [blame] | 1061 | if (IsAligned<kMipsDoublewordSize>(offset)) { |
| 1062 | Sdc1(reg, base, offset); |
| 1063 | null_checker(); |
| 1064 | } else { |
| 1065 | if (Is32BitFPU()) { |
| 1066 | Swc1(reg, base, offset); |
| 1067 | null_checker(); |
| 1068 | Swc1(static_cast<FRegister>(reg + 1), base, offset + kMipsWordSize); |
| 1069 | } else { |
| 1070 | // 64-bit FPU. |
| 1071 | Mfhc1(T8, reg); |
| 1072 | Swc1(reg, base, offset); |
| 1073 | null_checker(); |
| 1074 | Sw(T8, base, offset + kMipsWordSize); |
| 1075 | } |
| 1076 | } |
| 1077 | } |
| 1078 | |
Lena Djokic | 2e0a7e5 | 2017-07-06 11:55:24 +0200 | [diff] [blame] | 1079 | template <typename ImplicitNullChecker = NoImplicitNullChecker> |
| 1080 | void StoreQToOffset(FRegister reg, |
| 1081 | Register base, |
| 1082 | int32_t offset, |
| 1083 | ImplicitNullChecker null_checker = NoImplicitNullChecker()) { |
| 1084 | int element_size_shift = -1; |
| 1085 | AdjustBaseOffsetAndElementSizeShift(base, offset, element_size_shift); |
| 1086 | switch (element_size_shift) { |
| 1087 | case TIMES_1: StB(static_cast<VectorRegister>(reg), base, offset); break; |
| 1088 | case TIMES_2: StH(static_cast<VectorRegister>(reg), base, offset); break; |
| 1089 | case TIMES_4: StW(static_cast<VectorRegister>(reg), base, offset); break; |
| 1090 | case TIMES_8: StD(static_cast<VectorRegister>(reg), base, offset); break; |
| 1091 | default: |
| 1092 | LOG(FATAL) << "UNREACHABLE"; |
| 1093 | } |
| 1094 | null_checker(); |
| 1095 | } |
| 1096 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1097 | void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset); |
| 1098 | void LoadSFromOffset(FRegister reg, Register base, int32_t offset); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1099 | void LoadDFromOffset(FRegister reg, Register base, int32_t offset); |
Lena Djokic | 2e0a7e5 | 2017-07-06 11:55:24 +0200 | [diff] [blame] | 1100 | void LoadQFromOffset(FRegister reg, Register base, int32_t offset); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1101 | void StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset); |
Goran Jakovljevic | ff73498 | 2015-08-24 12:58:55 +0000 | [diff] [blame] | 1102 | void StoreSToOffset(FRegister reg, Register base, int32_t offset); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1103 | void StoreDToOffset(FRegister reg, Register base, int32_t offset); |
Lena Djokic | 2e0a7e5 | 2017-07-06 11:55:24 +0200 | [diff] [blame] | 1104 | void StoreQToOffset(FRegister reg, Register base, int32_t offset); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1105 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1106 | // Emit data (e.g. encoded instruction or immediate) to the instruction stream. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1107 | void Emit(uint32_t value); |
| 1108 | |
| 1109 | // Push/pop composite routines. |
| 1110 | void Push(Register rs); |
| 1111 | void Pop(Register rd); |
| 1112 | void PopAndReturn(Register rd, Register rt); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1113 | |
Alexey Frunze | c061de1 | 2017-02-14 13:27:23 -0800 | [diff] [blame] | 1114 | // |
| 1115 | // Heap poisoning. |
| 1116 | // |
| 1117 | |
| 1118 | // Poison a heap reference contained in `src` and store it in `dst`. |
| 1119 | void PoisonHeapReference(Register dst, Register src) { |
| 1120 | // dst = -src. |
| 1121 | Subu(dst, ZERO, src); |
| 1122 | } |
| 1123 | // Poison a heap reference contained in `reg`. |
| 1124 | void PoisonHeapReference(Register reg) { |
| 1125 | // reg = -reg. |
| 1126 | PoisonHeapReference(reg, reg); |
| 1127 | } |
| 1128 | // Unpoison a heap reference contained in `reg`. |
| 1129 | void UnpoisonHeapReference(Register reg) { |
| 1130 | // reg = -reg. |
| 1131 | Subu(reg, ZERO, reg); |
| 1132 | } |
| 1133 | // Poison a heap reference contained in `reg` if heap poisoning is enabled. |
| 1134 | void MaybePoisonHeapReference(Register reg) { |
| 1135 | if (kPoisonHeapReferences) { |
| 1136 | PoisonHeapReference(reg); |
| 1137 | } |
| 1138 | } |
| 1139 | // Unpoison a heap reference contained in `reg` if heap poisoning is enabled. |
| 1140 | void MaybeUnpoisonHeapReference(Register reg) { |
| 1141 | if (kPoisonHeapReferences) { |
| 1142 | UnpoisonHeapReference(reg); |
| 1143 | } |
| 1144 | } |
| 1145 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1146 | void Bind(Label* label) override { |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1147 | Bind(down_cast<MipsLabel*>(label)); |
Andreas Gampe | 85b62f2 | 2015-09-09 13:15:38 -0700 | [diff] [blame] | 1148 | } |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1149 | void Jump(Label* label ATTRIBUTE_UNUSED) override { |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1150 | UNIMPLEMENTED(FATAL) << "Do not use Jump for MIPS"; |
Andreas Gampe | 85b62f2 | 2015-09-09 13:15:38 -0700 | [diff] [blame] | 1151 | } |
| 1152 | |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 1153 | // Don't warn about a different virtual Bind/Jump in the base class. |
| 1154 | using JNIBase::Bind; |
| 1155 | using JNIBase::Jump; |
| 1156 | |
| 1157 | // Create a new label that can be used with Jump/Bind calls. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1158 | std::unique_ptr<JNIMacroLabel> CreateLabel() override { |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 1159 | LOG(FATAL) << "Not implemented on MIPS32"; |
| 1160 | UNREACHABLE(); |
| 1161 | } |
| 1162 | // Emit an unconditional jump to the label. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1163 | void Jump(JNIMacroLabel* label ATTRIBUTE_UNUSED) override { |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 1164 | LOG(FATAL) << "Not implemented on MIPS32"; |
| 1165 | UNREACHABLE(); |
| 1166 | } |
| 1167 | // Emit a conditional jump to the label by applying a unary condition test to the register. |
| 1168 | void Jump(JNIMacroLabel* label ATTRIBUTE_UNUSED, |
| 1169 | JNIMacroUnaryCondition cond ATTRIBUTE_UNUSED, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1170 | ManagedRegister test ATTRIBUTE_UNUSED) override { |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 1171 | LOG(FATAL) << "Not implemented on MIPS32"; |
| 1172 | UNREACHABLE(); |
| 1173 | } |
| 1174 | |
| 1175 | // Code at this offset will serve as the target for the Jump call. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1176 | void Bind(JNIMacroLabel* label ATTRIBUTE_UNUSED) override { |
Igor Murashkin | ae7ff92 | 2016-10-06 14:59:19 -0700 | [diff] [blame] | 1177 | LOG(FATAL) << "Not implemented on MIPS32"; |
| 1178 | UNREACHABLE(); |
| 1179 | } |
| 1180 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1181 | // Create a new literal with a given value. |
| 1182 | // NOTE: Force the template parameter to be explicitly specified. |
| 1183 | template <typename T> |
| 1184 | Literal* NewLiteral(typename Identity<T>::type value) { |
| 1185 | static_assert(std::is_integral<T>::value, "T must be an integral type."); |
| 1186 | return NewLiteral(sizeof(value), reinterpret_cast<const uint8_t*>(&value)); |
| 1187 | } |
| 1188 | |
Alexey Frunze | 3b8c82f | 2017-10-10 23:01:34 -0700 | [diff] [blame] | 1189 | // Load label address using PC-relative addressing. |
| 1190 | // To be used with data labels in the literal / jump table area only and not |
| 1191 | // with regular code labels. |
| 1192 | // |
| 1193 | // For R6 base_reg must be ZERO. |
| 1194 | // |
| 1195 | // On R2 there are two possible uses w.r.t. base_reg: |
| 1196 | // |
| 1197 | // - base_reg = ZERO: |
| 1198 | // The NAL instruction will be generated as part of the load and it will |
| 1199 | // clobber the RA register. |
| 1200 | // |
| 1201 | // - base_reg != ZERO: |
| 1202 | // The RA-clobbering NAL instruction won't be generated as part of the load. |
| 1203 | // The label pc_rel_base_label_ must be bound (with BindPcRelBaseLabel()) |
| 1204 | // and base_reg must hold the address of the label. Example: |
| 1205 | // __ Nal(); |
| 1206 | // __ Move(S3, RA); |
| 1207 | // __ BindPcRelBaseLabel(); // S3 holds the address of pc_rel_base_label_. |
| 1208 | // __ LoadLabelAddress(A0, S3, label1); |
| 1209 | // __ LoadLabelAddress(A1, S3, label2); |
| 1210 | // __ LoadLiteral(V0, S3, literal1); |
| 1211 | // __ LoadLiteral(V1, S3, literal2); |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1212 | void LoadLabelAddress(Register dest_reg, Register base_reg, MipsLabel* label); |
| 1213 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1214 | // Create a new literal with the given data. |
| 1215 | Literal* NewLiteral(size_t size, const uint8_t* data); |
| 1216 | |
Alexey Frunze | 3b8c82f | 2017-10-10 23:01:34 -0700 | [diff] [blame] | 1217 | // Load literal using PC-relative addressing. |
| 1218 | // See the above comments for LoadLabelAddress() on the value of base_reg. |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1219 | void LoadLiteral(Register dest_reg, Register base_reg, Literal* literal); |
| 1220 | |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1221 | // Create a jump table for the given labels that will be emitted when finalizing. |
| 1222 | // When the table is emitted, offsets will be relative to the location of the table. |
| 1223 | // The table location is determined by the location of its label (the label precedes |
| 1224 | // the table data) and should be loaded using LoadLabelAddress(). |
| 1225 | JumpTable* CreateJumpTable(std::vector<MipsLabel*>&& labels); |
| 1226 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1227 | // |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1228 | // Overridden common assembler high-level functionality. |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1229 | // |
| 1230 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1231 | // Emit code that will create an activation on the stack. |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1232 | void BuildFrame(size_t frame_size, |
| 1233 | ManagedRegister method_reg, |
Vladimir Marko | 3224838 | 2016-05-19 10:37:24 +0100 | [diff] [blame] | 1234 | ArrayRef<const ManagedRegister> callee_save_regs, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1235 | const ManagedRegisterEntrySpills& entry_spills) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1236 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1237 | // Emit code that will remove an activation from the stack. |
Roland Levillain | 0d127e1 | 2017-07-05 17:01:11 +0100 | [diff] [blame] | 1238 | void RemoveFrame(size_t frame_size, |
| 1239 | ArrayRef<const ManagedRegister> callee_save_regs, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1240 | bool may_suspend) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1241 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1242 | void IncreaseFrameSize(size_t adjust) override; |
| 1243 | void DecreaseFrameSize(size_t adjust) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1244 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1245 | // Store routines. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1246 | void Store(FrameOffset offs, ManagedRegister msrc, size_t size) override; |
| 1247 | void StoreRef(FrameOffset dest, ManagedRegister msrc) override; |
| 1248 | void StoreRawPtr(FrameOffset dest, ManagedRegister msrc) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1249 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1250 | void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1251 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1252 | void StoreStackOffsetToThread(ThreadOffset32 thr_offs, |
| 1253 | FrameOffset fr_offs, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1254 | ManagedRegister mscratch) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1255 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1256 | void StoreStackPointerToThread(ThreadOffset32 thr_offs) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1257 | |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1258 | void StoreSpanning(FrameOffset dest, |
| 1259 | ManagedRegister msrc, |
| 1260 | FrameOffset in_off, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1261 | ManagedRegister mscratch) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1262 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1263 | // Load routines. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1264 | void Load(ManagedRegister mdest, FrameOffset src, size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1265 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1266 | void LoadFromThread(ManagedRegister mdest, ThreadOffset32 src, size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1267 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1268 | void LoadRef(ManagedRegister dest, FrameOffset src) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1269 | |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1270 | void LoadRef(ManagedRegister mdest, |
| 1271 | ManagedRegister base, |
| 1272 | MemberOffset offs, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1273 | bool unpoison_reference) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1274 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1275 | void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1276 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1277 | void LoadRawPtrFromThread(ManagedRegister mdest, ThreadOffset32 offs) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1278 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1279 | // Copying routines. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1280 | void Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1281 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1282 | void CopyRawPtrFromThread(FrameOffset fr_offs, |
| 1283 | ThreadOffset32 thr_offs, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1284 | ManagedRegister mscratch) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1285 | |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1286 | void CopyRawPtrToThread(ThreadOffset32 thr_offs, |
| 1287 | FrameOffset fr_offs, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1288 | ManagedRegister mscratch) override; |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 1289 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1290 | void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister mscratch) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1291 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1292 | void Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1293 | |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1294 | void Copy(FrameOffset dest, |
| 1295 | ManagedRegister src_base, |
| 1296 | Offset src_offset, |
| 1297 | ManagedRegister mscratch, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1298 | size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1299 | |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1300 | void Copy(ManagedRegister dest_base, |
| 1301 | Offset dest_offset, |
| 1302 | FrameOffset src, |
| 1303 | ManagedRegister mscratch, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1304 | size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1305 | |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1306 | void Copy(FrameOffset dest, |
| 1307 | FrameOffset src_base, |
| 1308 | Offset src_offset, |
| 1309 | ManagedRegister mscratch, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1310 | size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1311 | |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1312 | void Copy(ManagedRegister dest, |
| 1313 | Offset dest_offset, |
| 1314 | ManagedRegister src, |
| 1315 | Offset src_offset, |
| 1316 | ManagedRegister mscratch, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1317 | size_t size) override; |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1318 | |
| 1319 | void Copy(FrameOffset dest, |
| 1320 | Offset dest_offset, |
| 1321 | FrameOffset src, |
| 1322 | Offset src_offset, |
| 1323 | ManagedRegister mscratch, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1324 | size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1325 | |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1326 | void MemoryBarrier(ManagedRegister) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1327 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1328 | // Sign extension. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1329 | void SignExtend(ManagedRegister mreg, size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1330 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1331 | // Zero extension. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1332 | void ZeroExtend(ManagedRegister mreg, size_t size) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1333 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1334 | // Exploit fast access in managed code to Thread::Current(). |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1335 | void GetCurrentThread(ManagedRegister tr) override; |
| 1336 | void GetCurrentThread(FrameOffset dest_offset, ManagedRegister mscratch) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1337 | |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 1338 | // Set up out_reg to hold a Object** into the handle scope, or to be null if the |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1339 | // value is null and null_allowed. in_reg holds a possibly stale reference |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 1340 | // that can be used to avoid loading the handle scope entry to see if the value is |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 1341 | // null. |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1342 | void CreateHandleScopeEntry(ManagedRegister out_reg, |
| 1343 | FrameOffset handlescope_offset, |
| 1344 | ManagedRegister in_reg, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1345 | bool null_allowed) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1346 | |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 1347 | // Set up out_off to hold a Object** into the handle scope, or to be null if the |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1348 | // value is null and null_allowed. |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1349 | void CreateHandleScopeEntry(FrameOffset out_off, |
| 1350 | FrameOffset handlescope_offset, |
| 1351 | ManagedRegister mscratch, |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1352 | bool null_allowed) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1353 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1354 | // src holds a handle scope entry (Object**) load this into dst. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1355 | void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1356 | |
| 1357 | // Heap::VerifyObject on src. In some cases (such as a reference to this) we |
| 1358 | // know that src may not be null. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1359 | void VerifyObject(ManagedRegister src, bool could_be_null) override; |
| 1360 | void VerifyObject(FrameOffset src, bool could_be_null) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1361 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1362 | // Call to address held at [base+offset]. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1363 | void Call(ManagedRegister base, Offset offset, ManagedRegister mscratch) override; |
| 1364 | void Call(FrameOffset base, Offset offset, ManagedRegister mscratch) override; |
| 1365 | void CallFromThread(ThreadOffset32 offset, ManagedRegister mscratch) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1366 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1367 | // Generate code to check if Thread::Current()->exception_ is non-null |
| 1368 | // and branch to a ExceptionSlowPath if it is. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1369 | void ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) override; |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1370 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1371 | // Emit slow paths queued during assembly and promote short branches to long if needed. |
Roland Levillain | bbc6e7e | 2018-08-24 16:58:47 +0100 | [diff] [blame] | 1372 | void FinalizeCode() override; |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1373 | |
| 1374 | // Emit branches and finalize all instructions. |
Yi Kong | 3940254 | 2019-03-24 02:47:16 -0700 | [diff] [blame^] | 1375 | void FinalizeInstructions(const MemoryRegion& region) override; |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1376 | |
| 1377 | // Returns the (always-)current location of a label (can be used in class CodeGeneratorMIPS, |
| 1378 | // must be used instead of MipsLabel::GetPosition()). |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1379 | uint32_t GetLabelLocation(const MipsLabel* label) const; |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1380 | |
| 1381 | // Get the final position of a label after local fixup based on the old position |
| 1382 | // recorded before FinalizeCode(). |
| 1383 | uint32_t GetAdjustedPosition(uint32_t old_position); |
| 1384 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1385 | // R2 doesn't have PC-relative addressing, which we need to access literals. We simulate it by |
| 1386 | // reading the PC value into a general-purpose register with the NAL instruction and then loading |
| 1387 | // literals through this base register. The code generator calls this method (at most once per |
| 1388 | // method being compiled) to bind a label to the location for which the PC value is acquired. |
| 1389 | // The assembler then computes literal offsets relative to this label. |
| 1390 | void BindPcRelBaseLabel(); |
| 1391 | |
Alexey Frunze | 06a46c4 | 2016-07-19 15:00:40 -0700 | [diff] [blame] | 1392 | // Returns the location of the label bound with BindPcRelBaseLabel(). |
| 1393 | uint32_t GetPcRelBaseLabelLocation() const; |
| 1394 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1395 | // Note that PC-relative literal loads are handled as pseudo branches because they need very |
| 1396 | // similar relocation and may similarly expand in size to accomodate for larger offsets relative |
| 1397 | // to PC. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1398 | enum BranchCondition { |
| 1399 | kCondLT, |
| 1400 | kCondGE, |
| 1401 | kCondLE, |
| 1402 | kCondGT, |
| 1403 | kCondLTZ, |
| 1404 | kCondGEZ, |
| 1405 | kCondLEZ, |
| 1406 | kCondGTZ, |
| 1407 | kCondEQ, |
| 1408 | kCondNE, |
| 1409 | kCondEQZ, |
| 1410 | kCondNEZ, |
| 1411 | kCondLTU, |
| 1412 | kCondGEU, |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1413 | kCondF, // Floating-point predicate false. |
| 1414 | kCondT, // Floating-point predicate true. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1415 | kUncond, |
| 1416 | }; |
| 1417 | friend std::ostream& operator<<(std::ostream& os, const BranchCondition& rhs); |
| 1418 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1419 | // Enables or disables instruction reordering (IOW, automatic filling of delay slots) |
| 1420 | // similarly to ".set reorder" / ".set noreorder" in traditional MIPS assembly. |
| 1421 | // Returns the last state, which may be useful for temporary enabling/disabling of |
| 1422 | // reordering. |
| 1423 | bool SetReorder(bool enable); |
| 1424 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1425 | private: |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1426 | // Description of the last instruction in terms of input and output registers. |
| 1427 | // Used to make the decision of moving the instruction into a delay slot. |
| 1428 | struct DelaySlot { |
| 1429 | DelaySlot(); |
Alexey Frunze | a247dea | 2017-11-03 18:43:04 -0700 | [diff] [blame] | 1430 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1431 | // Encoded instruction that may be used to fill the delay slot or 0 |
| 1432 | // (0 conveniently represents NOP). |
| 1433 | uint32_t instruction_; |
Alexey Frunze | a247dea | 2017-11-03 18:43:04 -0700 | [diff] [blame] | 1434 | |
| 1435 | // Input/output register masks. |
| 1436 | InOutRegMasks masks_; |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 1437 | |
| 1438 | // Label for patchable instructions to allow moving them into delay slots. |
| 1439 | MipsLabel* patcher_label_; |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1440 | }; |
| 1441 | |
| 1442 | // Delay slot finite state machine's (DS FSM's) state. The FSM state is updated |
| 1443 | // upon every new instruction and label generated. The FSM detects instructions |
| 1444 | // suitable for delay slots and immediately preceded with labels. These are target |
| 1445 | // instructions for branches. If an unconditional R2 branch does not get its delay |
| 1446 | // slot filled with the immediately preceding instruction, it may instead get the |
| 1447 | // slot filled with the target instruction (the branch will need its offset |
| 1448 | // incremented past the target instruction). We call this "absorption". The FSM |
| 1449 | // records PCs of the target instructions suitable for this optimization. |
| 1450 | enum DsFsmState { |
| 1451 | kExpectingLabel, |
| 1452 | kExpectingInstruction, |
| 1453 | kExpectingCommit |
| 1454 | }; |
| 1455 | friend std::ostream& operator<<(std::ostream& os, const DsFsmState& rhs); |
| 1456 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1457 | class Branch { |
| 1458 | public: |
| 1459 | enum Type { |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1460 | // R2 short branches (can be promoted to long). |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1461 | kUncondBranch, |
| 1462 | kCondBranch, |
| 1463 | kCall, |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1464 | // R2 short branches (can't be promoted to long), delay slots filled manually. |
| 1465 | kBareUncondBranch, |
| 1466 | kBareCondBranch, |
| 1467 | kBareCall, |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1468 | // R2 near label. |
| 1469 | kLabel, |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1470 | // R2 near literal. |
| 1471 | kLiteral, |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1472 | // R2 long branches. |
| 1473 | kLongUncondBranch, |
| 1474 | kLongCondBranch, |
| 1475 | kLongCall, |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1476 | // R2 far label. |
| 1477 | kFarLabel, |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1478 | // R2 far literal. |
| 1479 | kFarLiteral, |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1480 | // R6 short branches (can be promoted to long). |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1481 | kR6UncondBranch, |
| 1482 | kR6CondBranch, |
| 1483 | kR6Call, |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1484 | // R6 short branches (can't be promoted to long), forbidden/delay slots filled manually. |
| 1485 | kR6BareUncondBranch, |
| 1486 | kR6BareCondBranch, |
| 1487 | kR6BareCall, |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1488 | // R6 near label. |
| 1489 | kR6Label, |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1490 | // R6 near literal. |
| 1491 | kR6Literal, |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1492 | // R6 long branches. |
| 1493 | kR6LongUncondBranch, |
| 1494 | kR6LongCondBranch, |
| 1495 | kR6LongCall, |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1496 | // R6 far label. |
| 1497 | kR6FarLabel, |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1498 | // R6 far literal. |
| 1499 | kR6FarLiteral, |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1500 | }; |
| 1501 | // Bit sizes of offsets defined as enums to minimize chance of typos. |
| 1502 | enum OffsetBits { |
| 1503 | kOffset16 = 16, |
| 1504 | kOffset18 = 18, |
| 1505 | kOffset21 = 21, |
| 1506 | kOffset23 = 23, |
| 1507 | kOffset28 = 28, |
| 1508 | kOffset32 = 32, |
| 1509 | }; |
| 1510 | |
| 1511 | static constexpr uint32_t kUnresolved = 0xffffffff; // Unresolved target_ |
| 1512 | static constexpr int32_t kMaxBranchLength = 32; |
| 1513 | static constexpr int32_t kMaxBranchSize = kMaxBranchLength * sizeof(uint32_t); |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1514 | // The following two instruction encodings can never legally occur in branch delay |
| 1515 | // slots and are used as markers. |
| 1516 | // |
| 1517 | // kUnfilledDelaySlot means that the branch may use either the preceding or the target |
| 1518 | // instruction to fill its delay slot (the latter is only possible with unconditional |
| 1519 | // R2 branches and is termed here as "absorption"). |
| 1520 | static constexpr uint32_t kUnfilledDelaySlot = 0x10000000; // beq zero, zero, 0. |
| 1521 | // kUnfillableDelaySlot means that the branch cannot use an instruction (other than NOP) |
| 1522 | // to fill its delay slot. This is only used for unconditional R2 branches to prevent |
| 1523 | // absorption of the target instruction when reordering is disabled. |
| 1524 | static constexpr uint32_t kUnfillableDelaySlot = 0x13FF0000; // beq ra, ra, 0. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1525 | |
| 1526 | struct BranchInfo { |
| 1527 | // Branch length as a number of 4-byte-long instructions. |
| 1528 | uint32_t length; |
| 1529 | // Ordinal number (0-based) of the first (or the only) instruction that contains the branch's |
| 1530 | // PC-relative offset (or its most significant 16-bit half, which goes first). |
| 1531 | uint32_t instr_offset; |
| 1532 | // Different MIPS instructions with PC-relative offsets apply said offsets to slightly |
| 1533 | // different origins, e.g. to PC or PC+4. Encode the origin distance (as a number of 4-byte |
| 1534 | // instructions) from the instruction containing the offset. |
| 1535 | uint32_t pc_org; |
| 1536 | // How large (in bits) a PC-relative offset can be for a given type of branch (kR6CondBranch |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1537 | // and kR6BareCondBranch are an exception: use kOffset23 for beqzc/bnezc). |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1538 | OffsetBits offset_size; |
| 1539 | // Some MIPS instructions with PC-relative offsets shift the offset by 2. Encode the shift |
| 1540 | // count. |
| 1541 | int offset_shift; |
| 1542 | }; |
| 1543 | static const BranchInfo branch_info_[/* Type */]; |
| 1544 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1545 | // Unconditional branch or call. |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1546 | Branch(bool is_r6, uint32_t location, uint32_t target, bool is_call, bool is_bare); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1547 | // Conditional branch. |
| 1548 | Branch(bool is_r6, |
| 1549 | uint32_t location, |
| 1550 | uint32_t target, |
| 1551 | BranchCondition condition, |
| 1552 | Register lhs_reg, |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1553 | Register rhs_reg, |
| 1554 | bool is_bare); |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1555 | // Label address (in literal area) or literal. |
| 1556 | Branch(bool is_r6, |
| 1557 | uint32_t location, |
| 1558 | Register dest_reg, |
| 1559 | Register base_reg, |
| 1560 | Type label_or_literal_type); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1561 | |
| 1562 | // Some conditional branches with lhs = rhs are effectively NOPs, while some |
| 1563 | // others are effectively unconditional. MIPSR6 conditional branches require lhs != rhs. |
| 1564 | // So, we need a way to identify such branches in order to emit no instructions for them |
| 1565 | // or change them to unconditional. |
| 1566 | static bool IsNop(BranchCondition condition, Register lhs, Register rhs); |
| 1567 | static bool IsUncond(BranchCondition condition, Register lhs, Register rhs); |
| 1568 | |
| 1569 | static BranchCondition OppositeCondition(BranchCondition cond); |
| 1570 | |
| 1571 | Type GetType() const; |
| 1572 | BranchCondition GetCondition() const; |
| 1573 | Register GetLeftRegister() const; |
| 1574 | Register GetRightRegister() const; |
| 1575 | uint32_t GetTarget() const; |
| 1576 | uint32_t GetLocation() const; |
| 1577 | uint32_t GetOldLocation() const; |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1578 | uint32_t GetPrecedingInstructionLength(Type type) const; |
| 1579 | uint32_t GetPrecedingInstructionSize(Type type) const; |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1580 | uint32_t GetLength() const; |
| 1581 | uint32_t GetOldLength() const; |
| 1582 | uint32_t GetSize() const; |
| 1583 | uint32_t GetOldSize() const; |
| 1584 | uint32_t GetEndLocation() const; |
| 1585 | uint32_t GetOldEndLocation() const; |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1586 | bool IsBare() const; |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1587 | bool IsLong() const; |
| 1588 | bool IsResolved() const; |
| 1589 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1590 | // Various helpers for branch delay slot management. |
| 1591 | bool CanHaveDelayedInstruction(const DelaySlot& delay_slot) const; |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 1592 | void SetDelayedInstruction(uint32_t instruction, MipsLabel* patcher_label = nullptr); |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1593 | uint32_t GetDelayedInstruction() const; |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 1594 | MipsLabel* GetPatcherLabel() const; |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1595 | void DecrementLocations(); |
| 1596 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1597 | // Returns the bit size of the signed offset that the branch instruction can handle. |
| 1598 | OffsetBits GetOffsetSize() const; |
| 1599 | |
| 1600 | // Calculates the distance between two byte locations in the assembler buffer and |
| 1601 | // returns the number of bits needed to represent the distance as a signed integer. |
| 1602 | // |
| 1603 | // Branch instructions have signed offsets of 16, 19 (addiupc), 21 (beqzc/bnezc), |
| 1604 | // and 26 (bc) bits, which are additionally shifted left 2 positions at run time. |
| 1605 | // |
| 1606 | // Composite branches (made of several instructions) with longer reach have 32-bit |
| 1607 | // offsets encoded as 2 16-bit "halves" in two instructions (high half goes first). |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1608 | // The composite branches cover the range of PC + +/-2GB on MIPS32 CPUs. However, |
| 1609 | // the range is not end-to-end on MIPS64 (unless addresses are forced to zero- or |
| 1610 | // sign-extend from 32 to 64 bits by the appropriate CPU configuration). |
| 1611 | // Consider the following implementation of a long unconditional branch, for |
| 1612 | // example: |
| 1613 | // |
| 1614 | // auipc at, offset_31_16 // at = pc + sign_extend(offset_31_16) << 16 |
| 1615 | // jic at, offset_15_0 // pc = at + sign_extend(offset_15_0) |
| 1616 | // |
| 1617 | // Both of the above instructions take 16-bit signed offsets as immediate operands. |
| 1618 | // When bit 15 of offset_15_0 is 1, it effectively causes subtraction of 0x10000 |
| 1619 | // due to sign extension. This must be compensated for by incrementing offset_31_16 |
| 1620 | // by 1. offset_31_16 can only be incremented by 1 if it's not 0x7FFF. If it is |
| 1621 | // 0x7FFF, adding 1 will overflow the positive offset into the negative range. |
| 1622 | // Therefore, the long branch range is something like from PC - 0x80000000 to |
| 1623 | // PC + 0x7FFF7FFF, IOW, shorter by 32KB on one side. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1624 | // |
| 1625 | // The returned values are therefore: 18, 21, 23, 28 and 32. There's also a special |
| 1626 | // case with the addiu instruction and a 16 bit offset. |
| 1627 | static OffsetBits GetOffsetSizeNeeded(uint32_t location, uint32_t target); |
| 1628 | |
| 1629 | // Resolve a branch when the target is known. |
| 1630 | void Resolve(uint32_t target); |
| 1631 | |
| 1632 | // Relocate a branch by a given delta if needed due to expansion of this or another |
| 1633 | // branch at a given location by this delta (just changes location_ and target_). |
| 1634 | void Relocate(uint32_t expand_location, uint32_t delta); |
| 1635 | |
| 1636 | // If the branch is short, changes its type to long. |
| 1637 | void PromoteToLong(); |
| 1638 | |
| 1639 | // If necessary, updates the type by promoting a short branch to a long branch |
| 1640 | // based on the branch location and target. Returns the amount (in bytes) by |
| 1641 | // which the branch size has increased. |
| 1642 | // max_short_distance caps the maximum distance between location_ and target_ |
| 1643 | // that is allowed for short branches. This is for debugging/testing purposes. |
| 1644 | // max_short_distance = 0 forces all short branches to become long. |
| 1645 | // Use the implicit default argument when not debugging/testing. |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1646 | uint32_t PromoteIfNeeded(uint32_t location, |
| 1647 | uint32_t max_short_distance = std::numeric_limits<uint32_t>::max()); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1648 | |
| 1649 | // Returns the location of the instruction(s) containing the offset. |
| 1650 | uint32_t GetOffsetLocation() const; |
| 1651 | |
| 1652 | // Calculates and returns the offset ready for encoding in the branch instruction(s). |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1653 | uint32_t GetOffset(uint32_t location) const; |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1654 | |
| 1655 | private: |
| 1656 | // Completes branch construction by determining and recording its type. |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1657 | void InitializeType(Type initial_type, bool is_r6); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1658 | // Helper for the above. |
| 1659 | void InitShortOrLong(OffsetBits ofs_size, Type short_type, Type long_type); |
| 1660 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1661 | uint32_t old_location_; // Offset into assembler buffer in bytes. |
| 1662 | uint32_t location_; // Offset into assembler buffer in bytes. |
| 1663 | uint32_t target_; // Offset into assembler buffer in bytes. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1664 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1665 | uint32_t lhs_reg_; // Left-hand side register in conditional branches or |
| 1666 | // FPU condition code. Destination register in literals. |
| 1667 | uint32_t rhs_reg_; // Right-hand side register in conditional branches. |
| 1668 | // Base register in literals (ZERO on R6). |
| 1669 | BranchCondition condition_; // Condition for conditional branches. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1670 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1671 | Type type_; // Current type of the branch. |
| 1672 | Type old_type_; // Initial type of the branch. |
| 1673 | |
| 1674 | uint32_t delayed_instruction_; // Encoded instruction for the delay slot or |
| 1675 | // kUnfilledDelaySlot if none but fillable or |
| 1676 | // kUnfillableDelaySlot if none and unfillable |
| 1677 | // (the latter is only used for unconditional R2 |
| 1678 | // branches). |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 1679 | |
| 1680 | MipsLabel* patcher_label_; // Patcher label for the instruction in the delay slot. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1681 | }; |
| 1682 | friend std::ostream& operator<<(std::ostream& os, const Branch::Type& rhs); |
| 1683 | friend std::ostream& operator<<(std::ostream& os, const Branch::OffsetBits& rhs); |
| 1684 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1685 | uint32_t EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct); |
| 1686 | uint32_t EmitI(int opcode, Register rs, Register rt, uint16_t imm); |
| 1687 | uint32_t EmitI21(int opcode, Register rs, uint32_t imm21); |
| 1688 | uint32_t EmitI26(int opcode, uint32_t imm26); |
| 1689 | uint32_t EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, int funct); |
| 1690 | uint32_t EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm); |
Alexey Frunze | cd7b0ee | 2015-12-03 16:46:38 -0800 | [diff] [blame] | 1691 | void EmitBcondR2(BranchCondition cond, Register rs, Register rt, uint16_t imm16); |
| 1692 | void EmitBcondR6(BranchCondition cond, Register rs, Register rt, uint32_t imm16_21); |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 1693 | uint32_t EmitMsa3R(int operation, |
| 1694 | int df, |
| 1695 | VectorRegister wt, |
| 1696 | VectorRegister ws, |
| 1697 | VectorRegister wd, |
| 1698 | int minor_opcode); |
| 1699 | uint32_t EmitMsaBIT(int operation, |
| 1700 | int df_m, |
| 1701 | VectorRegister ws, |
| 1702 | VectorRegister wd, |
| 1703 | int minor_opcode); |
| 1704 | uint32_t EmitMsaELM(int operation, |
| 1705 | int df_n, |
| 1706 | VectorRegister ws, |
| 1707 | VectorRegister wd, |
| 1708 | int minor_opcode); |
| 1709 | uint32_t EmitMsaMI10(int s10, Register rs, VectorRegister wd, int minor_opcode, int df); |
| 1710 | uint32_t EmitMsaI10(int operation, int df, int i10, VectorRegister wd, int minor_opcode); |
| 1711 | uint32_t EmitMsa2R(int operation, int df, VectorRegister ws, VectorRegister wd, int minor_opcode); |
| 1712 | uint32_t EmitMsa2RF(int operation, |
| 1713 | int df, |
| 1714 | VectorRegister ws, |
| 1715 | VectorRegister wd, |
| 1716 | int minor_opcode); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1717 | |
Alexey Frunze | 0cab656 | 2017-07-25 15:19:36 -0700 | [diff] [blame] | 1718 | void Buncond(MipsLabel* label, bool is_r6, bool is_bare); |
| 1719 | void Bcond(MipsLabel* label, |
| 1720 | bool is_r6, |
| 1721 | bool is_bare, |
| 1722 | BranchCondition condition, |
| 1723 | Register lhs, |
| 1724 | Register rhs = ZERO); |
| 1725 | void Call(MipsLabel* label, bool is_r6, bool is_bare); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1726 | void FinalizeLabeledBranch(MipsLabel* label); |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1727 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1728 | // Various helpers for branch delay slot management. |
Alexey Frunze | a247dea | 2017-11-03 18:43:04 -0700 | [diff] [blame] | 1729 | InOutRegMasks& DsFsmInstr(uint32_t instruction, MipsLabel* patcher_label = nullptr); |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1730 | void DsFsmInstrNop(uint32_t instruction); |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1731 | void DsFsmLabel(); |
| 1732 | void DsFsmCommitLabel(); |
| 1733 | void DsFsmDropLabel(); |
| 1734 | void MoveInstructionToDelaySlot(Branch& branch); |
| 1735 | bool CanExchangeWithSlt(Register rs, Register rt) const; |
| 1736 | void ExchangeWithSlt(const DelaySlot& forwarded_slot); |
| 1737 | void GenerateSltForCondBranch(bool unsigned_slt, Register rs, Register rt); |
| 1738 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1739 | Branch* GetBranch(uint32_t branch_id); |
| 1740 | const Branch* GetBranch(uint32_t branch_id) const; |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1741 | uint32_t GetBranchLocationOrPcRelBase(const MipsAssembler::Branch* branch) const; |
| 1742 | uint32_t GetBranchOrPcRelBaseForEncoding(const MipsAssembler::Branch* branch) const; |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 1743 | void BindRelativeToPrecedingBranch(MipsLabel* label, |
| 1744 | uint32_t prev_branch_id_plus_one, |
| 1745 | uint32_t position); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1746 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1747 | void EmitLiterals(); |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1748 | void ReserveJumpTableSpace(); |
| 1749 | void EmitJumpTables(); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1750 | void PromoteBranches(); |
Alexey Frunze | a663d9d | 2017-07-31 18:43:18 -0700 | [diff] [blame] | 1751 | void EmitBranch(uint32_t branch_id); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1752 | void EmitBranches(); |
Vladimir Marko | 10ef694 | 2015-10-22 15:25:54 +0100 | [diff] [blame] | 1753 | void PatchCFI(size_t number_of_delayed_adjust_pcs); |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1754 | |
| 1755 | // Emits exception block. |
| 1756 | void EmitExceptionPoll(MipsExceptionSlowPath* exception); |
| 1757 | |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 1758 | bool HasMsa() const { |
| 1759 | return has_msa_; |
| 1760 | } |
| 1761 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1762 | bool IsR6() const { |
| 1763 | if (isa_features_ != nullptr) { |
| 1764 | return isa_features_->IsR6(); |
| 1765 | } else { |
| 1766 | return false; |
| 1767 | } |
Goran Jakovljevic | ff73498 | 2015-08-24 12:58:55 +0000 | [diff] [blame] | 1768 | } |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1769 | |
| 1770 | bool Is32BitFPU() const { |
| 1771 | if (isa_features_ != nullptr) { |
| 1772 | return isa_features_->Is32BitFloatingPoint(); |
| 1773 | } else { |
| 1774 | return true; |
| 1775 | } |
Goran Jakovljevic | ff73498 | 2015-08-24 12:58:55 +0000 | [diff] [blame] | 1776 | } |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1777 | |
| 1778 | // List of exception blocks to generate at the end of the code cache. |
| 1779 | std::vector<MipsExceptionSlowPath> exception_blocks_; |
| 1780 | |
| 1781 | std::vector<Branch> branches_; |
| 1782 | |
| 1783 | // Whether appending instructions at the end of the buffer or overwriting the existing ones. |
| 1784 | bool overwriting_; |
| 1785 | // The current overwrite location. |
| 1786 | uint32_t overwrite_location_; |
| 1787 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1788 | // Whether instruction reordering (IOW, automatic filling of delay slots) is enabled. |
| 1789 | bool reordering_; |
| 1790 | // Information about the last instruction that may be used to fill a branch delay slot. |
| 1791 | DelaySlot delay_slot_; |
| 1792 | // Delay slot FSM state. |
| 1793 | DsFsmState ds_fsm_state_; |
| 1794 | // PC of the current labeled target instruction. |
| 1795 | uint32_t ds_fsm_target_pc_; |
| 1796 | // PCs of labeled target instructions. |
| 1797 | std::vector<uint32_t> ds_fsm_target_pcs_; |
| 1798 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1799 | // Use std::deque<> for literal labels to allow insertions at the end |
| 1800 | // without invalidating pointers and references to existing elements. |
| 1801 | ArenaDeque<Literal> literals_; |
| 1802 | |
Alexey Frunze | 96b6682 | 2016-09-10 02:32:44 -0700 | [diff] [blame] | 1803 | // Jump table list. |
| 1804 | ArenaDeque<JumpTable> jump_tables_; |
| 1805 | |
Alexey Frunze | e3fb245 | 2016-05-10 16:08:05 -0700 | [diff] [blame] | 1806 | // There's no PC-relative addressing on MIPS32R2. So, in order to access literals relative to PC |
| 1807 | // we get PC using the NAL instruction. This label marks the position within the assembler buffer |
| 1808 | // that PC (from NAL) points to. |
| 1809 | MipsLabel pc_rel_base_label_; |
| 1810 | |
Alexey Frunze | 57eb0f5 | 2016-07-29 22:04:46 -0700 | [diff] [blame] | 1811 | // Data for GetAdjustedPosition(), see the description there. |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1812 | uint32_t last_position_adjustment_; |
| 1813 | uint32_t last_old_position_; |
| 1814 | uint32_t last_branch_id_; |
| 1815 | |
Lena Djokic | 0758ae7 | 2017-05-23 11:06:23 +0200 | [diff] [blame] | 1816 | const bool has_msa_; |
| 1817 | |
Goran Jakovljevic | 8c434dc | 2015-08-26 14:39:44 +0200 | [diff] [blame] | 1818 | const MipsInstructionSetFeatures* isa_features_; |
Goran Jakovljevic | ff73498 | 2015-08-24 12:58:55 +0000 | [diff] [blame] | 1819 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1820 | DISALLOW_COPY_AND_ASSIGN(MipsAssembler); |
| 1821 | }; |
| 1822 | |
jeffhao | 7fbee07 | 2012-08-24 17:56:54 -0700 | [diff] [blame] | 1823 | } // namespace mips |
| 1824 | } // namespace art |
| 1825 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 1826 | #endif // ART_COMPILER_UTILS_MIPS_ASSEMBLER_MIPS_H_ |