Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the Mips ISA */ |
| 18 | |
| 19 | #include "codegen_mips.h" |
| 20 | #include "dex/quick/mir_to_lir-inl.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 21 | #include "entrypoints/quick/quick_entrypoints.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 22 | #include "mips_lir.h" |
| 23 | #include "mirror/array.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 24 | |
| 25 | namespace art { |
| 26 | |
| 27 | /* |
| 28 | * Compare two 64-bit values |
| 29 | * x = y return 0 |
| 30 | * x < y return -1 |
| 31 | * x > y return 1 |
| 32 | * |
| 33 | * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 |
| 34 | * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 |
| 35 | * subu res, t0, t1 # res = -1:1:0 for [ < > = ] |
| 36 | * bnez res, finish |
| 37 | * sltu t0, x.lo, y.lo |
| 38 | * sgtu r1, x.lo, y.lo |
| 39 | * subu res, t0, t1 |
| 40 | * finish: |
| 41 | * |
| 42 | */ |
| 43 | void MipsMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 44 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 45 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 46 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 47 | int t0 = AllocTemp().GetReg(); |
| 48 | int t1 = AllocTemp().GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 50 | NewLIR3(kMipsSlt, t0, rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); |
| 51 | NewLIR3(kMipsSlt, t1, rl_src2.reg.GetHighReg(), rl_src1.reg.GetHighReg()); |
| 52 | NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1, t0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 53 | LIR* branch = OpCmpImmBranch(kCondNe, rl_result.reg, 0, NULL); |
| 54 | NewLIR3(kMipsSltu, t0, rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); |
| 55 | NewLIR3(kMipsSltu, t1, rl_src2.reg.GetLowReg(), rl_src1.reg.GetLowReg()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 56 | NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1, t0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 57 | FreeTemp(t0); |
| 58 | FreeTemp(t1); |
| 59 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 60 | branch->target = target; |
| 61 | StoreValue(rl_dest, rl_result); |
| 62 | } |
| 63 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 64 | LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 65 | LIR* branch; |
| 66 | MipsOpCode slt_op; |
| 67 | MipsOpCode br_op; |
| 68 | bool cmp_zero = false; |
| 69 | bool swapped = false; |
| 70 | switch (cond) { |
| 71 | case kCondEq: |
| 72 | br_op = kMipsBeq; |
| 73 | cmp_zero = true; |
| 74 | break; |
| 75 | case kCondNe: |
| 76 | br_op = kMipsBne; |
| 77 | cmp_zero = true; |
| 78 | break; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 79 | case kCondUlt: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 80 | slt_op = kMipsSltu; |
| 81 | br_op = kMipsBnez; |
| 82 | break; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 83 | case kCondUge: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 84 | slt_op = kMipsSltu; |
| 85 | br_op = kMipsBeqz; |
| 86 | break; |
| 87 | case kCondGe: |
| 88 | slt_op = kMipsSlt; |
| 89 | br_op = kMipsBeqz; |
| 90 | break; |
| 91 | case kCondGt: |
| 92 | slt_op = kMipsSlt; |
| 93 | br_op = kMipsBnez; |
| 94 | swapped = true; |
| 95 | break; |
| 96 | case kCondLe: |
| 97 | slt_op = kMipsSlt; |
| 98 | br_op = kMipsBeqz; |
| 99 | swapped = true; |
| 100 | break; |
| 101 | case kCondLt: |
| 102 | slt_op = kMipsSlt; |
| 103 | br_op = kMipsBnez; |
| 104 | break; |
| 105 | case kCondHi: // Gtu |
| 106 | slt_op = kMipsSltu; |
| 107 | br_op = kMipsBnez; |
| 108 | swapped = true; |
| 109 | break; |
| 110 | default: |
| 111 | LOG(FATAL) << "No support for ConditionCode: " << cond; |
| 112 | return NULL; |
| 113 | } |
| 114 | if (cmp_zero) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 115 | branch = NewLIR2(br_op, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 116 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 117 | int t_reg = AllocTemp().GetReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 118 | if (swapped) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 119 | NewLIR3(slt_op, t_reg, src2.GetReg(), src1.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 120 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 121 | NewLIR3(slt_op, t_reg, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 122 | } |
| 123 | branch = NewLIR1(br_op, t_reg); |
| 124 | FreeTemp(t_reg); |
| 125 | } |
| 126 | branch->target = target; |
| 127 | return branch; |
| 128 | } |
| 129 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 130 | LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 131 | LIR* branch; |
| 132 | if (check_value != 0) { |
| 133 | // TUNING: handle s16 & kCondLt/Mi case using slti |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 134 | RegStorage t_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 135 | LoadConstant(t_reg, check_value); |
| 136 | branch = OpCmpBranch(cond, reg, t_reg, target); |
| 137 | FreeTemp(t_reg); |
| 138 | return branch; |
| 139 | } |
| 140 | MipsOpCode opc; |
| 141 | switch (cond) { |
| 142 | case kCondEq: opc = kMipsBeqz; break; |
| 143 | case kCondGe: opc = kMipsBgez; break; |
| 144 | case kCondGt: opc = kMipsBgtz; break; |
| 145 | case kCondLe: opc = kMipsBlez; break; |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 146 | // case KCondMi: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 147 | case kCondLt: opc = kMipsBltz; break; |
| 148 | case kCondNe: opc = kMipsBnez; break; |
| 149 | default: |
| 150 | // Tuning: use slti when applicable |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 151 | RegStorage t_reg = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 152 | LoadConstant(t_reg, check_value); |
| 153 | branch = OpCmpBranch(cond, reg, t_reg, target); |
| 154 | FreeTemp(t_reg); |
| 155 | return branch; |
| 156 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 157 | branch = NewLIR1(opc, reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 158 | branch->target = target; |
| 159 | return branch; |
| 160 | } |
| 161 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 162 | LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
| 163 | // If src or dest is a pair, we'll be using low reg. |
| 164 | if (r_dest.IsPair()) { |
| 165 | r_dest = r_dest.GetLow(); |
| 166 | } |
| 167 | if (r_src.IsPair()) { |
| 168 | r_src = r_src.GetLow(); |
| 169 | } |
| 170 | if (MIPS_FPREG(r_dest.GetReg()) || MIPS_FPREG(r_src.GetReg())) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 171 | return OpFpRegCopy(r_dest, r_src); |
| 172 | LIR* res = RawLIR(current_dalvik_offset_, kMipsMove, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 173 | r_dest.GetReg(), r_src.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 174 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
| 175 | res->flags.is_nop = true; |
| 176 | } |
| 177 | return res; |
| 178 | } |
| 179 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 180 | LIR* MipsMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 181 | LIR *res = OpRegCopyNoInsert(r_dest, r_src); |
| 182 | AppendLIR(res); |
| 183 | return res; |
| 184 | } |
| 185 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 186 | void MipsMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
| 187 | bool dest_fp = MIPS_FPREG(r_dest.GetLowReg()); |
| 188 | bool src_fp = MIPS_FPREG(r_src.GetLowReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 189 | if (dest_fp) { |
| 190 | if (src_fp) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 191 | // FIXME: handle this here - reserve OpRegCopy for 32-bit copies. |
| 192 | OpRegCopy(RegStorage::Solo64(S2d(r_dest.GetLowReg(), r_dest.GetHighReg())), |
| 193 | RegStorage::Solo64(S2d(r_src.GetLowReg(), r_src.GetHighReg()))); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 194 | } else { |
| 195 | /* note the operands are swapped for the mtc1 instr */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 196 | NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetLowReg()); |
| 197 | NewLIR2(kMipsMtc1, r_src.GetHighReg(), r_dest.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 198 | } |
| 199 | } else { |
| 200 | if (src_fp) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 201 | NewLIR2(kMipsMfc1, r_dest.GetLowReg(), r_src.GetLowReg()); |
| 202 | NewLIR2(kMipsMfc1, r_dest.GetHighReg(), r_src.GetHighReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 203 | } else { |
| 204 | // Handle overlap |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 205 | if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 206 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 207 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 208 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 209 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 210 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 211 | } |
| 212 | } |
| 213 | } |
| 214 | } |
| 215 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 216 | void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 217 | UNIMPLEMENTED(FATAL) << "Need codegen for select"; |
| 218 | } |
| 219 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 220 | void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 221 | UNIMPLEMENTED(FATAL) << "Need codegen for fused long cmp branch"; |
| 222 | } |
| 223 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 224 | RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStorage reg2, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 225 | bool is_div) { |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 226 | NewLIR2(kMipsDiv, reg1.GetReg(), reg2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 227 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 228 | if (is_div) { |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 229 | NewLIR1(kMipsMflo, rl_result.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 230 | } else { |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 231 | NewLIR1(kMipsMfhi, rl_result.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 232 | } |
| 233 | return rl_result; |
| 234 | } |
| 235 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 236 | RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 237 | bool is_div) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 238 | int t_reg = AllocTemp().GetReg(); |
| 239 | NewLIR3(kMipsAddiu, t_reg, rZERO, lit); |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 240 | NewLIR2(kMipsDiv, reg1.GetReg(), t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 241 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 242 | if (is_div) { |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 243 | NewLIR1(kMipsMflo, rl_result.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 244 | } else { |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 245 | NewLIR1(kMipsMfhi, rl_result.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 246 | } |
| 247 | FreeTemp(t_reg); |
| 248 | return rl_result; |
| 249 | } |
| 250 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 251 | RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
| 252 | RegLocation rl_src2, bool is_div, bool check_zero) { |
| 253 | LOG(FATAL) << "Unexpected use of GenDivRem for Mips"; |
| 254 | return rl_dest; |
| 255 | } |
| 256 | |
| 257 | RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) { |
| 258 | LOG(FATAL) << "Unexpected use of GenDivRemLit for Mips"; |
| 259 | return rl_dest; |
| 260 | } |
| 261 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 262 | void MipsMir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, |
| 263 | int offset) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 264 | LOG(FATAL) << "Unexpected use of OpLea for Arm"; |
| 265 | } |
| 266 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 267 | void MipsMir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 268 | LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm"; |
| 269 | } |
| 270 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 271 | bool MipsMir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 272 | DCHECK_NE(cu_->instruction_set, kThumb2); |
| 273 | return false; |
| 274 | } |
| 275 | |
| 276 | bool MipsMir2Lir::GenInlinedSqrt(CallInfo* info) { |
| 277 | DCHECK_NE(cu_->instruction_set, kThumb2); |
| 278 | return false; |
| 279 | } |
| 280 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 281 | bool MipsMir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
| 282 | if (size != kSignedByte) { |
| 283 | // MIPS supports only aligned access. Defer unaligned access to JNI implementation. |
| 284 | return false; |
| 285 | } |
| 286 | RegLocation rl_src_address = info->args[0]; // long address |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 287 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 288 | RegLocation rl_dest = InlineTarget(info); |
| 289 | RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); |
| 290 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 291 | DCHECK(size == kSignedByte); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 292 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, INVALID_SREG); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 293 | StoreValue(rl_dest, rl_result); |
| 294 | return true; |
| 295 | } |
| 296 | |
| 297 | bool MipsMir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
| 298 | if (size != kSignedByte) { |
| 299 | // MIPS supports only aligned access. Defer unaligned access to JNI implementation. |
| 300 | return false; |
| 301 | } |
| 302 | RegLocation rl_src_address = info->args[0]; // long address |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 303 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 304 | RegLocation rl_src_value = info->args[2]; // [size] value |
| 305 | RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); |
| 306 | DCHECK(size == kSignedByte); |
| 307 | RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 308 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 309 | return true; |
| 310 | } |
| 311 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 312 | LIR* MipsMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 313 | LOG(FATAL) << "Unexpected use of OpPcRelLoad for Mips"; |
| 314 | return NULL; |
| 315 | } |
| 316 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 317 | LIR* MipsMir2Lir::OpVldm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 318 | LOG(FATAL) << "Unexpected use of OpVldm for Mips"; |
| 319 | return NULL; |
| 320 | } |
| 321 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 322 | LIR* MipsMir2Lir::OpVstm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 323 | LOG(FATAL) << "Unexpected use of OpVstm for Mips"; |
| 324 | return NULL; |
| 325 | } |
| 326 | |
| 327 | void MipsMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 328 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 329 | int first_bit, int second_bit) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 330 | RegStorage t_reg = AllocTemp(); |
| 331 | OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); |
| 332 | OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 333 | FreeTemp(t_reg); |
| 334 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 335 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 336 | } |
| 337 | } |
| 338 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 339 | void MipsMir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 340 | DCHECK(reg.IsPair()); // TODO: support k64BitSolo. |
| 341 | RegStorage t_reg = AllocTemp(); |
| 342 | OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); |
Mingyao Yang | d15f4e2 | 2014-04-17 18:46:24 -0700 | [diff] [blame] | 343 | GenDivZeroCheck(t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 344 | FreeTemp(t_reg); |
| 345 | } |
| 346 | |
| 347 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 348 | LIR* MipsMir2Lir::OpTestSuspend(LIR* target) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 349 | OpRegImm(kOpSub, rs_rMIPS_SUSPEND, 1); |
| 350 | return OpCmpImmBranch((target == NULL) ? kCondEq : kCondNe, rs_rMIPS_SUSPEND, 0, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | // Decrement register and branch on condition |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 354 | LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 355 | OpRegImm(kOpSub, reg, 1); |
| 356 | return OpCmpImmBranch(c_code, reg, 0, target); |
| 357 | } |
| 358 | |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 359 | bool MipsMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 360 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 361 | LOG(FATAL) << "Unexpected use of smallLiteralDive in Mips"; |
| 362 | return false; |
| 363 | } |
| 364 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 365 | bool MipsMir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
| 366 | LOG(FATAL) << "Unexpected use of easyMultiply in Mips"; |
| 367 | return false; |
| 368 | } |
| 369 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 370 | LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 371 | LOG(FATAL) << "Unexpected use of OpIT in Mips"; |
| 372 | return NULL; |
| 373 | } |
| 374 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 375 | void MipsMir2Lir::OpEndIT(LIR* it) { |
| 376 | LOG(FATAL) << "Unexpected use of OpEndIT in Mips"; |
| 377 | } |
| 378 | |
| 379 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 380 | void MipsMir2Lir::GenMulLong(Instruction::Code opcode, RegLocation rl_dest, |
| 381 | RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 382 | LOG(FATAL) << "Unexpected use of GenMulLong for Mips"; |
| 383 | } |
| 384 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 385 | void MipsMir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, |
| 386 | RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 387 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 388 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 389 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 390 | /* |
| 391 | * [v1 v0] = [a1 a0] + [a3 a2]; |
| 392 | * addu v0,a2,a0 |
| 393 | * addu t1,a3,a1 |
| 394 | * sltu v1,v0,a2 |
| 395 | * addu v1,v1,t1 |
| 396 | */ |
| 397 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 398 | OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src2.reg.GetLow(), rl_src1.reg.GetLow()); |
| 399 | RegStorage t_reg = AllocTemp(); |
| 400 | OpRegRegReg(kOpAdd, t_reg, rl_src2.reg.GetHigh(), rl_src1.reg.GetHigh()); |
| 401 | NewLIR3(kMipsSltu, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), rl_src2.reg.GetLowReg()); |
| 402 | OpRegRegReg(kOpAdd, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 403 | FreeTemp(t_reg); |
| 404 | StoreValueWide(rl_dest, rl_result); |
| 405 | } |
| 406 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 407 | void MipsMir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, |
| 408 | RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 409 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 410 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 411 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 412 | /* |
| 413 | * [v1 v0] = [a1 a0] - [a3 a2]; |
| 414 | * sltu t1,a0,a2 |
| 415 | * subu v0,a0,a2 |
| 416 | * subu v1,a1,a3 |
| 417 | * subu v1,v1,t1 |
| 418 | */ |
| 419 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 420 | RegStorage t_reg = AllocTemp(); |
| 421 | NewLIR3(kMipsSltu, t_reg.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); |
| 422 | OpRegRegReg(kOpSub, rl_result.reg.GetLow(), rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); |
| 423 | OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); |
| 424 | OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 425 | FreeTemp(t_reg); |
| 426 | StoreValueWide(rl_dest, rl_result); |
| 427 | } |
| 428 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 429 | void MipsMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 430 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 431 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 432 | /* |
| 433 | * [v1 v0] = -[a1 a0] |
| 434 | * negu v0,a0 |
| 435 | * negu v1,a1 |
| 436 | * sltu t1,r_zero |
| 437 | * subu v1,v1,t1 |
| 438 | */ |
| 439 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 440 | OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
| 441 | OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 442 | RegStorage t_reg = AllocTemp(); |
| 443 | NewLIR3(kMipsSltu, t_reg.GetReg(), rZERO, rl_result.reg.GetLowReg()); |
| 444 | OpRegRegReg(kOpSub, rl_result.reg.GetHigh(), rl_result.reg.GetHigh(), t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 445 | FreeTemp(t_reg); |
| 446 | StoreValueWide(rl_dest, rl_result); |
| 447 | } |
| 448 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 449 | void MipsMir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, |
| 450 | RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 451 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 452 | LOG(FATAL) << "Unexpected use of GenAndLong for Mips"; |
| 453 | } |
| 454 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 455 | void MipsMir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, |
| 456 | RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 457 | LOG(FATAL) << "Unexpected use of GenOrLong for Mips"; |
| 458 | } |
| 459 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 460 | void MipsMir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, |
| 461 | RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 462 | LOG(FATAL) << "Unexpected use of GenXorLong for Mips"; |
| 463 | } |
| 464 | |
| 465 | /* |
| 466 | * Generate array load |
| 467 | */ |
| 468 | void MipsMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 469 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 470 | RegisterClass reg_class = oat_reg_class_by_size(size); |
| 471 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 472 | int data_offset; |
| 473 | RegLocation rl_result; |
| 474 | rl_array = LoadValue(rl_array, kCoreReg); |
| 475 | rl_index = LoadValue(rl_index, kCoreReg); |
| 476 | |
| 477 | if (size == kLong || size == kDouble) { |
| 478 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 479 | } else { |
| 480 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 481 | } |
| 482 | |
| 483 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 484 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 485 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 486 | RegStorage reg_ptr = AllocTemp(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 487 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 488 | RegStorage reg_len; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 489 | if (needs_range_check) { |
| 490 | reg_len = AllocTemp(); |
| 491 | /* Get len */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 492 | LoadWordDisp(rl_array.reg, len_offset, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 493 | } |
| 494 | /* reg_ptr -> array data */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 495 | OpRegRegImm(kOpAdd, reg_ptr, rl_array.reg, data_offset); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 496 | FreeTemp(rl_array.reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 497 | if ((size == kLong) || (size == kDouble)) { |
| 498 | if (scale) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 499 | RegStorage r_new_index = AllocTemp(); |
| 500 | OpRegRegImm(kOpLsl, r_new_index, rl_index.reg, scale); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 501 | OpRegReg(kOpAdd, reg_ptr, r_new_index); |
| 502 | FreeTemp(r_new_index); |
| 503 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 504 | OpRegReg(kOpAdd, reg_ptr, rl_index.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 505 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 506 | FreeTemp(rl_index.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 507 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 508 | |
| 509 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 510 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 511 | FreeTemp(reg_len); |
| 512 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 513 | LoadBaseDispWide(reg_ptr, 0, rl_result.reg, INVALID_SREG); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 514 | |
| 515 | FreeTemp(reg_ptr); |
| 516 | StoreValueWide(rl_dest, rl_result); |
| 517 | } else { |
| 518 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 519 | |
| 520 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 521 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 522 | FreeTemp(reg_len); |
| 523 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 524 | LoadBaseIndexed(reg_ptr, rl_index.reg, rl_result.reg, scale, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 525 | |
| 526 | FreeTemp(reg_ptr); |
| 527 | StoreValue(rl_dest, rl_result); |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | /* |
| 532 | * Generate array store |
| 533 | * |
| 534 | */ |
| 535 | void MipsMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 536 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 537 | RegisterClass reg_class = oat_reg_class_by_size(size); |
| 538 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 539 | int data_offset; |
| 540 | |
| 541 | if (size == kLong || size == kDouble) { |
| 542 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 543 | } else { |
| 544 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 545 | } |
| 546 | |
| 547 | rl_array = LoadValue(rl_array, kCoreReg); |
| 548 | rl_index = LoadValue(rl_index, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 549 | RegStorage reg_ptr; |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 550 | bool allocated_reg_ptr_temp = false; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 551 | if (IsTemp(rl_array.reg.GetReg()) && !card_mark) { |
| 552 | Clobber(rl_array.reg.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 553 | reg_ptr = rl_array.reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 554 | } else { |
| 555 | reg_ptr = AllocTemp(); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 556 | OpRegCopy(reg_ptr, rl_array.reg); |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 557 | allocated_reg_ptr_temp = true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 558 | } |
| 559 | |
| 560 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 561 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 562 | |
| 563 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 564 | RegStorage reg_len; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 565 | if (needs_range_check) { |
| 566 | reg_len = AllocTemp(); |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 567 | // NOTE: max live temps(4) here. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 568 | /* Get len */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 569 | LoadWordDisp(rl_array.reg, len_offset, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 570 | } |
| 571 | /* reg_ptr -> array data */ |
| 572 | OpRegImm(kOpAdd, reg_ptr, data_offset); |
| 573 | /* at this point, reg_ptr points to array, 2 live temps */ |
| 574 | if ((size == kLong) || (size == kDouble)) { |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 575 | // TUNING: specific wide routine that can handle fp regs |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 576 | if (scale) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 577 | RegStorage r_new_index = AllocTemp(); |
| 578 | OpRegRegImm(kOpLsl, r_new_index, rl_index.reg, scale); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 579 | OpRegReg(kOpAdd, reg_ptr, r_new_index); |
| 580 | FreeTemp(r_new_index); |
| 581 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 582 | OpRegReg(kOpAdd, reg_ptr, rl_index.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 583 | } |
| 584 | rl_src = LoadValueWide(rl_src, reg_class); |
| 585 | |
| 586 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 587 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 588 | FreeTemp(reg_len); |
| 589 | } |
| 590 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 591 | StoreBaseDispWide(reg_ptr, 0, rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 592 | } else { |
| 593 | rl_src = LoadValue(rl_src, reg_class); |
| 594 | if (needs_range_check) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 595 | GenArrayBoundsCheck(rl_index.reg, reg_len); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 596 | FreeTemp(reg_len); |
| 597 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 598 | StoreBaseIndexed(reg_ptr, rl_index.reg, rl_src.reg, scale, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 599 | } |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 600 | if (allocated_reg_ptr_temp) { |
| 601 | FreeTemp(reg_ptr); |
| 602 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 603 | if (card_mark) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 604 | MarkGCCard(rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 605 | } |
| 606 | } |
| 607 | |
| 608 | void MipsMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 609 | RegLocation rl_src1, RegLocation rl_shift) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 610 | // Default implementation is just to ignore the constant case. |
| 611 | GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift); |
| 612 | } |
| 613 | |
| 614 | void MipsMir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 615 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 616 | // Default - bail to non-const handler. |
| 617 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 618 | } |
| 619 | |
| 620 | } // namespace art |