Sebastien Hertz | 807a256 | 2013-04-15 09:33:39 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_SRC_DEX_INSTRUCTION_INL_H_ |
| 18 | #define ART_SRC_DEX_INSTRUCTION_INL_H_ |
| 19 | |
| 20 | #include "dex_instruction.h" |
| 21 | |
| 22 | namespace art { |
| 23 | |
Jeff Hao | 9cec247 | 2013-05-14 18:17:06 -0700 | [diff] [blame] | 24 | inline const Instruction* Instruction::Next_51l() const { |
| 25 | DCHECK_EQ(FormatOf(Opcode()), k51l); |
| 26 | size_t current_size_in_bytes = 5 * sizeof(uint16_t); |
| 27 | const uint8_t* ptr = reinterpret_cast<const uint8_t*>(this); |
| 28 | return reinterpret_cast<const Instruction*>(ptr + current_size_in_bytes); |
| 29 | } |
| 30 | |
Sebastien Hertz | 807a256 | 2013-04-15 09:33:39 +0200 | [diff] [blame] | 31 | //------------------------------------------------------------------------------ |
| 32 | // VRegA |
| 33 | //------------------------------------------------------------------------------ |
| 34 | inline int8_t Instruction::VRegA_10t() const { |
| 35 | DCHECK_EQ(FormatOf(Opcode()), k10t); |
| 36 | return static_cast<int8_t>(InstAA()); |
| 37 | } |
| 38 | |
Sebastien Hertz | 5243e91 | 2013-05-21 10:55:07 +0200 | [diff] [blame^] | 39 | inline uint8_t Instruction::VRegA_10x() const { |
| 40 | DCHECK_EQ(FormatOf(Opcode()), k10x); |
| 41 | return InstAA(); |
| 42 | } |
| 43 | |
Sebastien Hertz | 807a256 | 2013-04-15 09:33:39 +0200 | [diff] [blame] | 44 | inline uint4_t Instruction::VRegA_11n() const { |
| 45 | DCHECK_EQ(FormatOf(Opcode()), k11n); |
| 46 | return InstA(); |
| 47 | } |
| 48 | |
| 49 | inline uint8_t Instruction::VRegA_11x() const { |
| 50 | DCHECK_EQ(FormatOf(Opcode()), k11x); |
| 51 | return InstAA(); |
| 52 | } |
| 53 | |
| 54 | inline uint4_t Instruction::VRegA_12x() const { |
| 55 | DCHECK_EQ(FormatOf(Opcode()), k12x); |
| 56 | return InstA(); |
| 57 | } |
| 58 | |
| 59 | inline int16_t Instruction::VRegA_20t() const { |
| 60 | DCHECK_EQ(FormatOf(Opcode()), k20t); |
| 61 | return static_cast<int16_t>(Fetch16(1)); |
| 62 | } |
| 63 | |
| 64 | inline uint8_t Instruction::VRegA_21c() const { |
| 65 | DCHECK_EQ(FormatOf(Opcode()), k21c); |
| 66 | return InstAA(); |
| 67 | } |
| 68 | |
| 69 | inline uint8_t Instruction::VRegA_21h() const { |
| 70 | DCHECK_EQ(FormatOf(Opcode()), k21h); |
| 71 | return InstAA(); |
| 72 | } |
| 73 | |
| 74 | inline uint8_t Instruction::VRegA_21s() const { |
| 75 | DCHECK_EQ(FormatOf(Opcode()), k21s); |
| 76 | return InstAA(); |
| 77 | } |
| 78 | |
| 79 | inline uint8_t Instruction::VRegA_21t() const { |
| 80 | DCHECK_EQ(FormatOf(Opcode()), k21t); |
| 81 | return InstAA(); |
| 82 | } |
| 83 | |
| 84 | inline uint8_t Instruction::VRegA_22b() const { |
| 85 | DCHECK_EQ(FormatOf(Opcode()), k22b); |
| 86 | return InstAA(); |
| 87 | } |
| 88 | |
| 89 | inline uint4_t Instruction::VRegA_22c() const { |
| 90 | DCHECK_EQ(FormatOf(Opcode()), k22c); |
| 91 | return InstA(); |
| 92 | } |
| 93 | |
| 94 | inline uint4_t Instruction::VRegA_22s() const { |
| 95 | DCHECK_EQ(FormatOf(Opcode()), k22s); |
| 96 | return InstA(); |
| 97 | } |
| 98 | |
| 99 | inline uint4_t Instruction::VRegA_22t() const { |
| 100 | DCHECK_EQ(FormatOf(Opcode()), k22t); |
| 101 | return InstA(); |
| 102 | } |
| 103 | |
| 104 | inline uint8_t Instruction::VRegA_22x() const { |
| 105 | DCHECK_EQ(FormatOf(Opcode()), k22x); |
| 106 | return InstAA(); |
| 107 | } |
| 108 | |
| 109 | inline uint8_t Instruction::VRegA_23x() const { |
| 110 | DCHECK_EQ(FormatOf(Opcode()), k23x); |
| 111 | return InstAA(); |
| 112 | } |
| 113 | |
| 114 | inline int32_t Instruction::VRegA_30t() const { |
| 115 | DCHECK_EQ(FormatOf(Opcode()), k30t); |
| 116 | return static_cast<int32_t>(Fetch32(1)); |
| 117 | } |
| 118 | |
| 119 | inline uint8_t Instruction::VRegA_31c() const { |
| 120 | DCHECK_EQ(FormatOf(Opcode()), k31c); |
| 121 | return InstAA(); |
| 122 | } |
| 123 | |
| 124 | inline uint8_t Instruction::VRegA_31i() const { |
| 125 | DCHECK_EQ(FormatOf(Opcode()), k31i); |
| 126 | return InstAA(); |
| 127 | } |
| 128 | |
| 129 | inline uint8_t Instruction::VRegA_31t() const { |
| 130 | DCHECK_EQ(FormatOf(Opcode()), k31t); |
| 131 | return InstAA(); |
| 132 | } |
| 133 | |
| 134 | inline uint16_t Instruction::VRegA_32x() const { |
| 135 | DCHECK_EQ(FormatOf(Opcode()), k32x); |
| 136 | return Fetch16(1); |
| 137 | } |
| 138 | |
| 139 | inline uint4_t Instruction::VRegA_35c() const { |
| 140 | DCHECK_EQ(FormatOf(Opcode()), k35c); |
| 141 | return InstB(); // This is labeled A in the spec. |
| 142 | } |
| 143 | |
| 144 | inline uint8_t Instruction::VRegA_3rc() const { |
| 145 | DCHECK_EQ(FormatOf(Opcode()), k3rc); |
| 146 | return InstAA(); |
| 147 | } |
| 148 | |
| 149 | inline uint8_t Instruction::VRegA_51l() const { |
| 150 | DCHECK_EQ(FormatOf(Opcode()), k51l); |
| 151 | return InstAA(); |
| 152 | } |
| 153 | |
| 154 | //------------------------------------------------------------------------------ |
| 155 | // VRegB |
| 156 | //------------------------------------------------------------------------------ |
| 157 | inline int4_t Instruction::VRegB_11n() const { |
| 158 | DCHECK_EQ(FormatOf(Opcode()), k11n); |
| 159 | return static_cast<int4_t>((InstB() << 28) >> 28); |
| 160 | } |
| 161 | |
| 162 | inline uint4_t Instruction::VRegB_12x() const { |
| 163 | DCHECK_EQ(FormatOf(Opcode()), k12x); |
| 164 | return InstB(); |
| 165 | } |
| 166 | |
| 167 | inline uint16_t Instruction::VRegB_21c() const { |
| 168 | DCHECK_EQ(FormatOf(Opcode()), k21c); |
| 169 | return Fetch16(1); |
| 170 | } |
| 171 | |
| 172 | inline uint16_t Instruction::VRegB_21h() const { |
| 173 | DCHECK_EQ(FormatOf(Opcode()), k21h); |
| 174 | return Fetch16(1); |
| 175 | } |
| 176 | |
| 177 | inline int16_t Instruction::VRegB_21s() const { |
| 178 | DCHECK_EQ(FormatOf(Opcode()), k21s); |
| 179 | return static_cast<int16_t>(Fetch16(1)); |
| 180 | } |
| 181 | |
| 182 | inline int16_t Instruction::VRegB_21t() const { |
| 183 | DCHECK_EQ(FormatOf(Opcode()), k21t); |
| 184 | return static_cast<int16_t>(Fetch16(1)); |
| 185 | } |
| 186 | |
| 187 | inline uint8_t Instruction::VRegB_22b() const { |
| 188 | DCHECK_EQ(FormatOf(Opcode()), k22b); |
| 189 | return static_cast<uint8_t>(Fetch16(1) & 0xff); |
| 190 | } |
| 191 | |
| 192 | inline uint4_t Instruction::VRegB_22c() const { |
| 193 | DCHECK_EQ(FormatOf(Opcode()), k22c); |
| 194 | return InstB(); |
| 195 | } |
| 196 | |
| 197 | inline uint4_t Instruction::VRegB_22s() const { |
| 198 | DCHECK_EQ(FormatOf(Opcode()), k22s); |
| 199 | return InstB(); |
| 200 | } |
| 201 | |
| 202 | inline uint4_t Instruction::VRegB_22t() const { |
| 203 | DCHECK_EQ(FormatOf(Opcode()), k22t); |
| 204 | return InstB(); |
| 205 | } |
| 206 | |
| 207 | inline uint16_t Instruction::VRegB_22x() const { |
| 208 | DCHECK_EQ(FormatOf(Opcode()), k22x); |
| 209 | return Fetch16(1); |
| 210 | } |
| 211 | |
| 212 | inline uint8_t Instruction::VRegB_23x() const { |
| 213 | DCHECK_EQ(FormatOf(Opcode()), k23x); |
| 214 | return static_cast<uint8_t>(Fetch16(1) & 0xff); |
| 215 | } |
| 216 | |
| 217 | inline uint32_t Instruction::VRegB_31c() const { |
| 218 | DCHECK_EQ(FormatOf(Opcode()), k31c); |
| 219 | return Fetch32(1); |
| 220 | } |
| 221 | |
| 222 | inline int32_t Instruction::VRegB_31i() const { |
| 223 | DCHECK_EQ(FormatOf(Opcode()), k31i); |
| 224 | return static_cast<int32_t>(Fetch32(1)); |
| 225 | } |
| 226 | |
| 227 | inline int32_t Instruction::VRegB_31t() const { |
| 228 | DCHECK_EQ(FormatOf(Opcode()), k31t); |
| 229 | return static_cast<int32_t>(Fetch32(1)); |
| 230 | } |
| 231 | |
| 232 | inline uint16_t Instruction::VRegB_32x() const { |
| 233 | DCHECK_EQ(FormatOf(Opcode()), k32x); |
| 234 | return Fetch16(2); |
| 235 | } |
| 236 | |
| 237 | inline uint16_t Instruction::VRegB_35c() const { |
| 238 | DCHECK_EQ(FormatOf(Opcode()), k35c); |
| 239 | return Fetch16(1); |
| 240 | } |
| 241 | |
| 242 | inline uint16_t Instruction::VRegB_3rc() const { |
| 243 | DCHECK_EQ(FormatOf(Opcode()), k3rc); |
| 244 | return Fetch16(1); |
| 245 | } |
| 246 | |
| 247 | inline uint64_t Instruction::VRegB_51l() const { |
| 248 | DCHECK_EQ(FormatOf(Opcode()), k51l); |
| 249 | uint64_t vB_wide = Fetch32(1) | ((uint64_t) Fetch32(3) << 32); |
| 250 | return vB_wide; |
| 251 | } |
| 252 | |
| 253 | //------------------------------------------------------------------------------ |
| 254 | // VRegC |
| 255 | //------------------------------------------------------------------------------ |
| 256 | inline int8_t Instruction::VRegC_22b() const { |
| 257 | DCHECK_EQ(FormatOf(Opcode()), k22b); |
| 258 | return static_cast<int8_t>(Fetch16(1) >> 8); |
| 259 | } |
| 260 | |
| 261 | inline uint16_t Instruction::VRegC_22c() const { |
| 262 | DCHECK_EQ(FormatOf(Opcode()), k22c); |
| 263 | return Fetch16(1); |
| 264 | } |
| 265 | |
| 266 | inline int16_t Instruction::VRegC_22s() const { |
| 267 | DCHECK_EQ(FormatOf(Opcode()), k22s); |
| 268 | return static_cast<int16_t>(Fetch16(1)); |
| 269 | } |
| 270 | |
| 271 | inline int16_t Instruction::VRegC_22t() const { |
| 272 | DCHECK_EQ(FormatOf(Opcode()), k22t); |
| 273 | return static_cast<int16_t>(Fetch16(1)); |
| 274 | } |
| 275 | |
| 276 | inline uint8_t Instruction::VRegC_23x() const { |
| 277 | DCHECK_EQ(FormatOf(Opcode()), k23x); |
| 278 | return static_cast<uint8_t>(Fetch16(1) >> 8); |
| 279 | } |
| 280 | |
| 281 | inline uint4_t Instruction::VRegC_35c() const { |
| 282 | DCHECK_EQ(FormatOf(Opcode()), k35c); |
| 283 | return static_cast<uint4_t>(Fetch16(2) & 0x0f); |
| 284 | } |
| 285 | |
| 286 | inline uint16_t Instruction::VRegC_3rc() const { |
| 287 | DCHECK_EQ(FormatOf(Opcode()), k3rc); |
| 288 | return Fetch16(2); |
| 289 | } |
| 290 | |
| 291 | inline void Instruction::GetArgs(uint32_t arg[5]) const { |
| 292 | DCHECK_EQ(FormatOf(Opcode()), k35c); |
| 293 | |
| 294 | /* |
| 295 | * Note that the fields mentioned in the spec don't appear in |
| 296 | * their "usual" positions here compared to most formats. This |
| 297 | * was done so that the field names for the argument count and |
| 298 | * reference index match between this format and the corresponding |
| 299 | * range formats (3rc and friends). |
| 300 | * |
| 301 | * Bottom line: The argument count is always in vA, and the |
| 302 | * method constant (or equivalent) is always in vB. |
| 303 | */ |
| 304 | uint16_t regList = Fetch16(2); |
| 305 | uint4_t count = InstB(); // This is labeled A in the spec. |
| 306 | |
| 307 | /* |
| 308 | * Copy the argument registers into the arg[] array, and |
| 309 | * also copy the first argument (if any) into vC. (The |
| 310 | * DecodedInstruction structure doesn't have separate |
| 311 | * fields for {vD, vE, vF, vG}, so there's no need to make |
| 312 | * copies of those.) Note that cases 5..2 fall through. |
| 313 | */ |
| 314 | switch (count) { |
| 315 | case 5: arg[4] = InstA(); |
| 316 | case 4: arg[3] = (regList >> 12) & 0x0f; |
| 317 | case 3: arg[2] = (regList >> 8) & 0x0f; |
| 318 | case 2: arg[1] = (regList >> 4) & 0x0f; |
| 319 | case 1: arg[0] = regList & 0x0f; break; |
| 320 | case 0: break; // Valid, but no need to do anything. |
| 321 | default: |
| 322 | LOG(ERROR) << "Invalid arg count in 35c (" << count << ")"; |
| 323 | return; |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | } // namespace art |
| 328 | |
| 329 | #endif // ART_SRC_DEX_INSTRUCTION_INL_H_ |