Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2017 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "code_generator_arm_vixl.h" |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 18 | #include "mirror/array-inl.h" |
| 19 | |
| 20 | namespace vixl32 = vixl::aarch32; |
| 21 | using namespace vixl32; // NOLINT(build/namespaces) |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 22 | |
| 23 | namespace art { |
| 24 | namespace arm { |
| 25 | |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 26 | using helpers::DRegisterFrom; |
| 27 | using helpers::Int64ConstantFrom; |
| 28 | using helpers::InputDRegisterAt; |
| 29 | using helpers::InputRegisterAt; |
| 30 | using helpers::OutputDRegister; |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 31 | using helpers::OutputRegister; |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 32 | using helpers::RegisterFrom; |
| 33 | |
| 34 | #define __ GetVIXLAssembler()-> |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 35 | |
| 36 | void LocationsBuilderARMVIXL::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 37 | LocationSummary* locations = new (GetGraph()->GetAllocator()) LocationSummary(instruction); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 38 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 39 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 40 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 41 | case DataType::Type::kInt8: |
| 42 | case DataType::Type::kUint16: |
| 43 | case DataType::Type::kInt16: |
| 44 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 45 | locations->SetInAt(0, Location::RequiresRegister()); |
| 46 | locations->SetOut(Location::RequiresFpuRegister()); |
| 47 | break; |
| 48 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 49 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 50 | UNREACHABLE(); |
| 51 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | void InstructionCodeGeneratorARMVIXL::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 55 | LocationSummary* locations = instruction->GetLocations(); |
| 56 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 57 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 58 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 59 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 60 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 61 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 62 | __ Vdup(Untyped8, dst, InputRegisterAt(instruction, 0)); |
| 63 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 64 | case DataType::Type::kUint16: |
| 65 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 66 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 67 | __ Vdup(Untyped16, dst, InputRegisterAt(instruction, 0)); |
| 68 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 69 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 70 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 71 | __ Vdup(Untyped32, dst, InputRegisterAt(instruction, 0)); |
| 72 | break; |
| 73 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 74 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 75 | UNREACHABLE(); |
| 76 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 77 | } |
| 78 | |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 79 | void LocationsBuilderARMVIXL::VisitVecExtractScalar(HVecExtractScalar* instruction) { |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 80 | LocationSummary* locations = new (GetGraph()->GetAllocator()) LocationSummary(instruction); |
| 81 | switch (instruction->GetPackedType()) { |
| 82 | case DataType::Type::kInt32: |
| 83 | locations->SetInAt(0, Location::RequiresFpuRegister()); |
| 84 | locations->SetOut(Location::RequiresRegister()); |
| 85 | break; |
| 86 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 87 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 88 | UNREACHABLE(); |
| 89 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 90 | } |
| 91 | |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 92 | void InstructionCodeGeneratorARMVIXL::VisitVecExtractScalar(HVecExtractScalar* instruction) { |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 93 | LocationSummary* locations = instruction->GetLocations(); |
| 94 | vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); |
| 95 | switch (instruction->GetPackedType()) { |
| 96 | case DataType::Type::kInt32: |
| 97 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 98 | __ Vmov(OutputRegister(instruction), DRegisterLane(src, 0)); |
| 99 | break; |
| 100 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 101 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 102 | UNREACHABLE(); |
| 103 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | // Helper to set up locations for vector unary operations. |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 107 | static void CreateVecUnOpLocations(ArenaAllocator* allocator, HVecUnaryOperation* instruction) { |
| 108 | LocationSummary* locations = new (allocator) LocationSummary(instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 109 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 110 | case DataType::Type::kBool: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 111 | locations->SetInAt(0, Location::RequiresFpuRegister()); |
| 112 | locations->SetOut(Location::RequiresFpuRegister(), |
| 113 | instruction->IsVecNot() ? Location::kOutputOverlap |
| 114 | : Location::kNoOutputOverlap); |
| 115 | break; |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 116 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 117 | case DataType::Type::kInt8: |
| 118 | case DataType::Type::kUint16: |
| 119 | case DataType::Type::kInt16: |
| 120 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 121 | locations->SetInAt(0, Location::RequiresFpuRegister()); |
| 122 | locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 123 | break; |
| 124 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 125 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 126 | UNREACHABLE(); |
| 127 | } |
| 128 | } |
| 129 | |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 130 | void LocationsBuilderARMVIXL::VisitVecReduce(HVecReduce* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 131 | CreateVecUnOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | void InstructionCodeGeneratorARMVIXL::VisitVecReduce(HVecReduce* instruction) { |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 135 | LocationSummary* locations = instruction->GetLocations(); |
| 136 | vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); |
| 137 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 138 | switch (instruction->GetPackedType()) { |
| 139 | case DataType::Type::kInt32: |
| 140 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 141 | switch (instruction->GetKind()) { |
| 142 | case HVecReduce::kSum: |
| 143 | __ Vpadd(DataTypeValue::I32, dst, src, src); |
| 144 | break; |
| 145 | case HVecReduce::kMin: |
| 146 | __ Vpmin(DataTypeValue::S32, dst, src, src); |
| 147 | break; |
| 148 | case HVecReduce::kMax: |
| 149 | __ Vpmax(DataTypeValue::S32, dst, src, src); |
| 150 | break; |
| 151 | } |
| 152 | break; |
| 153 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 154 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 155 | UNREACHABLE(); |
| 156 | } |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 157 | } |
| 158 | |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 159 | void LocationsBuilderARMVIXL::VisitVecCnv(HVecCnv* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 160 | CreateVecUnOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | void InstructionCodeGeneratorARMVIXL::VisitVecCnv(HVecCnv* instruction) { |
| 164 | LOG(FATAL) << "No SIMD for " << instruction->GetId(); |
| 165 | } |
| 166 | |
| 167 | void LocationsBuilderARMVIXL::VisitVecNeg(HVecNeg* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 168 | CreateVecUnOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | void InstructionCodeGeneratorARMVIXL::VisitVecNeg(HVecNeg* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 172 | LocationSummary* locations = instruction->GetLocations(); |
| 173 | vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); |
| 174 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 175 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 176 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 177 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 178 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 179 | __ Vneg(DataTypeValue::S8, dst, src); |
| 180 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 181 | case DataType::Type::kUint16: |
| 182 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 183 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 184 | __ Vneg(DataTypeValue::S16, dst, src); |
| 185 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 186 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 187 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 188 | __ Vneg(DataTypeValue::S32, dst, src); |
| 189 | break; |
| 190 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 191 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 192 | UNREACHABLE(); |
| 193 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 194 | } |
| 195 | |
Aart Bik | 6daebeb | 2017-04-03 14:35:41 -0700 | [diff] [blame] | 196 | void LocationsBuilderARMVIXL::VisitVecAbs(HVecAbs* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 197 | CreateVecUnOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | 6daebeb | 2017-04-03 14:35:41 -0700 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | void InstructionCodeGeneratorARMVIXL::VisitVecAbs(HVecAbs* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 201 | LocationSummary* locations = instruction->GetLocations(); |
| 202 | vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); |
| 203 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 204 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 205 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 206 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 207 | __ Vabs(DataTypeValue::S8, dst, src); |
| 208 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 209 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 210 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 211 | __ Vabs(DataTypeValue::S16, dst, src); |
| 212 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 213 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 214 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 215 | __ Vabs(DataTypeValue::S32, dst, src); |
| 216 | break; |
| 217 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 218 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 219 | UNREACHABLE(); |
| 220 | } |
Aart Bik | 6daebeb | 2017-04-03 14:35:41 -0700 | [diff] [blame] | 221 | } |
| 222 | |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 223 | void LocationsBuilderARMVIXL::VisitVecNot(HVecNot* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 224 | CreateVecUnOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | void InstructionCodeGeneratorARMVIXL::VisitVecNot(HVecNot* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 228 | LocationSummary* locations = instruction->GetLocations(); |
| 229 | vixl32::DRegister src = DRegisterFrom(locations->InAt(0)); |
| 230 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 231 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 232 | case DataType::Type::kBool: // special case boolean-not |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 233 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 234 | __ Vmov(I8, dst, 1); |
| 235 | __ Veor(dst, dst, src); |
| 236 | break; |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 237 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 238 | case DataType::Type::kInt8: |
| 239 | case DataType::Type::kUint16: |
| 240 | case DataType::Type::kInt16: |
| 241 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 242 | __ Vmvn(I8, dst, src); // lanes do not matter |
| 243 | break; |
| 244 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 245 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 246 | UNREACHABLE(); |
| 247 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | // Helper to set up locations for vector binary operations. |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 251 | static void CreateVecBinOpLocations(ArenaAllocator* allocator, HVecBinaryOperation* instruction) { |
| 252 | LocationSummary* locations = new (allocator) LocationSummary(instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 253 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 254 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 255 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 256 | case DataType::Type::kInt8: |
| 257 | case DataType::Type::kUint16: |
| 258 | case DataType::Type::kInt16: |
| 259 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 260 | locations->SetInAt(0, Location::RequiresFpuRegister()); |
| 261 | locations->SetInAt(1, Location::RequiresFpuRegister()); |
| 262 | locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 263 | break; |
| 264 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 265 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 266 | UNREACHABLE(); |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | void LocationsBuilderARMVIXL::VisitVecAdd(HVecAdd* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 271 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | void InstructionCodeGeneratorARMVIXL::VisitVecAdd(HVecAdd* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 275 | LocationSummary* locations = instruction->GetLocations(); |
| 276 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 277 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 278 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 279 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 280 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 281 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 282 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 283 | __ Vadd(I8, dst, lhs, rhs); |
| 284 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 285 | case DataType::Type::kUint16: |
| 286 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 287 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 288 | __ Vadd(I16, dst, lhs, rhs); |
| 289 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 290 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 291 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 292 | __ Vadd(I32, dst, lhs, rhs); |
| 293 | break; |
| 294 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 295 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
| 296 | UNREACHABLE(); |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | void LocationsBuilderARMVIXL::VisitVecSaturationAdd(HVecSaturationAdd* instruction) { |
| 301 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
| 302 | } |
| 303 | |
| 304 | void InstructionCodeGeneratorARMVIXL::VisitVecSaturationAdd(HVecSaturationAdd* instruction) { |
| 305 | LocationSummary* locations = instruction->GetLocations(); |
| 306 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 307 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 308 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 309 | switch (instruction->GetPackedType()) { |
| 310 | case DataType::Type::kUint8: |
| 311 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 312 | __ Vqadd(DataTypeValue::U8, dst, lhs, rhs); |
| 313 | break; |
| 314 | case DataType::Type::kInt8: |
| 315 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 316 | __ Vqadd(DataTypeValue::S8, dst, lhs, rhs); |
| 317 | break; |
| 318 | case DataType::Type::kUint16: |
| 319 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 320 | __ Vqadd(DataTypeValue::U16, dst, lhs, rhs); |
| 321 | break; |
| 322 | case DataType::Type::kInt16: |
| 323 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 324 | __ Vqadd(DataTypeValue::S16, dst, lhs, rhs); |
| 325 | break; |
| 326 | default: |
| 327 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 328 | UNREACHABLE(); |
| 329 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 330 | } |
| 331 | |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 332 | void LocationsBuilderARMVIXL::VisitVecHalvingAdd(HVecHalvingAdd* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 333 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | void InstructionCodeGeneratorARMVIXL::VisitVecHalvingAdd(HVecHalvingAdd* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 337 | LocationSummary* locations = instruction->GetLocations(); |
| 338 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 339 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 340 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 341 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 342 | case DataType::Type::kUint8: |
| 343 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 344 | instruction->IsRounded() |
| 345 | ? __ Vrhadd(DataTypeValue::U8, dst, lhs, rhs) |
| 346 | : __ Vhadd(DataTypeValue::U8, dst, lhs, rhs); |
| 347 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 348 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 349 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 350 | instruction->IsRounded() |
| 351 | ? __ Vrhadd(DataTypeValue::S8, dst, lhs, rhs) |
| 352 | : __ Vhadd(DataTypeValue::S8, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 353 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 354 | case DataType::Type::kUint16: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 355 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 356 | instruction->IsRounded() |
| 357 | ? __ Vrhadd(DataTypeValue::U16, dst, lhs, rhs) |
| 358 | : __ Vhadd(DataTypeValue::U16, dst, lhs, rhs); |
| 359 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 360 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 361 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 362 | instruction->IsRounded() |
| 363 | ? __ Vrhadd(DataTypeValue::S16, dst, lhs, rhs) |
| 364 | : __ Vhadd(DataTypeValue::S16, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 365 | break; |
| 366 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 367 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 368 | UNREACHABLE(); |
| 369 | } |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 370 | } |
| 371 | |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 372 | void LocationsBuilderARMVIXL::VisitVecSub(HVecSub* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 373 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 374 | } |
| 375 | |
| 376 | void InstructionCodeGeneratorARMVIXL::VisitVecSub(HVecSub* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 377 | LocationSummary* locations = instruction->GetLocations(); |
| 378 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 379 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 380 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 381 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 382 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 383 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 384 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 385 | __ Vsub(I8, dst, lhs, rhs); |
| 386 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 387 | case DataType::Type::kUint16: |
| 388 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 389 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 390 | __ Vsub(I16, dst, lhs, rhs); |
| 391 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 392 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 393 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 394 | __ Vsub(I32, dst, lhs, rhs); |
| 395 | break; |
| 396 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 397 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
| 398 | UNREACHABLE(); |
| 399 | } |
| 400 | } |
| 401 | |
| 402 | void LocationsBuilderARMVIXL::VisitVecSaturationSub(HVecSaturationSub* instruction) { |
| 403 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
| 404 | } |
| 405 | |
| 406 | void InstructionCodeGeneratorARMVIXL::VisitVecSaturationSub(HVecSaturationSub* instruction) { |
| 407 | LocationSummary* locations = instruction->GetLocations(); |
| 408 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 409 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 410 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 411 | switch (instruction->GetPackedType()) { |
| 412 | case DataType::Type::kUint8: |
| 413 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 414 | __ Vqsub(DataTypeValue::U8, dst, lhs, rhs); |
| 415 | break; |
| 416 | case DataType::Type::kInt8: |
| 417 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 418 | __ Vqsub(DataTypeValue::S8, dst, lhs, rhs); |
| 419 | break; |
| 420 | case DataType::Type::kUint16: |
| 421 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 422 | __ Vqsub(DataTypeValue::U16, dst, lhs, rhs); |
| 423 | break; |
| 424 | case DataType::Type::kInt16: |
| 425 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 426 | __ Vqsub(DataTypeValue::S16, dst, lhs, rhs); |
| 427 | break; |
| 428 | default: |
| 429 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 430 | UNREACHABLE(); |
| 431 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | void LocationsBuilderARMVIXL::VisitVecMul(HVecMul* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 435 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 436 | } |
| 437 | |
| 438 | void InstructionCodeGeneratorARMVIXL::VisitVecMul(HVecMul* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 439 | LocationSummary* locations = instruction->GetLocations(); |
| 440 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 441 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 442 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 443 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 444 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 445 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 446 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 447 | __ Vmul(I8, dst, lhs, rhs); |
| 448 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 449 | case DataType::Type::kUint16: |
| 450 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 451 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 452 | __ Vmul(I16, dst, lhs, rhs); |
| 453 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 454 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 455 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 456 | __ Vmul(I32, dst, lhs, rhs); |
| 457 | break; |
| 458 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 459 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 460 | UNREACHABLE(); |
| 461 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 462 | } |
| 463 | |
| 464 | void LocationsBuilderARMVIXL::VisitVecDiv(HVecDiv* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 465 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 466 | } |
| 467 | |
| 468 | void InstructionCodeGeneratorARMVIXL::VisitVecDiv(HVecDiv* instruction) { |
| 469 | LOG(FATAL) << "No SIMD for " << instruction->GetId(); |
| 470 | } |
| 471 | |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 472 | void LocationsBuilderARMVIXL::VisitVecMin(HVecMin* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 473 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | void InstructionCodeGeneratorARMVIXL::VisitVecMin(HVecMin* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 477 | LocationSummary* locations = instruction->GetLocations(); |
| 478 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 479 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 480 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 481 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 482 | case DataType::Type::kUint8: |
| 483 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 484 | __ Vmin(DataTypeValue::U8, dst, lhs, rhs); |
| 485 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 486 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 487 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 488 | __ Vmin(DataTypeValue::S8, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 489 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 490 | case DataType::Type::kUint16: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 491 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 492 | __ Vmin(DataTypeValue::U16, dst, lhs, rhs); |
| 493 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 494 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 495 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 496 | __ Vmin(DataTypeValue::S16, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 497 | break; |
Aart Bik | 66c158e | 2018-01-31 12:55:04 -0800 | [diff] [blame] | 498 | case DataType::Type::kUint32: |
| 499 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 500 | __ Vmin(DataTypeValue::U32, dst, lhs, rhs); |
| 501 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 502 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 503 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
Aart Bik | 66c158e | 2018-01-31 12:55:04 -0800 | [diff] [blame] | 504 | __ Vmin(DataTypeValue::S32, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 505 | break; |
| 506 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 507 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 508 | UNREACHABLE(); |
| 509 | } |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 510 | } |
| 511 | |
| 512 | void LocationsBuilderARMVIXL::VisitVecMax(HVecMax* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 513 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 514 | } |
| 515 | |
| 516 | void InstructionCodeGeneratorARMVIXL::VisitVecMax(HVecMax* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 517 | LocationSummary* locations = instruction->GetLocations(); |
| 518 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 519 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 520 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 521 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 522 | case DataType::Type::kUint8: |
| 523 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 524 | __ Vmax(DataTypeValue::U8, dst, lhs, rhs); |
| 525 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 526 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 527 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 528 | __ Vmax(DataTypeValue::S8, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 529 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 530 | case DataType::Type::kUint16: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 531 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 532 | __ Vmax(DataTypeValue::U16, dst, lhs, rhs); |
| 533 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 534 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 535 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 536 | __ Vmax(DataTypeValue::S16, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 537 | break; |
Aart Bik | 66c158e | 2018-01-31 12:55:04 -0800 | [diff] [blame] | 538 | case DataType::Type::kUint32: |
| 539 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 540 | __ Vmax(DataTypeValue::U32, dst, lhs, rhs); |
| 541 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 542 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 543 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
Aart Bik | 66c158e | 2018-01-31 12:55:04 -0800 | [diff] [blame] | 544 | __ Vmax(DataTypeValue::S32, dst, lhs, rhs); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 545 | break; |
| 546 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 547 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 548 | UNREACHABLE(); |
| 549 | } |
Aart Bik | f3e61ee | 2017-04-12 17:09:20 -0700 | [diff] [blame] | 550 | } |
| 551 | |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 552 | void LocationsBuilderARMVIXL::VisitVecAnd(HVecAnd* instruction) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 553 | // TODO: Allow constants supported by VAND (immediate). |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 554 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 555 | } |
| 556 | |
| 557 | void InstructionCodeGeneratorARMVIXL::VisitVecAnd(HVecAnd* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 558 | LocationSummary* locations = instruction->GetLocations(); |
| 559 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 560 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 561 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 562 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 563 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 564 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 565 | case DataType::Type::kInt8: |
| 566 | case DataType::Type::kUint16: |
| 567 | case DataType::Type::kInt16: |
| 568 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 569 | __ Vand(I8, dst, lhs, rhs); |
| 570 | break; |
| 571 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 572 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 573 | UNREACHABLE(); |
| 574 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | void LocationsBuilderARMVIXL::VisitVecAndNot(HVecAndNot* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 578 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 579 | } |
| 580 | |
| 581 | void InstructionCodeGeneratorARMVIXL::VisitVecAndNot(HVecAndNot* instruction) { |
| 582 | LOG(FATAL) << "No SIMD for " << instruction->GetId(); |
| 583 | } |
| 584 | |
| 585 | void LocationsBuilderARMVIXL::VisitVecOr(HVecOr* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 586 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | void InstructionCodeGeneratorARMVIXL::VisitVecOr(HVecOr* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 590 | LocationSummary* locations = instruction->GetLocations(); |
| 591 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 592 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 593 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 594 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 595 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 596 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 597 | case DataType::Type::kInt8: |
| 598 | case DataType::Type::kUint16: |
| 599 | case DataType::Type::kInt16: |
| 600 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 601 | __ Vorr(I8, dst, lhs, rhs); |
| 602 | break; |
| 603 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 604 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 605 | UNREACHABLE(); |
| 606 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 607 | } |
| 608 | |
| 609 | void LocationsBuilderARMVIXL::VisitVecXor(HVecXor* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 610 | CreateVecBinOpLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 611 | } |
| 612 | |
| 613 | void InstructionCodeGeneratorARMVIXL::VisitVecXor(HVecXor* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 614 | LocationSummary* locations = instruction->GetLocations(); |
| 615 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 616 | vixl32::DRegister rhs = DRegisterFrom(locations->InAt(1)); |
| 617 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 618 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 619 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 620 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 621 | case DataType::Type::kInt8: |
| 622 | case DataType::Type::kUint16: |
| 623 | case DataType::Type::kInt16: |
| 624 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 625 | __ Veor(I8, dst, lhs, rhs); |
| 626 | break; |
| 627 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 628 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 629 | UNREACHABLE(); |
| 630 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 631 | } |
| 632 | |
| 633 | // Helper to set up locations for vector shift operations. |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 634 | static void CreateVecShiftLocations(ArenaAllocator* allocator, HVecBinaryOperation* instruction) { |
| 635 | LocationSummary* locations = new (allocator) LocationSummary(instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 636 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 637 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 638 | case DataType::Type::kInt8: |
| 639 | case DataType::Type::kUint16: |
| 640 | case DataType::Type::kInt16: |
| 641 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 642 | locations->SetInAt(0, Location::RequiresFpuRegister()); |
| 643 | locations->SetInAt(1, Location::ConstantLocation(instruction->InputAt(1)->AsConstant())); |
| 644 | locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 645 | break; |
| 646 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 647 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 648 | UNREACHABLE(); |
| 649 | } |
| 650 | } |
| 651 | |
| 652 | void LocationsBuilderARMVIXL::VisitVecShl(HVecShl* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 653 | CreateVecShiftLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 654 | } |
| 655 | |
| 656 | void InstructionCodeGeneratorARMVIXL::VisitVecShl(HVecShl* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 657 | LocationSummary* locations = instruction->GetLocations(); |
| 658 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 659 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 660 | int32_t value = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); |
| 661 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 662 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 663 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 664 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 665 | __ Vshl(I8, dst, lhs, value); |
| 666 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 667 | case DataType::Type::kUint16: |
| 668 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 669 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 670 | __ Vshl(I16, dst, lhs, value); |
| 671 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 672 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 673 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 674 | __ Vshl(I32, dst, lhs, value); |
| 675 | break; |
| 676 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 677 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 678 | UNREACHABLE(); |
| 679 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 680 | } |
| 681 | |
| 682 | void LocationsBuilderARMVIXL::VisitVecShr(HVecShr* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 683 | CreateVecShiftLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 684 | } |
| 685 | |
| 686 | void InstructionCodeGeneratorARMVIXL::VisitVecShr(HVecShr* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 687 | LocationSummary* locations = instruction->GetLocations(); |
| 688 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 689 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 690 | int32_t value = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); |
| 691 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 692 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 693 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 694 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 695 | __ Vshr(DataTypeValue::S8, dst, lhs, value); |
| 696 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 697 | case DataType::Type::kUint16: |
| 698 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 699 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 700 | __ Vshr(DataTypeValue::S16, dst, lhs, value); |
| 701 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 702 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 703 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 704 | __ Vshr(DataTypeValue::S32, dst, lhs, value); |
| 705 | break; |
| 706 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 707 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 708 | UNREACHABLE(); |
| 709 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 710 | } |
| 711 | |
| 712 | void LocationsBuilderARMVIXL::VisitVecUShr(HVecUShr* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 713 | CreateVecShiftLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 714 | } |
| 715 | |
| 716 | void InstructionCodeGeneratorARMVIXL::VisitVecUShr(HVecUShr* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 717 | LocationSummary* locations = instruction->GetLocations(); |
| 718 | vixl32::DRegister lhs = DRegisterFrom(locations->InAt(0)); |
| 719 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 720 | int32_t value = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); |
| 721 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 722 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 723 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 724 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 725 | __ Vshr(DataTypeValue::U8, dst, lhs, value); |
| 726 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 727 | case DataType::Type::kUint16: |
| 728 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 729 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 730 | __ Vshr(DataTypeValue::U16, dst, lhs, value); |
| 731 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 732 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 733 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 734 | __ Vshr(DataTypeValue::U32, dst, lhs, value); |
| 735 | break; |
| 736 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 737 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 738 | UNREACHABLE(); |
| 739 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 740 | } |
| 741 | |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 742 | void LocationsBuilderARMVIXL::VisitVecSetScalars(HVecSetScalars* instruction) { |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 743 | LocationSummary* locations = new (GetGraph()->GetAllocator()) LocationSummary(instruction); |
| 744 | |
| 745 | DCHECK_EQ(1u, instruction->InputCount()); // only one input currently implemented |
| 746 | |
| 747 | HInstruction* input = instruction->InputAt(0); |
| 748 | bool is_zero = IsZeroBitPattern(input); |
| 749 | |
| 750 | switch (instruction->GetPackedType()) { |
| 751 | case DataType::Type::kInt32: |
| 752 | locations->SetInAt(0, is_zero ? Location::ConstantLocation(input->AsConstant()) |
| 753 | : Location::RequiresRegister()); |
| 754 | locations->SetOut(Location::RequiresFpuRegister()); |
| 755 | break; |
| 756 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 757 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 758 | UNREACHABLE(); |
| 759 | } |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | void InstructionCodeGeneratorARMVIXL::VisitVecSetScalars(HVecSetScalars* instruction) { |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 763 | LocationSummary* locations = instruction->GetLocations(); |
| 764 | vixl32::DRegister dst = DRegisterFrom(locations->Out()); |
| 765 | |
| 766 | DCHECK_EQ(1u, instruction->InputCount()); // only one input currently implemented |
| 767 | |
| 768 | // Zero out all other elements first. |
| 769 | __ Vmov(I32, dst, 0); |
| 770 | |
| 771 | // Shorthand for any type of zero. |
| 772 | if (IsZeroBitPattern(instruction->InputAt(0))) { |
| 773 | return; |
| 774 | } |
| 775 | |
| 776 | // Set required elements. |
| 777 | switch (instruction->GetPackedType()) { |
| 778 | case DataType::Type::kInt32: |
| 779 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 780 | __ Vmov(Untyped32, DRegisterLane(dst, 0), InputRegisterAt(instruction, 0)); |
| 781 | break; |
| 782 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 783 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 784 | UNREACHABLE(); |
| 785 | } |
Aart Bik | 0148de4 | 2017-09-05 09:25:01 -0700 | [diff] [blame] | 786 | } |
| 787 | |
Aart Bik | dbbac8f | 2017-09-01 13:06:08 -0700 | [diff] [blame] | 788 | // Helper to set up locations for vector accumulations. |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 789 | static void CreateVecAccumLocations(ArenaAllocator* allocator, HVecOperation* instruction) { |
| 790 | LocationSummary* locations = new (allocator) LocationSummary(instruction); |
Aart Bik | dbbac8f | 2017-09-01 13:06:08 -0700 | [diff] [blame] | 791 | switch (instruction->GetPackedType()) { |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 792 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 793 | case DataType::Type::kInt8: |
| 794 | case DataType::Type::kUint16: |
| 795 | case DataType::Type::kInt16: |
| 796 | case DataType::Type::kInt32: |
| 797 | case DataType::Type::kInt64: |
Aart Bik | dbbac8f | 2017-09-01 13:06:08 -0700 | [diff] [blame] | 798 | locations->SetInAt(0, Location::RequiresFpuRegister()); |
| 799 | locations->SetInAt(1, Location::RequiresFpuRegister()); |
| 800 | locations->SetInAt(2, Location::RequiresFpuRegister()); |
| 801 | locations->SetOut(Location::SameAsFirstInput()); |
| 802 | break; |
| 803 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 804 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Aart Bik | dbbac8f | 2017-09-01 13:06:08 -0700 | [diff] [blame] | 805 | UNREACHABLE(); |
| 806 | } |
Artem Serov | f34dd20 | 2017-04-10 17:41:46 +0100 | [diff] [blame] | 807 | } |
| 808 | |
Aart Bik | dbbac8f | 2017-09-01 13:06:08 -0700 | [diff] [blame] | 809 | void LocationsBuilderARMVIXL::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 810 | CreateVecAccumLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | dbbac8f | 2017-09-01 13:06:08 -0700 | [diff] [blame] | 811 | } |
| 812 | |
| 813 | void InstructionCodeGeneratorARMVIXL::VisitVecMultiplyAccumulate(HVecMultiplyAccumulate* instruction) { |
| 814 | LOG(FATAL) << "No SIMD for " << instruction->GetId(); |
| 815 | } |
| 816 | |
| 817 | void LocationsBuilderARMVIXL::VisitVecSADAccumulate(HVecSADAccumulate* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 818 | CreateVecAccumLocations(GetGraph()->GetAllocator(), instruction); |
Aart Bik | dbbac8f | 2017-09-01 13:06:08 -0700 | [diff] [blame] | 819 | } |
| 820 | |
| 821 | void InstructionCodeGeneratorARMVIXL::VisitVecSADAccumulate(HVecSADAccumulate* instruction) { |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 822 | LocationSummary* locations = instruction->GetLocations(); |
| 823 | vixl32::DRegister acc = DRegisterFrom(locations->InAt(0)); |
| 824 | vixl32::DRegister left = DRegisterFrom(locations->InAt(1)); |
| 825 | vixl32::DRegister right = DRegisterFrom(locations->InAt(2)); |
| 826 | |
| 827 | DCHECK(locations->InAt(0).Equals(locations->Out())); |
| 828 | |
| 829 | // Handle all feasible acc_T += sad(a_S, b_S) type combinations (T x S). |
| 830 | HVecOperation* a = instruction->InputAt(1)->AsVecOperation(); |
| 831 | HVecOperation* b = instruction->InputAt(2)->AsVecOperation(); |
| 832 | DCHECK_EQ(a->GetPackedType(), b->GetPackedType()); |
| 833 | switch (a->GetPackedType()) { |
| 834 | case DataType::Type::kInt32: |
| 835 | DCHECK_EQ(2u, a->GetVectorLength()); |
| 836 | switch (instruction->GetPackedType()) { |
| 837 | case DataType::Type::kInt32: { |
| 838 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 839 | UseScratchRegisterScope temps(GetVIXLAssembler()); |
| 840 | vixl32::DRegister tmp = temps.AcquireD(); |
| 841 | __ Vsub(DataTypeValue::I32, tmp, left, right); |
| 842 | __ Vabs(DataTypeValue::S32, tmp, tmp); |
| 843 | __ Vadd(DataTypeValue::I32, acc, acc, tmp); |
| 844 | break; |
| 845 | } |
| 846 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 847 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 848 | UNREACHABLE(); |
| 849 | } |
| 850 | break; |
| 851 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 852 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 6e9b137 | 2017-10-05 16:48:30 +0100 | [diff] [blame] | 853 | UNREACHABLE(); |
| 854 | } |
Artem Serov | f34dd20 | 2017-04-10 17:41:46 +0100 | [diff] [blame] | 855 | } |
| 856 | |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 857 | // Return whether the vector memory access operation is guaranteed to be word-aligned (ARM word |
| 858 | // size equals to 4). |
| 859 | static bool IsWordAligned(HVecMemoryOperation* instruction) { |
| 860 | return instruction->GetAlignment().IsAlignedAt(4u); |
| 861 | } |
| 862 | |
| 863 | // Helper to set up locations for vector memory operations. |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 864 | static void CreateVecMemLocations(ArenaAllocator* allocator, |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 865 | HVecMemoryOperation* instruction, |
| 866 | bool is_load) { |
Vladimir Marko | e764d2e | 2017-10-05 14:35:55 +0100 | [diff] [blame] | 867 | LocationSummary* locations = new (allocator) LocationSummary(instruction); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 868 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 869 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 870 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 871 | case DataType::Type::kInt8: |
| 872 | case DataType::Type::kUint16: |
| 873 | case DataType::Type::kInt16: |
| 874 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 875 | locations->SetInAt(0, Location::RequiresRegister()); |
| 876 | locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1))); |
| 877 | if (is_load) { |
| 878 | locations->SetOut(Location::RequiresFpuRegister()); |
| 879 | } else { |
| 880 | locations->SetInAt(2, Location::RequiresFpuRegister()); |
| 881 | } |
| 882 | break; |
| 883 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 884 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 885 | UNREACHABLE(); |
| 886 | } |
| 887 | } |
| 888 | |
| 889 | // Helper to set up locations for vector memory operations. Returns the memory operand and, |
| 890 | // if used, sets the output parameter scratch to a temporary register used in this operand, |
| 891 | // so that the client can release it right after the memory operand use. |
| 892 | MemOperand InstructionCodeGeneratorARMVIXL::VecAddress( |
| 893 | HVecMemoryOperation* instruction, |
| 894 | UseScratchRegisterScope* temps_scope, |
| 895 | /*out*/ vixl32::Register* scratch) { |
| 896 | LocationSummary* locations = instruction->GetLocations(); |
| 897 | vixl32::Register base = InputRegisterAt(instruction, 0); |
| 898 | |
| 899 | Location index = locations->InAt(1); |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 900 | size_t size = DataType::Size(instruction->GetPackedType()); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 901 | uint32_t offset = mirror::Array::DataOffset(size).Uint32Value(); |
| 902 | size_t shift = ComponentSizeShiftWidth(size); |
| 903 | |
| 904 | // HIntermediateAddress optimization is only applied for scalar ArrayGet and ArraySet. |
| 905 | DCHECK(!instruction->InputAt(0)->IsIntermediateAddress()); |
| 906 | |
| 907 | if (index.IsConstant()) { |
| 908 | offset += Int64ConstantFrom(index) << shift; |
| 909 | return MemOperand(base, offset); |
| 910 | } else { |
| 911 | *scratch = temps_scope->Acquire(); |
| 912 | __ Add(*scratch, base, Operand(RegisterFrom(index), ShiftType::LSL, shift)); |
| 913 | |
| 914 | return MemOperand(*scratch, offset); |
| 915 | } |
| 916 | } |
| 917 | |
| 918 | AlignedMemOperand InstructionCodeGeneratorARMVIXL::VecAddressUnaligned( |
| 919 | HVecMemoryOperation* instruction, |
| 920 | UseScratchRegisterScope* temps_scope, |
| 921 | /*out*/ vixl32::Register* scratch) { |
| 922 | LocationSummary* locations = instruction->GetLocations(); |
| 923 | vixl32::Register base = InputRegisterAt(instruction, 0); |
| 924 | |
| 925 | Location index = locations->InAt(1); |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 926 | size_t size = DataType::Size(instruction->GetPackedType()); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 927 | uint32_t offset = mirror::Array::DataOffset(size).Uint32Value(); |
| 928 | size_t shift = ComponentSizeShiftWidth(size); |
| 929 | |
| 930 | // HIntermediateAddress optimization is only applied for scalar ArrayGet and ArraySet. |
| 931 | DCHECK(!instruction->InputAt(0)->IsIntermediateAddress()); |
| 932 | |
| 933 | if (index.IsConstant()) { |
| 934 | offset += Int64ConstantFrom(index) << shift; |
| 935 | __ Add(*scratch, base, offset); |
| 936 | } else { |
| 937 | *scratch = temps_scope->Acquire(); |
| 938 | __ Add(*scratch, base, offset); |
| 939 | __ Add(*scratch, *scratch, Operand(RegisterFrom(index), ShiftType::LSL, shift)); |
| 940 | } |
| 941 | return AlignedMemOperand(*scratch, kNoAlignment); |
| 942 | } |
| 943 | |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 944 | void LocationsBuilderARMVIXL::VisitVecLoad(HVecLoad* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 945 | CreateVecMemLocations(GetGraph()->GetAllocator(), instruction, /*is_load*/ true); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 946 | } |
| 947 | |
| 948 | void InstructionCodeGeneratorARMVIXL::VisitVecLoad(HVecLoad* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 949 | vixl32::DRegister reg = OutputDRegister(instruction); |
| 950 | UseScratchRegisterScope temps(GetVIXLAssembler()); |
| 951 | vixl32::Register scratch; |
| 952 | |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 953 | DCHECK(instruction->GetPackedType() != DataType::Type::kUint16 || !instruction->IsStringCharAt()); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 954 | |
| 955 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 956 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 957 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 958 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 959 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 960 | if (IsWordAligned(instruction)) { |
| 961 | __ Vldr(reg, VecAddress(instruction, &temps, &scratch)); |
| 962 | } else { |
| 963 | __ Vld1(Untyped8, |
| 964 | NeonRegisterList(reg, kMultipleLanes), |
| 965 | VecAddressUnaligned(instruction, &temps, &scratch)); |
| 966 | } |
| 967 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 968 | case DataType::Type::kUint16: |
| 969 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 970 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 971 | if (IsWordAligned(instruction)) { |
| 972 | __ Vldr(reg, VecAddress(instruction, &temps, &scratch)); |
| 973 | } else { |
| 974 | __ Vld1(Untyped16, |
| 975 | NeonRegisterList(reg, kMultipleLanes), |
| 976 | VecAddressUnaligned(instruction, &temps, &scratch)); |
| 977 | } |
| 978 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 979 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 980 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 981 | if (IsWordAligned(instruction)) { |
| 982 | __ Vldr(reg, VecAddress(instruction, &temps, &scratch)); |
| 983 | } else { |
| 984 | __ Vld1(Untyped32, |
| 985 | NeonRegisterList(reg, kMultipleLanes), |
| 986 | VecAddressUnaligned(instruction, &temps, &scratch)); |
| 987 | } |
| 988 | break; |
| 989 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 990 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 991 | UNREACHABLE(); |
| 992 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 993 | } |
| 994 | |
| 995 | void LocationsBuilderARMVIXL::VisitVecStore(HVecStore* instruction) { |
Vladimir Marko | ca6fff8 | 2017-10-03 14:49:14 +0100 | [diff] [blame] | 996 | CreateVecMemLocations(GetGraph()->GetAllocator(), instruction, /*is_load*/ false); |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 997 | } |
| 998 | |
| 999 | void InstructionCodeGeneratorARMVIXL::VisitVecStore(HVecStore* instruction) { |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 1000 | vixl32::DRegister reg = InputDRegisterAt(instruction, 2); |
| 1001 | UseScratchRegisterScope temps(GetVIXLAssembler()); |
| 1002 | vixl32::Register scratch; |
| 1003 | switch (instruction->GetPackedType()) { |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 1004 | case DataType::Type::kBool: |
Vladimir Marko | d5d2f2c | 2017-09-26 12:37:26 +0100 | [diff] [blame] | 1005 | case DataType::Type::kUint8: |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 1006 | case DataType::Type::kInt8: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 1007 | DCHECK_EQ(8u, instruction->GetVectorLength()); |
| 1008 | if (IsWordAligned(instruction)) { |
| 1009 | __ Vstr(reg, VecAddress(instruction, &temps, &scratch)); |
| 1010 | } else { |
| 1011 | __ Vst1(Untyped8, |
| 1012 | NeonRegisterList(reg, kMultipleLanes), |
| 1013 | VecAddressUnaligned(instruction, &temps, &scratch)); |
| 1014 | } |
| 1015 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 1016 | case DataType::Type::kUint16: |
| 1017 | case DataType::Type::kInt16: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 1018 | DCHECK_EQ(4u, instruction->GetVectorLength()); |
| 1019 | if (IsWordAligned(instruction)) { |
| 1020 | __ Vstr(reg, VecAddress(instruction, &temps, &scratch)); |
| 1021 | } else { |
| 1022 | __ Vst1(Untyped16, |
| 1023 | NeonRegisterList(reg, kMultipleLanes), |
| 1024 | VecAddressUnaligned(instruction, &temps, &scratch)); |
| 1025 | } |
| 1026 | break; |
Vladimir Marko | 0ebe0d8 | 2017-09-21 22:50:39 +0100 | [diff] [blame] | 1027 | case DataType::Type::kInt32: |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 1028 | DCHECK_EQ(2u, instruction->GetVectorLength()); |
| 1029 | if (IsWordAligned(instruction)) { |
| 1030 | __ Vstr(reg, VecAddress(instruction, &temps, &scratch)); |
| 1031 | } else { |
| 1032 | __ Vst1(Untyped32, |
| 1033 | NeonRegisterList(reg, kMultipleLanes), |
| 1034 | VecAddressUnaligned(instruction, &temps, &scratch)); |
| 1035 | } |
| 1036 | break; |
| 1037 | default: |
Aart Bik | 29aa082 | 2018-03-08 11:28:00 -0800 | [diff] [blame] | 1038 | LOG(FATAL) << "Unsupported SIMD type: " << instruction->GetPackedType(); |
Artem Serov | 8f7c410 | 2017-06-21 11:21:37 +0100 | [diff] [blame] | 1039 | UNREACHABLE(); |
| 1040 | } |
Aart Bik | f8f5a16 | 2017-02-06 15:35:29 -0800 | [diff] [blame] | 1041 | } |
| 1042 | |
| 1043 | #undef __ |
| 1044 | |
| 1045 | } // namespace arm |
| 1046 | } // namespace art |