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Ian Rogers166db042013-07-26 12:05:57 -07001/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef ART_RUNTIME_ARCH_MIPS_REGISTERS_MIPS_H_
18#define ART_RUNTIME_ARCH_MIPS_REGISTERS_MIPS_H_
19
20#include <iosfwd>
21
Andreas Gampe57943812017-12-06 21:39:13 -080022#include <android-base/logging.h>
23
Ian Rogers166db042013-07-26 12:05:57 -070024#include "base/macros.h"
25#include "globals.h"
26
27namespace art {
28namespace mips {
29
30enum Register {
31 ZERO = 0,
32 AT = 1, // Assembler temporary.
33 V0 = 2, // Values.
34 V1 = 3,
35 A0 = 4, // Arguments.
36 A1 = 5,
37 A2 = 6,
38 A3 = 7,
Alexey Frunze1b8464d2016-11-12 17:22:05 -080039 T0 = 8, // Two extra arguments / temporaries.
Ian Rogers166db042013-07-26 12:05:57 -070040 T1 = 9,
Alexey Frunze1b8464d2016-11-12 17:22:05 -080041 T2 = 10, // Temporaries.
Ian Rogers166db042013-07-26 12:05:57 -070042 T3 = 11,
43 T4 = 12,
44 T5 = 13,
45 T6 = 14,
46 T7 = 15,
47 S0 = 16, // Saved values.
48 S1 = 17,
49 S2 = 18,
50 S3 = 19,
51 S4 = 20,
52 S5 = 21,
53 S6 = 22,
54 S7 = 23,
55 T8 = 24, // More temporaries.
56 T9 = 25,
57 K0 = 26, // Reserved for trap handler.
58 K1 = 27,
59 GP = 28, // Global pointer.
60 SP = 29, // Stack pointer.
61 FP = 30, // Saved value/frame pointer.
62 RA = 31, // Return address.
Chris Larsen16ba2b42015-11-02 10:58:31 -080063 TR = S1, // ART Thread Register
64 TMP = T8, // scratch register (in addition to AT)
Ian Rogers166db042013-07-26 12:05:57 -070065 kNumberOfCoreRegisters = 32,
66 kNoRegister = -1 // Signals an illegal register.
67};
68std::ostream& operator<<(std::ostream& os, const Register& rhs);
69
70// Values for single-precision floating point registers.
71enum FRegister {
72 F0 = 0,
73 F1 = 1,
74 F2 = 2,
75 F3 = 3,
76 F4 = 4,
77 F5 = 5,
78 F6 = 6,
79 F7 = 7,
80 F8 = 8,
81 F9 = 9,
82 F10 = 10,
83 F11 = 11,
84 F12 = 12,
85 F13 = 13,
86 F14 = 14,
87 F15 = 15,
88 F16 = 16,
89 F17 = 17,
90 F18 = 18,
91 F19 = 19,
92 F20 = 20,
93 F21 = 21,
94 F22 = 22,
95 F23 = 23,
96 F24 = 24,
97 F25 = 25,
98 F26 = 26,
99 F27 = 27,
100 F28 = 28,
101 F29 = 29,
102 F30 = 30,
103 F31 = 31,
Goran Jakovljevice7de5ec2017-12-14 10:25:20 +0100104 FTMP = F6, // scratch register
105 FTMP2 = F7, // scratch register (in addition to FTMP, reserved for MSA instructions)
Ian Rogers166db042013-07-26 12:05:57 -0700106 kNumberOfFRegisters = 32,
107 kNoFRegister = -1,
108};
109std::ostream& operator<<(std::ostream& os, const FRegister& rhs);
110
Lena Djokic0758ae72017-05-23 11:06:23 +0200111// Values for vector registers.
112enum VectorRegister {
113 W0 = 0,
114 W1 = 1,
115 W2 = 2,
116 W3 = 3,
117 W4 = 4,
118 W5 = 5,
119 W6 = 6,
120 W7 = 7,
121 W8 = 8,
122 W9 = 9,
123 W10 = 10,
124 W11 = 11,
125 W12 = 12,
126 W13 = 13,
127 W14 = 14,
128 W15 = 15,
129 W16 = 16,
130 W17 = 17,
131 W18 = 18,
132 W19 = 19,
133 W20 = 20,
134 W21 = 21,
135 W22 = 22,
136 W23 = 23,
137 W24 = 24,
138 W25 = 25,
139 W26 = 26,
140 W27 = 27,
141 W28 = 28,
142 W29 = 29,
143 W30 = 30,
144 W31 = 31,
145 kNumberOfVectorRegisters = 32,
146 kNoVectorRegister = -1,
147};
148std::ostream& operator<<(std::ostream& os, const VectorRegister& rhs);
149
Ian Rogers166db042013-07-26 12:05:57 -0700150} // namespace mips
151} // namespace art
152
153#endif // ART_RUNTIME_ARCH_MIPS_REGISTERS_MIPS_H_