Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 21 | #include "dex/quick/mir_to_lir.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 22 | #include "mips_lir.h" |
| 23 | |
| 24 | namespace art { |
| 25 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 26 | class MipsMir2Lir FINAL : public Mir2Lir { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | public: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 28 | MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); |
| 29 | |
| 30 | // Required for target - codegen utilities. |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 31 | bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 32 | RegLocation rl_dest, int lit); |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 33 | bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 34 | LIR* CheckSuspendUsingLoad() OVERRIDE; |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 35 | RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 36 | LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 37 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 38 | LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 39 | OpSize size) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 40 | LIR* LoadConstantNoClobber(RegStorage r_dest, int value); |
| 41 | LIR* LoadConstantWide(RegStorage r_dest, int64_t value); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 42 | LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 43 | OpSize size, VolatileKind is_volatile) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 44 | LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 45 | OpSize size) OVERRIDE; |
Douglas Leung | d9cb8ae | 2014-07-09 14:28:35 -0700 | [diff] [blame] | 46 | LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest); |
| 47 | LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 48 | void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 49 | |
| 50 | // Required for target - register utilities. |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 51 | RegStorage Solo64ToPair64(RegStorage reg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 52 | RegStorage TargetReg(SpecialTargetRegister reg); |
| 53 | RegStorage GetArgMappingToPhysicalReg(int arg_num); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 54 | RegLocation GetReturnAlt(); |
| 55 | RegLocation GetReturnWideAlt(); |
| 56 | RegLocation LocCReturn(); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 57 | RegLocation LocCReturnRef(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 58 | RegLocation LocCReturnDouble(); |
| 59 | RegLocation LocCReturnFloat(); |
| 60 | RegLocation LocCReturnWide(); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 61 | ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 62 | void AdjustSpillMask(); |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 63 | void ClobberCallerSave(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 64 | void FreeCallTemps(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 65 | void LockCallTemps(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | void CompilerInitializeRegAlloc(); |
| 67 | |
| 68 | // Required for target - miscellaneous. |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 69 | void AssembleLIR(); |
| 70 | int AssignInsnOffsets(); |
| 71 | void AssignOffsets(); |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 72 | AssemblerStatus AssembleInstructions(CodeOffset start_addr); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 73 | void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; |
| 74 | void SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 75 | ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 76 | const char* GetTargetInstFmt(int opcode); |
| 77 | const char* GetTargetInstName(int opcode); |
| 78 | std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 79 | ResourceMask GetPCUseDefEncoding() const OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 80 | uint64_t GetTargetInstFlags(int opcode); |
Ian Rogers | 5aa6e04 | 2014-06-13 16:38:24 -0700 | [diff] [blame] | 81 | size_t GetInsnSize(LIR* lir) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 82 | bool IsUnconditionalBranch(LIR* lir); |
| 83 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 84 | // Get the register class for load/store of a field. |
| 85 | RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; |
| 86 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 87 | // Required for target - Dalvik-level generators. |
| 88 | void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 89 | RegLocation rl_src1, RegLocation rl_src2, int flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 90 | void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 91 | RegLocation rl_index, RegLocation rl_dest, int scale); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 92 | void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 93 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 94 | void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 95 | RegLocation rl_shift, int flags); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 96 | void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 97 | RegLocation rl_src2); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 98 | void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 99 | RegLocation rl_src2); |
| 100 | void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 101 | RegLocation rl_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 102 | void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); |
Vladimir Marko | 5030d3e | 2014-07-17 10:43:08 +0100 | [diff] [blame] | 103 | bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; |
| 104 | bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 105 | bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 106 | bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | bool GenInlinedSqrt(CallInfo* info); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 108 | bool GenInlinedPeek(CallInfo* info, OpSize size); |
| 109 | bool GenInlinedPoke(CallInfo* info, OpSize size); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 110 | void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 111 | RegLocation rl_src2, int flags) OVERRIDE; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 112 | RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); |
| 113 | RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 114 | void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 115 | void GenDivZeroCheckWide(RegStorage reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 116 | void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); |
| 117 | void GenExitSequence(); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 118 | void GenSpecialExitSequence(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 119 | void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); |
| 120 | void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); |
| 121 | void GenSelect(BasicBlock* bb, MIR* mir); |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 122 | void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 123 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 124 | int dest_reg_class) OVERRIDE; |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 125 | bool GenMemBarrier(MemBarrierKind barrier_kind); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 126 | void GenMoveException(RegLocation rl_dest); |
| 127 | void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 128 | int first_bit, int second_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 129 | void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); |
| 130 | void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); |
Andreas Gampe | 48971b3 | 2014-08-06 10:09:01 -0700 | [diff] [blame] | 131 | void GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src); |
| 132 | void GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 133 | bool GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 134 | |
| 135 | // Required for target - single operation generators. |
| 136 | LIR* OpUnconditionalBranch(LIR* target); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 137 | LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); |
| 138 | LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | LIR* OpCondBranch(ConditionCode cc, LIR* target); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 140 | LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); |
| 141 | LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 142 | LIR* OpIT(ConditionCode cond, const char* guide); |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 143 | void OpEndIT(LIR* it); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 144 | LIR* OpMem(OpKind op, RegStorage r_base, int disp); |
| 145 | LIR* OpPcRelLoad(RegStorage reg, LIR* target); |
| 146 | LIR* OpReg(OpKind op, RegStorage r_dest_src); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 147 | void OpRegCopy(RegStorage r_dest, RegStorage r_src); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 148 | LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); |
| 149 | LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 150 | LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); |
| 151 | LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); |
| 152 | LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); |
| 153 | LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); |
| 154 | LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); |
| 155 | LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 156 | LIR* OpTestSuspend(LIR* target); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 157 | LIR* OpVldm(RegStorage r_base, int count); |
| 158 | LIR* OpVstm(RegStorage r_base, int count); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 159 | void OpRegCopyWide(RegStorage dest, RegStorage src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 160 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 161 | // TODO: collapse r_dest. |
| 162 | LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 163 | OpSize size); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 164 | // TODO: collapse r_src. |
| 165 | LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 166 | OpSize size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 167 | void SpillCoreRegs(); |
| 168 | void UnSpillCoreRegs(); |
| 169 | static const MipsEncodingMap EncodingMap[kMipsLast]; |
| 170 | bool InexpensiveConstantInt(int32_t value); |
| 171 | bool InexpensiveConstantFloat(int32_t value); |
| 172 | bool InexpensiveConstantLong(int64_t value); |
| 173 | bool InexpensiveConstantDouble(int64_t value); |
| 174 | |
Serguei Katkov | 59a42af | 2014-07-05 00:55:46 +0700 | [diff] [blame] | 175 | bool WideGPRsAreAliases() OVERRIDE { |
| 176 | return false; // Wide GPRs are formed by pairing. |
| 177 | } |
| 178 | bool WideFPRsAreAliases() OVERRIDE { |
| 179 | return false; // Wide FPRs are formed by pairing. |
| 180 | } |
| 181 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 182 | LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; |
| 183 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 184 | private: |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 185 | void GenNegLong(RegLocation rl_dest, RegLocation rl_src); |
| 186 | void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 187 | RegLocation rl_src2); |
| 188 | void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 189 | RegLocation rl_src2); |
| 190 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 191 | void ConvertShortToLongBranch(LIR* lir); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 192 | RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
Razvan A Lupusoru | 5c5676b | 2014-09-29 16:42:11 -0700 | [diff] [blame^] | 193 | RegLocation rl_src2, bool is_div, int flags) OVERRIDE; |
| 194 | RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div) OVERRIDE; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | } // namespace art |
| 198 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 199 | #endif // ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ |