Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the Thumb2 ISA. */ |
| 18 | |
| 19 | #include "arm64_lir.h" |
| 20 | #include "codegen_arm64.h" |
| 21 | #include "dex/quick/mir_to_lir-inl.h" |
| 22 | #include "entrypoints/quick/quick_entrypoints.h" |
| 23 | |
| 24 | namespace art { |
| 25 | |
| 26 | /* |
| 27 | * The sparse table in the literal pool is an array of <key,displacement> |
| 28 | * pairs. For each set, we'll load them as a pair using ldmia. |
| 29 | * This means that the register number of the temp we use for the key |
| 30 | * must be lower than the reg for the displacement. |
| 31 | * |
| 32 | * The test loop will look something like: |
| 33 | * |
| 34 | * adr r_base, <table> |
| 35 | * ldr r_val, [rARM_SP, v_reg_off] |
| 36 | * mov r_idx, #table_size |
| 37 | * lp: |
| 38 | * ldmia r_base!, {r_key, r_disp} |
| 39 | * sub r_idx, #1 |
| 40 | * cmp r_val, r_key |
| 41 | * ifeq |
| 42 | * add rARM_PC, r_disp ; This is the branch from which we compute displacement |
| 43 | * cbnz r_idx, lp |
| 44 | */ |
| 45 | void Arm64Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset, |
| 46 | RegLocation rl_src) { |
| 47 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 48 | if (cu_->verbose) { |
| 49 | DumpSparseSwitchTable(table); |
| 50 | } |
| 51 | // Add the table to the list - we'll process it later |
| 52 | SwitchTable *tab_rec = |
| 53 | static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), kArenaAllocData)); |
| 54 | tab_rec->table = table; |
| 55 | tab_rec->vaddr = current_dalvik_offset_; |
| 56 | uint32_t size = table[1]; |
| 57 | tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), kArenaAllocLIR)); |
| 58 | switch_tables_.Insert(tab_rec); |
| 59 | |
| 60 | // Get the switch value |
| 61 | rl_src = LoadValue(rl_src, kCoreReg); |
| 62 | RegStorage r_base = AllocTemp(); |
| 63 | /* Allocate key and disp temps */ |
| 64 | RegStorage r_key = AllocTemp(); |
| 65 | RegStorage r_disp = AllocTemp(); |
| 66 | // Make sure r_key's register number is less than r_disp's number for ldmia |
| 67 | if (r_key.GetReg() > r_disp.GetReg()) { |
| 68 | RegStorage tmp = r_disp; |
| 69 | r_disp = r_key; |
| 70 | r_key = tmp; |
| 71 | } |
| 72 | // Materialize a pointer to the switch table |
| 73 | NewLIR3(kThumb2Adr, r_base.GetReg(), 0, WrapPointer(tab_rec)); |
| 74 | // Set up r_idx |
| 75 | RegStorage r_idx = AllocTemp(); |
| 76 | LoadConstant(r_idx, size); |
| 77 | // Establish loop branch target |
| 78 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 79 | // Load next key/disp |
| 80 | NewLIR2(kThumb2LdmiaWB, r_base.GetReg(), (1 << r_key.GetRegNum()) | (1 << r_disp.GetRegNum())); |
| 81 | OpRegReg(kOpCmp, r_key, rl_src.reg); |
| 82 | // Go if match. NOTE: No instruction set switch here - must stay Thumb2 |
| 83 | LIR* it = OpIT(kCondEq, ""); |
| 84 | LIR* switch_branch = NewLIR1(kThumb2AddPCR, r_disp.GetReg()); |
| 85 | OpEndIT(it); |
| 86 | tab_rec->anchor = switch_branch; |
| 87 | // Needs to use setflags encoding here |
| 88 | OpRegRegImm(kOpSub, r_idx, r_idx, 1); // For value == 1, this should set flags. |
| 89 | DCHECK(last_lir_insn_->u.m.def_mask & ENCODE_CCODE); |
| 90 | OpCondBranch(kCondNe, target); |
| 91 | } |
| 92 | |
| 93 | |
| 94 | void Arm64Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset, |
| 95 | RegLocation rl_src) { |
| 96 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 97 | if (cu_->verbose) { |
| 98 | DumpPackedSwitchTable(table); |
| 99 | } |
| 100 | // Add the table to the list - we'll process it later |
| 101 | SwitchTable *tab_rec = |
| 102 | static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), kArenaAllocData)); |
| 103 | tab_rec->table = table; |
| 104 | tab_rec->vaddr = current_dalvik_offset_; |
| 105 | uint32_t size = table[1]; |
| 106 | tab_rec->targets = |
| 107 | static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), kArenaAllocLIR)); |
| 108 | switch_tables_.Insert(tab_rec); |
| 109 | |
| 110 | // Get the switch value |
| 111 | rl_src = LoadValue(rl_src, kCoreReg); |
| 112 | RegStorage table_base = AllocTemp(); |
| 113 | // Materialize a pointer to the switch table |
| 114 | NewLIR3(kThumb2Adr, table_base.GetReg(), 0, WrapPointer(tab_rec)); |
| 115 | int low_key = s4FromSwitchData(&table[2]); |
| 116 | RegStorage keyReg; |
| 117 | // Remove the bias, if necessary |
| 118 | if (low_key == 0) { |
| 119 | keyReg = rl_src.reg; |
| 120 | } else { |
| 121 | keyReg = AllocTemp(); |
| 122 | OpRegRegImm(kOpSub, keyReg, rl_src.reg, low_key); |
| 123 | } |
| 124 | // Bounds check - if < 0 or >= size continue following switch |
| 125 | OpRegImm(kOpCmp, keyReg, size-1); |
| 126 | LIR* branch_over = OpCondBranch(kCondHi, NULL); |
| 127 | |
| 128 | // Load the displacement from the switch table |
| 129 | RegStorage disp_reg = AllocTemp(); |
| 130 | LoadBaseIndexed(table_base, keyReg, disp_reg, 2, k32); |
| 131 | |
| 132 | // ..and go! NOTE: No instruction set switch here - must stay Thumb2 |
| 133 | LIR* switch_branch = NewLIR1(kThumb2AddPCR, disp_reg.GetReg()); |
| 134 | tab_rec->anchor = switch_branch; |
| 135 | |
| 136 | /* branch_over target here */ |
| 137 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 138 | branch_over->target = target; |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * Array data table format: |
| 143 | * ushort ident = 0x0300 magic value |
| 144 | * ushort width width of each element in the table |
| 145 | * uint size number of elements in the table |
| 146 | * ubyte data[size*width] table of data values (may contain a single-byte |
| 147 | * padding at the end) |
| 148 | * |
| 149 | * Total size is 4+(width * size + 1)/2 16-bit code units. |
| 150 | */ |
| 151 | void Arm64Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) { |
| 152 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 153 | // Add the table to the list - we'll process it later |
| 154 | FillArrayData *tab_rec = |
| 155 | static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), kArenaAllocData)); |
| 156 | tab_rec->table = table; |
| 157 | tab_rec->vaddr = current_dalvik_offset_; |
| 158 | uint16_t width = tab_rec->table[1]; |
| 159 | uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); |
| 160 | tab_rec->size = (size * width) + 8; |
| 161 | |
| 162 | fill_array_data_.Insert(tab_rec); |
| 163 | |
| 164 | // Making a call - use explicit registers |
| 165 | FlushAllRegs(); /* Everything to home location */ |
| 166 | LoadValueDirectFixed(rl_src, rs_r0); |
| 167 | LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pHandleFillArrayData).Int32Value(), |
| 168 | rs_rARM_LR); |
| 169 | // Materialize a pointer to the fill data image |
| 170 | NewLIR3(kThumb2Adr, rs_r1.GetReg(), 0, WrapPointer(tab_rec)); |
| 171 | ClobberCallerSave(); |
| 172 | LIR* call_inst = OpReg(kOpBlx, rs_rARM_LR); |
| 173 | MarkSafepointPC(call_inst); |
| 174 | } |
| 175 | |
| 176 | /* |
| 177 | * Handle unlocked -> thin locked transition inline or else call out to quick entrypoint. For more |
| 178 | * details see monitor.cc. |
| 179 | */ |
| 180 | void Arm64Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { |
| 181 | FlushAllRegs(); |
| 182 | // FIXME: need separate LoadValues for object references. |
| 183 | LoadValueDirectFixed(rl_src, rs_r0); // Get obj |
| 184 | LockCallTemps(); // Prepare for explicit register usage |
| 185 | constexpr bool kArchVariantHasGoodBranchPredictor = false; // TODO: true if cortex-A15. |
| 186 | if (kArchVariantHasGoodBranchPredictor) { |
| 187 | LIR* null_check_branch = nullptr; |
| 188 | if ((opt_flags & MIR_IGNORE_NULL_CHECK) && !(cu_->disable_opt & (1 << kNullCheckElimination))) { |
| 189 | null_check_branch = nullptr; // No null check. |
| 190 | } else { |
| 191 | // If the null-check fails its handled by the slow-path to reduce exception related meta-data. |
| 192 | if (Runtime::Current()->ExplicitNullChecks()) { |
| 193 | null_check_branch = OpCmpImmBranch(kCondEq, rs_r0, 0, NULL); |
| 194 | } |
| 195 | } |
| 196 | Load32Disp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2); |
| 197 | NewLIR3(kThumb2Ldrex, rs_r1.GetReg(), rs_r0.GetReg(), |
| 198 | mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 199 | MarkPossibleNullPointerException(opt_flags); |
| 200 | LIR* not_unlocked_branch = OpCmpImmBranch(kCondNe, rs_r1, 0, NULL); |
| 201 | NewLIR4(kThumb2Strex, rs_r1.GetReg(), rs_r2.GetReg(), rs_r0.GetReg(), |
| 202 | mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 203 | LIR* lock_success_branch = OpCmpImmBranch(kCondEq, rs_r1, 0, NULL); |
| 204 | |
| 205 | |
| 206 | LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); |
| 207 | not_unlocked_branch->target = slow_path_target; |
| 208 | if (null_check_branch != nullptr) { |
| 209 | null_check_branch->target = slow_path_target; |
| 210 | } |
| 211 | // TODO: move to a slow path. |
| 212 | // Go expensive route - artLockObjectFromCode(obj); |
| 213 | LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pLockObject).Int32Value(), rs_rARM_LR); |
| 214 | ClobberCallerSave(); |
| 215 | LIR* call_inst = OpReg(kOpBlx, rs_rARM_LR); |
| 216 | MarkSafepointPC(call_inst); |
| 217 | |
| 218 | LIR* success_target = NewLIR0(kPseudoTargetLabel); |
| 219 | lock_success_branch->target = success_target; |
| 220 | GenMemBarrier(kLoadLoad); |
| 221 | } else { |
| 222 | // Explicit null-check as slow-path is entered using an IT. |
| 223 | GenNullCheck(rs_r0, opt_flags); |
| 224 | Load32Disp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2); |
| 225 | NewLIR3(kThumb2Ldrex, rs_r1.GetReg(), rs_r0.GetReg(), |
| 226 | mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 227 | MarkPossibleNullPointerException(opt_flags); |
| 228 | OpRegImm(kOpCmp, rs_r1, 0); |
| 229 | LIR* it = OpIT(kCondEq, ""); |
| 230 | NewLIR4(kThumb2Strex/*eq*/, rs_r1.GetReg(), rs_r2.GetReg(), rs_r0.GetReg(), |
| 231 | mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 232 | OpEndIT(it); |
| 233 | OpRegImm(kOpCmp, rs_r1, 0); |
| 234 | it = OpIT(kCondNe, "T"); |
| 235 | // Go expensive route - artLockObjectFromCode(self, obj); |
| 236 | LoadWordDisp/*ne*/(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pLockObject).Int32Value(), |
| 237 | rs_rARM_LR); |
| 238 | ClobberCallerSave(); |
| 239 | LIR* call_inst = OpReg(kOpBlx/*ne*/, rs_rARM_LR); |
| 240 | OpEndIT(it); |
| 241 | MarkSafepointPC(call_inst); |
| 242 | GenMemBarrier(kLoadLoad); |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | /* |
| 247 | * Handle thin locked -> unlocked transition inline or else call out to quick entrypoint. For more |
| 248 | * details see monitor.cc. Note the code below doesn't use ldrex/strex as the code holds the lock |
| 249 | * and can only give away ownership if its suspended. |
| 250 | */ |
| 251 | void Arm64Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { |
| 252 | FlushAllRegs(); |
| 253 | LoadValueDirectFixed(rl_src, rs_r0); // Get obj |
| 254 | LockCallTemps(); // Prepare for explicit register usage |
| 255 | LIR* null_check_branch = nullptr; |
| 256 | Load32Disp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2); |
| 257 | constexpr bool kArchVariantHasGoodBranchPredictor = false; // TODO: true if cortex-A15. |
| 258 | if (kArchVariantHasGoodBranchPredictor) { |
| 259 | if ((opt_flags & MIR_IGNORE_NULL_CHECK) && !(cu_->disable_opt & (1 << kNullCheckElimination))) { |
| 260 | null_check_branch = nullptr; // No null check. |
| 261 | } else { |
| 262 | // If the null-check fails its handled by the slow-path to reduce exception related meta-data. |
| 263 | if (Runtime::Current()->ExplicitNullChecks()) { |
| 264 | null_check_branch = OpCmpImmBranch(kCondEq, rs_r0, 0, NULL); |
| 265 | } |
| 266 | } |
| 267 | Load32Disp(rs_r0, mirror::Object::MonitorOffset().Int32Value(), rs_r1); |
| 268 | MarkPossibleNullPointerException(opt_flags); |
| 269 | LoadConstantNoClobber(rs_r3, 0); |
| 270 | LIR* slow_unlock_branch = OpCmpBranch(kCondNe, rs_r1, rs_r2, NULL); |
| 271 | Store32Disp(rs_r0, mirror::Object::MonitorOffset().Int32Value(), rs_r3); |
| 272 | LIR* unlock_success_branch = OpUnconditionalBranch(NULL); |
| 273 | |
| 274 | LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); |
| 275 | slow_unlock_branch->target = slow_path_target; |
| 276 | if (null_check_branch != nullptr) { |
| 277 | null_check_branch->target = slow_path_target; |
| 278 | } |
| 279 | // TODO: move to a slow path. |
| 280 | // Go expensive route - artUnlockObjectFromCode(obj); |
| 281 | LoadWordDisp(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject).Int32Value(), rs_rARM_LR); |
| 282 | ClobberCallerSave(); |
| 283 | LIR* call_inst = OpReg(kOpBlx, rs_rARM_LR); |
| 284 | MarkSafepointPC(call_inst); |
| 285 | |
| 286 | LIR* success_target = NewLIR0(kPseudoTargetLabel); |
| 287 | unlock_success_branch->target = success_target; |
| 288 | GenMemBarrier(kStoreLoad); |
| 289 | } else { |
| 290 | // Explicit null-check as slow-path is entered using an IT. |
| 291 | GenNullCheck(rs_r0, opt_flags); |
| 292 | Load32Disp(rs_r0, mirror::Object::MonitorOffset().Int32Value(), rs_r1); // Get lock |
| 293 | MarkPossibleNullPointerException(opt_flags); |
| 294 | Load32Disp(rs_rARM_SELF, Thread::ThinLockIdOffset<4>().Int32Value(), rs_r2); |
| 295 | LoadConstantNoClobber(rs_r3, 0); |
| 296 | // Is lock unheld on lock or held by us (==thread_id) on unlock? |
| 297 | OpRegReg(kOpCmp, rs_r1, rs_r2); |
| 298 | LIR* it = OpIT(kCondEq, "EE"); |
| 299 | Store32Disp/*eq*/(rs_r0, mirror::Object::MonitorOffset().Int32Value(), rs_r3); |
| 300 | // Go expensive route - UnlockObjectFromCode(obj); |
| 301 | LoadWordDisp/*ne*/(rs_rARM_SELF, QUICK_ENTRYPOINT_OFFSET(4, pUnlockObject).Int32Value(), |
| 302 | rs_rARM_LR); |
| 303 | ClobberCallerSave(); |
| 304 | LIR* call_inst = OpReg(kOpBlx/*ne*/, rs_rARM_LR); |
| 305 | OpEndIT(it); |
| 306 | MarkSafepointPC(call_inst); |
| 307 | GenMemBarrier(kStoreLoad); |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | void Arm64Mir2Lir::GenMoveException(RegLocation rl_dest) { |
| 312 | int ex_offset = Thread::ExceptionOffset<4>().Int32Value(); |
| 313 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 314 | RegStorage reset_reg = AllocTemp(); |
| 315 | Load32Disp(rs_rARM_SELF, ex_offset, rl_result.reg); |
| 316 | LoadConstant(reset_reg, 0); |
| 317 | Store32Disp(rs_rARM_SELF, ex_offset, reset_reg); |
| 318 | FreeTemp(reset_reg); |
| 319 | StoreValue(rl_dest, rl_result); |
| 320 | } |
| 321 | |
| 322 | /* |
| 323 | * Mark garbage collection card. Skip if the value we're storing is null. |
| 324 | */ |
| 325 | void Arm64Mir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { |
| 326 | RegStorage reg_card_base = AllocTemp(); |
| 327 | RegStorage reg_card_no = AllocTemp(); |
| 328 | LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); |
| 329 | LoadWordDisp(rs_rARM_SELF, Thread::CardTableOffset<4>().Int32Value(), reg_card_base); |
| 330 | OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); |
| 331 | StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte); |
| 332 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 333 | branch_over->target = target; |
| 334 | FreeTemp(reg_card_base); |
| 335 | FreeTemp(reg_card_no); |
| 336 | } |
| 337 | |
| 338 | void Arm64Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { |
| 339 | int spill_count = num_core_spills_ + num_fp_spills_; |
| 340 | /* |
| 341 | * On entry, r0, r1, r2 & r3 are live. Let the register allocation |
| 342 | * mechanism know so it doesn't try to use any of them when |
| 343 | * expanding the frame or flushing. This leaves the utility |
| 344 | * code with a single temp: r12. This should be enough. |
| 345 | */ |
| 346 | LockTemp(rs_r0); |
| 347 | LockTemp(rs_r1); |
| 348 | LockTemp(rs_r2); |
| 349 | LockTemp(rs_r3); |
| 350 | |
| 351 | /* |
| 352 | * We can safely skip the stack overflow check if we're |
| 353 | * a leaf *and* our frame size < fudge factor. |
| 354 | */ |
| 355 | bool skip_overflow_check = (mir_graph_->MethodIsLeaf() && |
| 356 | (static_cast<size_t>(frame_size_) < |
| 357 | Thread::kStackOverflowReservedBytes)); |
| 358 | NewLIR0(kPseudoMethodEntry); |
| 359 | if (!skip_overflow_check) { |
| 360 | if (Runtime::Current()->ExplicitStackOverflowChecks()) { |
| 361 | /* Load stack limit */ |
| 362 | Load32Disp(rs_rARM_SELF, Thread::StackEndOffset<4>().Int32Value(), rs_r12); |
| 363 | } |
| 364 | } |
| 365 | /* Spill core callee saves */ |
| 366 | NewLIR1(kThumb2Push, core_spill_mask_); |
| 367 | /* Need to spill any FP regs? */ |
| 368 | if (num_fp_spills_) { |
| 369 | /* |
| 370 | * NOTE: fp spills are a little different from core spills in that |
| 371 | * they are pushed as a contiguous block. When promoting from |
| 372 | * the fp set, we must allocate all singles from s16..highest-promoted |
| 373 | */ |
| 374 | NewLIR1(kThumb2VPushCS, num_fp_spills_); |
| 375 | } |
| 376 | |
| 377 | const int spill_size = spill_count * 4; |
| 378 | const int frame_size_without_spills = frame_size_ - spill_size; |
| 379 | if (!skip_overflow_check) { |
| 380 | if (Runtime::Current()->ExplicitStackOverflowChecks()) { |
| 381 | class StackOverflowSlowPath : public LIRSlowPath { |
| 382 | public: |
| 383 | StackOverflowSlowPath(Mir2Lir* m2l, LIR* branch, bool restore_lr, size_t sp_displace) |
| 384 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch, nullptr), restore_lr_(restore_lr), |
| 385 | sp_displace_(sp_displace) { |
| 386 | } |
| 387 | void Compile() OVERRIDE { |
| 388 | m2l_->ResetRegPool(); |
| 389 | m2l_->ResetDefTracking(); |
| 390 | GenerateTargetLabel(kPseudoThrowTarget); |
| 391 | if (restore_lr_) { |
| 392 | m2l_->LoadWordDisp(rs_rARM_SP, sp_displace_ - 4, rs_rARM_LR); |
| 393 | } |
| 394 | m2l_->OpRegImm(kOpAdd, rs_rARM_SP, sp_displace_); |
| 395 | m2l_->ClobberCallerSave(); |
| 396 | ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowStackOverflow); |
| 397 | // Load the entrypoint directly into the pc instead of doing a load + branch. Assumes |
| 398 | // codegen and target are in thumb2 mode. |
| 399 | // NOTE: native pointer. |
| 400 | m2l_->LoadWordDisp(rs_rARM_SELF, func_offset.Int32Value(), rs_rARM_PC); |
| 401 | } |
| 402 | |
| 403 | private: |
| 404 | const bool restore_lr_; |
| 405 | const size_t sp_displace_; |
| 406 | }; |
| 407 | if (static_cast<size_t>(frame_size_) > Thread::kStackOverflowReservedUsableBytes) { |
| 408 | OpRegRegImm(kOpSub, rs_rARM_LR, rs_rARM_SP, frame_size_without_spills); |
| 409 | LIR* branch = OpCmpBranch(kCondUlt, rs_rARM_LR, rs_r12, nullptr); |
| 410 | // Need to restore LR since we used it as a temp. |
| 411 | AddSlowPath(new(arena_)StackOverflowSlowPath(this, branch, true, spill_size)); |
| 412 | OpRegCopy(rs_rARM_SP, rs_rARM_LR); // Establish stack |
| 413 | } else { |
| 414 | // If the frame is small enough we are guaranteed to have enough space that remains to |
| 415 | // handle signals on the user stack. |
| 416 | OpRegRegImm(kOpSub, rs_rARM_SP, rs_rARM_SP, frame_size_without_spills); |
| 417 | LIR* branch = OpCmpBranch(kCondUlt, rs_rARM_SP, rs_r12, nullptr); |
| 418 | AddSlowPath(new(arena_)StackOverflowSlowPath(this, branch, false, frame_size_)); |
| 419 | } |
| 420 | } else { |
| 421 | // Implicit stack overflow check. |
| 422 | // Generate a load from [sp, #-overflowsize]. If this is in the stack |
| 423 | // redzone we will get a segmentation fault. |
| 424 | // |
| 425 | // Caveat coder: if someone changes the kStackOverflowReservedBytes value |
| 426 | // we need to make sure that it's loadable in an immediate field of |
| 427 | // a sub instruction. Otherwise we will get a temp allocation and the |
| 428 | // code size will increase. |
| 429 | OpRegRegImm(kOpSub, rs_r12, rs_rARM_SP, Thread::kStackOverflowReservedBytes); |
| 430 | Load32Disp(rs_r12, 0, rs_r12); |
| 431 | MarkPossibleStackOverflowException(); |
| 432 | OpRegImm(kOpSub, rs_rARM_SP, frame_size_without_spills); |
| 433 | } |
| 434 | } else { |
| 435 | OpRegImm(kOpSub, rs_rARM_SP, frame_size_without_spills); |
| 436 | } |
| 437 | |
| 438 | FlushIns(ArgLocs, rl_method); |
| 439 | |
| 440 | FreeTemp(rs_r0); |
| 441 | FreeTemp(rs_r1); |
| 442 | FreeTemp(rs_r2); |
| 443 | FreeTemp(rs_r3); |
| 444 | } |
| 445 | |
| 446 | void Arm64Mir2Lir::GenExitSequence() { |
| 447 | int spill_count = num_core_spills_ + num_fp_spills_; |
| 448 | /* |
| 449 | * In the exit path, r0/r1 are live - make sure they aren't |
| 450 | * allocated by the register utilities as temps. |
| 451 | */ |
| 452 | LockTemp(rs_r0); |
| 453 | LockTemp(rs_r1); |
| 454 | |
| 455 | NewLIR0(kPseudoMethodExit); |
| 456 | OpRegImm(kOpAdd, rs_rARM_SP, frame_size_ - (spill_count * 4)); |
| 457 | /* Need to restore any FP callee saves? */ |
| 458 | if (num_fp_spills_) { |
| 459 | NewLIR1(kThumb2VPopCS, num_fp_spills_); |
| 460 | } |
| 461 | if (core_spill_mask_ & (1 << rs_rARM_LR.GetRegNum())) { |
| 462 | /* Unspill rARM_LR to rARM_PC */ |
| 463 | core_spill_mask_ &= ~(1 << rs_rARM_LR.GetRegNum()); |
| 464 | core_spill_mask_ |= (1 << rs_rARM_PC.GetRegNum()); |
| 465 | } |
| 466 | NewLIR1(kThumb2Pop, core_spill_mask_); |
| 467 | if (!(core_spill_mask_ & (1 << rs_rARM_PC.GetRegNum()))) { |
| 468 | /* We didn't pop to rARM_PC, so must do a bv rARM_LR */ |
| 469 | NewLIR1(kThumbBx, rs_rARM_LR.GetReg()); |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | void Arm64Mir2Lir::GenSpecialExitSequence() { |
| 474 | NewLIR1(kThumbBx, rs_rARM_LR.GetReg()); |
| 475 | } |
| 476 | |
| 477 | } // namespace art |