Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_ |
| 18 | #define ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_ |
| 19 | |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 20 | #include "code_generator.h" |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 21 | #include "locations.h" |
| 22 | #include "nodes.h" |
| 23 | #include "utils/arm64/assembler_arm64.h" |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 24 | |
Artem Serov | af4e42a | 2016-08-08 15:11:24 +0100 | [diff] [blame] | 25 | // TODO(VIXL): Make VIXL compile with -Wshadow. |
| 26 | #pragma GCC diagnostic push |
| 27 | #pragma GCC diagnostic ignored "-Wshadow" |
| 28 | #include "aarch64/disasm-aarch64.h" |
| 29 | #include "aarch64/macro-assembler-aarch64.h" |
| 30 | #include "aarch64/simulator-aarch64.h" |
| 31 | #pragma GCC diagnostic pop |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 32 | |
| 33 | namespace art { |
| 34 | namespace arm64 { |
| 35 | namespace helpers { |
| 36 | |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 37 | // Convenience helpers to ease conversion to and from VIXL operands. |
| 38 | static_assert((SP == 31) && (WSP == 31) && (XZR == 32) && (WZR == 32), |
| 39 | "Unexpected values for register codes."); |
| 40 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 41 | inline int VIXLRegCodeFromART(int code) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 42 | if (code == SP) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 43 | return vixl::aarch64::kSPRegInternalCode; |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 44 | } |
| 45 | if (code == XZR) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 46 | return vixl::aarch64::kZeroRegCode; |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 47 | } |
| 48 | return code; |
| 49 | } |
| 50 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 51 | inline int ARTRegCodeFromVIXL(int code) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 52 | if (code == vixl::aarch64::kSPRegInternalCode) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 53 | return SP; |
| 54 | } |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 55 | if (code == vixl::aarch64::kZeroRegCode) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 56 | return XZR; |
| 57 | } |
| 58 | return code; |
| 59 | } |
| 60 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 61 | inline vixl::aarch64::Register XRegisterFrom(Location location) { |
Roland Levillain | 3a448e4 | 2016-04-01 18:37:46 +0100 | [diff] [blame] | 62 | DCHECK(location.IsRegister()) << location; |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 63 | return vixl::aarch64::Register::GetXRegFromCode(VIXLRegCodeFromART(location.reg())); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 64 | } |
| 65 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 66 | inline vixl::aarch64::Register WRegisterFrom(Location location) { |
Roland Levillain | 3a448e4 | 2016-04-01 18:37:46 +0100 | [diff] [blame] | 67 | DCHECK(location.IsRegister()) << location; |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 68 | return vixl::aarch64::Register::GetWRegFromCode(VIXLRegCodeFromART(location.reg())); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 69 | } |
| 70 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 71 | inline vixl::aarch64::Register RegisterFrom(Location location, Primitive::Type type) { |
Roland Levillain | 3a448e4 | 2016-04-01 18:37:46 +0100 | [diff] [blame] | 72 | DCHECK(type != Primitive::kPrimVoid && !Primitive::IsFloatingPointType(type)) << type; |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 73 | return type == Primitive::kPrimLong ? XRegisterFrom(location) : WRegisterFrom(location); |
| 74 | } |
| 75 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 76 | inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 77 | return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); |
| 78 | } |
| 79 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 80 | inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 81 | return RegisterFrom(instr->GetLocations()->InAt(input_index), |
| 82 | instr->InputAt(input_index)->GetType()); |
| 83 | } |
| 84 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 85 | inline vixl::aarch64::FPRegister DRegisterFrom(Location location) { |
Roland Levillain | 3a448e4 | 2016-04-01 18:37:46 +0100 | [diff] [blame] | 86 | DCHECK(location.IsFpuRegister()) << location; |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 87 | return vixl::aarch64::FPRegister::GetDRegFromCode(location.reg()); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 88 | } |
| 89 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 90 | inline vixl::aarch64::FPRegister SRegisterFrom(Location location) { |
Roland Levillain | 3a448e4 | 2016-04-01 18:37:46 +0100 | [diff] [blame] | 91 | DCHECK(location.IsFpuRegister()) << location; |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 92 | return vixl::aarch64::FPRegister::GetSRegFromCode(location.reg()); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 93 | } |
| 94 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 95 | inline vixl::aarch64::FPRegister FPRegisterFrom(Location location, Primitive::Type type) { |
Roland Levillain | 3a448e4 | 2016-04-01 18:37:46 +0100 | [diff] [blame] | 96 | DCHECK(Primitive::IsFloatingPointType(type)) << type; |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 97 | return type == Primitive::kPrimDouble ? DRegisterFrom(location) : SRegisterFrom(location); |
| 98 | } |
| 99 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 100 | inline vixl::aarch64::FPRegister OutputFPRegister(HInstruction* instr) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 101 | return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); |
| 102 | } |
| 103 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 104 | inline vixl::aarch64::FPRegister InputFPRegisterAt(HInstruction* instr, int input_index) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 105 | return FPRegisterFrom(instr->GetLocations()->InAt(input_index), |
| 106 | instr->InputAt(input_index)->GetType()); |
| 107 | } |
| 108 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 109 | inline vixl::aarch64::CPURegister CPURegisterFrom(Location location, Primitive::Type type) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 110 | return Primitive::IsFloatingPointType(type) |
| 111 | ? vixl::aarch64::CPURegister(FPRegisterFrom(location, type)) |
| 112 | : vixl::aarch64::CPURegister(RegisterFrom(location, type)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 113 | } |
| 114 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 115 | inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) { |
Alexandre Rames | 542361f | 2015-01-29 16:57:31 +0000 | [diff] [blame] | 116 | return Primitive::IsFloatingPointType(instr->GetType()) |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 117 | ? static_cast<vixl::aarch64::CPURegister>(OutputFPRegister(instr)) |
| 118 | : static_cast<vixl::aarch64::CPURegister>(OutputRegister(instr)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 119 | } |
| 120 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 121 | inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) { |
Alexandre Rames | 542361f | 2015-01-29 16:57:31 +0000 | [diff] [blame] | 122 | return Primitive::IsFloatingPointType(instr->InputAt(index)->GetType()) |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 123 | ? static_cast<vixl::aarch64::CPURegister>(InputFPRegisterAt(instr, index)) |
| 124 | : static_cast<vixl::aarch64::CPURegister>(InputRegisterAt(instr, index)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 125 | } |
| 126 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 127 | inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr, |
Alexandre Rames | be919d9 | 2016-08-23 18:33:36 +0100 | [diff] [blame] | 128 | int index) { |
| 129 | HInstruction* input = instr->InputAt(index); |
| 130 | Primitive::Type input_type = input->GetType(); |
| 131 | if (input->IsConstant() && input->AsConstant()->IsZeroBitPattern()) { |
| 132 | return (Primitive::ComponentSize(input_type) >= vixl::aarch64::kXRegSizeInBytes) |
Scott Wakeling | 79db997 | 2017-01-19 14:08:42 +0000 | [diff] [blame^] | 133 | ? vixl::aarch64::Register(vixl::aarch64::xzr) |
| 134 | : vixl::aarch64::Register(vixl::aarch64::wzr); |
Alexandre Rames | be919d9 | 2016-08-23 18:33:36 +0100 | [diff] [blame] | 135 | } |
| 136 | return InputCPURegisterAt(instr, index); |
| 137 | } |
| 138 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 139 | inline int64_t Int64ConstantFrom(Location location) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 140 | HConstant* instr = location.GetConstant(); |
Nicolas Geoffray | de0eb6f | 2015-03-04 10:28:04 +0000 | [diff] [blame] | 141 | if (instr->IsIntConstant()) { |
| 142 | return instr->AsIntConstant()->GetValue(); |
| 143 | } else if (instr->IsNullConstant()) { |
| 144 | return 0; |
| 145 | } else { |
Roland Levillain | 3a448e4 | 2016-04-01 18:37:46 +0100 | [diff] [blame] | 146 | DCHECK(instr->IsLongConstant()) << instr->DebugName(); |
Nicolas Geoffray | de0eb6f | 2015-03-04 10:28:04 +0000 | [diff] [blame] | 147 | return instr->AsLongConstant()->GetValue(); |
| 148 | } |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 149 | } |
| 150 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 151 | inline vixl::aarch64::Operand OperandFrom(Location location, Primitive::Type type) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 152 | if (location.IsRegister()) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 153 | return vixl::aarch64::Operand(RegisterFrom(location, type)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 154 | } else { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 155 | return vixl::aarch64::Operand(Int64ConstantFrom(location)); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 156 | } |
| 157 | } |
| 158 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 159 | inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 160 | return OperandFrom(instr->GetLocations()->InAt(input_index), |
| 161 | instr->InputAt(input_index)->GetType()); |
| 162 | } |
| 163 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 164 | inline vixl::aarch64::MemOperand StackOperandFrom(Location location) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 165 | return vixl::aarch64::MemOperand(vixl::aarch64::sp, location.GetStackIndex()); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 166 | } |
| 167 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 168 | inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base, |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 169 | size_t offset = 0) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 170 | // A heap reference must be 32bit, so fit in a W register. |
| 171 | DCHECK(base.IsW()); |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 172 | return vixl::aarch64::MemOperand(base.X(), offset); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 173 | } |
| 174 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 175 | inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base, |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 176 | const vixl::aarch64::Register& regoffset, |
| 177 | vixl::aarch64::Shift shift = vixl::aarch64::LSL, |
| 178 | unsigned shift_amount = 0) { |
Alexandre Rames | 82000b0 | 2015-07-07 11:34:16 +0100 | [diff] [blame] | 179 | // A heap reference must be 32bit, so fit in a W register. |
| 180 | DCHECK(base.IsW()); |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 181 | return vixl::aarch64::MemOperand(base.X(), regoffset, shift, shift_amount); |
Alexandre Rames | 82000b0 | 2015-07-07 11:34:16 +0100 | [diff] [blame] | 182 | } |
| 183 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 184 | inline vixl::aarch64::MemOperand HeapOperand(const vixl::aarch64::Register& base, |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 185 | Offset offset) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 186 | return HeapOperand(base, offset.SizeValue()); |
| 187 | } |
| 188 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 189 | inline vixl::aarch64::MemOperand HeapOperandFrom(Location location, Offset offset) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 190 | return HeapOperand(RegisterFrom(location, Primitive::kPrimNot), offset); |
| 191 | } |
| 192 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 193 | inline Location LocationFrom(const vixl::aarch64::Register& reg) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 194 | return Location::RegisterLocation(ARTRegCodeFromVIXL(reg.GetCode())); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 195 | } |
| 196 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 197 | inline Location LocationFrom(const vixl::aarch64::FPRegister& fpreg) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 198 | return Location::FpuRegisterLocation(fpreg.GetCode()); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 199 | } |
| 200 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 201 | inline vixl::aarch64::Operand OperandFromMemOperand( |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 202 | const vixl::aarch64::MemOperand& mem_op) { |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 203 | if (mem_op.IsImmediateOffset()) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 204 | return vixl::aarch64::Operand(mem_op.GetOffset()); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 205 | } else { |
| 206 | DCHECK(mem_op.IsRegisterOffset()); |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 207 | if (mem_op.GetExtend() != vixl::aarch64::NO_EXTEND) { |
| 208 | return vixl::aarch64::Operand(mem_op.GetRegisterOffset(), |
| 209 | mem_op.GetExtend(), |
| 210 | mem_op.GetShiftAmount()); |
| 211 | } else if (mem_op.GetShift() != vixl::aarch64::NO_SHIFT) { |
| 212 | return vixl::aarch64::Operand(mem_op.GetRegisterOffset(), |
| 213 | mem_op.GetShift(), |
| 214 | mem_op.GetShiftAmount()); |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 215 | } else { |
| 216 | LOG(FATAL) << "Should not reach here"; |
| 217 | UNREACHABLE(); |
| 218 | } |
| 219 | } |
| 220 | } |
| 221 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 222 | inline bool CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) { |
Roland Levillain | 22c4922 | 2016-03-18 14:04:28 +0000 | [diff] [blame] | 223 | DCHECK(constant->IsIntConstant() || constant->IsLongConstant() || constant->IsNullConstant()) |
| 224 | << constant->DebugName(); |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 225 | |
| 226 | // For single uses we let VIXL handle the constant generation since it will |
| 227 | // use registers that are not managed by the register allocator (wip0, wip1). |
Vladimir Marko | 46817b8 | 2016-03-29 12:21:58 +0100 | [diff] [blame] | 228 | if (constant->GetUses().HasExactlyOneElement()) { |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 229 | return true; |
| 230 | } |
| 231 | |
Scott Wakeling | 40a04bf | 2015-12-11 09:50:36 +0000 | [diff] [blame] | 232 | // Our code generator ensures shift distances are within an encodable range. |
| 233 | if (instr->IsRor()) { |
| 234 | return true; |
| 235 | } |
| 236 | |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 237 | int64_t value = CodeGenerator::GetInt64ValueOf(constant); |
| 238 | |
Alexandre Rames | e6dbf48 | 2015-10-19 10:10:41 +0100 | [diff] [blame] | 239 | if (instr->IsAnd() || instr->IsOr() || instr->IsXor()) { |
| 240 | // Uses logical operations. |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 241 | return vixl::aarch64::Assembler::IsImmLogical(value, vixl::aarch64::kXRegSize); |
Alexandre Rames | e6dbf48 | 2015-10-19 10:10:41 +0100 | [diff] [blame] | 242 | } else if (instr->IsNeg()) { |
| 243 | // Uses mov -immediate. |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 244 | return vixl::aarch64::Assembler::IsImmMovn(value, vixl::aarch64::kXRegSize); |
Alexandre Rames | e6dbf48 | 2015-10-19 10:10:41 +0100 | [diff] [blame] | 245 | } else { |
| 246 | DCHECK(instr->IsAdd() || |
Artem Serov | 328429f | 2016-07-06 16:23:04 +0100 | [diff] [blame] | 247 | instr->IsIntermediateAddress() || |
Alexandre Rames | e6dbf48 | 2015-10-19 10:10:41 +0100 | [diff] [blame] | 248 | instr->IsBoundsCheck() || |
| 249 | instr->IsCompare() || |
| 250 | instr->IsCondition() || |
Roland Levillain | 22c4922 | 2016-03-18 14:04:28 +0000 | [diff] [blame] | 251 | instr->IsSub()) |
| 252 | << instr->DebugName(); |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 253 | // Uses aliases of ADD/SUB instructions. |
Alexandre Rames | b69fbfb | 2015-10-16 09:08:46 +0100 | [diff] [blame] | 254 | // If `value` does not fit but `-value` does, VIXL will automatically use |
| 255 | // the 'opposite' instruction. |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 256 | return vixl::aarch64::Assembler::IsImmAddSub(value) |
| 257 | || vixl::aarch64::Assembler::IsImmAddSub(-value); |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 258 | } |
| 259 | } |
| 260 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 261 | inline Location ARM64EncodableConstantOrRegister(HInstruction* constant, |
Serban Constantinescu | 2d35d9d | 2015-02-22 22:08:01 +0000 | [diff] [blame] | 262 | HInstruction* instr) { |
| 263 | if (constant->IsConstant() |
| 264 | && CanEncodeConstantAsImmediate(constant->AsConstant(), instr)) { |
| 265 | return Location::ConstantLocation(constant->AsConstant()); |
| 266 | } |
| 267 | |
| 268 | return Location::RequiresRegister(); |
| 269 | } |
| 270 | |
Zheng Xu | da40309 | 2015-04-24 17:35:39 +0800 | [diff] [blame] | 271 | // Check if registers in art register set have the same register code in vixl. If the register |
| 272 | // codes are same, we can initialize vixl register list simply by the register masks. Currently, |
| 273 | // only SP/WSP and ZXR/WZR codes are different between art and vixl. |
| 274 | // Note: This function is only used for debug checks. |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 275 | inline bool ArtVixlRegCodeCoherentForRegSet(uint32_t art_core_registers, |
Vladimir Marko | 804b03f | 2016-09-14 16:26:36 +0100 | [diff] [blame] | 276 | size_t num_core, |
| 277 | uint32_t art_fpu_registers, |
| 278 | size_t num_fpu) { |
Zheng Xu | da40309 | 2015-04-24 17:35:39 +0800 | [diff] [blame] | 279 | // The register masks won't work if the number of register is larger than 32. |
| 280 | DCHECK_GE(sizeof(art_core_registers) * 8, num_core); |
| 281 | DCHECK_GE(sizeof(art_fpu_registers) * 8, num_fpu); |
| 282 | for (size_t art_reg_code = 0; art_reg_code < num_core; ++art_reg_code) { |
| 283 | if (RegisterSet::Contains(art_core_registers, art_reg_code)) { |
| 284 | if (art_reg_code != static_cast<size_t>(VIXLRegCodeFromART(art_reg_code))) { |
| 285 | return false; |
| 286 | } |
| 287 | } |
| 288 | } |
| 289 | // There is no register code translation for float registers. |
| 290 | return true; |
| 291 | } |
| 292 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 293 | inline vixl::aarch64::Shift ShiftFromOpKind(HArm64DataProcWithShifterOp::OpKind op_kind) { |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 294 | switch (op_kind) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 295 | case HArm64DataProcWithShifterOp::kASR: return vixl::aarch64::ASR; |
| 296 | case HArm64DataProcWithShifterOp::kLSL: return vixl::aarch64::LSL; |
| 297 | case HArm64DataProcWithShifterOp::kLSR: return vixl::aarch64::LSR; |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 298 | default: |
| 299 | LOG(FATAL) << "Unexpected op kind " << op_kind; |
| 300 | UNREACHABLE(); |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 301 | return vixl::aarch64::NO_SHIFT; |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 302 | } |
| 303 | } |
| 304 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 305 | inline vixl::aarch64::Extend ExtendFromOpKind(HArm64DataProcWithShifterOp::OpKind op_kind) { |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 306 | switch (op_kind) { |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 307 | case HArm64DataProcWithShifterOp::kUXTB: return vixl::aarch64::UXTB; |
| 308 | case HArm64DataProcWithShifterOp::kUXTH: return vixl::aarch64::UXTH; |
| 309 | case HArm64DataProcWithShifterOp::kUXTW: return vixl::aarch64::UXTW; |
| 310 | case HArm64DataProcWithShifterOp::kSXTB: return vixl::aarch64::SXTB; |
| 311 | case HArm64DataProcWithShifterOp::kSXTH: return vixl::aarch64::SXTH; |
| 312 | case HArm64DataProcWithShifterOp::kSXTW: return vixl::aarch64::SXTW; |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 313 | default: |
| 314 | LOG(FATAL) << "Unexpected op kind " << op_kind; |
| 315 | UNREACHABLE(); |
Scott Wakeling | 97c72b7 | 2016-06-24 16:19:36 +0100 | [diff] [blame] | 316 | return vixl::aarch64::NO_EXTEND; |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 317 | } |
| 318 | } |
| 319 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 320 | inline bool CanFitInShifterOperand(HInstruction* instruction) { |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 321 | if (instruction->IsTypeConversion()) { |
| 322 | HTypeConversion* conversion = instruction->AsTypeConversion(); |
| 323 | Primitive::Type result_type = conversion->GetResultType(); |
| 324 | Primitive::Type input_type = conversion->GetInputType(); |
| 325 | // We don't expect to see the same type as input and result. |
| 326 | return Primitive::IsIntegralType(result_type) && Primitive::IsIntegralType(input_type) && |
| 327 | (result_type != input_type); |
| 328 | } else { |
| 329 | return (instruction->IsShl() && instruction->AsShl()->InputAt(1)->IsIntConstant()) || |
| 330 | (instruction->IsShr() && instruction->AsShr()->InputAt(1)->IsIntConstant()) || |
| 331 | (instruction->IsUShr() && instruction->AsUShr()->InputAt(1)->IsIntConstant()); |
| 332 | } |
| 333 | } |
| 334 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 335 | inline bool HasShifterOperand(HInstruction* instr) { |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 336 | // `neg` instructions are an alias of `sub` using the zero register as the |
| 337 | // first register input. |
| 338 | bool res = instr->IsAdd() || instr->IsAnd() || instr->IsNeg() || |
| 339 | instr->IsOr() || instr->IsSub() || instr->IsXor(); |
| 340 | return res; |
| 341 | } |
| 342 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 343 | inline bool ShifterOperandSupportsExtension(HInstruction* instruction) { |
Alexandre Rames | 8626b74 | 2015-11-25 16:28:08 +0000 | [diff] [blame] | 344 | DCHECK(HasShifterOperand(instruction)); |
| 345 | // Although the `neg` instruction is an alias of the `sub` instruction, `HNeg` |
| 346 | // does *not* support extension. This is because the `extended register` form |
| 347 | // of the `sub` instruction interprets the left register with code 31 as the |
| 348 | // stack pointer and not the zero register. (So does the `immediate` form.) In |
| 349 | // the other form `shifted register, the register with code 31 is interpreted |
| 350 | // as the zero register. |
| 351 | return instruction->IsAdd() || instruction->IsSub(); |
| 352 | } |
| 353 | |
Alexandre Rames | badf2b2 | 2016-08-24 17:08:49 +0100 | [diff] [blame] | 354 | inline bool IsConstantZeroBitPattern(const HInstruction* instruction) { |
Alexandre Rames | be919d9 | 2016-08-23 18:33:36 +0100 | [diff] [blame] | 355 | return instruction->IsConstant() && instruction->AsConstant()->IsZeroBitPattern(); |
| 356 | } |
| 357 | |
Andreas Gampe | 878d58c | 2015-01-15 23:24:00 -0800 | [diff] [blame] | 358 | } // namespace helpers |
| 359 | } // namespace arm64 |
| 360 | } // namespace art |
| 361 | |
| 362 | #endif // ART_COMPILER_OPTIMIZING_COMMON_ARM64_H_ |