Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the X86 ISA */ |
| 18 | |
| 19 | #include "codegen_x86.h" |
| 20 | #include "dex/quick/mir_to_lir-inl.h" |
| 21 | #include "mirror/array.h" |
| 22 | #include "x86_lir.h" |
| 23 | |
| 24 | namespace art { |
| 25 | |
| 26 | /* |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | * Compare two 64-bit values |
| 28 | * x = y return 0 |
| 29 | * x < y return -1 |
| 30 | * x > y return 1 |
| 31 | */ |
| 32 | void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 33 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 34 | FlushAllRegs(); |
| 35 | LockCallTemps(); // Prepare for explicit register usage |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 36 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 37 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 38 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 39 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 40 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 41 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 42 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 43 | NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 |
| 44 | NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 45 | OpReg(kOpNeg, rs_r2); // r2 = -r2 |
| 46 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 47 | NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 48 | NewLIR2(kX86Movzx8RR, r0, r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 49 | OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 50 | RegLocation rl_result = LocCReturn(); |
| 51 | StoreValue(rl_dest, rl_result); |
| 52 | } |
| 53 | |
| 54 | X86ConditionCode X86ConditionEncoding(ConditionCode cond) { |
| 55 | switch (cond) { |
| 56 | case kCondEq: return kX86CondEq; |
| 57 | case kCondNe: return kX86CondNe; |
| 58 | case kCondCs: return kX86CondC; |
| 59 | case kCondCc: return kX86CondNc; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 60 | case kCondUlt: return kX86CondC; |
| 61 | case kCondUge: return kX86CondNc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 62 | case kCondMi: return kX86CondS; |
| 63 | case kCondPl: return kX86CondNs; |
| 64 | case kCondVs: return kX86CondO; |
| 65 | case kCondVc: return kX86CondNo; |
| 66 | case kCondHi: return kX86CondA; |
| 67 | case kCondLs: return kX86CondBe; |
| 68 | case kCondGe: return kX86CondGe; |
| 69 | case kCondLt: return kX86CondL; |
| 70 | case kCondGt: return kX86CondG; |
| 71 | case kCondLe: return kX86CondLe; |
| 72 | case kCondAl: |
| 73 | case kCondNv: LOG(FATAL) << "Should not reach here"; |
| 74 | } |
| 75 | return kX86CondO; |
| 76 | } |
| 77 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 78 | LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
| 79 | NewLIR2(kX86Cmp32RR, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 80 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 81 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , |
| 82 | cc); |
| 83 | branch->target = target; |
| 84 | return branch; |
| 85 | } |
| 86 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 87 | LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 88 | int check_value, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 89 | if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { |
| 90 | // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 91 | NewLIR2(kX86Test32RR, reg.GetReg(), reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 92 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 93 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 94 | } |
| 95 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 96 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); |
| 97 | branch->target = target; |
| 98 | return branch; |
| 99 | } |
| 100 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 101 | LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
| 102 | // If src or dest is a pair, we'll be using low reg. |
| 103 | if (r_dest.IsPair()) { |
| 104 | r_dest = r_dest.GetLow(); |
| 105 | } |
| 106 | if (r_src.IsPair()) { |
| 107 | r_src = r_src.GetLow(); |
| 108 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 109 | if (r_dest.IsFloat() || r_src.IsFloat()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | return OpFpRegCopy(r_dest, r_src); |
| 111 | LIR* res = RawLIR(current_dalvik_offset_, kX86Mov32RR, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 112 | r_dest.GetReg(), r_src.GetReg()); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 113 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 114 | res->flags.is_nop = true; |
| 115 | } |
| 116 | return res; |
| 117 | } |
| 118 | |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 119 | void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
| 120 | if (r_dest != r_src) { |
| 121 | LIR *res = OpRegCopyNoInsert(r_dest, r_src); |
| 122 | AppendLIR(res); |
| 123 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 124 | } |
| 125 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 126 | void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 127 | if (r_dest != r_src) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 128 | bool dest_fp = r_dest.IsFloat(); |
| 129 | bool src_fp = r_src.IsFloat(); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 130 | if (dest_fp) { |
| 131 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 132 | OpRegCopy(r_dest, r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 133 | } else { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 134 | // TODO: Prevent this from happening in the code. The result is often |
| 135 | // unused or could have been loaded more easily from memory. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 136 | NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 137 | RegStorage r_tmp = AllocTempDouble(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 138 | NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); |
| 139 | NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 140 | FreeTemp(r_tmp); |
| 141 | } |
| 142 | } else { |
| 143 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 144 | NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); |
Mark Mendell | 99380ed | 2014-05-07 07:53:06 -0400 | [diff] [blame] | 145 | RegStorage temp_reg = AllocTempDouble(); |
| 146 | NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); |
| 147 | NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); |
| 148 | NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 149 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 150 | DCHECK(r_dest.IsPair()); |
| 151 | DCHECK(r_src.IsPair()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 152 | // Handle overlap |
| 153 | if (r_src.GetHighReg() == r_dest.GetLowReg() && r_src.GetLowReg() == r_dest.GetHighReg()) { |
| 154 | // Deal with cycles. |
| 155 | RegStorage temp_reg = AllocTemp(); |
| 156 | OpRegCopy(temp_reg, r_dest.GetHigh()); |
| 157 | OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); |
| 158 | OpRegCopy(r_dest.GetLow(), temp_reg); |
| 159 | FreeTemp(temp_reg); |
| 160 | } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 161 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 162 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 163 | } else { |
| 164 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 165 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 166 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 167 | } |
| 168 | } |
| 169 | } |
| 170 | } |
| 171 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 172 | void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 173 | RegLocation rl_result; |
| 174 | RegLocation rl_src = mir_graph_->GetSrc(mir, 0); |
| 175 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
| 176 | rl_src = LoadValue(rl_src, kCoreReg); |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 177 | ConditionCode ccode = mir->meta.ccode; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 178 | |
| 179 | // The kMirOpSelect has two variants, one for constants and one for moves. |
| 180 | const bool is_constant_case = (mir->ssa_rep->num_uses == 1); |
| 181 | |
| 182 | if (is_constant_case) { |
| 183 | int true_val = mir->dalvikInsn.vB; |
| 184 | int false_val = mir->dalvikInsn.vC; |
| 185 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 186 | |
| 187 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 188 | * For ccode == kCondEq: |
| 189 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 190 | * 1) When the true case is zero and result_reg is not same as src_reg: |
| 191 | * xor result_reg, result_reg |
| 192 | * cmp $0, src_reg |
| 193 | * mov t1, $false_case |
| 194 | * cmovnz result_reg, t1 |
| 195 | * 2) When the false case is zero and result_reg is not same as src_reg: |
| 196 | * xor result_reg, result_reg |
| 197 | * cmp $0, src_reg |
| 198 | * mov t1, $true_case |
| 199 | * cmovz result_reg, t1 |
| 200 | * 3) All other cases (we do compare first to set eflags): |
| 201 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 202 | * mov result_reg, $false_case |
| 203 | * mov t1, $true_case |
| 204 | * cmovz result_reg, t1 |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 205 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 206 | const bool result_reg_same_as_src = |
| 207 | (rl_src.location == kLocPhysReg && rl_src.reg.GetReg() == rl_result.reg.GetReg()); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 208 | const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); |
| 209 | const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); |
| 210 | const bool catch_all_case = !(true_zero_case || false_zero_case); |
| 211 | |
| 212 | if (true_zero_case || false_zero_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 213 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 214 | } |
| 215 | |
| 216 | if (true_zero_case || false_zero_case || catch_all_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 217 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | if (catch_all_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 221 | OpRegImm(kOpMov, rl_result.reg, false_val); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | if (true_zero_case || false_zero_case || catch_all_case) { |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 225 | ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; |
| 226 | int immediateForTemp = true_zero_case ? false_val : true_val; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 227 | RegStorage temp1_reg = AllocTemp(); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 228 | OpRegImm(kOpMov, temp1_reg, immediateForTemp); |
| 229 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 230 | OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 231 | |
| 232 | FreeTemp(temp1_reg); |
| 233 | } |
| 234 | } else { |
| 235 | RegLocation rl_true = mir_graph_->GetSrc(mir, 1); |
| 236 | RegLocation rl_false = mir_graph_->GetSrc(mir, 2); |
| 237 | rl_true = LoadValue(rl_true, kCoreReg); |
| 238 | rl_false = LoadValue(rl_false, kCoreReg); |
| 239 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 240 | |
| 241 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 242 | * For ccode == kCondEq: |
| 243 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 244 | * 1) When true case is already in place: |
| 245 | * cmp $0, src_reg |
| 246 | * cmovnz result_reg, false_reg |
| 247 | * 2) When false case is already in place: |
| 248 | * cmp $0, src_reg |
| 249 | * cmovz result_reg, true_reg |
| 250 | * 3) When neither cases are in place: |
| 251 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 252 | * mov result_reg, false_reg |
| 253 | * cmovz result_reg, true_reg |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 254 | */ |
| 255 | |
| 256 | // kMirOpSelect is generated just for conditional cases when comparison is done with zero. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 257 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 258 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 259 | if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 260 | OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 261 | } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 262 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 263 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 264 | OpRegCopy(rl_result.reg, rl_false.reg); |
| 265 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 266 | } |
| 267 | } |
| 268 | |
| 269 | StoreValue(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 270 | } |
| 271 | |
| 272 | void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 273 | LIR* taken = &block_label_list_[bb->taken]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 274 | RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 275 | RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
Vladimir Marko | a894607 | 2014-01-22 10:30:44 +0000 | [diff] [blame] | 276 | ConditionCode ccode = mir->meta.ccode; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 277 | |
| 278 | if (rl_src1.is_const) { |
| 279 | std::swap(rl_src1, rl_src2); |
| 280 | ccode = FlipComparisonOrder(ccode); |
| 281 | } |
| 282 | if (rl_src2.is_const) { |
| 283 | // Do special compare/branch against simple const operand |
| 284 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 285 | GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); |
| 286 | return; |
| 287 | } |
| 288 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 289 | FlushAllRegs(); |
| 290 | LockCallTemps(); // Prepare for explicit register usage |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 291 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 292 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 293 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 294 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 295 | // Swap operands and condition code to prevent use of zero flag. |
| 296 | if (ccode == kCondLe || ccode == kCondGt) { |
| 297 | // Compute (r3:r2) = (r3:r2) - (r1:r0) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 298 | OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 |
| 299 | OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 300 | } else { |
| 301 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 302 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 303 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 304 | } |
| 305 | switch (ccode) { |
| 306 | case kCondEq: |
| 307 | case kCondNe: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 308 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 309 | break; |
| 310 | case kCondLe: |
| 311 | ccode = kCondGe; |
| 312 | break; |
| 313 | case kCondGt: |
| 314 | ccode = kCondLt; |
| 315 | break; |
| 316 | case kCondLt: |
| 317 | case kCondGe: |
| 318 | break; |
| 319 | default: |
| 320 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 321 | } |
| 322 | OpCondBranch(ccode, taken); |
| 323 | } |
| 324 | |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 325 | void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 326 | int64_t val, ConditionCode ccode) { |
| 327 | int32_t val_lo = Low32Bits(val); |
| 328 | int32_t val_hi = High32Bits(val); |
| 329 | LIR* taken = &block_label_list_[bb->taken]; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 330 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 331 | bool is_equality_test = ccode == kCondEq || ccode == kCondNe; |
| 332 | if (is_equality_test && val != 0) { |
| 333 | rl_src1 = ForceTempWide(rl_src1); |
| 334 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 335 | RegStorage low_reg = rl_src1.reg.GetLow(); |
| 336 | RegStorage high_reg = rl_src1.reg.GetHigh(); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 337 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 338 | if (is_equality_test) { |
| 339 | // We can simpolify of comparing for ==, != to 0. |
| 340 | if (val == 0) { |
| 341 | if (IsTemp(low_reg)) { |
| 342 | OpRegReg(kOpOr, low_reg, high_reg); |
| 343 | // We have now changed it; ignore the old values. |
| 344 | Clobber(rl_src1.reg); |
| 345 | } else { |
| 346 | RegStorage t_reg = AllocTemp(); |
| 347 | OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); |
| 348 | FreeTemp(t_reg); |
| 349 | } |
| 350 | OpCondBranch(ccode, taken); |
| 351 | return; |
| 352 | } |
| 353 | |
| 354 | // Need to compute the actual value for ==, !=. |
| 355 | OpRegImm(kOpSub, low_reg, val_lo); |
| 356 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 357 | OpRegReg(kOpOr, high_reg, low_reg); |
| 358 | Clobber(rl_src1.reg); |
| 359 | } else if (ccode == kCondLe || ccode == kCondGt) { |
| 360 | // Swap operands and condition code to prevent use of zero flag. |
| 361 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 362 | LoadConstantWide(tmp, val); |
| 363 | OpRegReg(kOpSub, tmp.GetLow(), low_reg); |
| 364 | OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); |
| 365 | ccode = (ccode == kCondLe) ? kCondGe : kCondLt; |
| 366 | FreeTemp(tmp); |
| 367 | } else { |
| 368 | // We can use a compare for the low word to set CF. |
| 369 | OpRegImm(kOpCmp, low_reg, val_lo); |
| 370 | if (IsTemp(high_reg)) { |
| 371 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 372 | // We have now changed it; ignore the old values. |
| 373 | Clobber(rl_src1.reg); |
| 374 | } else { |
| 375 | // mov temp_reg, high_reg; sbb temp_reg, high_constant |
| 376 | RegStorage t_reg = AllocTemp(); |
| 377 | OpRegCopy(t_reg, high_reg); |
| 378 | NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); |
| 379 | FreeTemp(t_reg); |
| 380 | } |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 381 | } |
| 382 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 383 | OpCondBranch(ccode, taken); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 384 | } |
| 385 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 386 | void X86Mir2Lir::CalculateMagicAndShift(int divisor, int& magic, int& shift) { |
| 387 | // It does not make sense to calculate magic and shift for zero divisor. |
| 388 | DCHECK_NE(divisor, 0); |
| 389 | |
| 390 | /* According to H.S.Warren's Hacker's Delight Chapter 10 and |
| 391 | * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 392 | * The magic number M and shift S can be calculated in the following way: |
| 393 | * Let nc be the most positive value of numerator(n) such that nc = kd - 1, |
| 394 | * where divisor(d) >=2. |
| 395 | * Let nc be the most negative value of numerator(n) such that nc = kd + 1, |
| 396 | * where divisor(d) <= -2. |
| 397 | * Thus nc can be calculated like: |
| 398 | * nc = 2^31 + 2^31 % d - 1, where d >= 2 |
| 399 | * nc = -2^31 + (2^31 + 1) % d, where d >= 2. |
| 400 | * |
| 401 | * So the shift p is the smallest p satisfying |
| 402 | * 2^p > nc * (d - 2^p % d), where d >= 2 |
| 403 | * 2^p > nc * (d + 2^p % d), where d <= -2. |
| 404 | * |
| 405 | * the magic number M is calcuated by |
| 406 | * M = (2^p + d - 2^p % d) / d, where d >= 2 |
| 407 | * M = (2^p - d - 2^p % d) / d, where d <= -2. |
| 408 | * |
| 409 | * Notice that p is always bigger than or equal to 32, so we just return 32-p as |
| 410 | * the shift number S. |
| 411 | */ |
| 412 | |
| 413 | int32_t p = 31; |
| 414 | const uint32_t two31 = 0x80000000U; |
| 415 | |
| 416 | // Initialize the computations. |
| 417 | uint32_t abs_d = (divisor >= 0) ? divisor : -divisor; |
| 418 | uint32_t tmp = two31 + (static_cast<uint32_t>(divisor) >> 31); |
| 419 | uint32_t abs_nc = tmp - 1 - tmp % abs_d; |
| 420 | uint32_t quotient1 = two31 / abs_nc; |
| 421 | uint32_t remainder1 = two31 % abs_nc; |
| 422 | uint32_t quotient2 = two31 / abs_d; |
| 423 | uint32_t remainder2 = two31 % abs_d; |
| 424 | |
| 425 | /* |
| 426 | * To avoid handling both positive and negative divisor, Hacker's Delight |
| 427 | * introduces a method to handle these 2 cases together to avoid duplication. |
| 428 | */ |
| 429 | uint32_t delta; |
| 430 | do { |
| 431 | p++; |
| 432 | quotient1 = 2 * quotient1; |
| 433 | remainder1 = 2 * remainder1; |
| 434 | if (remainder1 >= abs_nc) { |
| 435 | quotient1++; |
| 436 | remainder1 = remainder1 - abs_nc; |
| 437 | } |
| 438 | quotient2 = 2 * quotient2; |
| 439 | remainder2 = 2 * remainder2; |
| 440 | if (remainder2 >= abs_d) { |
| 441 | quotient2++; |
| 442 | remainder2 = remainder2 - abs_d; |
| 443 | } |
| 444 | delta = abs_d - remainder2; |
| 445 | } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); |
| 446 | |
| 447 | magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); |
| 448 | shift = p - 32; |
| 449 | } |
| 450 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 451 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 452 | LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; |
| 453 | return rl_dest; |
| 454 | } |
| 455 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 456 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, |
| 457 | int imm, bool is_div) { |
| 458 | // Use a multiply (and fixup) to perform an int div/rem by a constant. |
| 459 | |
| 460 | // We have to use fixed registers, so flush all the temps. |
| 461 | FlushAllRegs(); |
| 462 | LockCallTemps(); // Prepare for explicit register usage. |
| 463 | |
| 464 | // Assume that the result will be in EDX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 465 | RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r2, INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 466 | |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 467 | // handle div/rem by 1 special case. |
| 468 | if (imm == 1) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 469 | if (is_div) { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 470 | // x / 1 == x. |
| 471 | StoreValue(rl_result, rl_src); |
| 472 | } else { |
| 473 | // x % 1 == 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 474 | LoadConstantNoClobber(rs_r0, 0); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 475 | // For this case, return the result in EAX. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 476 | rl_result.reg.SetReg(r0); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 477 | } |
| 478 | } else if (imm == -1) { // handle 0x80000000 / -1 special case. |
| 479 | if (is_div) { |
| 480 | LIR *minint_branch = 0; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 481 | LoadValueDirectFixed(rl_src, rs_r0); |
| 482 | OpRegImm(kOpCmp, rs_r0, 0x80000000); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 483 | minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 484 | |
| 485 | // for x != MIN_INT, x / -1 == -x. |
| 486 | NewLIR1(kX86Neg32R, r0); |
| 487 | |
| 488 | LIR* branch_around = NewLIR1(kX86Jmp8, 0); |
| 489 | // The target for cmp/jmp above. |
| 490 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
| 491 | // EAX already contains the right value (0x80000000), |
| 492 | branch_around->target = NewLIR0(kPseudoTargetLabel); |
| 493 | } else { |
| 494 | // x % -1 == 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 495 | LoadConstantNoClobber(rs_r0, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 496 | } |
| 497 | // For this case, return the result in EAX. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 498 | rl_result.reg.SetReg(r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 499 | } else { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 500 | CHECK(imm <= -2 || imm >= 2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 501 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 502 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 503 | int magic, shift; |
| 504 | CalculateMagicAndShift(imm, magic, shift); |
| 505 | |
| 506 | /* |
| 507 | * For imm >= 2, |
| 508 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 509 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 510 | * For imm <= -2, |
| 511 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 512 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 513 | * We implement this algorithm in the following way: |
| 514 | * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX |
| 515 | * 2. if imm > 0 and magic < 0, add numerator to EDX |
| 516 | * if imm < 0 and magic > 0, sub numerator from EDX |
| 517 | * 3. if S !=0, SAR S bits for EDX |
| 518 | * 4. add 1 to EDX if EDX < 0 |
| 519 | * 5. Thus, EDX is the quotient |
| 520 | */ |
| 521 | |
| 522 | // Numerator into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 523 | RegStorage numerator_reg; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 524 | if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { |
| 525 | // We will need the value later. |
| 526 | if (rl_src.location == kLocPhysReg) { |
| 527 | // We can use it directly. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 528 | DCHECK(rl_src.reg.GetReg() != rs_r0.GetReg() && rl_src.reg.GetReg() != rs_r2.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 529 | numerator_reg = rl_src.reg; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 530 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 531 | numerator_reg = rs_r1; |
| 532 | LoadValueDirectFixed(rl_src, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 533 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 534 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 535 | } else { |
| 536 | // Only need this once. Just put it into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 537 | LoadValueDirectFixed(rl_src, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 538 | } |
| 539 | |
| 540 | // EDX = magic. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 541 | LoadConstantNoClobber(rs_r2, magic); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 542 | |
| 543 | // EDX:EAX = magic & dividend. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 544 | NewLIR1(kX86Imul32DaR, rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 545 | |
| 546 | if (imm > 0 && magic < 0) { |
| 547 | // Add numerator to EDX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 548 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 549 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 550 | } else if (imm < 0 && magic > 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 551 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 552 | NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | // Do we need the shift? |
| 556 | if (shift != 0) { |
| 557 | // Shift EDX by 'shift' bits. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 558 | NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | // Add 1 to EDX if EDX < 0. |
| 562 | |
| 563 | // Move EDX to EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 564 | OpRegCopy(rs_r0, rs_r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 565 | |
| 566 | // Move sign bit to bit 0, zeroing the rest. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 567 | NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 568 | |
| 569 | // EDX = EDX + EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 570 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 571 | |
| 572 | // Quotient is in EDX. |
| 573 | if (!is_div) { |
| 574 | // We need to compute the remainder. |
| 575 | // Remainder is divisor - (quotient * imm). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 576 | DCHECK(numerator_reg.Valid()); |
| 577 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 578 | |
| 579 | // EAX = numerator * imm. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 580 | OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 581 | |
| 582 | // EDX -= EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 583 | NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 584 | |
| 585 | // For this case, return the result in EAX. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 586 | rl_result.reg.SetReg(r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 587 | } |
| 588 | } |
| 589 | |
| 590 | return rl_result; |
| 591 | } |
| 592 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 593 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, |
| 594 | bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 595 | LOG(FATAL) << "Unexpected use of GenDivRem for x86"; |
| 596 | return rl_dest; |
| 597 | } |
| 598 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 599 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
| 600 | RegLocation rl_src2, bool is_div, bool check_zero) { |
| 601 | // We have to use fixed registers, so flush all the temps. |
| 602 | FlushAllRegs(); |
| 603 | LockCallTemps(); // Prepare for explicit register usage. |
| 604 | |
| 605 | // Load LHS into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 606 | LoadValueDirectFixed(rl_src1, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 607 | |
| 608 | // Load RHS into EBX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 609 | LoadValueDirectFixed(rl_src2, rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 610 | |
| 611 | // Copy LHS sign bit into EDX. |
| 612 | NewLIR0(kx86Cdq32Da); |
| 613 | |
| 614 | if (check_zero) { |
| 615 | // Handle division by zero case. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 616 | GenDivZeroCheck(rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 617 | } |
| 618 | |
| 619 | // Have to catch 0x80000000/-1 case, or we will get an exception! |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 620 | OpRegImm(kOpCmp, rs_r1, -1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 621 | LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 622 | |
| 623 | // RHS is -1. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 624 | OpRegImm(kOpCmp, rs_r0, 0x80000000); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 625 | LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 626 | |
| 627 | // In 0x80000000/-1 case. |
| 628 | if (!is_div) { |
| 629 | // For DIV, EAX is already right. For REM, we need EDX 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 630 | LoadConstantNoClobber(rs_r2, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 631 | } |
| 632 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 633 | |
| 634 | // Expected case. |
| 635 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 636 | minint_branch->target = minus_one_branch->target; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 637 | NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 638 | done->target = NewLIR0(kPseudoTargetLabel); |
| 639 | |
| 640 | // Result is in EAX for div and EDX for rem. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 641 | RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 642 | if (!is_div) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 643 | rl_result.reg.SetReg(r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 644 | } |
| 645 | return rl_result; |
| 646 | } |
| 647 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 648 | bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 649 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 650 | |
| 651 | // Get the two arguments to the invoke and place them in GP registers. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 652 | RegLocation rl_src1 = info->args[0]; |
| 653 | RegLocation rl_src2 = info->args[1]; |
| 654 | rl_src1 = LoadValue(rl_src1, kCoreReg); |
| 655 | rl_src2 = LoadValue(rl_src2, kCoreReg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 656 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 657 | RegLocation rl_dest = InlineTarget(info); |
| 658 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 659 | |
| 660 | /* |
| 661 | * If the result register is the same as the second element, then we need to be careful. |
| 662 | * The reason is that the first copy will inadvertently clobber the second element with |
| 663 | * the first one thus yielding the wrong result. Thus we do a swap in that case. |
| 664 | */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 665 | if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 666 | std::swap(rl_src1, rl_src2); |
| 667 | } |
| 668 | |
| 669 | // Pick the first integer as min/max. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 670 | OpRegCopy(rl_result.reg, rl_src1.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 671 | |
| 672 | // If the integers are both in the same register, then there is nothing else to do |
| 673 | // because they are equal and we have already moved one into the result. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 674 | if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 675 | // It is possible we didn't pick correctly so do the actual comparison now. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 676 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 677 | |
| 678 | // Conditionally move the other integer into the destination register. |
| 679 | ConditionCode condition_code = is_min ? kCondGt : kCondLt; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 680 | OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 681 | } |
| 682 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 683 | StoreValue(rl_dest, rl_result); |
| 684 | return true; |
| 685 | } |
| 686 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 687 | bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
| 688 | RegLocation rl_src_address = info->args[0]; // long address |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 689 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 690 | RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 691 | RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); |
| 692 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Vladimir Marko | 455759b | 2014-05-06 20:49:36 +0100 | [diff] [blame] | 693 | // Unaligned access is allowed on x86. |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 694 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 695 | if (size == k64) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 696 | StoreValueWide(rl_dest, rl_result); |
| 697 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 698 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 699 | StoreValue(rl_dest, rl_result); |
| 700 | } |
| 701 | return true; |
| 702 | } |
| 703 | |
| 704 | bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
| 705 | RegLocation rl_src_address = info->args[0]; // long address |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 706 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[1] |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 707 | RegLocation rl_src_value = info->args[2]; // [size] value |
| 708 | RegLocation rl_address = LoadValue(rl_src_address, kCoreReg); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 709 | if (size == k64) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 710 | // Unaligned access is allowed on x86. |
| 711 | RegLocation rl_value = LoadValueWide(rl_src_value, kCoreReg); |
Vladimir Marko | 455759b | 2014-05-06 20:49:36 +0100 | [diff] [blame] | 712 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 713 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 714 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 715 | // Unaligned access is allowed on x86. |
| 716 | RegLocation rl_value = LoadValue(rl_src_value, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 717 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size); |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 718 | } |
| 719 | return true; |
| 720 | } |
| 721 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 722 | void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { |
| 723 | NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 724 | } |
| 725 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 726 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 727 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 728 | } |
| 729 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 730 | static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { |
| 731 | return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 732 | } |
| 733 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 734 | bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 735 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 736 | // Unused - RegLocation rl_src_unsafe = info->args[0]; |
| 737 | RegLocation rl_src_obj = info->args[1]; // Object - known non-null |
| 738 | RegLocation rl_src_offset = info->args[2]; // long low |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 739 | rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 740 | RegLocation rl_src_expected = info->args[4]; // int, long or Object |
| 741 | // If is_long, high half is in info->args[5] |
| 742 | RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object |
| 743 | // If is_long, high half is in info->args[7] |
| 744 | |
| 745 | if (is_long) { |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 746 | // TODO: avoid unnecessary loads of SI and DI when the values are in registers. |
| 747 | // TODO: CFI support. |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 748 | FlushAllRegs(); |
| 749 | LockCallTemps(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 750 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 751 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 752 | LoadValueDirectWideFixed(rl_src_expected, r_tmp1); |
| 753 | LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 754 | NewLIR1(kX86Push32R, rs_rDI.GetReg()); |
| 755 | MarkTemp(rs_rDI); |
| 756 | LockTemp(rs_rDI); |
| 757 | NewLIR1(kX86Push32R, rs_rSI.GetReg()); |
| 758 | MarkTemp(rs_rSI); |
| 759 | LockTemp(rs_rSI); |
Vladimir Marko | a6fd8ba | 2013-12-13 10:53:49 +0000 | [diff] [blame] | 760 | const int push_offset = 4 /* push edi */ + 4 /* push esi */; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 761 | int srcObjSp = IsInReg(this, rl_src_obj, rs_rSI) ? 0 |
| 762 | : (IsInReg(this, rl_src_obj, rs_rDI) ? 4 |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 763 | : (SRegOffset(rl_src_obj.s_reg_low) + push_offset)); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 764 | // FIXME: needs 64-bit update. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 765 | LoadWordDisp(TargetReg(kSp), srcObjSp, rs_rDI); |
| 766 | int srcOffsetSp = IsInReg(this, rl_src_offset, rs_rSI) ? 0 |
| 767 | : (IsInReg(this, rl_src_offset, rs_rDI) ? 4 |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 768 | : (SRegOffset(rl_src_offset.s_reg_low) + push_offset)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 769 | LoadWordDisp(TargetReg(kSp), srcOffsetSp, rs_rSI); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 770 | NewLIR4(kX86LockCmpxchg8bA, rs_rDI.GetReg(), rs_rSI.GetReg(), 0, 0); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 771 | |
| 772 | // After a store we need to insert barrier in case of potential load. Since the |
| 773 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. |
| 774 | GenMemBarrier(kStoreLoad); |
| 775 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 776 | FreeTemp(rs_rSI); |
| 777 | UnmarkTemp(rs_rSI); |
| 778 | NewLIR1(kX86Pop32R, rs_rSI.GetReg()); |
| 779 | FreeTemp(rs_rDI); |
| 780 | UnmarkTemp(rs_rDI); |
| 781 | NewLIR1(kX86Pop32R, rs_rDI.GetReg()); |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 782 | FreeCallTemps(); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 783 | } else { |
| 784 | // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 785 | FlushReg(rs_r0); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 786 | Clobber(rs_r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 787 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 788 | |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 789 | RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg); |
| 790 | RegLocation rl_new_value = LoadValue(rl_src_new_value, kCoreReg); |
| 791 | |
| 792 | if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { |
| 793 | // Mark card for object assuming new value is stored. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 794 | FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 795 | MarkGCCard(rl_new_value.reg, rl_object.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 796 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 797 | } |
| 798 | |
| 799 | RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 800 | LoadValueDirect(rl_src_expected, rs_r0); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 801 | NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, rl_new_value.reg.GetReg()); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 802 | |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 803 | // After a store we need to insert barrier in case of potential load. Since the |
| 804 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. |
| 805 | GenMemBarrier(kStoreLoad); |
| 806 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 807 | FreeTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 808 | } |
| 809 | |
| 810 | // Convert ZF to boolean |
| 811 | RegLocation rl_dest = InlineTarget(info); // boolean place for result |
| 812 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 813 | NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondZ); |
| 814 | NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 815 | StoreValue(rl_dest, rl_result); |
| 816 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 817 | } |
| 818 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 819 | LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 820 | CHECK(base_of_code_ != nullptr); |
| 821 | |
| 822 | // Address the start of the method |
| 823 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
| 824 | LoadValueDirectFixed(rl_method, reg); |
| 825 | store_method_addr_used_ = true; |
| 826 | |
| 827 | // Load the proper value from the literal area. |
| 828 | // We don't know the proper offset for the value, so pick one that will force |
| 829 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 830 | // value. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 831 | LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256, |
| 832 | 0, 0, target); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 833 | res->target = target; |
| 834 | res->flags.fixup = kFixupLoad; |
| 835 | SetMemRefType(res, true, kLiteral); |
| 836 | store_method_addr_used_ = true; |
| 837 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 838 | } |
| 839 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 840 | LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 841 | LOG(FATAL) << "Unexpected use of OpVldm for x86"; |
| 842 | return NULL; |
| 843 | } |
| 844 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 845 | LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 846 | LOG(FATAL) << "Unexpected use of OpVstm for x86"; |
| 847 | return NULL; |
| 848 | } |
| 849 | |
| 850 | void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 851 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 852 | int first_bit, int second_bit) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 853 | RegStorage t_reg = AllocTemp(); |
| 854 | OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); |
| 855 | OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 856 | FreeTemp(t_reg); |
| 857 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 858 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 859 | } |
| 860 | } |
| 861 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 862 | void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 863 | DCHECK(reg.IsPair()); // TODO: allow 64BitSolo. |
| 864 | // We are not supposed to clobber the incoming storage, so allocate a temporary. |
| 865 | RegStorage t_reg = AllocTemp(); |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 866 | |
| 867 | // Doing an OR is a quick way to check if both registers are zero. This will set the flags. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 868 | OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 869 | |
| 870 | // In case of zero, throw ArithmeticException. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 871 | GenDivZeroCheck(kCondEq); |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 872 | |
| 873 | // The temp is no longer needed so free it at this time. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 874 | FreeTemp(t_reg); |
| 875 | } |
| 876 | |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 877 | void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, |
| 878 | RegStorage array_base, |
| 879 | int len_offset) { |
| 880 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 881 | public: |
| 882 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 883 | RegStorage index, RegStorage array_base, int32_t len_offset) |
| 884 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 885 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 886 | } |
| 887 | |
| 888 | void Compile() OVERRIDE { |
| 889 | m2l_->ResetRegPool(); |
| 890 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 891 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 892 | |
| 893 | RegStorage new_index = index_; |
| 894 | // Move index out of kArg1, either directly to kArg0, or to kArg2. |
| 895 | if (index_.GetReg() == m2l_->TargetReg(kArg1).GetReg()) { |
| 896 | if (array_base_.GetReg() == m2l_->TargetReg(kArg0).GetReg()) { |
| 897 | m2l_->OpRegCopy(m2l_->TargetReg(kArg2), index_); |
| 898 | new_index = m2l_->TargetReg(kArg2); |
| 899 | } else { |
| 900 | m2l_->OpRegCopy(m2l_->TargetReg(kArg0), index_); |
| 901 | new_index = m2l_->TargetReg(kArg0); |
| 902 | } |
| 903 | } |
| 904 | // Load array length to kArg1. |
| 905 | m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); |
| 906 | m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), |
| 907 | new_index, m2l_->TargetReg(kArg1), true); |
| 908 | } |
| 909 | |
| 910 | private: |
| 911 | const RegStorage index_; |
| 912 | const RegStorage array_base_; |
| 913 | const int32_t len_offset_; |
| 914 | }; |
| 915 | |
| 916 | OpRegMem(kOpCmp, index, array_base, len_offset); |
| 917 | LIR* branch = OpCondBranch(kCondUge, nullptr); |
| 918 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 919 | index, array_base, len_offset)); |
| 920 | } |
| 921 | |
| 922 | void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, |
| 923 | RegStorage array_base, |
| 924 | int32_t len_offset) { |
| 925 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 926 | public: |
| 927 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 928 | int32_t index, RegStorage array_base, int32_t len_offset) |
| 929 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 930 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 931 | } |
| 932 | |
| 933 | void Compile() OVERRIDE { |
| 934 | m2l_->ResetRegPool(); |
| 935 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 936 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 937 | |
| 938 | // Load array length to kArg1. |
| 939 | m2l_->OpRegMem(kOpMov, m2l_->TargetReg(kArg1), array_base_, len_offset_); |
| 940 | m2l_->LoadConstant(m2l_->TargetReg(kArg0), index_); |
| 941 | m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(4, pThrowArrayBounds), |
| 942 | m2l_->TargetReg(kArg0), m2l_->TargetReg(kArg1), true); |
| 943 | } |
| 944 | |
| 945 | private: |
| 946 | const int32_t index_; |
| 947 | const RegStorage array_base_; |
| 948 | const int32_t len_offset_; |
| 949 | }; |
| 950 | |
| 951 | NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); |
| 952 | LIR* branch = OpCondBranch(kCondLs, nullptr); |
| 953 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 954 | index, array_base, len_offset)); |
| 955 | } |
| 956 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 957 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 958 | LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 959 | OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 960 | return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); |
| 961 | } |
| 962 | |
| 963 | // Decrement register and branch on condition |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 964 | LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 965 | OpRegImm(kOpSub, reg, 1); |
Yixin Shou | a0dac3e | 2014-01-23 05:01:22 -0800 | [diff] [blame] | 966 | return OpCondBranch(c_code, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 967 | } |
| 968 | |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 969 | bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 970 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 971 | LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; |
| 972 | return false; |
| 973 | } |
| 974 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 975 | bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
| 976 | LOG(FATAL) << "Unexpected use of easyMultiply in x86"; |
| 977 | return false; |
| 978 | } |
| 979 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 980 | LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 981 | LOG(FATAL) << "Unexpected use of OpIT in x86"; |
| 982 | return NULL; |
| 983 | } |
| 984 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 985 | void X86Mir2Lir::OpEndIT(LIR* it) { |
| 986 | LOG(FATAL) << "Unexpected use of OpEndIT in x86"; |
| 987 | } |
| 988 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 989 | void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 990 | switch (val) { |
| 991 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 992 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 993 | break; |
| 994 | case 1: |
| 995 | OpRegCopy(dest, src); |
| 996 | break; |
| 997 | default: |
| 998 | OpRegRegImm(kOpMul, dest, src, val); |
| 999 | break; |
| 1000 | } |
| 1001 | } |
| 1002 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1003 | void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1004 | LIR *m; |
| 1005 | switch (val) { |
| 1006 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1007 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1008 | break; |
| 1009 | case 1: |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1010 | LoadBaseDisp(rs_rX86_SP, displacement, dest, k32); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1011 | break; |
| 1012 | default: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1013 | m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), |
| 1014 | rs_rX86_SP.GetReg(), displacement, val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1015 | AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); |
| 1016 | break; |
| 1017 | } |
| 1018 | } |
| 1019 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1020 | void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1021 | RegLocation rl_src2) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1022 | if (rl_src1.is_const) { |
| 1023 | std::swap(rl_src1, rl_src2); |
| 1024 | } |
| 1025 | // Are we multiplying by a constant? |
| 1026 | if (rl_src2.is_const) { |
| 1027 | // Do special compare/branch against simple const operand |
| 1028 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 1029 | if (val == 0) { |
| 1030 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1031 | OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); |
| 1032 | OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1033 | StoreValueWide(rl_dest, rl_result); |
| 1034 | return; |
| 1035 | } else if (val == 1) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1036 | StoreValueWide(rl_dest, rl_src1); |
| 1037 | return; |
| 1038 | } else if (val == 2) { |
| 1039 | GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); |
| 1040 | return; |
| 1041 | } else if (IsPowerOfTwo(val)) { |
| 1042 | int shift_amount = LowestSetBit(val); |
| 1043 | if (!BadOverlap(rl_src1, rl_dest)) { |
| 1044 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1045 | RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, |
| 1046 | rl_src1, shift_amount); |
| 1047 | StoreValueWide(rl_dest, rl_result); |
| 1048 | return; |
| 1049 | } |
| 1050 | } |
| 1051 | |
| 1052 | // Okay, just bite the bullet and do it. |
| 1053 | int32_t val_lo = Low32Bits(val); |
| 1054 | int32_t val_hi = High32Bits(val); |
| 1055 | FlushAllRegs(); |
| 1056 | LockCallTemps(); // Prepare for explicit register usage. |
| 1057 | rl_src1 = UpdateLocWide(rl_src1); |
| 1058 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1059 | int displacement = SRegOffset(rl_src1.s_reg_low); |
| 1060 | |
| 1061 | // ECX <- 1H * 2L |
| 1062 | // EAX <- 1L * 2H |
| 1063 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1064 | GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); |
| 1065 | GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1066 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1067 | GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); |
| 1068 | GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1069 | } |
| 1070 | |
| 1071 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1072 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1073 | |
| 1074 | // EAX <- 2L |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1075 | LoadConstantNoClobber(rs_r0, val_lo); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1076 | |
| 1077 | // EDX:EAX <- 2L * 1L (double precision) |
| 1078 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1079 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1080 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1081 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1082 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1083 | true /* is_load */, true /* is_64bit */); |
| 1084 | } |
| 1085 | |
| 1086 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1087 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1088 | |
| 1089 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1090 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
| 1091 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1092 | StoreValueWide(rl_dest, rl_result); |
| 1093 | return; |
| 1094 | } |
| 1095 | |
| 1096 | // Nope. Do it the hard way |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1097 | // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. |
| 1098 | bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == |
| 1099 | mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 1100 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1101 | FlushAllRegs(); |
| 1102 | LockCallTemps(); // Prepare for explicit register usage. |
| 1103 | rl_src1 = UpdateLocWide(rl_src1); |
| 1104 | rl_src2 = UpdateLocWide(rl_src2); |
| 1105 | |
| 1106 | // At this point, the VRs are in their home locations. |
| 1107 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1108 | bool src2_in_reg = rl_src2.location == kLocPhysReg; |
| 1109 | |
| 1110 | // ECX <- 1H |
| 1111 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1112 | NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1113 | } else { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1114 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1115 | } |
| 1116 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1117 | if (is_square) { |
| 1118 | // Take advantage of the fact that the values are the same. |
| 1119 | // ECX <- ECX * 2L (1H * 2L) |
| 1120 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1121 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1122 | } else { |
| 1123 | int displacement = SRegOffset(rl_src2.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1124 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
| 1125 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1126 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1127 | true /* is_load */, true /* is_64bit */); |
| 1128 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1129 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1130 | // ECX <- 2*ECX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1131 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1132 | } else { |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1133 | // EAX <- 2H |
| 1134 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1135 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1136 | } else { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1137 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1138 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1139 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1140 | // EAX <- EAX * 1L (2H * 1L) |
| 1141 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1142 | NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1143 | } else { |
| 1144 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1145 | LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP.GetReg(), |
| 1146 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1147 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1148 | true /* is_load */, true /* is_64bit */); |
| 1149 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1150 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1151 | // ECX <- ECX * 2L (1H * 2L) |
| 1152 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1153 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1154 | } else { |
| 1155 | int displacement = SRegOffset(rl_src2.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1156 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
| 1157 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1158 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1159 | true /* is_load */, true /* is_64bit */); |
| 1160 | } |
| 1161 | |
| 1162 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1163 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1164 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1165 | |
| 1166 | // EAX <- 2L |
| 1167 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1168 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1169 | } else { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1170 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1171 | } |
| 1172 | |
| 1173 | // EDX:EAX <- 2L * 1L (double precision) |
| 1174 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1175 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1176 | } else { |
| 1177 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1178 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1179 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1180 | true /* is_load */, true /* is_64bit */); |
| 1181 | } |
| 1182 | |
| 1183 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1184 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1185 | |
| 1186 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1187 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1188 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1189 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1190 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1191 | |
| 1192 | void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, |
| 1193 | Instruction::Code op) { |
| 1194 | DCHECK_EQ(rl_dest.location, kLocPhysReg); |
| 1195 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
| 1196 | if (rl_src.location == kLocPhysReg) { |
| 1197 | // Both operands are in registers. |
Serguei Katkov | ab5545f | 2014-03-25 10:51:15 +0700 | [diff] [blame] | 1198 | // But we must ensure that rl_src is in pair |
| 1199 | rl_src = EvalLocWide(rl_src, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1200 | if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1201 | // The registers are the same, so we would clobber it before the use. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1202 | RegStorage temp_reg = AllocTemp(); |
| 1203 | OpRegCopy(temp_reg, rl_dest.reg); |
| 1204 | rl_src.reg.SetHighReg(temp_reg.GetReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1205 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1206 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1207 | |
| 1208 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1209 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1210 | FreeTemp(rl_src.reg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1211 | return; |
| 1212 | } |
| 1213 | |
| 1214 | // RHS is in memory. |
| 1215 | DCHECK((rl_src.location == kLocDalvikFrame) || |
| 1216 | (rl_src.location == kLocCompilerTemp)); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1217 | int r_base = TargetReg(kSp).GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1218 | int displacement = SRegOffset(rl_src.s_reg_low); |
| 1219 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1220 | LIR *lir = NewLIR3(x86op, rl_dest.reg.GetLowReg(), r_base, displacement + LOWORD_OFFSET); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1221 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 1222 | true /* is_load */, true /* is64bit */); |
| 1223 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1224 | lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1225 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1226 | true /* is_load */, true /* is64bit */); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1227 | } |
| 1228 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1229 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
| 1230 | rl_dest = UpdateLocWide(rl_dest); |
| 1231 | if (rl_dest.location == kLocPhysReg) { |
| 1232 | // Ensure we are in a register pair |
| 1233 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1234 | |
| 1235 | rl_src = UpdateLocWide(rl_src); |
| 1236 | GenLongRegOrMemOp(rl_result, rl_src, op); |
| 1237 | StoreFinalValueWide(rl_dest, rl_result); |
| 1238 | return; |
| 1239 | } |
| 1240 | |
| 1241 | // It wasn't in registers, so it better be in memory. |
| 1242 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1243 | (rl_dest.location == kLocCompilerTemp)); |
| 1244 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1245 | |
| 1246 | // Operate directly into memory. |
| 1247 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1248 | int r_base = TargetReg(kSp).GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1249 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 1250 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1251 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1252 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1253 | true /* is_load */, true /* is64bit */); |
| 1254 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1255 | false /* is_load */, true /* is64bit */); |
| 1256 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1257 | lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1258 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1259 | true /* is_load */, true /* is64bit */); |
| 1260 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1261 | false /* is_load */, true /* is64bit */); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1262 | FreeTemp(rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1263 | } |
| 1264 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1265 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, |
| 1266 | RegLocation rl_src2, Instruction::Code op, |
| 1267 | bool is_commutative) { |
| 1268 | // Is this really a 2 operand operation? |
| 1269 | switch (op) { |
| 1270 | case Instruction::ADD_LONG_2ADDR: |
| 1271 | case Instruction::SUB_LONG_2ADDR: |
| 1272 | case Instruction::AND_LONG_2ADDR: |
| 1273 | case Instruction::OR_LONG_2ADDR: |
| 1274 | case Instruction::XOR_LONG_2ADDR: |
| 1275 | GenLongArith(rl_dest, rl_src2, op); |
| 1276 | return; |
| 1277 | default: |
| 1278 | break; |
| 1279 | } |
| 1280 | |
| 1281 | if (rl_dest.location == kLocPhysReg) { |
| 1282 | RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); |
| 1283 | |
| 1284 | // We are about to clobber the LHS, so it needs to be a temp. |
| 1285 | rl_result = ForceTempWide(rl_result); |
| 1286 | |
| 1287 | // Perform the operation using the RHS. |
| 1288 | rl_src2 = UpdateLocWide(rl_src2); |
| 1289 | GenLongRegOrMemOp(rl_result, rl_src2, op); |
| 1290 | |
| 1291 | // And now record that the result is in the temp. |
| 1292 | StoreFinalValueWide(rl_dest, rl_result); |
| 1293 | return; |
| 1294 | } |
| 1295 | |
| 1296 | // It wasn't in registers, so it better be in memory. |
| 1297 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1298 | (rl_dest.location == kLocCompilerTemp)); |
| 1299 | rl_src1 = UpdateLocWide(rl_src1); |
| 1300 | rl_src2 = UpdateLocWide(rl_src2); |
| 1301 | |
| 1302 | // Get one of the source operands into temporary register. |
| 1303 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1304 | if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1305 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1306 | } else if (is_commutative) { |
| 1307 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1308 | // We need at least one of them to be a temporary. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1309 | if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1310 | rl_src1 = ForceTempWide(rl_src1); |
Yevgeny Rouban | 91b6ffa | 2014-03-07 14:35:44 +0700 | [diff] [blame] | 1311 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1312 | } else { |
| 1313 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 1314 | StoreFinalValueWide(rl_dest, rl_src2); |
| 1315 | return; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1316 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1317 | } else { |
| 1318 | // Need LHS to be the temp. |
| 1319 | rl_src1 = ForceTempWide(rl_src1); |
| 1320 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1321 | } |
| 1322 | |
| 1323 | StoreFinalValueWide(rl_dest, rl_src1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1324 | } |
| 1325 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1326 | void X86Mir2Lir::GenAddLong(Instruction::Code opcode, RegLocation rl_dest, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1327 | RegLocation rl_src1, RegLocation rl_src2) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1328 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1329 | } |
| 1330 | |
| 1331 | void X86Mir2Lir::GenSubLong(Instruction::Code opcode, RegLocation rl_dest, |
| 1332 | RegLocation rl_src1, RegLocation rl_src2) { |
| 1333 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); |
| 1334 | } |
| 1335 | |
| 1336 | void X86Mir2Lir::GenAndLong(Instruction::Code opcode, RegLocation rl_dest, |
| 1337 | RegLocation rl_src1, RegLocation rl_src2) { |
| 1338 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1339 | } |
| 1340 | |
| 1341 | void X86Mir2Lir::GenOrLong(Instruction::Code opcode, RegLocation rl_dest, |
| 1342 | RegLocation rl_src1, RegLocation rl_src2) { |
| 1343 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1344 | } |
| 1345 | |
| 1346 | void X86Mir2Lir::GenXorLong(Instruction::Code opcode, RegLocation rl_dest, |
| 1347 | RegLocation rl_src1, RegLocation rl_src2) { |
| 1348 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1349 | } |
| 1350 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1351 | void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1352 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1353 | RegLocation rl_result = ForceTempWide(rl_src); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1354 | if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) && |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1355 | ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1356 | // The registers are the same, so we would clobber it before the use. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1357 | RegStorage temp_reg = AllocTemp(); |
| 1358 | OpRegCopy(temp_reg, rl_result.reg); |
| 1359 | rl_result.reg.SetHighReg(temp_reg.GetReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1360 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1361 | OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow |
| 1362 | OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF |
| 1363 | OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1364 | StoreValueWide(rl_dest, rl_result); |
| 1365 | } |
| 1366 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1367 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1368 | X86OpCode opcode = kX86Bkpt; |
| 1369 | switch (op) { |
| 1370 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 1371 | case kOpMov: opcode = kX86Mov32RT; break; |
| 1372 | default: |
| 1373 | LOG(FATAL) << "Bad opcode: " << op; |
| 1374 | break; |
| 1375 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1376 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1377 | } |
| 1378 | |
| 1379 | /* |
| 1380 | * Generate array load |
| 1381 | */ |
| 1382 | void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1383 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1384 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1385 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1386 | RegLocation rl_result; |
| 1387 | rl_array = LoadValue(rl_array, kCoreReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1388 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1389 | int data_offset; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1390 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1391 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 1392 | } else { |
| 1393 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 1394 | } |
| 1395 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1396 | bool constant_index = rl_index.is_const; |
| 1397 | int32_t constant_index_value = 0; |
| 1398 | if (!constant_index) { |
| 1399 | rl_index = LoadValue(rl_index, kCoreReg); |
| 1400 | } else { |
| 1401 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 1402 | // If index is constant, just fold it into the data offset |
| 1403 | data_offset += constant_index_value << scale; |
| 1404 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1405 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1406 | } |
| 1407 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1408 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1409 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1410 | |
| 1411 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1412 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1413 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1414 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1415 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1416 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1417 | } |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1418 | rl_result = EvalLoc(rl_dest, reg_class, true); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1419 | LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1420 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1421 | StoreValueWide(rl_dest, rl_result); |
| 1422 | } else { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1423 | StoreValue(rl_dest, rl_result); |
| 1424 | } |
| 1425 | } |
| 1426 | |
| 1427 | /* |
| 1428 | * Generate array store |
| 1429 | * |
| 1430 | */ |
| 1431 | void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1432 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1433 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1434 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 1435 | int data_offset; |
| 1436 | |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1437 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1438 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 1439 | } else { |
| 1440 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 1441 | } |
| 1442 | |
| 1443 | rl_array = LoadValue(rl_array, kCoreReg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1444 | bool constant_index = rl_index.is_const; |
| 1445 | int32_t constant_index_value = 0; |
| 1446 | if (!constant_index) { |
| 1447 | rl_index = LoadValue(rl_index, kCoreReg); |
| 1448 | } else { |
| 1449 | // If index is constant, just fold it into the data offset |
| 1450 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 1451 | data_offset += constant_index_value << scale; |
| 1452 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1453 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1454 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1455 | |
| 1456 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1457 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1458 | |
| 1459 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1460 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1461 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1462 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1463 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1464 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1465 | } |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1466 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1467 | rl_src = LoadValueWide(rl_src, reg_class); |
| 1468 | } else { |
| 1469 | rl_src = LoadValue(rl_src, reg_class); |
| 1470 | } |
| 1471 | // If the src reg can't be byte accessed, move it to a temp first. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1472 | if ((size == kSignedByte || size == kUnsignedByte) && |
| 1473 | rl_src.reg.GetRegNum() >= rs_rX86_SP.GetRegNum()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1474 | RegStorage temp = AllocTemp(); |
| 1475 | OpRegCopy(temp, rl_src.reg); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1476 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1477 | } else { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1478 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1479 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 1480 | if (card_mark) { |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 1481 | // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1482 | if (!constant_index) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1483 | FreeTemp(rl_index.reg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 1484 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1485 | MarkGCCard(rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1486 | } |
| 1487 | } |
| 1488 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1489 | RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 1490 | RegLocation rl_src, int shift_amount) { |
| 1491 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1492 | switch (opcode) { |
| 1493 | case Instruction::SHL_LONG: |
| 1494 | case Instruction::SHL_LONG_2ADDR: |
| 1495 | DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. |
| 1496 | if (shift_amount == 32) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1497 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 1498 | LoadConstant(rl_result.reg.GetLow(), 0); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1499 | } else if (shift_amount > 31) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1500 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1501 | FreeTemp(rl_src.reg.GetHigh()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1502 | NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1503 | LoadConstant(rl_result.reg.GetLow(), 0); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1504 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1505 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1506 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 1507 | NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), shift_amount); |
| 1508 | NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1509 | } |
| 1510 | break; |
| 1511 | case Instruction::SHR_LONG: |
| 1512 | case Instruction::SHR_LONG_2ADDR: |
| 1513 | if (shift_amount == 32) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1514 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 1515 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1516 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1517 | } else if (shift_amount > 31) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1518 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 1519 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 1520 | NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1521 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1522 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1523 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1524 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 1525 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), shift_amount); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1526 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1527 | } |
| 1528 | break; |
| 1529 | case Instruction::USHR_LONG: |
| 1530 | case Instruction::USHR_LONG_2ADDR: |
| 1531 | if (shift_amount == 32) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1532 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 1533 | LoadConstant(rl_result.reg.GetHigh(), 0); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1534 | } else if (shift_amount > 31) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1535 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 1536 | NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 1537 | LoadConstant(rl_result.reg.GetHigh(), 0); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1538 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1539 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1540 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 1541 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), shift_amount); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1542 | NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1543 | } |
| 1544 | break; |
| 1545 | default: |
| 1546 | LOG(FATAL) << "Unexpected case"; |
| 1547 | } |
| 1548 | return rl_result; |
| 1549 | } |
| 1550 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1551 | void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1552 | RegLocation rl_src, RegLocation rl_shift) { |
| 1553 | // Per spec, we only care about low 6 bits of shift amount. |
| 1554 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 1555 | if (shift_amount == 0) { |
| 1556 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1557 | StoreValueWide(rl_dest, rl_src); |
| 1558 | return; |
| 1559 | } else if (shift_amount == 1 && |
| 1560 | (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { |
| 1561 | // Need to handle this here to avoid calling StoreValueWide twice. |
| 1562 | GenAddLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src); |
| 1563 | return; |
| 1564 | } |
| 1565 | if (BadOverlap(rl_src, rl_dest)) { |
| 1566 | GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); |
| 1567 | return; |
| 1568 | } |
| 1569 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1570 | RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount); |
| 1571 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1572 | } |
| 1573 | |
| 1574 | void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1575 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1576 | switch (opcode) { |
| 1577 | case Instruction::ADD_LONG: |
| 1578 | case Instruction::AND_LONG: |
| 1579 | case Instruction::OR_LONG: |
| 1580 | case Instruction::XOR_LONG: |
| 1581 | if (rl_src2.is_const) { |
| 1582 | GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
| 1583 | } else { |
| 1584 | DCHECK(rl_src1.is_const); |
| 1585 | GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
| 1586 | } |
| 1587 | break; |
| 1588 | case Instruction::SUB_LONG: |
| 1589 | case Instruction::SUB_LONG_2ADDR: |
| 1590 | if (rl_src2.is_const) { |
| 1591 | GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
| 1592 | } else { |
| 1593 | GenSubLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1594 | } |
| 1595 | break; |
| 1596 | case Instruction::ADD_LONG_2ADDR: |
| 1597 | case Instruction::OR_LONG_2ADDR: |
| 1598 | case Instruction::XOR_LONG_2ADDR: |
| 1599 | case Instruction::AND_LONG_2ADDR: |
| 1600 | if (rl_src2.is_const) { |
| 1601 | GenLongImm(rl_dest, rl_src2, opcode); |
| 1602 | } else { |
| 1603 | DCHECK(rl_src1.is_const); |
| 1604 | GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
| 1605 | } |
| 1606 | break; |
| 1607 | default: |
| 1608 | // Default - bail to non-const handler. |
| 1609 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1610 | break; |
| 1611 | } |
| 1612 | } |
| 1613 | |
| 1614 | bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { |
| 1615 | switch (op) { |
| 1616 | case Instruction::AND_LONG_2ADDR: |
| 1617 | case Instruction::AND_LONG: |
| 1618 | return value == -1; |
| 1619 | case Instruction::OR_LONG: |
| 1620 | case Instruction::OR_LONG_2ADDR: |
| 1621 | case Instruction::XOR_LONG: |
| 1622 | case Instruction::XOR_LONG_2ADDR: |
| 1623 | return value == 0; |
| 1624 | default: |
| 1625 | return false; |
| 1626 | } |
| 1627 | } |
| 1628 | |
| 1629 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 1630 | bool is_high_op) { |
| 1631 | bool rhs_in_mem = rhs.location != kLocPhysReg; |
| 1632 | bool dest_in_mem = dest.location != kLocPhysReg; |
| 1633 | DCHECK(!rhs_in_mem || !dest_in_mem); |
| 1634 | switch (op) { |
| 1635 | case Instruction::ADD_LONG: |
| 1636 | case Instruction::ADD_LONG_2ADDR: |
| 1637 | if (dest_in_mem) { |
| 1638 | return is_high_op ? kX86Adc32MR : kX86Add32MR; |
| 1639 | } else if (rhs_in_mem) { |
| 1640 | return is_high_op ? kX86Adc32RM : kX86Add32RM; |
| 1641 | } |
| 1642 | return is_high_op ? kX86Adc32RR : kX86Add32RR; |
| 1643 | case Instruction::SUB_LONG: |
| 1644 | case Instruction::SUB_LONG_2ADDR: |
| 1645 | if (dest_in_mem) { |
| 1646 | return is_high_op ? kX86Sbb32MR : kX86Sub32MR; |
| 1647 | } else if (rhs_in_mem) { |
| 1648 | return is_high_op ? kX86Sbb32RM : kX86Sub32RM; |
| 1649 | } |
| 1650 | return is_high_op ? kX86Sbb32RR : kX86Sub32RR; |
| 1651 | case Instruction::AND_LONG_2ADDR: |
| 1652 | case Instruction::AND_LONG: |
| 1653 | if (dest_in_mem) { |
| 1654 | return kX86And32MR; |
| 1655 | } |
| 1656 | return rhs_in_mem ? kX86And32RM : kX86And32RR; |
| 1657 | case Instruction::OR_LONG: |
| 1658 | case Instruction::OR_LONG_2ADDR: |
| 1659 | if (dest_in_mem) { |
| 1660 | return kX86Or32MR; |
| 1661 | } |
| 1662 | return rhs_in_mem ? kX86Or32RM : kX86Or32RR; |
| 1663 | case Instruction::XOR_LONG: |
| 1664 | case Instruction::XOR_LONG_2ADDR: |
| 1665 | if (dest_in_mem) { |
| 1666 | return kX86Xor32MR; |
| 1667 | } |
| 1668 | return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; |
| 1669 | default: |
| 1670 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 1671 | return kX86Add32RR; |
| 1672 | } |
| 1673 | } |
| 1674 | |
| 1675 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, |
| 1676 | int32_t value) { |
| 1677 | bool in_mem = loc.location != kLocPhysReg; |
| 1678 | bool byte_imm = IS_SIMM8(value); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1679 | DCHECK(in_mem || !loc.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1680 | switch (op) { |
| 1681 | case Instruction::ADD_LONG: |
| 1682 | case Instruction::ADD_LONG_2ADDR: |
| 1683 | if (byte_imm) { |
| 1684 | if (in_mem) { |
| 1685 | return is_high_op ? kX86Adc32MI8 : kX86Add32MI8; |
| 1686 | } |
| 1687 | return is_high_op ? kX86Adc32RI8 : kX86Add32RI8; |
| 1688 | } |
| 1689 | if (in_mem) { |
| 1690 | return is_high_op ? kX86Adc32MI : kX86Add32MI; |
| 1691 | } |
| 1692 | return is_high_op ? kX86Adc32RI : kX86Add32RI; |
| 1693 | case Instruction::SUB_LONG: |
| 1694 | case Instruction::SUB_LONG_2ADDR: |
| 1695 | if (byte_imm) { |
| 1696 | if (in_mem) { |
| 1697 | return is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; |
| 1698 | } |
| 1699 | return is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; |
| 1700 | } |
| 1701 | if (in_mem) { |
| 1702 | return is_high_op ? kX86Sbb32MI : kX86Sub32MI; |
| 1703 | } |
| 1704 | return is_high_op ? kX86Sbb32RI : kX86Sub32RI; |
| 1705 | case Instruction::AND_LONG_2ADDR: |
| 1706 | case Instruction::AND_LONG: |
| 1707 | if (byte_imm) { |
| 1708 | return in_mem ? kX86And32MI8 : kX86And32RI8; |
| 1709 | } |
| 1710 | return in_mem ? kX86And32MI : kX86And32RI; |
| 1711 | case Instruction::OR_LONG: |
| 1712 | case Instruction::OR_LONG_2ADDR: |
| 1713 | if (byte_imm) { |
| 1714 | return in_mem ? kX86Or32MI8 : kX86Or32RI8; |
| 1715 | } |
| 1716 | return in_mem ? kX86Or32MI : kX86Or32RI; |
| 1717 | case Instruction::XOR_LONG: |
| 1718 | case Instruction::XOR_LONG_2ADDR: |
| 1719 | if (byte_imm) { |
| 1720 | return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; |
| 1721 | } |
| 1722 | return in_mem ? kX86Xor32MI : kX86Xor32RI; |
| 1723 | default: |
| 1724 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 1725 | return kX86Add32MI; |
| 1726 | } |
| 1727 | } |
| 1728 | |
| 1729 | void X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
| 1730 | DCHECK(rl_src.is_const); |
| 1731 | int64_t val = mir_graph_->ConstantValueWide(rl_src); |
| 1732 | int32_t val_lo = Low32Bits(val); |
| 1733 | int32_t val_hi = High32Bits(val); |
| 1734 | rl_dest = UpdateLocWide(rl_dest); |
| 1735 | |
| 1736 | // Can we just do this into memory? |
| 1737 | if ((rl_dest.location == kLocDalvikFrame) || |
| 1738 | (rl_dest.location == kLocCompilerTemp)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1739 | int r_base = TargetReg(kSp).GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1740 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 1741 | |
| 1742 | if (!IsNoOp(op, val_lo)) { |
| 1743 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1744 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1745 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1746 | true /* is_load */, true /* is64bit */); |
| 1747 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1748 | false /* is_load */, true /* is64bit */); |
| 1749 | } |
| 1750 | if (!IsNoOp(op, val_hi)) { |
| 1751 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1752 | LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1753 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1754 | true /* is_load */, true /* is64bit */); |
| 1755 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1756 | false /* is_load */, true /* is64bit */); |
| 1757 | } |
| 1758 | return; |
| 1759 | } |
| 1760 | |
| 1761 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1762 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1763 | DCHECK(!rl_result.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1764 | |
| 1765 | if (!IsNoOp(op, val_lo)) { |
| 1766 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1767 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1768 | } |
| 1769 | if (!IsNoOp(op, val_hi)) { |
| 1770 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1771 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1772 | } |
| 1773 | StoreValueWide(rl_dest, rl_result); |
| 1774 | } |
| 1775 | |
| 1776 | void X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, |
| 1777 | RegLocation rl_src2, Instruction::Code op) { |
| 1778 | DCHECK(rl_src2.is_const); |
| 1779 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 1780 | int32_t val_lo = Low32Bits(val); |
| 1781 | int32_t val_hi = High32Bits(val); |
| 1782 | rl_dest = UpdateLocWide(rl_dest); |
| 1783 | rl_src1 = UpdateLocWide(rl_src1); |
| 1784 | |
| 1785 | // Can we do this directly into the destination registers? |
| 1786 | if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1787 | rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1788 | rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1789 | if (!IsNoOp(op, val_lo)) { |
| 1790 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1791 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1792 | } |
| 1793 | if (!IsNoOp(op, val_hi)) { |
| 1794 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1795 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1796 | } |
Maxim Kazantsev | 653f2bf | 2014-02-13 15:11:17 +0700 | [diff] [blame] | 1797 | |
| 1798 | StoreFinalValueWide(rl_dest, rl_dest); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1799 | return; |
| 1800 | } |
| 1801 | |
| 1802 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1803 | DCHECK_EQ(rl_src1.location, kLocPhysReg); |
| 1804 | |
| 1805 | // We need the values to be in a temporary |
| 1806 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 1807 | if (!IsNoOp(op, val_lo)) { |
| 1808 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1809 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1810 | } |
| 1811 | if (!IsNoOp(op, val_hi)) { |
| 1812 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1813 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1814 | } |
| 1815 | |
| 1816 | StoreFinalValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1817 | } |
| 1818 | |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1819 | // For final classes there are no sub-classes to check and so we can answer the instance-of |
| 1820 | // question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. |
| 1821 | void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, |
| 1822 | RegLocation rl_dest, RegLocation rl_src) { |
| 1823 | RegLocation object = LoadValue(rl_src, kCoreReg); |
| 1824 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1825 | RegStorage result_reg = rl_result.reg; |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1826 | |
| 1827 | // SETcc only works with EAX..EDX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1828 | if (result_reg == object.reg || result_reg.GetRegNum() >= rs_rX86_SP.GetRegNum()) { |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1829 | result_reg = AllocTypedTemp(false, kCoreReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1830 | DCHECK_LT(result_reg.GetRegNum(), rs_rX86_SP.GetRegNum()); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | // Assume that there is no match. |
| 1834 | LoadConstant(result_reg, 0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1835 | LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1836 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1837 | RegStorage check_class = AllocTypedTemp(false, kCoreReg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1838 | |
| 1839 | // If Method* is already in a register, we can save a copy. |
| 1840 | RegLocation rl_method = mir_graph_->GetMethodLoc(); |
| 1841 | int32_t offset_of_type = mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + |
| 1842 | (sizeof(mirror::Class*) * type_idx); |
| 1843 | |
| 1844 | if (rl_method.location == kLocPhysReg) { |
| 1845 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1846 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1847 | check_class); |
| 1848 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1849 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1850 | check_class); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1851 | LoadRefDisp(check_class, offset_of_type, check_class); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1852 | } |
| 1853 | } else { |
| 1854 | LoadCurrMethodDirect(check_class); |
| 1855 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1856 | LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1857 | check_class); |
| 1858 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1859 | LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1860 | check_class); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1861 | LoadRefDisp(check_class, offset_of_type, check_class); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1862 | } |
| 1863 | } |
| 1864 | |
| 1865 | // Compare the computed class to the class in the object. |
| 1866 | DCHECK_EQ(object.location, kLocPhysReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1867 | OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1868 | |
| 1869 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1870 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1871 | |
| 1872 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 1873 | null_branchover->target = target; |
| 1874 | FreeTemp(check_class); |
| 1875 | if (IsTemp(result_reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1876 | OpRegCopy(rl_result.reg, result_reg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 1877 | FreeTemp(result_reg); |
| 1878 | } |
| 1879 | StoreValue(rl_dest, rl_result); |
| 1880 | } |
| 1881 | |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1882 | void X86Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, |
| 1883 | bool type_known_abstract, bool use_declaring_class, |
| 1884 | bool can_assume_type_is_in_dex_cache, |
| 1885 | uint32_t type_idx, RegLocation rl_dest, |
| 1886 | RegLocation rl_src) { |
| 1887 | FlushAllRegs(); |
| 1888 | // May generate a call - use explicit registers. |
| 1889 | LockCallTemps(); |
| 1890 | LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 gets current Method*. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1891 | RegStorage class_reg = TargetReg(kArg2); // kArg2 will hold the Class*. |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1892 | // Reference must end up in kArg0. |
| 1893 | if (needs_access_check) { |
| 1894 | // Check we have access to type_idx and if not throw IllegalAccessError, |
| 1895 | // Caller function returns Class* in kArg0. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1896 | CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeTypeAndVerifyAccess), |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1897 | type_idx, true); |
| 1898 | OpRegCopy(class_reg, TargetReg(kRet0)); |
| 1899 | LoadValueDirectFixed(rl_src, TargetReg(kArg0)); |
| 1900 | } else if (use_declaring_class) { |
| 1901 | LoadValueDirectFixed(rl_src, TargetReg(kArg0)); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1902 | LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1903 | class_reg); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1904 | } else { |
| 1905 | // Load dex cache entry into class_reg (kArg2). |
| 1906 | LoadValueDirectFixed(rl_src, TargetReg(kArg0)); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1907 | LoadRefDisp(TargetReg(kArg1), mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1908 | class_reg); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1909 | int32_t offset_of_type = |
| 1910 | mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) |
| 1911 | * type_idx); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1912 | LoadRefDisp(class_reg, offset_of_type, class_reg); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1913 | if (!can_assume_type_is_in_dex_cache) { |
| 1914 | // Need to test presence of type in dex cache at runtime. |
| 1915 | LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); |
| 1916 | // Type is not resolved. Call out to helper, which will return resolved type in kRet0/kArg0. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1917 | CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(4, pInitializeType), type_idx, true); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1918 | OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path. |
| 1919 | LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* Reload Ref. */ |
| 1920 | // Rejoin code paths |
| 1921 | LIR* hop_target = NewLIR0(kPseudoTargetLabel); |
| 1922 | hop_branch->target = hop_target; |
| 1923 | } |
| 1924 | } |
| 1925 | /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result. */ |
| 1926 | RegLocation rl_result = GetReturn(false); |
| 1927 | |
| 1928 | // SETcc only works with EAX..EDX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1929 | DCHECK_LT(rl_result.reg.GetRegNum(), 4); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1930 | |
| 1931 | // Is the class NULL? |
| 1932 | LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); |
| 1933 | |
| 1934 | /* Load object->klass_. */ |
| 1935 | DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1936 | LoadRefDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1937 | /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class. */ |
| 1938 | LIR* branchover = nullptr; |
| 1939 | if (type_known_final) { |
| 1940 | // Ensure top 3 bytes of result are 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1941 | LoadConstant(rl_result.reg, 0); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1942 | OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); |
| 1943 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 1944 | NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondEq); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1945 | } else { |
| 1946 | if (!type_known_abstract) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1947 | LoadConstant(rl_result.reg, 1); // Assume result succeeds. |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1948 | branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); |
| 1949 | } |
| 1950 | OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1951 | OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(4, pInstanceofNonTrivial)); |
Mark Mendell | 6607d97 | 2014-02-10 06:54:18 -0800 | [diff] [blame] | 1952 | } |
| 1953 | // TODO: only clobber when type isn't final? |
| 1954 | ClobberCallerSave(); |
| 1955 | /* Branch targets here. */ |
| 1956 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 1957 | StoreValue(rl_dest, rl_result); |
| 1958 | branch1->target = target; |
| 1959 | if (branchover != nullptr) { |
| 1960 | branchover->target = target; |
| 1961 | } |
| 1962 | } |
| 1963 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 1964 | void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, |
| 1965 | RegLocation rl_lhs, RegLocation rl_rhs) { |
| 1966 | OpKind op = kOpBkpt; |
| 1967 | bool is_div_rem = false; |
| 1968 | bool unary = false; |
| 1969 | bool shift_op = false; |
| 1970 | bool is_two_addr = false; |
| 1971 | RegLocation rl_result; |
| 1972 | switch (opcode) { |
| 1973 | case Instruction::NEG_INT: |
| 1974 | op = kOpNeg; |
| 1975 | unary = true; |
| 1976 | break; |
| 1977 | case Instruction::NOT_INT: |
| 1978 | op = kOpMvn; |
| 1979 | unary = true; |
| 1980 | break; |
| 1981 | case Instruction::ADD_INT_2ADDR: |
| 1982 | is_two_addr = true; |
| 1983 | // Fallthrough |
| 1984 | case Instruction::ADD_INT: |
| 1985 | op = kOpAdd; |
| 1986 | break; |
| 1987 | case Instruction::SUB_INT_2ADDR: |
| 1988 | is_two_addr = true; |
| 1989 | // Fallthrough |
| 1990 | case Instruction::SUB_INT: |
| 1991 | op = kOpSub; |
| 1992 | break; |
| 1993 | case Instruction::MUL_INT_2ADDR: |
| 1994 | is_two_addr = true; |
| 1995 | // Fallthrough |
| 1996 | case Instruction::MUL_INT: |
| 1997 | op = kOpMul; |
| 1998 | break; |
| 1999 | case Instruction::DIV_INT_2ADDR: |
| 2000 | is_two_addr = true; |
| 2001 | // Fallthrough |
| 2002 | case Instruction::DIV_INT: |
| 2003 | op = kOpDiv; |
| 2004 | is_div_rem = true; |
| 2005 | break; |
| 2006 | /* NOTE: returns in kArg1 */ |
| 2007 | case Instruction::REM_INT_2ADDR: |
| 2008 | is_two_addr = true; |
| 2009 | // Fallthrough |
| 2010 | case Instruction::REM_INT: |
| 2011 | op = kOpRem; |
| 2012 | is_div_rem = true; |
| 2013 | break; |
| 2014 | case Instruction::AND_INT_2ADDR: |
| 2015 | is_two_addr = true; |
| 2016 | // Fallthrough |
| 2017 | case Instruction::AND_INT: |
| 2018 | op = kOpAnd; |
| 2019 | break; |
| 2020 | case Instruction::OR_INT_2ADDR: |
| 2021 | is_two_addr = true; |
| 2022 | // Fallthrough |
| 2023 | case Instruction::OR_INT: |
| 2024 | op = kOpOr; |
| 2025 | break; |
| 2026 | case Instruction::XOR_INT_2ADDR: |
| 2027 | is_two_addr = true; |
| 2028 | // Fallthrough |
| 2029 | case Instruction::XOR_INT: |
| 2030 | op = kOpXor; |
| 2031 | break; |
| 2032 | case Instruction::SHL_INT_2ADDR: |
| 2033 | is_two_addr = true; |
| 2034 | // Fallthrough |
| 2035 | case Instruction::SHL_INT: |
| 2036 | shift_op = true; |
| 2037 | op = kOpLsl; |
| 2038 | break; |
| 2039 | case Instruction::SHR_INT_2ADDR: |
| 2040 | is_two_addr = true; |
| 2041 | // Fallthrough |
| 2042 | case Instruction::SHR_INT: |
| 2043 | shift_op = true; |
| 2044 | op = kOpAsr; |
| 2045 | break; |
| 2046 | case Instruction::USHR_INT_2ADDR: |
| 2047 | is_two_addr = true; |
| 2048 | // Fallthrough |
| 2049 | case Instruction::USHR_INT: |
| 2050 | shift_op = true; |
| 2051 | op = kOpLsr; |
| 2052 | break; |
| 2053 | default: |
| 2054 | LOG(FATAL) << "Invalid word arith op: " << opcode; |
| 2055 | } |
| 2056 | |
| 2057 | // Can we convert to a two address instruction? |
| 2058 | if (!is_two_addr && |
| 2059 | (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 2060 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { |
| 2061 | is_two_addr = true; |
| 2062 | } |
| 2063 | |
| 2064 | // Get the div/rem stuff out of the way. |
| 2065 | if (is_div_rem) { |
| 2066 | rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, true); |
| 2067 | StoreValue(rl_dest, rl_result); |
| 2068 | return; |
| 2069 | } |
| 2070 | |
| 2071 | if (unary) { |
| 2072 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 2073 | rl_result = UpdateLoc(rl_dest); |
| 2074 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2075 | OpRegReg(op, rl_result.reg, rl_lhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2076 | } else { |
| 2077 | if (shift_op) { |
| 2078 | // X86 doesn't require masking and must use ECX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2079 | RegStorage t_reg = TargetReg(kCount); // rCX |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2080 | LoadValueDirectFixed(rl_rhs, t_reg); |
| 2081 | if (is_two_addr) { |
| 2082 | // Can we do this directly into memory? |
| 2083 | rl_result = UpdateLoc(rl_dest); |
| 2084 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 2085 | if (rl_result.location != kLocPhysReg) { |
| 2086 | // Okay, we can do this into memory |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2087 | OpMemReg(op, rl_result, t_reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2088 | FreeTemp(t_reg); |
| 2089 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2090 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2091 | // Can do this directly into the result register |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2092 | OpRegReg(op, rl_result.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2093 | FreeTemp(t_reg); |
| 2094 | StoreFinalValue(rl_dest, rl_result); |
| 2095 | return; |
| 2096 | } |
| 2097 | } |
| 2098 | // Three address form, or we can't do directly. |
| 2099 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 2100 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2101 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2102 | FreeTemp(t_reg); |
| 2103 | } else { |
| 2104 | // Multiply is 3 operand only (sort of). |
| 2105 | if (is_two_addr && op != kOpMul) { |
| 2106 | // Can we do this directly into memory? |
| 2107 | rl_result = UpdateLoc(rl_dest); |
| 2108 | if (rl_result.location == kLocPhysReg) { |
Serguei Katkov | 366f8ae | 2014-04-15 16:55:26 +0700 | [diff] [blame] | 2109 | // Ensure res is in a core reg |
| 2110 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2111 | // Can we do this from memory directly? |
| 2112 | rl_rhs = UpdateLoc(rl_rhs); |
| 2113 | if (rl_rhs.location != kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2114 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2115 | StoreFinalValue(rl_dest, rl_result); |
| 2116 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2117 | } else if (!rl_rhs.reg.IsFloat()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2118 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2119 | StoreFinalValue(rl_dest, rl_result); |
| 2120 | return; |
| 2121 | } |
| 2122 | } |
| 2123 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 2124 | if (rl_result.location != kLocPhysReg) { |
| 2125 | // Okay, we can do this into memory. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2126 | OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2127 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2128 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2129 | // Can do this directly into the result register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2130 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2131 | StoreFinalValue(rl_dest, rl_result); |
| 2132 | return; |
| 2133 | } else { |
| 2134 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 2135 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2136 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2137 | } |
| 2138 | } else { |
| 2139 | // Try to use reg/memory instructions. |
| 2140 | rl_lhs = UpdateLoc(rl_lhs); |
| 2141 | rl_rhs = UpdateLoc(rl_rhs); |
| 2142 | // We can't optimize with FP registers. |
| 2143 | if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { |
| 2144 | // Something is difficult, so fall back to the standard case. |
| 2145 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 2146 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 2147 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2148 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2149 | } else { |
| 2150 | // We can optimize by moving to result and using memory operands. |
| 2151 | if (rl_rhs.location != kLocPhysReg) { |
| 2152 | // Force LHS into result. |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 2153 | // We should be careful with order here |
| 2154 | // If rl_dest and rl_lhs points to the same VR we should load first |
| 2155 | // If the are different we should find a register first for dest |
| 2156 | if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { |
| 2157 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 2158 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 2159 | } else { |
| 2160 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2161 | LoadValueDirect(rl_lhs, rl_result.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 2162 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2163 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2164 | } else if (rl_lhs.location != kLocPhysReg) { |
| 2165 | // RHS is in a register; LHS is in memory. |
| 2166 | if (op != kOpSub) { |
| 2167 | // Force RHS into result and operate on memory. |
| 2168 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2169 | OpRegCopy(rl_result.reg, rl_rhs.reg); |
| 2170 | OpRegMem(op, rl_result.reg, rl_lhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2171 | } else { |
| 2172 | // Subtraction isn't commutative. |
| 2173 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 2174 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 2175 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2176 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2177 | } |
| 2178 | } else { |
| 2179 | // Both are in registers. |
| 2180 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 2181 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 2182 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2183 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2184 | } |
| 2185 | } |
| 2186 | } |
| 2187 | } |
| 2188 | } |
| 2189 | StoreValue(rl_dest, rl_result); |
| 2190 | } |
| 2191 | |
| 2192 | bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { |
| 2193 | // If we have non-core registers, then we can't do good things. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2194 | if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2195 | return false; |
| 2196 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2197 | if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2198 | return false; |
| 2199 | } |
| 2200 | |
| 2201 | // Everything will be fine :-). |
| 2202 | return true; |
| 2203 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2204 | } // namespace art |