Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_DEX_QUICK_X86_X86_LIR_H_ |
| 18 | #define ART_COMPILER_DEX_QUICK_X86_X86_LIR_H_ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 19 | |
| 20 | #include "dex/compiler_internals.h" |
| 21 | |
| 22 | namespace art { |
| 23 | |
| 24 | /* |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 25 | * Runtime register conventions. We consider both x86, x86-64 and x32 (32bit mode x86-64). The ABI |
| 26 | * has different conventions and we capture those here. Changing something that is callee save and |
| 27 | * making it caller save places a burden on up-calls to save/restore the callee save register, |
| 28 | * however, there are few registers that are callee save in the ABI. Changing something that is |
| 29 | * caller save and making it callee save places a burden on down-calls to save/restore the callee |
| 30 | * save register. For these reasons we aim to match native conventions for caller and callee save. |
| 31 | * On x86 only the first 4 registers can be used for byte operations, for this reason they are |
| 32 | * preferred for temporary scratch registers. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 33 | * |
| 34 | * General Purpose Register: |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 35 | * Native: x86 | x86-64 / x32 | ART x86 | ART x86-64 |
| 36 | * r0/eax: caller | caller | caller, Method*, scratch, return value | caller, scratch, return value |
| 37 | * r1/ecx: caller | caller, arg4 | caller, arg1, scratch | caller, arg3, scratch |
| 38 | * r2/edx: caller | caller, arg3 | caller, arg2, scratch, high half of long return | caller, arg2, scratch |
| 39 | * r3/ebx: callEE | callEE | callER, arg3, scratch | callee, promotable |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 40 | * r4/esp: stack pointer |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 41 | * r5/ebp: callee | callee | callee, promotable | callee, promotable |
| 42 | * r6/esi: callEE | callER, arg2 | callee, promotable | caller, arg1, scratch |
| 43 | * r7/edi: callEE | callER, arg1 | callee, promotable | caller, Method*, scratch |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 44 | * --- x86-64/x32 registers |
| 45 | * Native: x86-64 / x32 | ART |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 46 | * r8: caller save, arg5 | caller, arg4, scratch |
| 47 | * r9: caller save, arg6 | caller, arg5, scratch |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 48 | * r10: caller save | caller, scratch |
| 49 | * r11: caller save | caller, scratch |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 50 | * r12: callee save | callee, available for register promotion (promotable) |
| 51 | * r13: callee save | callee, available for register promotion (promotable) |
| 52 | * r14: callee save | callee, available for register promotion (promotable) |
| 53 | * r15: callee save | callee, available for register promotion (promotable) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 54 | * |
| 55 | * There is no rSELF, instead on x86 fs: has a base address of Thread::Current, whereas on |
| 56 | * x86-64/x32 gs: holds it. |
| 57 | * |
| 58 | * For floating point we don't support CPUs without SSE2 support (ie newer than PIII): |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 59 | * Native: x86 | x86-64 / x32 | ART x86 | ART x86-64 |
| 60 | * XMM0: caller | caller, arg1 | caller, float return value | caller, arg1, float return value |
| 61 | * XMM1: caller | caller, arg2 | caller, scratch | caller, arg2, scratch |
| 62 | * XMM2: caller | caller, arg3 | caller, scratch | caller, arg3, scratch |
| 63 | * XMM3: caller | caller, arg4 | caller, scratch | caller, arg4, scratch |
| 64 | * XMM4: caller | caller, arg5 | caller, scratch | caller, arg5, scratch |
| 65 | * XMM5: caller | caller, arg6 | caller, scratch | caller, arg6, scratch |
| 66 | * XMM6: caller | caller, arg7 | caller, scratch | caller, arg7, scratch |
| 67 | * XMM7: caller | caller, arg8 | caller, scratch | caller, arg8, scratch |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 68 | * --- x86-64/x32 registers |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 69 | * XMM8 .. 15: caller save available as scratch registers for ART. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 70 | * |
Ian Rogers | 0177e53 | 2014-02-11 16:30:46 -0800 | [diff] [blame] | 71 | * X87 is a necessary evil outside of ART code for x86: |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 72 | * ST0: x86 float/double native return value, caller save |
| 73 | * ST1 .. ST7: caller save |
| 74 | * |
| 75 | * Stack frame diagram (stack grows down, higher addresses at top): |
| 76 | * |
| 77 | * +------------------------+ |
| 78 | * | IN[ins-1] | {Note: resides in caller's frame} |
| 79 | * | . | |
| 80 | * | IN[0] | |
| 81 | * | caller's Method* | |
| 82 | * +========================+ {Note: start of callee's frame} |
| 83 | * | return address | {pushed by call} |
| 84 | * | spill region | {variable sized} |
| 85 | * +------------------------+ |
| 86 | * | ...filler word... | {Note: used as 2nd word of V[locals-1] if long] |
| 87 | * +------------------------+ |
| 88 | * | V[locals-1] | |
| 89 | * | V[locals-2] | |
| 90 | * | . | |
| 91 | * | . | |
| 92 | * | V[1] | |
| 93 | * | V[0] | |
| 94 | * +------------------------+ |
| 95 | * | 0 to 3 words padding | |
| 96 | * +------------------------+ |
| 97 | * | OUT[outs-1] | |
| 98 | * | OUT[outs-2] | |
| 99 | * | . | |
| 100 | * | OUT[0] | |
| 101 | * | cur_method* | <<== sp w/ 16-byte alignment |
| 102 | * +========================+ |
| 103 | */ |
| 104 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 105 | enum X86ResourceEncodingPos { |
| 106 | kX86GPReg0 = 0, |
| 107 | kX86RegSP = 4, |
| 108 | kX86FPReg0 = 16, // xmm0 .. xmm7/xmm15. |
Serguei Katkov | e90501d | 2014-03-12 15:56:54 +0700 | [diff] [blame] | 109 | kX86FPRegEnd = 32, |
| 110 | kX86FPStack = 33, |
| 111 | kX86RegEnd = kX86FPStack, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 112 | }; |
| 113 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 114 | #define ENCODE_X86_REG_SP (1ULL << kX86RegSP) |
Serguei Katkov | e90501d | 2014-03-12 15:56:54 +0700 | [diff] [blame] | 115 | #define ENCODE_X86_FP_STACK (1ULL << kX86FPStack) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 116 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 117 | // FIXME: for 64-bit, perhaps add an X86_64NativeRegisterPool enum? |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 118 | enum X86NativeRegisterPool { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 119 | r0 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 0, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 120 | r0q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 0, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 121 | rAX = r0, |
| 122 | r1 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 1, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 123 | r1q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 1, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 124 | rCX = r1, |
| 125 | r2 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 2, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 126 | r2q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 2, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 127 | rDX = r2, |
| 128 | r3 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 3, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 129 | r3q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 3, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 130 | rBX = r3, |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 131 | r4sp_32 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 4, |
| 132 | rX86_SP_32 = r4sp_32, |
| 133 | r4sp_64 = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 4, |
| 134 | rX86_SP_64 = r4sp_64, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 135 | r5 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 5, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 136 | r5q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 5, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 137 | rBP = r5, |
| 138 | r5sib_no_base = r5, |
| 139 | r6 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 6, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 140 | r6q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 6, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 141 | rSI = r6, |
| 142 | r7 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 7, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 143 | r7q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 7, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 144 | rDI = r7, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 145 | #ifndef TARGET_REX_SUPPORT |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 146 | // fake return address register for core spill mask. |
| 147 | rRET = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 8, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 148 | #else |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 149 | r8 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 8, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 150 | r8q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 8, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 151 | r9 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 9, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 152 | r9q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 9, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 153 | r10 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 10, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 154 | r10q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 10, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 155 | r11 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 11, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 156 | r11q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 11, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 157 | r12 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 12, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 158 | r12q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 12, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 159 | r13 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 13, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 160 | r13q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 13, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 161 | r14 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 14, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 162 | r14q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 14, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 163 | r15 = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 15, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 164 | r15q = RegStorage::k64BitSolo | RegStorage::kCoreRegister | 15, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 165 | // fake return address register for core spill mask. |
| 166 | rRET = RegStorage::k32BitSolo | RegStorage::kCoreRegister | 16, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 167 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 168 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 169 | // xmm registers, single precision view. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 170 | fr0 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 0, |
| 171 | fr1 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 1, |
| 172 | fr2 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 2, |
| 173 | fr3 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 3, |
| 174 | fr4 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 4, |
| 175 | fr5 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 5, |
| 176 | fr6 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 6, |
| 177 | fr7 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 7, |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 178 | #ifdef TARGET_REX_SUPPORT |
| 179 | fr8 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 8, |
| 180 | fr9 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 9, |
| 181 | fr10 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 10, |
| 182 | fr11 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 11, |
| 183 | fr12 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 12, |
| 184 | fr13 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 13, |
| 185 | fr14 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 14, |
| 186 | fr15 = RegStorage::k32BitSolo | RegStorage::kFloatingPoint | 15, |
| 187 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 188 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 189 | // xmm registers, double precision aliases. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 190 | dr0 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 0, |
| 191 | dr1 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 1, |
| 192 | dr2 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 2, |
| 193 | dr3 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 3, |
| 194 | dr4 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 4, |
| 195 | dr5 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 5, |
| 196 | dr6 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 6, |
| 197 | dr7 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 7, |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 198 | #ifdef TARGET_REX_SUPPORT |
| 199 | dr8 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 8, |
| 200 | dr9 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 9, |
| 201 | dr10 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 10, |
| 202 | dr11 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 11, |
| 203 | dr12 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 12, |
| 204 | dr13 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 13, |
| 205 | dr14 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 14, |
| 206 | dr15 = RegStorage::k64BitSolo | RegStorage::kFloatingPoint | 15, |
| 207 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 208 | |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 209 | // xmm registers, quad precision aliases |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 210 | xr0 = RegStorage::k128BitSolo | 0, |
| 211 | xr1 = RegStorage::k128BitSolo | 1, |
| 212 | xr2 = RegStorage::k128BitSolo | 2, |
| 213 | xr3 = RegStorage::k128BitSolo | 3, |
| 214 | xr4 = RegStorage::k128BitSolo | 4, |
| 215 | xr5 = RegStorage::k128BitSolo | 5, |
| 216 | xr6 = RegStorage::k128BitSolo | 6, |
| 217 | xr7 = RegStorage::k128BitSolo | 7, |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 218 | #ifdef TARGET_REX_SUPPORT |
| 219 | xr8 = RegStorage::k128BitSolo | 8, |
| 220 | xr9 = RegStorage::k128BitSolo | 9, |
| 221 | xr10 = RegStorage::k128BitSolo | 10, |
| 222 | xr11 = RegStorage::k128BitSolo | 11, |
| 223 | xr12 = RegStorage::k128BitSolo | 12, |
| 224 | xr13 = RegStorage::k128BitSolo | 13, |
| 225 | xr14 = RegStorage::k128BitSolo | 14, |
| 226 | xr15 = RegStorage::k128BitSolo | 15, |
| 227 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 228 | |
| 229 | // TODO: as needed, add 256, 512 and 1024-bit xmm views. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 230 | }; |
| 231 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 232 | constexpr RegStorage rs_r0(RegStorage::kValid | r0); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 233 | constexpr RegStorage rs_r0q(RegStorage::kValid | r0q); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 234 | constexpr RegStorage rs_rAX = rs_r0; |
| 235 | constexpr RegStorage rs_r1(RegStorage::kValid | r1); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 236 | constexpr RegStorage rs_r1q(RegStorage::kValid | r1q); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 237 | constexpr RegStorage rs_rCX = rs_r1; |
| 238 | constexpr RegStorage rs_r2(RegStorage::kValid | r2); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 239 | constexpr RegStorage rs_r2q(RegStorage::kValid | r2q); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 240 | constexpr RegStorage rs_rDX = rs_r2; |
| 241 | constexpr RegStorage rs_r3(RegStorage::kValid | r3); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 242 | constexpr RegStorage rs_r3q(RegStorage::kValid | r3q); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 243 | constexpr RegStorage rs_rBX = rs_r3; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 244 | constexpr RegStorage rs_rX86_SP_64(RegStorage::kValid | r4sp_64); |
| 245 | constexpr RegStorage rs_rX86_SP_32(RegStorage::kValid | r4sp_32); |
| 246 | extern RegStorage rs_rX86_SP; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 247 | constexpr RegStorage rs_r5(RegStorage::kValid | r5); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 248 | constexpr RegStorage rs_r5q(RegStorage::kValid | r5q); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 249 | constexpr RegStorage rs_rBP = rs_r5; |
| 250 | constexpr RegStorage rs_r6(RegStorage::kValid | r6); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 251 | constexpr RegStorage rs_r6q(RegStorage::kValid | r6q); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 252 | constexpr RegStorage rs_rSI = rs_r6; |
| 253 | constexpr RegStorage rs_r7(RegStorage::kValid | r7); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 254 | constexpr RegStorage rs_r7q(RegStorage::kValid | r7q); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 255 | constexpr RegStorage rs_rDI = rs_r7; |
| 256 | constexpr RegStorage rs_rRET(RegStorage::kValid | rRET); |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 257 | #ifdef TARGET_REX_SUPPORT |
| 258 | constexpr RegStorage rs_r8(RegStorage::kValid | r8); |
| 259 | constexpr RegStorage rs_r8q(RegStorage::kValid | r8q); |
| 260 | constexpr RegStorage rs_r9(RegStorage::kValid | r9); |
| 261 | constexpr RegStorage rs_r9q(RegStorage::kValid | r9q); |
| 262 | constexpr RegStorage rs_r10(RegStorage::kValid | r10); |
| 263 | constexpr RegStorage rs_r10q(RegStorage::kValid | r10q); |
| 264 | constexpr RegStorage rs_r11(RegStorage::kValid | r11); |
| 265 | constexpr RegStorage rs_r11q(RegStorage::kValid | r11q); |
| 266 | constexpr RegStorage rs_r12(RegStorage::kValid | r12); |
| 267 | constexpr RegStorage rs_r12q(RegStorage::kValid | r12q); |
| 268 | constexpr RegStorage rs_r13(RegStorage::kValid | r13); |
| 269 | constexpr RegStorage rs_r13q(RegStorage::kValid | r13q); |
| 270 | constexpr RegStorage rs_r14(RegStorage::kValid | r14); |
| 271 | constexpr RegStorage rs_r14q(RegStorage::kValid | r14q); |
| 272 | constexpr RegStorage rs_r15(RegStorage::kValid | r15); |
| 273 | constexpr RegStorage rs_r15q(RegStorage::kValid | r15q); |
| 274 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 275 | |
| 276 | constexpr RegStorage rs_fr0(RegStorage::kValid | fr0); |
| 277 | constexpr RegStorage rs_fr1(RegStorage::kValid | fr1); |
| 278 | constexpr RegStorage rs_fr2(RegStorage::kValid | fr2); |
| 279 | constexpr RegStorage rs_fr3(RegStorage::kValid | fr3); |
| 280 | constexpr RegStorage rs_fr4(RegStorage::kValid | fr4); |
| 281 | constexpr RegStorage rs_fr5(RegStorage::kValid | fr5); |
| 282 | constexpr RegStorage rs_fr6(RegStorage::kValid | fr6); |
| 283 | constexpr RegStorage rs_fr7(RegStorage::kValid | fr7); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 284 | #ifdef TARGET_REX_SUPPORT |
| 285 | constexpr RegStorage rs_fr8(RegStorage::kValid | fr8); |
| 286 | constexpr RegStorage rs_fr9(RegStorage::kValid | fr9); |
| 287 | constexpr RegStorage rs_fr10(RegStorage::kValid | fr10); |
| 288 | constexpr RegStorage rs_fr11(RegStorage::kValid | fr11); |
| 289 | constexpr RegStorage rs_fr12(RegStorage::kValid | fr12); |
| 290 | constexpr RegStorage rs_fr13(RegStorage::kValid | fr13); |
| 291 | constexpr RegStorage rs_fr14(RegStorage::kValid | fr14); |
| 292 | constexpr RegStorage rs_fr15(RegStorage::kValid | fr15); |
| 293 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 294 | |
| 295 | constexpr RegStorage rs_dr0(RegStorage::kValid | dr0); |
| 296 | constexpr RegStorage rs_dr1(RegStorage::kValid | dr1); |
| 297 | constexpr RegStorage rs_dr2(RegStorage::kValid | dr2); |
| 298 | constexpr RegStorage rs_dr3(RegStorage::kValid | dr3); |
| 299 | constexpr RegStorage rs_dr4(RegStorage::kValid | dr4); |
| 300 | constexpr RegStorage rs_dr5(RegStorage::kValid | dr5); |
| 301 | constexpr RegStorage rs_dr6(RegStorage::kValid | dr6); |
| 302 | constexpr RegStorage rs_dr7(RegStorage::kValid | dr7); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 303 | #ifdef TARGET_REX_SUPPORT |
| 304 | constexpr RegStorage rs_dr8(RegStorage::kValid | dr8); |
| 305 | constexpr RegStorage rs_dr9(RegStorage::kValid | dr9); |
| 306 | constexpr RegStorage rs_dr10(RegStorage::kValid | dr10); |
| 307 | constexpr RegStorage rs_dr11(RegStorage::kValid | dr11); |
| 308 | constexpr RegStorage rs_dr12(RegStorage::kValid | dr12); |
| 309 | constexpr RegStorage rs_dr13(RegStorage::kValid | dr13); |
| 310 | constexpr RegStorage rs_dr14(RegStorage::kValid | dr14); |
| 311 | constexpr RegStorage rs_dr15(RegStorage::kValid | dr15); |
| 312 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 313 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 314 | constexpr RegStorage rs_xr0(RegStorage::kValid | xr0); |
| 315 | constexpr RegStorage rs_xr1(RegStorage::kValid | xr1); |
| 316 | constexpr RegStorage rs_xr2(RegStorage::kValid | xr2); |
| 317 | constexpr RegStorage rs_xr3(RegStorage::kValid | xr3); |
| 318 | constexpr RegStorage rs_xr4(RegStorage::kValid | xr4); |
| 319 | constexpr RegStorage rs_xr5(RegStorage::kValid | xr5); |
| 320 | constexpr RegStorage rs_xr6(RegStorage::kValid | xr6); |
| 321 | constexpr RegStorage rs_xr7(RegStorage::kValid | xr7); |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 322 | #ifdef TARGET_REX_SUPPORT |
| 323 | constexpr RegStorage rs_xr8(RegStorage::kValid | xr8); |
| 324 | constexpr RegStorage rs_xr9(RegStorage::kValid | xr9); |
| 325 | constexpr RegStorage rs_xr10(RegStorage::kValid | xr10); |
| 326 | constexpr RegStorage rs_xr11(RegStorage::kValid | xr11); |
| 327 | constexpr RegStorage rs_xr12(RegStorage::kValid | xr12); |
| 328 | constexpr RegStorage rs_xr13(RegStorage::kValid | xr13); |
| 329 | constexpr RegStorage rs_xr14(RegStorage::kValid | xr14); |
| 330 | constexpr RegStorage rs_xr15(RegStorage::kValid | xr15); |
| 331 | #endif |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 332 | |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 333 | extern X86NativeRegisterPool rX86_ARG0; |
| 334 | extern X86NativeRegisterPool rX86_ARG1; |
| 335 | extern X86NativeRegisterPool rX86_ARG2; |
| 336 | extern X86NativeRegisterPool rX86_ARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 337 | #ifdef TARGET_REX_SUPPORT |
| 338 | extern X86NativeRegisterPool rX86_ARG4; |
| 339 | extern X86NativeRegisterPool rX86_ARG5; |
| 340 | #endif |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 341 | extern X86NativeRegisterPool rX86_FARG0; |
| 342 | extern X86NativeRegisterPool rX86_FARG1; |
| 343 | extern X86NativeRegisterPool rX86_FARG2; |
| 344 | extern X86NativeRegisterPool rX86_FARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 345 | extern X86NativeRegisterPool rX86_FARG4; |
| 346 | extern X86NativeRegisterPool rX86_FARG5; |
| 347 | extern X86NativeRegisterPool rX86_FARG6; |
| 348 | extern X86NativeRegisterPool rX86_FARG7; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 349 | extern X86NativeRegisterPool rX86_RET0; |
| 350 | extern X86NativeRegisterPool rX86_RET1; |
| 351 | extern X86NativeRegisterPool rX86_INVOKE_TGT; |
| 352 | extern X86NativeRegisterPool rX86_COUNT; |
| 353 | |
| 354 | extern RegStorage rs_rX86_ARG0; |
| 355 | extern RegStorage rs_rX86_ARG1; |
| 356 | extern RegStorage rs_rX86_ARG2; |
| 357 | extern RegStorage rs_rX86_ARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 358 | extern RegStorage rs_rX86_ARG4; |
| 359 | extern RegStorage rs_rX86_ARG5; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 360 | extern RegStorage rs_rX86_FARG0; |
| 361 | extern RegStorage rs_rX86_FARG1; |
| 362 | extern RegStorage rs_rX86_FARG2; |
| 363 | extern RegStorage rs_rX86_FARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 364 | extern RegStorage rs_rX86_FARG4; |
| 365 | extern RegStorage rs_rX86_FARG5; |
| 366 | extern RegStorage rs_rX86_FARG6; |
| 367 | extern RegStorage rs_rX86_FARG7; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 368 | extern RegStorage rs_rX86_RET0; |
| 369 | extern RegStorage rs_rX86_RET1; |
| 370 | extern RegStorage rs_rX86_INVOKE_TGT; |
| 371 | extern RegStorage rs_rX86_COUNT; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 372 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 373 | // RegisterLocation templates return values (r_V0, or r_V0/r_V1). |
| 374 | const RegLocation x86_loc_c_return |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 375 | {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 376 | RegStorage(RegStorage::k32BitSolo, rAX), INVALID_SREG, INVALID_SREG}; |
| 377 | const RegLocation x86_loc_c_return_wide |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 378 | {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 379 | RegStorage(RegStorage::k64BitPair, rAX, rDX), INVALID_SREG, INVALID_SREG}; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 380 | const RegLocation x86_loc_c_return_float |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 381 | {kLocPhysReg, 0, 0, 0, 1, 0, 0, 0, 1, |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 382 | RegStorage(RegStorage::k32BitSolo, fr0), INVALID_SREG, INVALID_SREG}; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 383 | const RegLocation x86_loc_c_return_double |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 384 | {kLocPhysReg, 1, 0, 0, 1, 0, 0, 0, 1, |
| 385 | RegStorage(RegStorage::k64BitSolo, dr0), INVALID_SREG, INVALID_SREG}; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 386 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 387 | /* |
| 388 | * The following enum defines the list of supported X86 instructions by the |
| 389 | * assembler. Their corresponding EncodingMap positions will be defined in |
| 390 | * Assemble.cc. |
| 391 | */ |
| 392 | enum X86OpCode { |
| 393 | kX86First = 0, |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 394 | kX8632BitData = kX86First, // data [31..0]. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 395 | kX86Bkpt, |
| 396 | kX86Nop, |
| 397 | // Define groups of binary operations |
| 398 | // MR - Memory Register - opcode [base + disp], reg |
| 399 | // - lir operands - 0: base, 1: disp, 2: reg |
| 400 | // AR - Array Register - opcode [base + index * scale + disp], reg |
| 401 | // - lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg |
| 402 | // TR - Thread Register - opcode fs:[disp], reg - where fs: is equal to Thread::Current() |
| 403 | // - lir operands - 0: disp, 1: reg |
| 404 | // RR - Register Register - opcode reg1, reg2 |
| 405 | // - lir operands - 0: reg1, 1: reg2 |
| 406 | // RM - Register Memory - opcode reg, [base + disp] |
| 407 | // - lir operands - 0: reg, 1: base, 2: disp |
| 408 | // RA - Register Array - opcode reg, [base + index * scale + disp] |
| 409 | // - lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp |
| 410 | // RT - Register Thread - opcode reg, fs:[disp] - where fs: is equal to Thread::Current() |
| 411 | // - lir operands - 0: reg, 1: disp |
| 412 | // RI - Register Immediate - opcode reg, #immediate |
| 413 | // - lir operands - 0: reg, 1: immediate |
| 414 | // MI - Memory Immediate - opcode [base + disp], #immediate |
| 415 | // - lir operands - 0: base, 1: disp, 2: immediate |
| 416 | // AI - Array Immediate - opcode [base + index * scale + disp], #immediate |
| 417 | // - lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate |
Vladimir Marko | e6ed00b | 2013-10-24 14:52:37 +0100 | [diff] [blame] | 418 | // TI - Thread Immediate - opcode fs:[disp], imm - where fs: is equal to Thread::Current() |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 419 | // - lir operands - 0: disp, 1: imm |
| 420 | #define BinaryOpCode(opcode) \ |
| 421 | opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \ |
| 422 | opcode ## 8RR, opcode ## 8RM, opcode ## 8RA, opcode ## 8RT, \ |
| 423 | opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, opcode ## 8TI, \ |
| 424 | opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \ |
| 425 | opcode ## 16RR, opcode ## 16RM, opcode ## 16RA, opcode ## 16RT, \ |
| 426 | opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, opcode ## 16TI, \ |
| 427 | opcode ## 16RI8, opcode ## 16MI8, opcode ## 16AI8, opcode ## 16TI8, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 428 | opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \ |
| 429 | opcode ## 32RR, opcode ## 32RM, opcode ## 32RA, opcode ## 32RT, \ |
| 430 | opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, opcode ## 32TI, \ |
| 431 | opcode ## 32RI8, opcode ## 32MI8, opcode ## 32AI8, opcode ## 32TI8, \ |
| 432 | opcode ## 64MR, opcode ## 64AR, opcode ## 64TR, \ |
| 433 | opcode ## 64RR, opcode ## 64RM, opcode ## 64RA, opcode ## 64RT, \ |
| 434 | opcode ## 64RI, opcode ## 64MI, opcode ## 64AI, opcode ## 64TI, \ |
| 435 | opcode ## 64RI8, opcode ## 64MI8, opcode ## 64AI8, opcode ## 64TI8 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 436 | BinaryOpCode(kX86Add), |
| 437 | BinaryOpCode(kX86Or), |
| 438 | BinaryOpCode(kX86Adc), |
| 439 | BinaryOpCode(kX86Sbb), |
| 440 | BinaryOpCode(kX86And), |
| 441 | BinaryOpCode(kX86Sub), |
| 442 | BinaryOpCode(kX86Xor), |
| 443 | BinaryOpCode(kX86Cmp), |
| 444 | #undef BinaryOpCode |
| 445 | kX86Imul16RRI, kX86Imul16RMI, kX86Imul16RAI, |
| 446 | kX86Imul32RRI, kX86Imul32RMI, kX86Imul32RAI, |
| 447 | kX86Imul32RRI8, kX86Imul32RMI8, kX86Imul32RAI8, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 448 | kX86Imul64RRI, kX86Imul64RMI, kX86Imul64RAI, |
| 449 | kX86Imul64RRI8, kX86Imul64RMI8, kX86Imul64RAI8, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 450 | kX86Mov8MR, kX86Mov8AR, kX86Mov8TR, |
| 451 | kX86Mov8RR, kX86Mov8RM, kX86Mov8RA, kX86Mov8RT, |
| 452 | kX86Mov8RI, kX86Mov8MI, kX86Mov8AI, kX86Mov8TI, |
| 453 | kX86Mov16MR, kX86Mov16AR, kX86Mov16TR, |
| 454 | kX86Mov16RR, kX86Mov16RM, kX86Mov16RA, kX86Mov16RT, |
| 455 | kX86Mov16RI, kX86Mov16MI, kX86Mov16AI, kX86Mov16TI, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 456 | kX86Mov32MR, kX86Mov32AR, kX86Mov32TR, |
| 457 | kX86Mov32RR, kX86Mov32RM, kX86Mov32RA, kX86Mov32RT, |
| 458 | kX86Mov32RI, kX86Mov32MI, kX86Mov32AI, kX86Mov32TI, |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 459 | kX86Lea32RM, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 460 | kX86Lea32RA, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 461 | kX86Mov64MR, kX86Mov64AR, kX86Mov64TR, |
| 462 | kX86Mov64RR, kX86Mov64RM, kX86Mov64RA, kX86Mov64RT, |
| 463 | kX86Mov64RI, kX86Mov64MI, kX86Mov64AI, kX86Mov64TI, |
| 464 | kX86Lea64RM, |
| 465 | kX86Lea64RA, |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 466 | // RRC - Register Register ConditionCode - cond_opcode reg1, reg2 |
| 467 | // - lir operands - 0: reg1, 1: reg2, 2: CC |
| 468 | kX86Cmov32RRC, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 469 | kX86Cmov64RRC, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 470 | // RMC - Register Memory ConditionCode - cond_opcode reg1, [base + disp] |
| 471 | // - lir operands - 0: reg1, 1: base, 2: disp 3: CC |
| 472 | kX86Cmov32RMC, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 473 | kX86Cmov64RMC, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 474 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 475 | // RC - Register CL - opcode reg, CL |
| 476 | // - lir operands - 0: reg, 1: CL |
| 477 | // MC - Memory CL - opcode [base + disp], CL |
| 478 | // - lir operands - 0: base, 1: disp, 2: CL |
| 479 | // AC - Array CL - opcode [base + index * scale + disp], CL |
| 480 | // - lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: CL |
| 481 | #define BinaryShiftOpCode(opcode) \ |
| 482 | opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, \ |
| 483 | opcode ## 8RC, opcode ## 8MC, opcode ## 8AC, \ |
| 484 | opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, \ |
| 485 | opcode ## 16RC, opcode ## 16MC, opcode ## 16AC, \ |
| 486 | opcode ## 32RI, opcode ## 32MI, opcode ## 32AI, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 487 | opcode ## 32RC, opcode ## 32MC, opcode ## 32AC, \ |
| 488 | opcode ## 64RI, opcode ## 64MI, opcode ## 64AI, \ |
| 489 | opcode ## 64RC, opcode ## 64MC, opcode ## 64AC |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 490 | BinaryShiftOpCode(kX86Rol), |
| 491 | BinaryShiftOpCode(kX86Ror), |
| 492 | BinaryShiftOpCode(kX86Rcl), |
| 493 | BinaryShiftOpCode(kX86Rcr), |
| 494 | BinaryShiftOpCode(kX86Sal), |
| 495 | BinaryShiftOpCode(kX86Shr), |
| 496 | BinaryShiftOpCode(kX86Sar), |
| 497 | #undef BinaryShiftOpcode |
| 498 | kX86Cmc, |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 499 | kX86Shld32RRI, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 500 | kX86Shld32MRI, |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 501 | kX86Shrd32RRI, |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 502 | kX86Shrd32MRI, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 503 | kX86Shld64RRI, |
| 504 | kX86Shld64MRI, |
| 505 | kX86Shrd64RRI, |
| 506 | kX86Shrd64MRI, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 507 | #define UnaryOpcode(opcode, reg, mem, array) \ |
| 508 | opcode ## 8 ## reg, opcode ## 8 ## mem, opcode ## 8 ## array, \ |
| 509 | opcode ## 16 ## reg, opcode ## 16 ## mem, opcode ## 16 ## array, \ |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 510 | opcode ## 32 ## reg, opcode ## 32 ## mem, opcode ## 32 ## array, \ |
| 511 | opcode ## 64 ## reg, opcode ## 64 ## mem, opcode ## 64 ## array |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 512 | UnaryOpcode(kX86Test, RI, MI, AI), |
| 513 | kX86Test32RR, |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 514 | kX86Test64RR, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 515 | UnaryOpcode(kX86Not, R, M, A), |
| 516 | UnaryOpcode(kX86Neg, R, M, A), |
| 517 | UnaryOpcode(kX86Mul, DaR, DaM, DaA), |
| 518 | UnaryOpcode(kX86Imul, DaR, DaM, DaA), |
| 519 | UnaryOpcode(kX86Divmod, DaR, DaM, DaA), |
| 520 | UnaryOpcode(kX86Idivmod, DaR, DaM, DaA), |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 521 | kx86Cdq32Da, |
Vladimir Marko | a8b4caf | 2013-10-24 15:08:57 +0100 | [diff] [blame] | 522 | kX86Bswap32R, |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 523 | kX86Push32R, kX86Pop32R, |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 524 | #undef UnaryOpcode |
| 525 | #define Binary0fOpCode(opcode) \ |
| 526 | opcode ## RR, opcode ## RM, opcode ## RA |
| 527 | Binary0fOpCode(kX86Movsd), |
| 528 | kX86MovsdMR, |
| 529 | kX86MovsdAR, |
| 530 | Binary0fOpCode(kX86Movss), |
| 531 | kX86MovssMR, |
| 532 | kX86MovssAR, |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 533 | Binary0fOpCode(kX86Cvtsi2sd), // int to double |
| 534 | Binary0fOpCode(kX86Cvtsi2ss), // int to float |
| 535 | Binary0fOpCode(kX86Cvttsd2si), // truncating double to int |
| 536 | Binary0fOpCode(kX86Cvttss2si), // truncating float to int |
| 537 | Binary0fOpCode(kX86Cvtsd2si), // rounding double to int |
| 538 | Binary0fOpCode(kX86Cvtss2si), // rounding float to int |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 539 | Binary0fOpCode(kX86Ucomisd), // unordered double compare |
| 540 | Binary0fOpCode(kX86Ucomiss), // unordered float compare |
| 541 | Binary0fOpCode(kX86Comisd), // double compare |
| 542 | Binary0fOpCode(kX86Comiss), // float compare |
| 543 | Binary0fOpCode(kX86Orps), // or of floating point registers |
| 544 | Binary0fOpCode(kX86Xorps), // xor of floating point registers |
| 545 | Binary0fOpCode(kX86Addsd), // double add |
| 546 | Binary0fOpCode(kX86Addss), // float add |
| 547 | Binary0fOpCode(kX86Mulsd), // double multiply |
| 548 | Binary0fOpCode(kX86Mulss), // float multiply |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 549 | Binary0fOpCode(kX86Cvtsd2ss), // double to float |
| 550 | Binary0fOpCode(kX86Cvtss2sd), // float to double |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 551 | Binary0fOpCode(kX86Subsd), // double subtract |
| 552 | Binary0fOpCode(kX86Subss), // float subtract |
| 553 | Binary0fOpCode(kX86Divsd), // double divide |
| 554 | Binary0fOpCode(kX86Divss), // float divide |
Razvan A Lupusoru | d3266bc | 2014-01-24 12:55:31 -0800 | [diff] [blame] | 555 | Binary0fOpCode(kX86Punpckldq), // Interleave low-order double words |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 556 | Binary0fOpCode(kX86Sqrtsd), // square root |
| 557 | Binary0fOpCode(kX86Pmulld), // parallel integer multiply 32 bits x 4 |
| 558 | Binary0fOpCode(kX86Pmullw), // parallel integer multiply 16 bits x 8 |
| 559 | Binary0fOpCode(kX86Mulps), // parallel FP multiply 32 bits x 4 |
| 560 | Binary0fOpCode(kX86Mulpd), // parallel FP multiply 64 bits x 2 |
| 561 | Binary0fOpCode(kX86Paddb), // parallel integer addition 8 bits x 16 |
| 562 | Binary0fOpCode(kX86Paddw), // parallel integer addition 16 bits x 8 |
| 563 | Binary0fOpCode(kX86Paddd), // parallel integer addition 32 bits x 4 |
| 564 | Binary0fOpCode(kX86Addps), // parallel FP addition 32 bits x 4 |
| 565 | Binary0fOpCode(kX86Addpd), // parallel FP addition 64 bits x 2 |
| 566 | Binary0fOpCode(kX86Psubb), // parallel integer subtraction 8 bits x 16 |
| 567 | Binary0fOpCode(kX86Psubw), // parallel integer subtraction 16 bits x 8 |
| 568 | Binary0fOpCode(kX86Psubd), // parallel integer subtraction 32 bits x 4 |
| 569 | Binary0fOpCode(kX86Subps), // parallel FP subtraction 32 bits x 4 |
| 570 | Binary0fOpCode(kX86Subpd), // parallel FP subtraction 64 bits x 2 |
| 571 | Binary0fOpCode(kX86Pand), // parallel AND 128 bits x 1 |
| 572 | Binary0fOpCode(kX86Por), // parallel OR 128 bits x 1 |
| 573 | Binary0fOpCode(kX86Pxor), // parallel XOR 128 bits x 1 |
| 574 | Binary0fOpCode(kX86Phaddw), // parallel horizontal addition 16 bits x 8 |
| 575 | Binary0fOpCode(kX86Phaddd), // parallel horizontal addition 32 bits x 4 |
| 576 | kX86PextrbRRI, // Extract 8 bits from XMM into GPR |
| 577 | kX86PextrwRRI, // Extract 16 bits from XMM into GPR |
| 578 | kX86PextrdRRI, // Extract 32 bits from XMM into GPR |
| 579 | kX86PshuflwRRI, // Shuffle 16 bits in lower 64 bits of XMM. |
| 580 | kX86PshufdRRI, // Shuffle 32 bits in XMM. |
| 581 | kX86PsrawRI, // signed right shift of floating point registers 16 bits x 8 |
| 582 | kX86PsradRI, // signed right shift of floating point registers 32 bits x 4 |
| 583 | kX86PsrlwRI, // logical right shift of floating point registers 16 bits x 8 |
| 584 | kX86PsrldRI, // logical right shift of floating point registers 32 bits x 4 |
| 585 | kX86PsrlqRI, // logical right shift of floating point registers 64 bits x 2 |
| 586 | kX86PsllwRI, // left shift of floating point registers 16 bits x 8 |
| 587 | kX86PslldRI, // left shift of floating point registers 32 bits x 4 |
| 588 | kX86PsllqRI, // left shift of floating point registers 64 bits x 2 |
Razvan A Lupusoru | 614c2b4 | 2014-01-28 17:05:21 -0800 | [diff] [blame] | 589 | kX86Fild32M, // push 32-bit integer on x87 stack |
| 590 | kX86Fild64M, // push 64-bit integer on x87 stack |
| 591 | kX86Fstp32M, // pop top x87 fp stack and do 32-bit store |
| 592 | kX86Fstp64M, // pop top x87 fp stack and do 64-bit store |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 593 | Binary0fOpCode(kX86Mova128), // move 128 bits aligned |
| 594 | kX86Mova128MR, kX86Mova128AR, // store 128 bit aligned from xmm1 to m128 |
Razvan A Lupusoru | 2c498d1 | 2014-01-29 16:02:57 -0800 | [diff] [blame] | 595 | Binary0fOpCode(kX86Movups), // load unaligned packed single FP values from xmm2/m128 to xmm1 |
| 596 | kX86MovupsMR, kX86MovupsAR, // store unaligned packed single FP values from xmm1 to m128 |
| 597 | Binary0fOpCode(kX86Movaps), // load aligned packed single FP values from xmm2/m128 to xmm1 |
| 598 | kX86MovapsMR, kX86MovapsAR, // store aligned packed single FP values from xmm1 to m128 |
| 599 | kX86MovlpsRM, kX86MovlpsRA, // load packed single FP values from m64 to low quadword of xmm |
| 600 | kX86MovlpsMR, kX86MovlpsAR, // store packed single FP values from low quadword of xmm to m64 |
| 601 | kX86MovhpsRM, kX86MovhpsRA, // load packed single FP values from m64 to high quadword of xmm |
| 602 | kX86MovhpsMR, kX86MovhpsAR, // store packed single FP values from high quadword of xmm to m64 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 603 | Binary0fOpCode(kX86Movdxr), // move into xmm from gpr |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 604 | kX86MovdrxRR, kX86MovdrxMR, kX86MovdrxAR, // move into reg from xmm |
| 605 | kX86Set8R, kX86Set8M, kX86Set8A, // set byte depending on condition operand |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 606 | kX86Mfence, // memory barrier |
| 607 | Binary0fOpCode(kX86Imul16), // 16bit multiply |
| 608 | Binary0fOpCode(kX86Imul32), // 32bit multiply |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 609 | kX86CmpxchgRR, kX86CmpxchgMR, kX86CmpxchgAR, // compare and exchange |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 610 | kX86LockCmpxchgMR, kX86LockCmpxchgAR, // locked compare and exchange |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 611 | kX86LockCmpxchg8bM, kX86LockCmpxchg8bA, // locked compare and exchange |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 612 | kX86XchgMR, // exchange memory with register (automatically locked) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 613 | Binary0fOpCode(kX86Movzx8), // zero-extend 8-bit value |
| 614 | Binary0fOpCode(kX86Movzx16), // zero-extend 16-bit value |
| 615 | Binary0fOpCode(kX86Movsx8), // sign-extend 8-bit value |
| 616 | Binary0fOpCode(kX86Movsx16), // sign-extend 16-bit value |
| 617 | #undef Binary0fOpCode |
| 618 | kX86Jcc8, kX86Jcc32, // jCC rel8/32; lir operands - 0: rel, 1: CC, target assigned |
| 619 | kX86Jmp8, kX86Jmp32, // jmp rel8/32; lir operands - 0: rel, target assigned |
| 620 | kX86JmpR, // jmp reg; lir operands - 0: reg |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 621 | kX86Jecxz8, // jcexz rel8; jump relative if ECX is zero. |
Brian Carlstrom | 60d7a65 | 2014-03-13 18:10:08 -0700 | [diff] [blame] | 622 | kX86JmpT, // jmp fs:[disp]; fs: is equal to Thread::Current(); lir operands - 0: disp |
| 623 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 624 | kX86CallR, // call reg; lir operands - 0: reg |
| 625 | kX86CallM, // call [base + disp]; lir operands - 0: base, 1: disp |
| 626 | kX86CallA, // call [base + index * scale + disp] |
| 627 | // lir operands - 0: base, 1: index, 2: scale, 3: disp |
| 628 | kX86CallT, // call fs:[disp]; fs: is equal to Thread::Current(); lir operands - 0: disp |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 629 | kX86CallI, // call <relative> - 0: disp; Used for core.oat linking only |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 630 | kX86Ret, // ret; no lir operands |
| 631 | kX86StartOfMethod, // call 0; pop reg; sub reg, # - generate start of method into reg |
| 632 | // lir operands - 0: reg |
| 633 | kX86PcRelLoadRA, // mov reg, [base + index * scale + PC relative displacement] |
| 634 | // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table |
| 635 | kX86PcRelAdr, // mov reg, PC relative displacement; lir operands - 0: reg, 1: table |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 636 | kX86RepneScasw, // repne scasw |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 637 | kX86Last |
| 638 | }; |
| 639 | |
| 640 | /* Instruction assembly field_loc kind */ |
| 641 | enum X86EncodingKind { |
Dmitry Petrochenko | 96992e8 | 2014-05-20 04:03:46 +0700 | [diff] [blame] | 642 | kData, // Special case for raw data. |
| 643 | kNop, // Special case for variable length nop. |
| 644 | kNullary, // Opcode that takes no arguments. |
| 645 | kPrefix2Nullary, // Opcode that takes no arguments, but 2 prefixes. |
| 646 | kRegOpcode, // Shorter form of R instruction kind (opcode+rd) |
| 647 | kReg, kMem, kArray, // R, M and A instruction kinds. |
| 648 | kMemReg, kArrayReg, kThreadReg, // MR, AR and TR instruction kinds. |
| 649 | kRegReg, kRegMem, kRegArray, kRegThread, // RR, RM, RA and RT instruction kinds. |
| 650 | kRegRegStore, // RR following the store modrm reg-reg encoding rather than the load. |
| 651 | kRegImm, kMemImm, kArrayImm, kThreadImm, // RI, MI, AI and TI instruction kinds. |
| 652 | kRegRegImm, kRegMemImm, kRegArrayImm, // RRI, RMI and RAI instruction kinds. |
| 653 | kMovRegImm, // Shorter form move RI. |
| 654 | kRegRegImmRev, // RRI with first reg in r/m |
| 655 | kMemRegImm, // MRI instruction kinds. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 656 | kShiftRegImm, kShiftMemImm, kShiftArrayImm, // Shift opcode with immediate. |
| 657 | kShiftRegCl, kShiftMemCl, kShiftArrayCl, // Shift opcode with register CL. |
| 658 | kRegRegReg, kRegRegMem, kRegRegArray, // RRR, RRM, RRA instruction kinds. |
| 659 | kRegCond, kMemCond, kArrayCond, // R, M, A instruction kinds following by a condition. |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 660 | kRegRegCond, // RR instruction kind followed by a condition. |
Mark Mendell | 2637f2e | 2014-04-30 10:10:47 -0400 | [diff] [blame] | 661 | kRegMemCond, // RM instruction kind followed by a condition. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 662 | kJmp, kJcc, kCall, // Branch instruction kinds. |
| 663 | kPcRel, // Operation with displacement that is PC relative |
| 664 | kMacro, // An instruction composing multiple others |
| 665 | kUnimplemented // Encoding used when an instruction isn't yet implemented. |
| 666 | }; |
| 667 | |
| 668 | /* Struct used to define the EncodingMap positions for each X86 opcode */ |
| 669 | struct X86EncodingMap { |
| 670 | X86OpCode opcode; // e.g. kOpAddRI |
| 671 | X86EncodingKind kind; // Used to discriminate in the union below |
| 672 | uint64_t flags; |
| 673 | struct { |
| 674 | uint8_t prefix1; // non-zero => a prefix byte |
| 675 | uint8_t prefix2; // non-zero => a second prefix byte |
| 676 | uint8_t opcode; // 1 byte opcode |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 677 | uint8_t extra_opcode1; // possible extra opcode byte |
| 678 | uint8_t extra_opcode2; // possible second extra opcode byte |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 679 | // 3bit opcode that gets encoded in the register bits of the modrm byte, use determined by the |
| 680 | // encoding kind |
| 681 | uint8_t modrm_opcode; |
| 682 | uint8_t ax_opcode; // non-zero => shorter encoding for AX as a destination |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 683 | uint8_t immediate_bytes; // number of bytes of immediate |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 684 | } skeleton; |
| 685 | const char *name; |
| 686 | const char* fmt; |
| 687 | }; |
| 688 | |
| 689 | |
| 690 | // FIXME: mem barrier type - what do we do for x86? |
| 691 | #define kSY 0 |
| 692 | #define kST 0 |
| 693 | |
| 694 | // Offsets of high and low halves of a 64bit value. |
| 695 | #define LOWORD_OFFSET 0 |
| 696 | #define HIWORD_OFFSET 4 |
| 697 | |
| 698 | // Segment override instruction prefix used for quick TLS access to Thread::Current(). |
| 699 | #define THREAD_PREFIX 0x64 |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 700 | #define THREAD_PREFIX_GS 0x65 |
| 701 | |
| 702 | // 64 Bit Operand Size |
| 703 | #define REX_W 0x48 |
| 704 | // Extension of the ModR/M reg field |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 705 | #define REX_R 0x44 |
| 706 | // Extension of the SIB index field |
| 707 | #define REX_X 0x42 |
| 708 | // Extension of the ModR/M r/m field, SIB base field, or Opcode reg field |
| 709 | #define REX_B 0x41 |
| 710 | // Mask extracting the least 3 bits of r0..r15 |
| 711 | #define kRegNumMask32 0x07 |
| 712 | // Value indicating that base or reg is not used |
| 713 | #define NO_REG 0 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 714 | |
| 715 | #define IS_SIMM8(v) ((-128 <= (v)) && ((v) <= 127)) |
| 716 | #define IS_SIMM16(v) ((-32768 <= (v)) && ((v) <= 32767)) |
| 717 | |
| 718 | extern X86EncodingMap EncodingMap[kX86Last]; |
| 719 | extern X86ConditionCode X86ConditionEncoding(ConditionCode cond); |
| 720 | |
| 721 | } // namespace art |
| 722 | |
Brian Carlstrom | fc0e321 | 2013-07-17 14:40:12 -0700 | [diff] [blame] | 723 | #endif // ART_COMPILER_DEX_QUICK_X86_X86_LIR_H_ |