buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
buzbee | b046e16 | 2012-10-30 15:48:42 -0700 | [diff] [blame] | 17 | /* This file contains register alloction support. */ |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 18 | |
buzbee | 395116c | 2013-02-27 14:30:25 -0800 | [diff] [blame] | 19 | #include "compiler/dex/compiler_ir.h" |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 20 | #include "compiler/dex/compiler_internals.h" |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 21 | |
Elliott Hughes | 11d1b0c | 2012-01-23 16:57:47 -0800 | [diff] [blame] | 22 | namespace art { |
| 23 | |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 24 | /* |
| 25 | * Free all allocated temps in the temp pools. Note that this does |
| 26 | * not affect the "liveness" of a temp register, which will stay |
| 27 | * live until it is either explicitly killed or reallocated. |
| 28 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 29 | void Mir2Lir::ResetRegPool() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 30 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 31 | int i; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 32 | for (i=0; i < reg_pool_->num_core_regs; i++) { |
| 33 | if (reg_pool_->core_regs[i].is_temp) |
| 34 | reg_pool_->core_regs[i].in_use = false; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 35 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 36 | for (i=0; i < reg_pool_->num_fp_regs; i++) { |
| 37 | if (reg_pool_->FPRegs[i].is_temp) |
| 38 | reg_pool_->FPRegs[i].in_use = false; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 39 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 40 | } |
| 41 | |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 42 | /* |
| 43 | * Set up temp & preserved register pools specialized by target. |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 44 | * Note: num_regs may be zero. |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 45 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 46 | void Mir2Lir::CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 47 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 48 | int i; |
| 49 | for (i=0; i < num; i++) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 50 | regs[i].reg = reg_nums[i]; |
| 51 | regs[i].in_use = false; |
| 52 | regs[i].is_temp = false; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 53 | regs[i].pair = false; |
| 54 | regs[i].live = false; |
| 55 | regs[i].dirty = false; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 56 | regs[i].s_reg = INVALID_SREG; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 57 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 58 | } |
| 59 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 60 | void Mir2Lir::DumpRegPool(RegisterInfo* p, int num_regs) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 61 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 62 | LOG(INFO) << "================================================"; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 63 | for (int i = 0; i < num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 64 | LOG(INFO) << StringPrintf( |
| 65 | "R[%d]: T:%d, U:%d, P:%d, p:%d, LV:%d, D:%d, SR:%d, ST:%x, EN:%x", |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 66 | p[i].reg, p[i].is_temp, p[i].in_use, p[i].pair, p[i].partner, |
| 67 | p[i].live, p[i].dirty, p[i].s_reg, reinterpret_cast<uintptr_t>(p[i].def_start), |
| 68 | reinterpret_cast<uintptr_t>(p[i].def_end)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 69 | } |
| 70 | LOG(INFO) << "================================================"; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 71 | } |
| 72 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 73 | void Mir2Lir::DumpCoreRegPool() |
buzbee | 6181f79 | 2011-09-29 11:14:04 -0700 | [diff] [blame] | 74 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 75 | DumpRegPool(reg_pool_->core_regs, reg_pool_->num_core_regs); |
buzbee | 6181f79 | 2011-09-29 11:14:04 -0700 | [diff] [blame] | 76 | } |
| 77 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 78 | void Mir2Lir::DumpFpRegPool() |
buzbee | 6181f79 | 2011-09-29 11:14:04 -0700 | [diff] [blame] | 79 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 80 | DumpRegPool(reg_pool_->FPRegs, reg_pool_->num_fp_regs); |
buzbee | 6181f79 | 2011-09-29 11:14:04 -0700 | [diff] [blame] | 81 | } |
| 82 | |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 83 | /* Mark a temp register as dead. Does not affect allocation state. */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 84 | void Mir2Lir::ClobberBody(RegisterInfo* p) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 85 | { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 86 | if (p->is_temp) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 87 | DCHECK(!(p->live && p->dirty)) << "Live & dirty temp in clobber"; |
| 88 | p->live = false; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 89 | p->s_reg = INVALID_SREG; |
| 90 | p->def_start = NULL; |
| 91 | p->def_end = NULL; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 92 | if (p->pair) { |
| 93 | p->pair = false; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 94 | Clobber(p->partner); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 95 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 96 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 97 | } |
| 98 | |
buzbee | 5abfa3e | 2012-01-31 17:01:43 -0800 | [diff] [blame] | 99 | /* Mark a temp register as dead. Does not affect allocation state. */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 100 | void Mir2Lir::Clobber(int reg) |
buzbee | 5abfa3e | 2012-01-31 17:01:43 -0800 | [diff] [blame] | 101 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 102 | ClobberBody(GetRegInfo(reg)); |
buzbee | 5abfa3e | 2012-01-31 17:01:43 -0800 | [diff] [blame] | 103 | } |
| 104 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 105 | void Mir2Lir::ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 106 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 107 | int i; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 108 | for (i=0; i< num_regs; i++) { |
| 109 | if (p[i].s_reg == s_reg) { |
| 110 | if (p[i].is_temp) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 111 | p[i].live = false; |
| 112 | } |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 113 | p[i].def_start = NULL; |
| 114 | p[i].def_end = NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 115 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 116 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 117 | } |
| 118 | |
buzbee | 078fa45 | 2012-12-03 15:51:33 -0800 | [diff] [blame] | 119 | /* |
| 120 | * Break the association between a Dalvik vreg and a physical temp register of either register |
| 121 | * class. |
| 122 | * TODO: Ideally, the public version of this code should not exist. Besides its local usage |
| 123 | * in the register utilities, is is also used by code gen routines to work around a deficiency in |
| 124 | * local register allocation, which fails to distinguish between the "in" and "out" identities |
| 125 | * of Dalvik vregs. This can result in useless register copies when the same Dalvik vreg |
| 126 | * is used both as the source and destination register of an operation in which the type |
| 127 | * changes (for example: INT_TO_FLOAT v1, v1). Revisit when improved register allocation is |
| 128 | * addressed. |
| 129 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 130 | void Mir2Lir::ClobberSReg(int s_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 131 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 132 | /* Reset live temp tracking sanity checker */ |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 133 | if (kIsDebugBuild) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 134 | if (s_reg == live_sreg_) { |
| 135 | live_sreg_ = INVALID_SREG; |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 136 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 137 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 138 | ClobberSRegBody(reg_pool_->core_regs, reg_pool_->num_core_regs, s_reg); |
| 139 | ClobberSRegBody(reg_pool_->FPRegs, reg_pool_->num_fp_regs, s_reg); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 140 | } |
| 141 | |
buzbee | 9c044ce | 2012-03-18 13:24:07 -0700 | [diff] [blame] | 142 | /* |
| 143 | * SSA names associated with the initial definitions of Dalvik |
| 144 | * registers are the same as the Dalvik register number (and |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 145 | * thus take the same position in the promotion_map. However, |
buzbee | 9c044ce | 2012-03-18 13:24:07 -0700 | [diff] [blame] | 146 | * the special Method* and compiler temp resisters use negative |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 147 | * v_reg numbers to distinguish them and can have an arbitrary |
buzbee | 9c044ce | 2012-03-18 13:24:07 -0700 | [diff] [blame] | 148 | * ssa name (above the last original Dalvik register). This function |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 149 | * maps SSA names to positions in the promotion_map array. |
buzbee | 9c044ce | 2012-03-18 13:24:07 -0700 | [diff] [blame] | 150 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 151 | int Mir2Lir::SRegToPMap(int s_reg) |
buzbee | e196567 | 2012-03-11 18:39:19 -0700 | [diff] [blame] | 152 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 153 | DCHECK_LT(s_reg, mir_graph_->GetNumSSARegs()); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 154 | DCHECK_GE(s_reg, 0); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 155 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 156 | if (v_reg >= 0) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 157 | DCHECK_LT(v_reg, cu_->num_dalvik_registers); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 158 | return v_reg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 159 | } else { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 160 | int pos = std::abs(v_reg) - std::abs(SSA_METHOD_BASEREG); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 161 | DCHECK_LE(pos, cu_->num_compiler_temps); |
| 162 | return cu_->num_dalvik_registers + pos; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 163 | } |
buzbee | e196567 | 2012-03-11 18:39:19 -0700 | [diff] [blame] | 164 | } |
| 165 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 166 | void Mir2Lir::RecordCorePromotion(int reg, int s_reg) |
buzbee | ca7a5e4 | 2012-08-20 11:12:18 -0700 | [diff] [blame] | 167 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 168 | int p_map_idx = SRegToPMap(s_reg); |
| 169 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 170 | GetRegInfo(reg)->in_use = true; |
| 171 | core_spill_mask_ |= (1 << reg); |
buzbee | ca7a5e4 | 2012-08-20 11:12:18 -0700 | [diff] [blame] | 172 | // Include reg for later sort |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 173 | core_vmap_table_.push_back(reg << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); |
| 174 | num_core_spills_++; |
| 175 | promotion_map_[p_map_idx].core_location = kLocPhysReg; |
| 176 | promotion_map_[p_map_idx].core_reg = reg; |
buzbee | ca7a5e4 | 2012-08-20 11:12:18 -0700 | [diff] [blame] | 177 | } |
| 178 | |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 179 | /* Reserve a callee-save register. Return -1 if none available */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 180 | int Mir2Lir::AllocPreservedCoreReg(int s_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 181 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 182 | int res = -1; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 183 | RegisterInfo* core_regs = reg_pool_->core_regs; |
| 184 | for (int i = 0; i < reg_pool_->num_core_regs; i++) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 185 | if (!core_regs[i].is_temp && !core_regs[i].in_use) { |
| 186 | res = core_regs[i].reg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 187 | RecordCorePromotion(res, s_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 188 | break; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 189 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 190 | } |
| 191 | return res; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 192 | } |
| 193 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 194 | void Mir2Lir::RecordFpPromotion(int reg, int s_reg) |
buzbee | ca7a5e4 | 2012-08-20 11:12:18 -0700 | [diff] [blame] | 195 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 196 | int p_map_idx = SRegToPMap(s_reg); |
| 197 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 198 | GetRegInfo(reg)->in_use = true; |
| 199 | MarkPreservedSingle(v_reg, reg); |
| 200 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
| 201 | promotion_map_[p_map_idx].FpReg = reg; |
buzbee | ca7a5e4 | 2012-08-20 11:12:18 -0700 | [diff] [blame] | 202 | } |
| 203 | |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 204 | /* |
| 205 | * Reserve a callee-save fp single register. Try to fullfill request for |
| 206 | * even/odd allocation, but go ahead and allocate anything if not |
| 207 | * available. If nothing's available, return -1. |
| 208 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 209 | int Mir2Lir::AllocPreservedSingle(int s_reg, bool even) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 210 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 211 | int res = -1; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 212 | RegisterInfo* FPRegs = reg_pool_->FPRegs; |
| 213 | for (int i = 0; i < reg_pool_->num_fp_regs; i++) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 214 | if (!FPRegs[i].is_temp && !FPRegs[i].in_use && |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 215 | ((FPRegs[i].reg & 0x1) == 0) == even) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 216 | res = FPRegs[i].reg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 217 | RecordFpPromotion(res, s_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 218 | break; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 219 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 220 | } |
| 221 | return res; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | /* |
| 225 | * Somewhat messy code here. We want to allocate a pair of contiguous |
| 226 | * physical single-precision floating point registers starting with |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 227 | * an even numbered reg. It is possible that the paired s_reg (s_reg+1) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 228 | * has already been allocated - try to fit if possible. Fail to |
| 229 | * allocate if we can't meet the requirements for the pair of |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 230 | * s_reg<=sX[even] & (s_reg+1)<= sX+1. |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 231 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 232 | int Mir2Lir::AllocPreservedDouble(int s_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 233 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 234 | int res = -1; // Assume failure |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 235 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 236 | int p_map_idx = SRegToPMap(s_reg); |
| 237 | if (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 238 | // Upper reg is already allocated. Can we fit? |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 239 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 240 | if ((high_reg & 1) == 0) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 241 | // High reg is even - fail. |
| 242 | return res; |
| 243 | } |
| 244 | // Is the low reg of the pair free? |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 245 | RegisterInfo* p = GetRegInfo(high_reg-1); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 246 | if (p->in_use || p->is_temp) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 247 | // Already allocated or not preserved - fail. |
| 248 | return res; |
| 249 | } |
| 250 | // OK - good to go. |
| 251 | res = p->reg; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 252 | p->in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 253 | DCHECK_EQ((res & 1), 0); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 254 | MarkPreservedSingle(v_reg, res); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 255 | } else { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 256 | RegisterInfo* FPRegs = reg_pool_->FPRegs; |
| 257 | for (int i = 0; i < reg_pool_->num_fp_regs; i++) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 258 | if (!FPRegs[i].is_temp && !FPRegs[i].in_use && |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 259 | ((FPRegs[i].reg & 0x1) == 0x0) && |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 260 | !FPRegs[i+1].is_temp && !FPRegs[i+1].in_use && |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 261 | ((FPRegs[i+1].reg & 0x1) == 0x1) && |
| 262 | (FPRegs[i].reg + 1) == FPRegs[i+1].reg) { |
| 263 | res = FPRegs[i].reg; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 264 | FPRegs[i].in_use = true; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 265 | MarkPreservedSingle(v_reg, res); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 266 | FPRegs[i+1].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 267 | DCHECK_EQ(res + 1, FPRegs[i+1].reg); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 268 | MarkPreservedSingle(v_reg+1, res+1); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 269 | break; |
| 270 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 271 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 272 | } |
| 273 | if (res != -1) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 274 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
| 275 | promotion_map_[p_map_idx].FpReg = res; |
| 276 | promotion_map_[p_map_idx+1].fp_location = kLocPhysReg; |
| 277 | promotion_map_[p_map_idx+1].FpReg = res + 1; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 278 | } |
| 279 | return res; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | |
| 283 | /* |
| 284 | * Reserve a callee-save fp register. If this register can be used |
| 285 | * as the first of a double, attempt to allocate an even pair of fp |
| 286 | * single regs (but if can't still attempt to allocate a single, preferring |
| 287 | * first to allocate an odd register. |
| 288 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 289 | int Mir2Lir::AllocPreservedFPReg(int s_reg, bool double_start) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 290 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 291 | int res = -1; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 292 | if (double_start) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 293 | res = AllocPreservedDouble(s_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 294 | } |
| 295 | if (res == -1) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 296 | res = AllocPreservedSingle(s_reg, false /* try odd # */); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 297 | } |
| 298 | if (res == -1) |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 299 | res = AllocPreservedSingle(s_reg, true /* try even # */); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 300 | return res; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 301 | } |
| 302 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 303 | int Mir2Lir::AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp, |
| 304 | bool required) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 305 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 306 | int i; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 307 | int next = *next_temp; |
| 308 | for (i=0; i< num_regs; i++) { |
| 309 | if (next >= num_regs) |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 310 | next = 0; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 311 | if (p[next].is_temp && !p[next].in_use && !p[next].live) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 312 | Clobber(p[next].reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 313 | p[next].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 314 | p[next].pair = false; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 315 | *next_temp = next + 1; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 316 | return p[next].reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 317 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 318 | next++; |
| 319 | } |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 320 | next = *next_temp; |
| 321 | for (i=0; i< num_regs; i++) { |
| 322 | if (next >= num_regs) |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 323 | next = 0; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 324 | if (p[next].is_temp && !p[next].in_use) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 325 | Clobber(p[next].reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 326 | p[next].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 327 | p[next].pair = false; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 328 | *next_temp = next + 1; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 329 | return p[next].reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 330 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 331 | next++; |
| 332 | } |
| 333 | if (required) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 334 | CodegenDump(); |
| 335 | DumpRegPool(reg_pool_->core_regs, |
| 336 | reg_pool_->num_core_regs); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 337 | LOG(FATAL) << "No free temp registers"; |
| 338 | } |
| 339 | return -1; // No register available |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 340 | } |
| 341 | |
| 342 | //REDO: too many assumptions. |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 343 | int Mir2Lir::AllocTempDouble() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 344 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 345 | RegisterInfo* p = reg_pool_->FPRegs; |
| 346 | int num_regs = reg_pool_->num_fp_regs; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 347 | /* Start looking at an even reg */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 348 | int next = reg_pool_->next_fp_reg & ~0x1; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 349 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 350 | // First try to avoid allocating live registers |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 351 | for (int i=0; i < num_regs; i+=2) { |
| 352 | if (next >= num_regs) |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 353 | next = 0; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 354 | if ((p[next].is_temp && !p[next].in_use && !p[next].live) && |
| 355 | (p[next+1].is_temp && !p[next+1].in_use && !p[next+1].live)) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 356 | Clobber(p[next].reg); |
| 357 | Clobber(p[next+1].reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 358 | p[next].in_use = true; |
| 359 | p[next+1].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 360 | DCHECK_EQ((p[next].reg+1), p[next+1].reg); |
| 361 | DCHECK_EQ((p[next].reg & 0x1), 0); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 362 | reg_pool_->next_fp_reg = next + 2; |
| 363 | if (reg_pool_->next_fp_reg >= num_regs) { |
| 364 | reg_pool_->next_fp_reg = 0; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 365 | } |
| 366 | return p[next].reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 367 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 368 | next += 2; |
| 369 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 370 | next = reg_pool_->next_fp_reg & ~0x1; |
buzbee | a50638b | 2011-11-02 15:15:06 -0700 | [diff] [blame] | 371 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 372 | // No choice - find a pair and kill it. |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 373 | for (int i=0; i < num_regs; i+=2) { |
| 374 | if (next >= num_regs) |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 375 | next = 0; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 376 | if (p[next].is_temp && !p[next].in_use && p[next+1].is_temp && |
| 377 | !p[next+1].in_use) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 378 | Clobber(p[next].reg); |
| 379 | Clobber(p[next+1].reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 380 | p[next].in_use = true; |
| 381 | p[next+1].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 382 | DCHECK_EQ((p[next].reg+1), p[next+1].reg); |
| 383 | DCHECK_EQ((p[next].reg & 0x1), 0); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 384 | reg_pool_->next_fp_reg = next + 2; |
| 385 | if (reg_pool_->next_fp_reg >= num_regs) { |
| 386 | reg_pool_->next_fp_reg = 0; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 387 | } |
| 388 | return p[next].reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 389 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 390 | next += 2; |
| 391 | } |
| 392 | LOG(FATAL) << "No free temp registers (pair)"; |
| 393 | return -1; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 394 | } |
| 395 | |
| 396 | /* Return a temp if one is available, -1 otherwise */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 397 | int Mir2Lir::AllocFreeTemp() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 398 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 399 | return AllocTempBody(reg_pool_->core_regs, |
| 400 | reg_pool_->num_core_regs, |
| 401 | ®_pool_->next_core_reg, true); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 402 | } |
| 403 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 404 | int Mir2Lir::AllocTemp() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 405 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 406 | return AllocTempBody(reg_pool_->core_regs, |
| 407 | reg_pool_->num_core_regs, |
| 408 | ®_pool_->next_core_reg, true); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 409 | } |
| 410 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 411 | int Mir2Lir::AllocTempFloat() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 412 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 413 | return AllocTempBody(reg_pool_->FPRegs, |
| 414 | reg_pool_->num_fp_regs, |
| 415 | ®_pool_->next_fp_reg, true); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 416 | } |
| 417 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 418 | Mir2Lir::RegisterInfo* Mir2Lir::AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 419 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 420 | int i; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 421 | if (s_reg == -1) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 422 | return NULL; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 423 | for (i=0; i < num_regs; i++) { |
| 424 | if (p[i].live && (p[i].s_reg == s_reg)) { |
| 425 | if (p[i].is_temp) |
| 426 | p[i].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 427 | return &p[i]; |
| 428 | } |
| 429 | } |
| 430 | return NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 431 | } |
| 432 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 433 | Mir2Lir::RegisterInfo* Mir2Lir::AllocLive(int s_reg, int reg_class) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 434 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 435 | RegisterInfo* res = NULL; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 436 | switch (reg_class) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 437 | case kAnyReg: |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 438 | res = AllocLiveBody(reg_pool_->FPRegs, |
| 439 | reg_pool_->num_fp_regs, s_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 440 | if (res) |
| 441 | break; |
| 442 | /* Intentional fallthrough */ |
| 443 | case kCoreReg: |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 444 | res = AllocLiveBody(reg_pool_->core_regs, |
| 445 | reg_pool_->num_core_regs, s_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 446 | break; |
| 447 | case kFPReg: |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 448 | res = AllocLiveBody(reg_pool_->FPRegs, |
| 449 | reg_pool_->num_fp_regs, s_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 450 | break; |
| 451 | default: |
| 452 | LOG(FATAL) << "Invalid register type"; |
| 453 | } |
| 454 | return res; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 455 | } |
| 456 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 457 | void Mir2Lir::FreeTemp(int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 458 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 459 | RegisterInfo* p = reg_pool_->core_regs; |
| 460 | int num_regs = reg_pool_->num_core_regs; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 461 | int i; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 462 | for (i=0; i< num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 463 | if (p[i].reg == reg) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 464 | if (p[i].is_temp) { |
| 465 | p[i].in_use = false; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 466 | } |
| 467 | p[i].pair = false; |
| 468 | return; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 469 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 470 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 471 | p = reg_pool_->FPRegs; |
| 472 | num_regs = reg_pool_->num_fp_regs; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 473 | for (i=0; i< num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 474 | if (p[i].reg == reg) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 475 | if (p[i].is_temp) { |
| 476 | p[i].in_use = false; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 477 | } |
| 478 | p[i].pair = false; |
| 479 | return; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 480 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 481 | } |
| 482 | LOG(FATAL) << "Tried to free a non-existant temp: r" << reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 483 | } |
| 484 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 485 | Mir2Lir::RegisterInfo* Mir2Lir::IsLive(int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 486 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 487 | RegisterInfo* p = reg_pool_->core_regs; |
| 488 | int num_regs = reg_pool_->num_core_regs; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 489 | int i; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 490 | for (i=0; i< num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 491 | if (p[i].reg == reg) { |
| 492 | return p[i].live ? &p[i] : NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 493 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 494 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 495 | p = reg_pool_->FPRegs; |
| 496 | num_regs = reg_pool_->num_fp_regs; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 497 | for (i=0; i< num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 498 | if (p[i].reg == reg) { |
| 499 | return p[i].live ? &p[i] : NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 500 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 501 | } |
| 502 | return NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 503 | } |
| 504 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 505 | Mir2Lir::RegisterInfo* Mir2Lir::IsTemp(int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 506 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 507 | RegisterInfo* p = GetRegInfo(reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 508 | return (p->is_temp) ? p : NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 509 | } |
| 510 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 511 | Mir2Lir::RegisterInfo* Mir2Lir::IsPromoted(int reg) |
buzbee | b29e4d1 | 2011-09-26 15:05:48 -0700 | [diff] [blame] | 512 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 513 | RegisterInfo* p = GetRegInfo(reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 514 | return (p->is_temp) ? NULL : p; |
buzbee | b29e4d1 | 2011-09-26 15:05:48 -0700 | [diff] [blame] | 515 | } |
| 516 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 517 | bool Mir2Lir::IsDirty(int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 518 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 519 | RegisterInfo* p = GetRegInfo(reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 520 | return p->dirty; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 521 | } |
| 522 | |
| 523 | /* |
buzbee | 52a77fc | 2012-11-20 19:50:46 -0800 | [diff] [blame] | 524 | * Similar to AllocTemp(), but forces the allocation of a specific |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 525 | * register. No check is made to see if the register was previously |
| 526 | * allocated. Use with caution. |
| 527 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 528 | void Mir2Lir::LockTemp(int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 529 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 530 | RegisterInfo* p = reg_pool_->core_regs; |
| 531 | int num_regs = reg_pool_->num_core_regs; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 532 | int i; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 533 | for (i=0; i< num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 534 | if (p[i].reg == reg) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 535 | DCHECK(p[i].is_temp); |
| 536 | p[i].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 537 | p[i].live = false; |
| 538 | return; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 539 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 540 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 541 | p = reg_pool_->FPRegs; |
| 542 | num_regs = reg_pool_->num_fp_regs; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 543 | for (i=0; i< num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 544 | if (p[i].reg == reg) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 545 | DCHECK(p[i].is_temp); |
| 546 | p[i].in_use = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 547 | p[i].live = false; |
| 548 | return; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 549 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 550 | } |
| 551 | LOG(FATAL) << "Tried to lock a non-existant temp: r" << reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 552 | } |
| 553 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 554 | void Mir2Lir::ResetDefBody(RegisterInfo* p) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 555 | { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 556 | p->def_start = NULL; |
| 557 | p->def_end = NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 558 | } |
| 559 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 560 | void Mir2Lir::ResetDef(int reg) |
buzbee | 5abfa3e | 2012-01-31 17:01:43 -0800 | [diff] [blame] | 561 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 562 | ResetDefBody(GetRegInfo(reg)); |
buzbee | 5abfa3e | 2012-01-31 17:01:43 -0800 | [diff] [blame] | 563 | } |
| 564 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 565 | void Mir2Lir::NullifyRange(LIR *start, LIR *finish, int s_reg1, int s_reg2) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 566 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 567 | if (start && finish) { |
| 568 | LIR *p; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 569 | DCHECK_EQ(s_reg1, s_reg2); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 570 | for (p = start; ;p = p->next) { |
buzbee | 52a77fc | 2012-11-20 19:50:46 -0800 | [diff] [blame] | 571 | NopLIR(p); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 572 | if (p == finish) |
| 573 | break; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 574 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 575 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 576 | } |
| 577 | |
| 578 | /* |
| 579 | * Mark the beginning and end LIR of a def sequence. Note that |
| 580 | * on entry start points to the LIR prior to the beginning of the |
| 581 | * sequence. |
| 582 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 583 | void Mir2Lir::MarkDef(RegLocation rl, LIR *start, LIR *finish) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 584 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 585 | DCHECK(!rl.wide); |
| 586 | DCHECK(start && start->next); |
| 587 | DCHECK(finish); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 588 | RegisterInfo* p = GetRegInfo(rl.low_reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 589 | p->def_start = start->next; |
| 590 | p->def_end = finish; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | /* |
| 594 | * Mark the beginning and end LIR of a def sequence. Note that |
| 595 | * on entry start points to the LIR prior to the beginning of the |
| 596 | * sequence. |
| 597 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 598 | void Mir2Lir::MarkDefWide(RegLocation rl, LIR *start, LIR *finish) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 599 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 600 | DCHECK(rl.wide); |
| 601 | DCHECK(start && start->next); |
| 602 | DCHECK(finish); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 603 | RegisterInfo* p = GetRegInfo(rl.low_reg); |
| 604 | ResetDef(rl.high_reg); // Only track low of pair |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 605 | p->def_start = start->next; |
| 606 | p->def_end = finish; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 607 | } |
| 608 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 609 | RegLocation Mir2Lir::WideToNarrow(RegLocation rl) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 610 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 611 | DCHECK(rl.wide); |
| 612 | if (rl.location == kLocPhysReg) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 613 | RegisterInfo* info_lo = GetRegInfo(rl.low_reg); |
| 614 | RegisterInfo* info_hi = GetRegInfo(rl.high_reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 615 | if (info_lo->is_temp) { |
| 616 | info_lo->pair = false; |
| 617 | info_lo->def_start = NULL; |
| 618 | info_lo->def_end = NULL; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 619 | } |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 620 | if (info_hi->is_temp) { |
| 621 | info_hi->pair = false; |
| 622 | info_hi->def_start = NULL; |
| 623 | info_hi->def_end = NULL; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 624 | } |
| 625 | } |
| 626 | rl.wide = false; |
| 627 | return rl; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 628 | } |
| 629 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 630 | void Mir2Lir::ResetDefLoc(RegLocation rl) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 631 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 632 | DCHECK(!rl.wide); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 633 | RegisterInfo* p = IsTemp(rl.low_reg); |
| 634 | if (p && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 635 | DCHECK(!p->pair); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 636 | NullifyRange(p->def_start, p->def_end, p->s_reg, rl.s_reg_low); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 637 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 638 | ResetDef(rl.low_reg); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 639 | } |
| 640 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 641 | void Mir2Lir::ResetDefLocWide(RegLocation rl) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 642 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 643 | DCHECK(rl.wide); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 644 | RegisterInfo* p_low = IsTemp(rl.low_reg); |
| 645 | RegisterInfo* p_high = IsTemp(rl.high_reg); |
| 646 | if (p_low && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 647 | DCHECK(p_low->pair); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 648 | NullifyRange(p_low->def_start, p_low->def_end, p_low->s_reg, rl.s_reg_low); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 649 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 650 | if (p_high && !(cu_->disable_opt & (1 << kSuppressLoads))) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 651 | DCHECK(p_high->pair); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 652 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 653 | ResetDef(rl.low_reg); |
| 654 | ResetDef(rl.high_reg); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 655 | } |
| 656 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 657 | void Mir2Lir::ResetDefTracking() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 658 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 659 | int i; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 660 | for (i=0; i< reg_pool_->num_core_regs; i++) { |
| 661 | ResetDefBody(®_pool_->core_regs[i]); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 662 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 663 | for (i=0; i< reg_pool_->num_fp_regs; i++) { |
| 664 | ResetDefBody(®_pool_->FPRegs[i]); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 665 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 666 | } |
| 667 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 668 | void Mir2Lir::ClobberAllRegs() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 669 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 670 | int i; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 671 | for (i=0; i< reg_pool_->num_core_regs; i++) { |
| 672 | ClobberBody(®_pool_->core_regs[i]); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 673 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 674 | for (i=0; i< reg_pool_->num_fp_regs; i++) { |
| 675 | ClobberBody(®_pool_->FPRegs[i]); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 676 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 677 | } |
| 678 | |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 679 | // Make sure nothing is live and dirty |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 680 | void Mir2Lir::FlushAllRegsBody(RegisterInfo* info, int num_regs) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 681 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 682 | int i; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 683 | for (i=0; i < num_regs; i++) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 684 | if (info[i].live && info[i].dirty) { |
| 685 | if (info[i].pair) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 686 | FlushRegWide(info[i].reg, info[i].partner); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 687 | } else { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 688 | FlushReg(info[i].reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 689 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 690 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 691 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 692 | } |
| 693 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 694 | void Mir2Lir::FlushAllRegs() |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 695 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 696 | FlushAllRegsBody(reg_pool_->core_regs, |
| 697 | reg_pool_->num_core_regs); |
| 698 | FlushAllRegsBody(reg_pool_->FPRegs, |
| 699 | reg_pool_->num_fp_regs); |
| 700 | ClobberAllRegs(); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 701 | } |
| 702 | |
| 703 | |
| 704 | //TUNING: rewrite all of this reg stuff. Probably use an attribute table |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 705 | bool Mir2Lir::RegClassMatches(int reg_class, int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 706 | { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 707 | if (reg_class == kAnyReg) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 708 | return true; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 709 | } else if (reg_class == kCoreReg) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 710 | return !IsFpReg(reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 711 | } else { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 712 | return IsFpReg(reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 713 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 714 | } |
| 715 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 716 | void Mir2Lir::MarkLive(int reg, int s_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 717 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 718 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 719 | if ((info->reg == reg) && (info->s_reg == s_reg) && info->live) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 720 | return; /* already live */ |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 721 | } else if (s_reg != INVALID_SREG) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 722 | ClobberSReg(s_reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 723 | if (info->is_temp) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 724 | info->live = true; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 725 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 726 | } else { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 727 | /* Can't be live if no associated s_reg */ |
| 728 | DCHECK(info->is_temp); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 729 | info->live = false; |
| 730 | } |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 731 | info->s_reg = s_reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 732 | } |
| 733 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 734 | void Mir2Lir::MarkTemp(int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 735 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 736 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 737 | info->is_temp = true; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 738 | } |
| 739 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 740 | void Mir2Lir::UnmarkTemp(int reg) |
buzbee | 9e0f9b0 | 2011-08-24 15:32:46 -0700 | [diff] [blame] | 741 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 742 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 743 | info->is_temp = false; |
buzbee | 9e0f9b0 | 2011-08-24 15:32:46 -0700 | [diff] [blame] | 744 | } |
| 745 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 746 | void Mir2Lir::MarkPair(int low_reg, int high_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 747 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 748 | RegisterInfo* info_lo = GetRegInfo(low_reg); |
| 749 | RegisterInfo* info_hi = GetRegInfo(high_reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 750 | info_lo->pair = info_hi->pair = true; |
| 751 | info_lo->partner = high_reg; |
| 752 | info_hi->partner = low_reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 753 | } |
| 754 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 755 | void Mir2Lir::MarkClean(RegLocation loc) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 756 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 757 | RegisterInfo* info = GetRegInfo(loc.low_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 758 | info->dirty = false; |
| 759 | if (loc.wide) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 760 | info = GetRegInfo(loc.high_reg); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 761 | info->dirty = false; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 762 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 763 | } |
| 764 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 765 | void Mir2Lir::MarkDirty(RegLocation loc) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 766 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 767 | if (loc.home) { |
| 768 | // If already home, can't be dirty |
| 769 | return; |
| 770 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 771 | RegisterInfo* info = GetRegInfo(loc.low_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 772 | info->dirty = true; |
| 773 | if (loc.wide) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 774 | info = GetRegInfo(loc.high_reg); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 775 | info->dirty = true; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 776 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 777 | } |
| 778 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 779 | void Mir2Lir::MarkInUse(int reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 780 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 781 | RegisterInfo* info = GetRegInfo(reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 782 | info->in_use = true; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 783 | } |
| 784 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 785 | void Mir2Lir::CopyRegInfo(int new_reg, int old_reg) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 786 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 787 | RegisterInfo* new_info = GetRegInfo(new_reg); |
| 788 | RegisterInfo* old_info = GetRegInfo(old_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 789 | // Target temp status must not change |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 790 | bool is_temp = new_info->is_temp; |
| 791 | *new_info = *old_info; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 792 | // Restore target's temp status |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 793 | new_info->is_temp = is_temp; |
| 794 | new_info->reg = new_reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 795 | } |
| 796 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 797 | bool Mir2Lir::CheckCorePoolSanity() |
buzbee | 6181f79 | 2011-09-29 11:14:04 -0700 | [diff] [blame] | 798 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 799 | for (static int i = 0; i < reg_pool_->num_core_regs; i++) { |
| 800 | if (reg_pool_->core_regs[i].pair) { |
| 801 | static int my_reg = reg_pool_->core_regs[i].reg; |
| 802 | static int my_sreg = reg_pool_->core_regs[i].s_reg; |
| 803 | static int partner_reg = reg_pool_->core_regs[i].partner; |
| 804 | static RegisterInfo* partner = GetRegInfo(partner_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 805 | DCHECK(partner != NULL); |
| 806 | DCHECK(partner->pair); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 807 | DCHECK_EQ(my_reg, partner->partner); |
| 808 | static int partner_sreg = partner->s_reg; |
| 809 | if (my_sreg == INVALID_SREG) { |
| 810 | DCHECK_EQ(partner_sreg, INVALID_SREG); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 811 | } else { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 812 | int diff = my_sreg - partner_sreg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 813 | DCHECK((diff == -1) || (diff == 1)); |
buzbee | 6181f79 | 2011-09-29 11:14:04 -0700 | [diff] [blame] | 814 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 815 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 816 | if (!reg_pool_->core_regs[i].live) { |
| 817 | DCHECK(reg_pool_->core_regs[i].def_start == NULL); |
| 818 | DCHECK(reg_pool_->core_regs[i].def_end == NULL); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 819 | } |
buzbee | 6181f79 | 2011-09-29 11:14:04 -0700 | [diff] [blame] | 820 | } |
| 821 | return true; |
| 822 | } |
| 823 | |
buzbee | aad9438 | 2012-11-21 07:40:50 -0800 | [diff] [blame] | 824 | /* |
| 825 | * Return an updated location record with current in-register status. |
| 826 | * If the value lives in live temps, reflect that fact. No code |
| 827 | * is generated. If the live value is part of an older pair, |
| 828 | * clobber both low and high. |
| 829 | * TUNING: clobbering both is a bit heavy-handed, but the alternative |
| 830 | * is a bit complex when dealing with FP regs. Examine code to see |
| 831 | * if it's worthwhile trying to be more clever here. |
| 832 | */ |
| 833 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 834 | RegLocation Mir2Lir::UpdateLoc(RegLocation loc) |
buzbee | aad9438 | 2012-11-21 07:40:50 -0800 | [diff] [blame] | 835 | { |
| 836 | DCHECK(!loc.wide); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 837 | DCHECK(CheckCorePoolSanity()); |
buzbee | aad9438 | 2012-11-21 07:40:50 -0800 | [diff] [blame] | 838 | if (loc.location != kLocPhysReg) { |
| 839 | DCHECK((loc.location == kLocDalvikFrame) || |
| 840 | (loc.location == kLocCompilerTemp)); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 841 | RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 842 | if (info_lo) { |
| 843 | if (info_lo->pair) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 844 | Clobber(info_lo->reg); |
| 845 | Clobber(info_lo->partner); |
| 846 | FreeTemp(info_lo->reg); |
buzbee | aad9438 | 2012-11-21 07:40:50 -0800 | [diff] [blame] | 847 | } else { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 848 | loc.low_reg = info_lo->reg; |
buzbee | aad9438 | 2012-11-21 07:40:50 -0800 | [diff] [blame] | 849 | loc.location = kLocPhysReg; |
| 850 | } |
| 851 | } |
| 852 | } |
| 853 | |
| 854 | return loc; |
| 855 | } |
| 856 | |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 857 | /* see comments for update_loc */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 858 | RegLocation Mir2Lir::UpdateLocWide(RegLocation loc) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 859 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 860 | DCHECK(loc.wide); |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 861 | DCHECK(CheckCorePoolSanity()); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 862 | if (loc.location != kLocPhysReg) { |
| 863 | DCHECK((loc.location == kLocDalvikFrame) || |
| 864 | (loc.location == kLocCompilerTemp)); |
| 865 | // Are the dalvik regs already live in physical registers? |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 866 | RegisterInfo* info_lo = AllocLive(loc.s_reg_low, kAnyReg); |
| 867 | RegisterInfo* info_hi = AllocLive(GetSRegHi(loc.s_reg_low), kAnyReg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 868 | bool match = true; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 869 | match = match && (info_lo != NULL); |
| 870 | match = match && (info_hi != NULL); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 871 | // Are they both core or both FP? |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 872 | match = match && (IsFpReg(info_lo->reg) == IsFpReg(info_hi->reg)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 873 | // If a pair of floating point singles, are they properly aligned? |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 874 | if (match && IsFpReg(info_lo->reg)) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 875 | match &= ((info_lo->reg & 0x1) == 0); |
| 876 | match &= ((info_hi->reg - info_lo->reg) == 1); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 877 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 878 | // If previously used as a pair, it is the same pair? |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 879 | if (match && (info_lo->pair || info_hi->pair)) { |
| 880 | match = (info_lo->pair == info_hi->pair); |
| 881 | match &= ((info_lo->reg == info_hi->partner) && |
| 882 | (info_hi->reg == info_lo->partner)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 883 | } |
| 884 | if (match) { |
| 885 | // Can reuse - update the register usage info |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 886 | loc.low_reg = info_lo->reg; |
| 887 | loc.high_reg = info_hi->reg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 888 | loc.location = kLocPhysReg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 889 | MarkPair(loc.low_reg, loc.high_reg); |
| 890 | DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 891 | return loc; |
| 892 | } |
| 893 | // Can't easily reuse - clobber and free any overlaps |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 894 | if (info_lo) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 895 | Clobber(info_lo->reg); |
| 896 | FreeTemp(info_lo->reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 897 | if (info_lo->pair) |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 898 | Clobber(info_lo->partner); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 899 | } |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 900 | if (info_hi) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 901 | Clobber(info_hi->reg); |
| 902 | FreeTemp(info_hi->reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 903 | if (info_hi->pair) |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 904 | Clobber(info_hi->partner); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 905 | } |
| 906 | } |
| 907 | return loc; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 908 | } |
| 909 | |
buzbee | ed3e930 | 2011-09-23 17:34:19 -0700 | [diff] [blame] | 910 | |
| 911 | /* For use in cases we don't know (or care) width */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 912 | RegLocation Mir2Lir::UpdateRawLoc(RegLocation loc) |
buzbee | ed3e930 | 2011-09-23 17:34:19 -0700 | [diff] [blame] | 913 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 914 | if (loc.wide) |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 915 | return UpdateLocWide(loc); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 916 | else |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 917 | return UpdateLoc(loc); |
buzbee | ed3e930 | 2011-09-23 17:34:19 -0700 | [diff] [blame] | 918 | } |
| 919 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 920 | RegLocation Mir2Lir::EvalLocWide(RegLocation loc, int reg_class, bool update) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 921 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 922 | DCHECK(loc.wide); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 923 | int new_regs; |
| 924 | int low_reg; |
| 925 | int high_reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 926 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 927 | loc = UpdateLocWide(loc); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 928 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 929 | /* If already in registers, we can assume proper form. Right reg class? */ |
| 930 | if (loc.location == kLocPhysReg) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 931 | DCHECK_EQ(IsFpReg(loc.low_reg), IsFpReg(loc.high_reg)); |
| 932 | DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); |
| 933 | if (!RegClassMatches(reg_class, loc.low_reg)) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 934 | /* Wrong register class. Reallocate and copy */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 935 | new_regs = AllocTypedTempPair(loc.fp, reg_class); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 936 | low_reg = new_regs & 0xff; |
| 937 | high_reg = (new_regs >> 8) & 0xff; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 938 | OpRegCopyWide(low_reg, high_reg, loc.low_reg, loc.high_reg); |
| 939 | CopyRegInfo(low_reg, loc.low_reg); |
| 940 | CopyRegInfo(high_reg, loc.high_reg); |
| 941 | Clobber(loc.low_reg); |
| 942 | Clobber(loc.high_reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 943 | loc.low_reg = low_reg; |
| 944 | loc.high_reg = high_reg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 945 | MarkPair(loc.low_reg, loc.high_reg); |
| 946 | DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 947 | } |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 948 | return loc; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 949 | } |
| 950 | |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 951 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
| 952 | DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 953 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 954 | new_regs = AllocTypedTempPair(loc.fp, reg_class); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 955 | loc.low_reg = new_regs & 0xff; |
| 956 | loc.high_reg = (new_regs >> 8) & 0xff; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 957 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 958 | MarkPair(loc.low_reg, loc.high_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 959 | if (update) { |
| 960 | loc.location = kLocPhysReg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 961 | MarkLive(loc.low_reg, loc.s_reg_low); |
| 962 | MarkLive(loc.high_reg, GetSRegHi(loc.s_reg_low)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 963 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 964 | DCHECK(!IsFpReg(loc.low_reg) || ((loc.low_reg & 0x1) == 0)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 965 | return loc; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 966 | } |
| 967 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 968 | RegLocation Mir2Lir::EvalLoc(RegLocation loc, int reg_class, bool update) |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 969 | { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 970 | int new_reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 971 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 972 | if (loc.wide) |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 973 | return EvalLocWide(loc, reg_class, update); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 974 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 975 | loc = UpdateLoc(loc); |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 976 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 977 | if (loc.location == kLocPhysReg) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 978 | if (!RegClassMatches(reg_class, loc.low_reg)) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 979 | /* Wrong register class. Realloc, copy and transfer ownership */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 980 | new_reg = AllocTypedTemp(loc.fp, reg_class); |
| 981 | OpRegCopy(new_reg, loc.low_reg); |
| 982 | CopyRegInfo(new_reg, loc.low_reg); |
| 983 | Clobber(loc.low_reg); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 984 | loc.low_reg = new_reg; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 985 | } |
| 986 | return loc; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 987 | } |
| 988 | |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 989 | DCHECK_NE(loc.s_reg_low, INVALID_SREG); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 990 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 991 | new_reg = AllocTypedTemp(loc.fp, reg_class); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 992 | loc.low_reg = new_reg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 993 | |
| 994 | if (update) { |
| 995 | loc.location = kLocPhysReg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 996 | MarkLive(loc.low_reg, loc.s_reg_low); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 997 | } |
| 998 | return loc; |
buzbee | 67bf885 | 2011-08-17 17:51:35 -0700 | [diff] [blame] | 999 | } |
| 1000 | |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1001 | /* USE SSA names to count references of base Dalvik v_regs. */ |
buzbee | b0245ae | 2013-04-02 15:33:54 -0700 | [diff] [blame] | 1002 | void Mir2Lir::CountRefs(RefCounts* core_counts, RefCounts* fp_counts) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1003 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 1004 | RegLocation loc = mir_graph_->reg_location_[i]; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1005 | RefCounts* counts = loc.fp ? fp_counts : core_counts; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1006 | int p_map_idx = SRegToPMap(loc.s_reg_low); |
buzbee | 4ef3e45 | 2012-12-14 13:35:28 -0800 | [diff] [blame] | 1007 | //Don't count easily regenerated immediates |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1008 | if (loc.fp || !IsInexpensiveConstant(loc)) { |
| 1009 | counts[p_map_idx].count += mir_graph_->GetUseCount(i); |
buzbee | 239c4e7 | 2012-03-16 08:42:29 -0700 | [diff] [blame] | 1010 | } |
buzbee | c7d1f91 | 2013-02-07 15:22:39 -0800 | [diff] [blame] | 1011 | if (loc.wide && loc.fp && !loc.high_word) { |
| 1012 | counts[p_map_idx].double_start = true; |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1013 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1014 | } |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1015 | } |
| 1016 | |
| 1017 | /* qsort callback function, sort descending */ |
buzbee | aad9438 | 2012-11-21 07:40:50 -0800 | [diff] [blame] | 1018 | static int SortCounts(const void *val1, const void *val2) |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1019 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1020 | const Mir2Lir::RefCounts* op1 = reinterpret_cast<const Mir2Lir::RefCounts*>(val1); |
| 1021 | const Mir2Lir::RefCounts* op2 = reinterpret_cast<const Mir2Lir::RefCounts*>(val2); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1022 | return (op1->count == op2->count) ? 0 : (op1->count < op2->count ? 1 : -1); |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1023 | } |
| 1024 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1025 | void Mir2Lir::DumpCounts(const RefCounts* arr, int size, const char* msg) |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1026 | { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1027 | LOG(INFO) << msg; |
| 1028 | for (int i = 0; i < size; i++) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1029 | LOG(INFO) << "s_reg[" << arr[i].s_reg << "]: " << arr[i].count; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1030 | } |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1031 | } |
| 1032 | |
| 1033 | /* |
| 1034 | * Note: some portions of this code required even if the kPromoteRegs |
| 1035 | * optimization is disabled. |
| 1036 | */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1037 | void Mir2Lir::DoPromotion() |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1038 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1039 | int reg_bias = cu_->num_compiler_temps + 1; |
| 1040 | int dalvik_regs = cu_->num_dalvik_registers; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1041 | int num_regs = dalvik_regs + reg_bias; |
buzbee | b0245ae | 2013-04-02 15:33:54 -0700 | [diff] [blame] | 1042 | const int promotion_threshold = 1; |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1043 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1044 | // Allow target code to add any special registers |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1045 | AdjustSpillMask(); |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1046 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1047 | /* |
| 1048 | * Simple register promotion. Just do a static count of the uses |
| 1049 | * of Dalvik registers. Note that we examine the SSA names, but |
| 1050 | * count based on original Dalvik register name. Count refs |
| 1051 | * separately based on type in order to give allocation |
| 1052 | * preference to fp doubles - which must be allocated sequential |
| 1053 | * physical single fp registers started with an even-numbered |
| 1054 | * reg. |
| 1055 | * TUNING: replace with linear scan once we have the ability |
| 1056 | * to describe register live ranges for GC. |
| 1057 | */ |
buzbee | 862a760 | 2013-04-05 10:58:54 -0700 | [diff] [blame^] | 1058 | RefCounts *core_regs = |
| 1059 | static_cast<RefCounts*>(arena_->NewMem(sizeof(RefCounts) * num_regs, true, |
| 1060 | ArenaAllocator::kAllocRegAlloc)); |
| 1061 | RefCounts *FpRegs = |
| 1062 | static_cast<RefCounts *>(arena_->NewMem(sizeof(RefCounts) * num_regs, true, |
| 1063 | ArenaAllocator::kAllocRegAlloc)); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1064 | // Set ssa names for original Dalvik registers |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1065 | for (int i = 0; i < dalvik_regs; i++) { |
| 1066 | core_regs[i].s_reg = FpRegs[i].s_reg = i; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1067 | } |
| 1068 | // Set ssa name for Method* |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1069 | core_regs[dalvik_regs].s_reg = mir_graph_->GetMethodSReg(); |
| 1070 | FpRegs[dalvik_regs].s_reg = mir_graph_->GetMethodSReg(); // For consistecy |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1071 | // Set ssa names for compiler_temps |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1072 | for (int i = 1; i <= cu_->num_compiler_temps; i++) { |
buzbee | 862a760 | 2013-04-05 10:58:54 -0700 | [diff] [blame^] | 1073 | CompilerTemp* ct = mir_graph_->compiler_temps_.Get(i); |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1074 | core_regs[dalvik_regs + i].s_reg = ct->s_reg; |
| 1075 | FpRegs[dalvik_regs + i].s_reg = ct->s_reg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1076 | } |
| 1077 | |
buzbee | b0245ae | 2013-04-02 15:33:54 -0700 | [diff] [blame] | 1078 | // Sum use counts of SSA regs by original Dalvik vreg. |
| 1079 | CountRefs(core_regs, FpRegs); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1080 | |
| 1081 | /* |
| 1082 | * Ideally, we'd allocate doubles starting with an even-numbered |
| 1083 | * register. Bias the counts to try to allocate any vreg that's |
| 1084 | * used as the start of a pair first. |
| 1085 | */ |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1086 | for (int i = 0; i < num_regs; i++) { |
| 1087 | if (FpRegs[i].double_start) { |
buzbee | 52a77fc | 2012-11-20 19:50:46 -0800 | [diff] [blame] | 1088 | FpRegs[i].count *= 2; |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1089 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1090 | } |
| 1091 | |
| 1092 | // Sort the count arrays |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1093 | qsort(core_regs, num_regs, sizeof(RefCounts), SortCounts); |
| 1094 | qsort(FpRegs, num_regs, sizeof(RefCounts), SortCounts); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1095 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1096 | if (cu_->verbose) { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1097 | DumpCounts(core_regs, num_regs, "Core regs after sort"); |
| 1098 | DumpCounts(FpRegs, num_regs, "Fp regs after sort"); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1099 | } |
| 1100 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1101 | if (!(cu_->disable_opt & (1 << kPromoteRegs))) { |
buzbee | 52a77fc | 2012-11-20 19:50:46 -0800 | [diff] [blame] | 1102 | // Promote FpRegs |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1103 | for (int i = 0; (i < num_regs) && |
| 1104 | (FpRegs[i].count >= promotion_threshold ); i++) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1105 | int p_map_idx = SRegToPMap(FpRegs[i].s_reg); |
| 1106 | if (promotion_map_[p_map_idx].fp_location != kLocPhysReg) { |
| 1107 | int reg = AllocPreservedFPReg(FpRegs[i].s_reg, |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1108 | FpRegs[i].double_start); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1109 | if (reg < 0) { |
| 1110 | break; // No more left |
| 1111 | } |
| 1112 | } |
buzbee | 239c4e7 | 2012-03-16 08:42:29 -0700 | [diff] [blame] | 1113 | } |
buzbee | 9c044ce | 2012-03-18 13:24:07 -0700 | [diff] [blame] | 1114 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1115 | // Promote core regs |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1116 | for (int i = 0; (i < num_regs) && |
buzbee | b0245ae | 2013-04-02 15:33:54 -0700 | [diff] [blame] | 1117 | (core_regs[i].count >= promotion_threshold); i++) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1118 | int p_map_idx = SRegToPMap(core_regs[i].s_reg); |
| 1119 | if (promotion_map_[p_map_idx].core_location != |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1120 | kLocPhysReg) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1121 | int reg = AllocPreservedCoreReg(core_regs[i].s_reg); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1122 | if (reg < 0) { |
| 1123 | break; // No more left |
| 1124 | } |
| 1125 | } |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1126 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1127 | } |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1128 | |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1129 | // Now, update SSA names to new home locations |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1130 | for (int i = 0; i < mir_graph_->GetNumSSARegs(); i++) { |
| 1131 | RegLocation *curr = &mir_graph_->reg_location_[i]; |
| 1132 | int p_map_idx = SRegToPMap(curr->s_reg_low); |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1133 | if (!curr->wide) { |
| 1134 | if (curr->fp) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1135 | if (promotion_map_[p_map_idx].fp_location == kLocPhysReg) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1136 | curr->location = kLocPhysReg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1137 | curr->low_reg = promotion_map_[p_map_idx].FpReg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1138 | curr->home = true; |
| 1139 | } |
| 1140 | } else { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1141 | if (promotion_map_[p_map_idx].core_location == kLocPhysReg) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1142 | curr->location = kLocPhysReg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1143 | curr->low_reg = promotion_map_[p_map_idx].core_reg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1144 | curr->home = true; |
| 1145 | } |
| 1146 | } |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1147 | curr->high_reg = INVALID_REG; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1148 | } else { |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1149 | if (curr->high_word) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1150 | continue; |
| 1151 | } |
| 1152 | if (curr->fp) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1153 | if ((promotion_map_[p_map_idx].fp_location == kLocPhysReg) && |
| 1154 | (promotion_map_[p_map_idx+1].fp_location == |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1155 | kLocPhysReg)) { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1156 | int low_reg = promotion_map_[p_map_idx].FpReg; |
| 1157 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1158 | // Doubles require pair of singles starting at even reg |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1159 | if (((low_reg & 0x1) == 0) && ((low_reg + 1) == high_reg)) { |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1160 | curr->location = kLocPhysReg; |
buzbee | fa57c47 | 2012-11-21 12:06:18 -0800 | [diff] [blame] | 1161 | curr->low_reg = low_reg; |
| 1162 | curr->high_reg = high_reg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1163 | curr->home = true; |
| 1164 | } |
| 1165 | } |
| 1166 | } else { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1167 | if ((promotion_map_[p_map_idx].core_location == kLocPhysReg) |
| 1168 | && (promotion_map_[p_map_idx+1].core_location == |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1169 | kLocPhysReg)) { |
| 1170 | curr->location = kLocPhysReg; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1171 | curr->low_reg = promotion_map_[p_map_idx].core_reg; |
| 1172 | curr->high_reg = promotion_map_[p_map_idx+1].core_reg; |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1173 | curr->home = true; |
| 1174 | } |
| 1175 | } |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1176 | } |
Bill Buzbee | a114add | 2012-05-03 15:00:40 -0700 | [diff] [blame] | 1177 | } |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1178 | if (cu_->verbose) { |
| 1179 | DumpPromotionMap(); |
buzbee | ca7a5e4 | 2012-08-20 11:12:18 -0700 | [diff] [blame] | 1180 | } |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1181 | } |
| 1182 | |
| 1183 | /* Returns sp-relative offset in bytes for a VReg */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1184 | int Mir2Lir::VRegOffset(int v_reg) |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1185 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1186 | return StackVisitor::GetVRegOffset(cu_->code_item, core_spill_mask_, |
| 1187 | fp_spill_mask_, frame_size_, v_reg); |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1188 | } |
| 1189 | |
| 1190 | /* Returns sp-relative offset in bytes for a SReg */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1191 | int Mir2Lir::SRegOffset(int s_reg) |
buzbee | e3acd07 | 2012-02-25 17:03:10 -0800 | [diff] [blame] | 1192 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1193 | return VRegOffset(mir_graph_->SRegToVReg(s_reg)); |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1194 | } |
| 1195 | |
| 1196 | /* Mark register usage state and return long retloc */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1197 | RegLocation Mir2Lir::GetReturnWide(bool is_double) |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1198 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1199 | RegLocation gpr_res = LocCReturnWide(); |
| 1200 | RegLocation fpr_res = LocCReturnDouble(); |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1201 | RegLocation res = is_double ? fpr_res : gpr_res; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1202 | Clobber(res.low_reg); |
| 1203 | Clobber(res.high_reg); |
| 1204 | LockTemp(res.low_reg); |
| 1205 | LockTemp(res.high_reg); |
| 1206 | MarkPair(res.low_reg, res.high_reg); |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1207 | return res; |
| 1208 | } |
| 1209 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1210 | RegLocation Mir2Lir::GetReturn(bool is_float) |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1211 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1212 | RegLocation gpr_res = LocCReturn(); |
| 1213 | RegLocation fpr_res = LocCReturnFloat(); |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1214 | RegLocation res = is_float ? fpr_res : gpr_res; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1215 | Clobber(res.low_reg); |
| 1216 | if (cu_->instruction_set == kMips) { |
| 1217 | MarkInUse(res.low_reg); |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1218 | } else { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1219 | LockTemp(res.low_reg); |
buzbee | 02031b1 | 2012-11-23 09:41:35 -0800 | [diff] [blame] | 1220 | } |
| 1221 | return res; |
| 1222 | } |
| 1223 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1224 | void Mir2Lir::SimpleRegAlloc() |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 1225 | { |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1226 | DoPromotion(); |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 1227 | |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1228 | if (cu_->verbose && !(cu_->disable_opt & (1 << kPromoteRegs))) { |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 1229 | LOG(INFO) << "After Promotion"; |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1230 | mir_graph_->DumpRegLocTable(mir_graph_->reg_location_, mir_graph_->GetNumSSARegs()); |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 1231 | } |
| 1232 | |
| 1233 | /* Set the frame size */ |
buzbee | 1fd3346 | 2013-03-25 13:40:45 -0700 | [diff] [blame] | 1234 | frame_size_ = ComputeFrameSize(); |
| 1235 | } |
| 1236 | |
| 1237 | /* |
| 1238 | * Get the "real" sreg number associated with an s_reg slot. In general, |
| 1239 | * s_reg values passed through codegen are the SSA names created by |
| 1240 | * dataflow analysis and refer to slot numbers in the mir_graph_->reg_location |
| 1241 | * array. However, renaming is accomplished by simply replacing RegLocation |
| 1242 | * entries in the reglocation[] array. Therefore, when location |
| 1243 | * records for operands are first created, we need to ask the locRecord |
| 1244 | * identified by the dataflow pass what it's new name is. |
| 1245 | */ |
| 1246 | int Mir2Lir::GetSRegHi(int lowSreg) { |
| 1247 | return (lowSreg == INVALID_SREG) ? INVALID_SREG : lowSreg + 1; |
| 1248 | } |
| 1249 | |
| 1250 | bool Mir2Lir::oat_live_out(int s_reg) { |
| 1251 | //For now. |
| 1252 | return true; |
| 1253 | } |
| 1254 | |
| 1255 | int Mir2Lir::oatSSASrc(MIR* mir, int num) { |
| 1256 | DCHECK_GT(mir->ssa_rep->num_uses, num); |
| 1257 | return mir->ssa_rep->uses[num]; |
buzbee | 311ca16 | 2013-02-28 15:56:43 -0800 | [diff] [blame] | 1258 | } |
| 1259 | |
Elliott Hughes | 11d1b0c | 2012-01-23 16:57:47 -0800 | [diff] [blame] | 1260 | } // namespace art |