| Douglas Leung | 200f040 | 2016-02-25 20:05:47 -0800 | [diff] [blame] | 1 | %default {"preinstr":"", "result":"a0", "chkzero":"0"} |
| 2 | /* |
| 3 | * Generic 32-bit binary operation. Provide an "instr" line that |
| 4 | * specifies an instruction that performs "result = a0 op a1". |
| 5 | * This could be a MIPS instruction or a function call. (If the result |
| 6 | * comes back in a register other than a0, you can override "result".) |
| 7 | * |
| 8 | * If "chkzero" is set to 1, we perform a divide-by-zero check on |
| 9 | * vCC (a1). Useful for integer division and modulus. Note that we |
| Roland Levillain | f1e74af | 2016-03-04 15:55:51 +0000 | [diff] [blame] | 10 | * *don't* check for (INT_MIN / -1) here, because the CPU handles it |
| 11 | * correctly. |
| Douglas Leung | 200f040 | 2016-02-25 20:05:47 -0800 | [diff] [blame] | 12 | * |
| 13 | * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, |
| 14 | * xor-int, shl-int, shr-int, ushr-int |
| 15 | */ |
| 16 | /* binop vAA, vBB, vCC */ |
| 17 | FETCH(a0, 1) # a0 <- CCBB |
| 18 | GET_OPA(rOBJ) # rOBJ <- AA |
| 19 | srl a3, a0, 8 # a3 <- CC |
| 20 | and a2, a0, 255 # a2 <- BB |
| 21 | GET_VREG(a1, a3) # a1 <- vCC |
| 22 | GET_VREG(a0, a2) # a0 <- vBB |
| 23 | .if $chkzero |
| 24 | # is second operand zero? |
| 25 | beqz a1, common_errDivideByZero |
| 26 | .endif |
| 27 | |
| 28 | FETCH_ADVANCE_INST(2) # advance rPC, load rINST |
| 29 | $preinstr # optional op |
| 30 | $instr # $result <- op, a0-a3 changed |
| 31 | GET_INST_OPCODE(t0) # extract opcode from rINST |
| 32 | SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result |
| 33 | /* 11-14 instructions */ |