| Douglas Leung | 200f040 | 2016-02-25 20:05:47 -0800 | [diff] [blame] | 1 | %default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"} |
| 2 | /* |
| 3 | * Generic 64-bit "/2addr" binary operation. Provide an "instr" line |
| 4 | * that specifies an instruction that performs "result = a0-a1 op a2-a3". |
| 5 | * This could be a MIPS instruction or a function call. (If the result |
| 6 | * comes back in a register other than a0, you can override "result".) |
| 7 | * |
| 8 | * If "chkzero" is set to 1, we perform a divide-by-zero check on |
| 9 | * vCC (a1). Useful for integer division and modulus. |
| 10 | * |
| 11 | * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, |
| 12 | * and-long/2addr, or-long/2addr, xor-long/2addr |
| 13 | * rem-double/2addr |
| 14 | */ |
| 15 | /* binop/2addr vA, vB */ |
| 16 | GET_OPA4(rOBJ) # rOBJ <- A+ |
| 17 | GET_OPB(a1) # a1 <- B |
| 18 | EAS2(a1, rFP, a1) # a1 <- &fp[B] |
| 19 | EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] |
| 20 | LOAD64($arg2, $arg3, a1) # a2/a3 <- vBB/vBB+1 |
| 21 | LOAD64($arg0, $arg1, t0) # a0/a1 <- vAA/vAA+1 |
| 22 | .if $chkzero |
| 23 | or t0, $arg2, $arg3 # second arg (a2-a3) is zero? |
| 24 | beqz t0, common_errDivideByZero |
| 25 | .endif |
| 26 | FETCH_ADVANCE_INST(1) # advance rPC, load rINST |
| 27 | |
| 28 | $preinstr # optional op |
| 29 | $instr # result <- op, a0-a3 changed |
| 30 | GET_INST_OPCODE(t0) # extract opcode from rINST |
| 31 | SET_VREG64($result0, $result1, rOBJ) # vAA/vAA+1 <- $result0/$result1 |
| 32 | GOTO_OPCODE(t0) # jump to next instruction |
| 33 | /* 12-15 instructions */ |