Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_ |
| 18 | #define ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_ |
| 19 | |
| 20 | #include <vector> |
Vladimir Marko | 80afd02 | 2015-05-19 18:08:00 +0100 | [diff] [blame] | 21 | |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame^] | 22 | #include "base/arena_containers.h" |
Vladimir Marko | 80afd02 | 2015-05-19 18:08:00 +0100 | [diff] [blame] | 23 | #include "base/bit_utils.h" |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 24 | #include "base/macros.h" |
| 25 | #include "constants_x86_64.h" |
| 26 | #include "globals.h" |
| 27 | #include "managed_register_x86_64.h" |
| 28 | #include "offsets.h" |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame^] | 29 | #include "utils/array_ref.h" |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 30 | #include "utils/assembler.h" |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 31 | |
| 32 | namespace art { |
| 33 | namespace x86_64 { |
| 34 | |
avignate | 5408b6b | 2014-06-04 17:59:44 +0700 | [diff] [blame] | 35 | // Encodes an immediate value for operands. |
| 36 | // |
| 37 | // Note: Immediates can be 64b on x86-64 for certain instructions, but are often restricted |
| 38 | // to 32b. |
| 39 | // |
| 40 | // Note: As we support cross-compilation, the value type must be int64_t. Please be aware of |
| 41 | // conversion rules in expressions regarding negation, especially size_t on 32b. |
Ian Rogers | cf7f191 | 2014-10-22 22:06:39 -0700 | [diff] [blame] | 42 | class Immediate : public ValueObject { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 43 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 44 | explicit Immediate(int64_t value_in) : value_(value_in) {} |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 45 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 46 | int64_t value() const { return value_; } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 47 | |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 48 | bool is_int8() const { return IsInt<8>(value_); } |
| 49 | bool is_uint8() const { return IsUint<8>(value_); } |
| 50 | bool is_int16() const { return IsInt<16>(value_); } |
| 51 | bool is_uint16() const { return IsUint<16>(value_); } |
| 52 | bool is_int32() const { return IsInt<32>(value_); } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 53 | |
| 54 | private: |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 55 | const int64_t value_; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 56 | }; |
| 57 | |
| 58 | |
Ian Rogers | cf7f191 | 2014-10-22 22:06:39 -0700 | [diff] [blame] | 59 | class Operand : public ValueObject { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 60 | public: |
| 61 | uint8_t mod() const { |
| 62 | return (encoding_at(0) >> 6) & 3; |
| 63 | } |
| 64 | |
| 65 | Register rm() const { |
| 66 | return static_cast<Register>(encoding_at(0) & 7); |
| 67 | } |
| 68 | |
| 69 | ScaleFactor scale() const { |
| 70 | return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3); |
| 71 | } |
| 72 | |
| 73 | Register index() const { |
| 74 | return static_cast<Register>((encoding_at(1) >> 3) & 7); |
| 75 | } |
| 76 | |
| 77 | Register base() const { |
| 78 | return static_cast<Register>(encoding_at(1) & 7); |
| 79 | } |
| 80 | |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 81 | uint8_t rex() const { |
| 82 | return rex_; |
| 83 | } |
| 84 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 85 | int8_t disp8() const { |
| 86 | CHECK_GE(length_, 2); |
| 87 | return static_cast<int8_t>(encoding_[length_ - 1]); |
| 88 | } |
| 89 | |
| 90 | int32_t disp32() const { |
| 91 | CHECK_GE(length_, 5); |
| 92 | int32_t value; |
| 93 | memcpy(&value, &encoding_[length_ - 4], sizeof(value)); |
| 94 | return value; |
| 95 | } |
| 96 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 97 | bool IsRegister(CpuRegister reg) const { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 98 | return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only. |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 99 | && ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match. |
| 100 | && (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 101 | } |
| 102 | |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 103 | AssemblerFixup* GetFixup() const { |
| 104 | return fixup_; |
| 105 | } |
| 106 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 107 | protected: |
| 108 | // Operand can be sub classed (e.g: Address). |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 109 | Operand() : rex_(0), length_(0), fixup_(nullptr) { } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 110 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 111 | void SetModRM(uint8_t mod_in, CpuRegister rm_in) { |
| 112 | CHECK_EQ(mod_in & ~3, 0); |
| 113 | if (rm_in.NeedsRex()) { |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 114 | rex_ |= 0x41; // REX.000B |
| 115 | } |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 116 | encoding_[0] = (mod_in << 6) | rm_in.LowBits(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 117 | length_ = 1; |
| 118 | } |
| 119 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 120 | void SetSIB(ScaleFactor scale_in, CpuRegister index_in, CpuRegister base_in) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 121 | CHECK_EQ(length_, 1); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 122 | CHECK_EQ(scale_in & ~3, 0); |
| 123 | if (base_in.NeedsRex()) { |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 124 | rex_ |= 0x41; // REX.000B |
| 125 | } |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 126 | if (index_in.NeedsRex()) { |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 127 | rex_ |= 0x42; // REX.00X0 |
| 128 | } |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 129 | encoding_[1] = (scale_in << 6) | (static_cast<uint8_t>(index_in.LowBits()) << 3) | |
| 130 | static_cast<uint8_t>(base_in.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 131 | length_ = 2; |
| 132 | } |
| 133 | |
| 134 | void SetDisp8(int8_t disp) { |
| 135 | CHECK(length_ == 1 || length_ == 2); |
| 136 | encoding_[length_++] = static_cast<uint8_t>(disp); |
| 137 | } |
| 138 | |
| 139 | void SetDisp32(int32_t disp) { |
| 140 | CHECK(length_ == 1 || length_ == 2); |
| 141 | int disp_size = sizeof(disp); |
| 142 | memmove(&encoding_[length_], &disp, disp_size); |
| 143 | length_ += disp_size; |
| 144 | } |
| 145 | |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 146 | void SetFixup(AssemblerFixup* fixup) { |
| 147 | fixup_ = fixup; |
| 148 | } |
| 149 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 150 | private: |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 151 | uint8_t rex_; |
| 152 | uint8_t length_; |
| 153 | uint8_t encoding_[6]; |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 154 | AssemblerFixup* fixup_; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 155 | |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 156 | explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 157 | |
| 158 | // Get the operand encoding byte at the given index. |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 159 | uint8_t encoding_at(int index_in) const { |
| 160 | CHECK_GE(index_in, 0); |
| 161 | CHECK_LT(index_in, length_); |
| 162 | return encoding_[index_in]; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | friend class X86_64Assembler; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | |
| 169 | class Address : public Operand { |
| 170 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 171 | Address(CpuRegister base_in, int32_t disp) { |
| 172 | Init(base_in, disp); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 173 | } |
| 174 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 175 | Address(CpuRegister base_in, Offset disp) { |
| 176 | Init(base_in, disp.Int32Value()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 177 | } |
| 178 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 179 | Address(CpuRegister base_in, FrameOffset disp) { |
| 180 | CHECK_EQ(base_in.AsRegister(), RSP); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 181 | Init(CpuRegister(RSP), disp.Int32Value()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 182 | } |
| 183 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 184 | Address(CpuRegister base_in, MemberOffset disp) { |
| 185 | Init(base_in, disp.Int32Value()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 186 | } |
| 187 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 188 | void Init(CpuRegister base_in, int32_t disp) { |
Nicolas Geoffray | 784cc5c | 2014-12-18 20:25:18 +0000 | [diff] [blame] | 189 | if (disp == 0 && base_in.LowBits() != RBP) { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 190 | SetModRM(0, base_in); |
Nicolas Geoffray | 9889396 | 2015-01-21 12:32:32 +0000 | [diff] [blame] | 191 | if (base_in.LowBits() == RSP) { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 192 | SetSIB(TIMES_1, CpuRegister(RSP), base_in); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 193 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 194 | } else if (disp >= -128 && disp <= 127) { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 195 | SetModRM(1, base_in); |
Nicolas Geoffray | 9889396 | 2015-01-21 12:32:32 +0000 | [diff] [blame] | 196 | if (base_in.LowBits() == RSP) { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 197 | SetSIB(TIMES_1, CpuRegister(RSP), base_in); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 198 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 199 | SetDisp8(disp); |
| 200 | } else { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 201 | SetModRM(2, base_in); |
Nicolas Geoffray | 9889396 | 2015-01-21 12:32:32 +0000 | [diff] [blame] | 202 | if (base_in.LowBits() == RSP) { |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 203 | SetSIB(TIMES_1, CpuRegister(RSP), base_in); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 204 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 205 | SetDisp32(disp); |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 210 | Address(CpuRegister index_in, ScaleFactor scale_in, int32_t disp) { |
| 211 | CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 212 | SetModRM(0, CpuRegister(RSP)); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 213 | SetSIB(scale_in, index_in, CpuRegister(RBP)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 214 | SetDisp32(disp); |
| 215 | } |
| 216 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 217 | Address(CpuRegister base_in, CpuRegister index_in, ScaleFactor scale_in, int32_t disp) { |
| 218 | CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode. |
Nicolas Geoffray | 784cc5c | 2014-12-18 20:25:18 +0000 | [diff] [blame] | 219 | if (disp == 0 && base_in.LowBits() != RBP) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 220 | SetModRM(0, CpuRegister(RSP)); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 221 | SetSIB(scale_in, index_in, base_in); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 222 | } else if (disp >= -128 && disp <= 127) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 223 | SetModRM(1, CpuRegister(RSP)); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 224 | SetSIB(scale_in, index_in, base_in); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 225 | SetDisp8(disp); |
| 226 | } else { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 227 | SetModRM(2, CpuRegister(RSP)); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 228 | SetSIB(scale_in, index_in, base_in); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 229 | SetDisp32(disp); |
| 230 | } |
| 231 | } |
| 232 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 233 | // If no_rip is true then the Absolute address isn't RIP relative. |
Ian Rogers | 1373595 | 2014-10-08 12:43:28 -0700 | [diff] [blame] | 234 | static Address Absolute(uintptr_t addr, bool no_rip = false) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 235 | Address result; |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 236 | if (no_rip) { |
| 237 | result.SetModRM(0, CpuRegister(RSP)); |
| 238 | result.SetSIB(TIMES_1, CpuRegister(RSP), CpuRegister(RBP)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 239 | result.SetDisp32(addr); |
| 240 | } else { |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 241 | // RIP addressing is done using RBP as the base register. |
| 242 | // The value in RBP isn't used. Instead the offset is added to RIP. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 243 | result.SetModRM(0, CpuRegister(RBP)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 244 | result.SetDisp32(addr); |
| 245 | } |
| 246 | return result; |
| 247 | } |
| 248 | |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 249 | // An RIP relative address that will be fixed up later. |
| 250 | static Address RIP(AssemblerFixup* fixup) { |
| 251 | Address result; |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 252 | // RIP addressing is done using RBP as the base register. |
| 253 | // The value in RBP isn't used. Instead the offset is added to RIP. |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 254 | result.SetModRM(0, CpuRegister(RBP)); |
| 255 | result.SetDisp32(0); |
| 256 | result.SetFixup(fixup); |
| 257 | return result; |
| 258 | } |
| 259 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 260 | // If no_rip is true then the Absolute address isn't RIP relative. |
| 261 | static Address Absolute(ThreadOffset<8> addr, bool no_rip = false) { |
| 262 | return Absolute(addr.Int32Value(), no_rip); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | private: |
| 266 | Address() {} |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 270 | /** |
| 271 | * Class to handle constant area values. |
| 272 | */ |
| 273 | class ConstantArea { |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 274 | public: |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame^] | 275 | explicit ConstantArea(ArenaAllocator* arena) : buffer_(arena->Adapter(kArenaAllocAssembler)) {} |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 276 | |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 277 | // Add a double to the constant area, returning the offset into |
| 278 | // the constant area where the literal resides. |
| 279 | size_t AddDouble(double v); |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 280 | |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 281 | // Add a float to the constant area, returning the offset into |
| 282 | // the constant area where the literal resides. |
| 283 | size_t AddFloat(float v); |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 284 | |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 285 | // Add an int32_t to the constant area, returning the offset into |
| 286 | // the constant area where the literal resides. |
| 287 | size_t AddInt32(int32_t v); |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 288 | |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 289 | // Add an int32_t to the end of the constant area, returning the offset into |
| 290 | // the constant area where the literal resides. |
| 291 | size_t AppendInt32(int32_t v); |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 292 | |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 293 | // Add an int64_t to the constant area, returning the offset into |
| 294 | // the constant area where the literal resides. |
| 295 | size_t AddInt64(int64_t v); |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 296 | |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 297 | size_t GetSize() const { |
| 298 | return buffer_.size() * elem_size_; |
| 299 | } |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 300 | |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame^] | 301 | ArrayRef<const int32_t> GetBuffer() const { |
| 302 | return ArrayRef<const int32_t>(buffer_); |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 303 | } |
| 304 | |
| 305 | private: |
| 306 | static constexpr size_t elem_size_ = sizeof(int32_t); |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame^] | 307 | ArenaVector<int32_t> buffer_; |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 308 | }; |
| 309 | |
| 310 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 311 | // This is equivalent to the Label class, used in a slightly different context. We |
| 312 | // inherit the functionality of the Label class, but prevent unintended |
| 313 | // derived-to-base conversions by making the base class private. |
| 314 | class NearLabel : private Label { |
| 315 | public: |
| 316 | NearLabel() : Label() {} |
| 317 | |
| 318 | // Expose the Label routines that we need. |
| 319 | using Label::Position; |
| 320 | using Label::LinkPosition; |
| 321 | using Label::IsBound; |
| 322 | using Label::IsUnused; |
| 323 | using Label::IsLinked; |
| 324 | |
| 325 | private: |
| 326 | using Label::BindTo; |
| 327 | using Label::LinkTo; |
| 328 | |
| 329 | friend class x86_64::X86_64Assembler; |
| 330 | |
| 331 | DISALLOW_COPY_AND_ASSIGN(NearLabel); |
| 332 | }; |
| 333 | |
| 334 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 335 | class X86_64Assembler FINAL : public Assembler { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 336 | public: |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame^] | 337 | explicit X86_64Assembler(ArenaAllocator* arena) : Assembler(arena), constant_area_(arena) {} |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 338 | virtual ~X86_64Assembler() {} |
| 339 | |
| 340 | /* |
| 341 | * Emit Machine Instructions. |
| 342 | */ |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 343 | void call(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 344 | void call(const Address& address); |
| 345 | void call(Label* label); |
| 346 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 347 | void pushq(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 348 | void pushq(const Address& address); |
| 349 | void pushq(const Immediate& imm); |
| 350 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 351 | void popq(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 352 | void popq(const Address& address); |
| 353 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 354 | void movq(CpuRegister dst, const Immediate& src); |
| 355 | void movl(CpuRegister dst, const Immediate& src); |
| 356 | void movq(CpuRegister dst, CpuRegister src); |
| 357 | void movl(CpuRegister dst, CpuRegister src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 358 | |
Mark Mendell | 7a08fb5 | 2015-07-15 14:09:35 -0400 | [diff] [blame] | 359 | void movntl(const Address& dst, CpuRegister src); |
| 360 | void movntq(const Address& dst, CpuRegister src); |
| 361 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 362 | void movq(CpuRegister dst, const Address& src); |
| 363 | void movl(CpuRegister dst, const Address& src); |
| 364 | void movq(const Address& dst, CpuRegister src); |
Mark Mendell | cfa410b | 2015-05-25 16:02:44 -0400 | [diff] [blame] | 365 | void movq(const Address& dst, const Immediate& imm); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 366 | void movl(const Address& dst, CpuRegister src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 367 | void movl(const Address& dst, const Immediate& imm); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 368 | |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 369 | void cmov(Condition c, CpuRegister dst, CpuRegister src); // This is the 64b version. |
| 370 | void cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit); |
Mark Mendell | abdac47 | 2016-02-12 13:49:03 -0500 | [diff] [blame] | 371 | void cmov(Condition c, CpuRegister dst, const Address& src, bool is64bit); |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 372 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 373 | void movzxb(CpuRegister dst, CpuRegister src); |
| 374 | void movzxb(CpuRegister dst, const Address& src); |
| 375 | void movsxb(CpuRegister dst, CpuRegister src); |
| 376 | void movsxb(CpuRegister dst, const Address& src); |
| 377 | void movb(CpuRegister dst, const Address& src); |
| 378 | void movb(const Address& dst, CpuRegister src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 379 | void movb(const Address& dst, const Immediate& imm); |
| 380 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 381 | void movzxw(CpuRegister dst, CpuRegister src); |
| 382 | void movzxw(CpuRegister dst, const Address& src); |
| 383 | void movsxw(CpuRegister dst, CpuRegister src); |
| 384 | void movsxw(CpuRegister dst, const Address& src); |
| 385 | void movw(CpuRegister dst, const Address& src); |
| 386 | void movw(const Address& dst, CpuRegister src); |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 387 | void movw(const Address& dst, const Immediate& imm); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 388 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 389 | void leaq(CpuRegister dst, const Address& src); |
Nicolas Geoffray | 748f140 | 2015-01-27 08:17:54 +0000 | [diff] [blame] | 390 | void leal(CpuRegister dst, const Address& src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 391 | |
Nicolas Geoffray | 7fb49da | 2014-10-06 09:12:41 +0100 | [diff] [blame] | 392 | void movaps(XmmRegister dst, XmmRegister src); |
| 393 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 394 | void movss(XmmRegister dst, const Address& src); |
| 395 | void movss(const Address& dst, XmmRegister src); |
| 396 | void movss(XmmRegister dst, XmmRegister src); |
| 397 | |
Roland Levillain | dff1f28 | 2014-11-05 14:15:05 +0000 | [diff] [blame] | 398 | void movsxd(CpuRegister dst, CpuRegister src); |
| 399 | void movsxd(CpuRegister dst, const Address& src); |
| 400 | |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 401 | void movd(XmmRegister dst, CpuRegister src); // Note: this is the r64 version, formally movq. |
| 402 | void movd(CpuRegister dst, XmmRegister src); // Note: this is the r64 version, formally movq. |
| 403 | void movd(XmmRegister dst, CpuRegister src, bool is64bit); |
| 404 | void movd(CpuRegister dst, XmmRegister src, bool is64bit); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 405 | |
| 406 | void addss(XmmRegister dst, XmmRegister src); |
| 407 | void addss(XmmRegister dst, const Address& src); |
| 408 | void subss(XmmRegister dst, XmmRegister src); |
| 409 | void subss(XmmRegister dst, const Address& src); |
| 410 | void mulss(XmmRegister dst, XmmRegister src); |
| 411 | void mulss(XmmRegister dst, const Address& src); |
| 412 | void divss(XmmRegister dst, XmmRegister src); |
| 413 | void divss(XmmRegister dst, const Address& src); |
| 414 | |
| 415 | void movsd(XmmRegister dst, const Address& src); |
| 416 | void movsd(const Address& dst, XmmRegister src); |
| 417 | void movsd(XmmRegister dst, XmmRegister src); |
| 418 | |
| 419 | void addsd(XmmRegister dst, XmmRegister src); |
| 420 | void addsd(XmmRegister dst, const Address& src); |
| 421 | void subsd(XmmRegister dst, XmmRegister src); |
| 422 | void subsd(XmmRegister dst, const Address& src); |
| 423 | void mulsd(XmmRegister dst, XmmRegister src); |
| 424 | void mulsd(XmmRegister dst, const Address& src); |
| 425 | void divsd(XmmRegister dst, XmmRegister src); |
| 426 | void divsd(XmmRegister dst, const Address& src); |
| 427 | |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 428 | void cvtsi2ss(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version. |
Roland Levillain | 6d0e483 | 2014-11-27 18:31:21 +0000 | [diff] [blame] | 429 | void cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 430 | void cvtsi2ss(XmmRegister dst, const Address& src, bool is64bit); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 431 | void cvtsi2sd(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version. |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 432 | void cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 433 | void cvtsi2sd(XmmRegister dst, const Address& src, bool is64bit); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 434 | |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 435 | void cvtss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 436 | void cvtss2sd(XmmRegister dst, XmmRegister src); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 437 | void cvtss2sd(XmmRegister dst, const Address& src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 438 | |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 439 | void cvtsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 440 | void cvtsd2ss(XmmRegister dst, XmmRegister src); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 441 | void cvtsd2ss(XmmRegister dst, const Address& src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 442 | |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 443 | void cvttss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. |
Roland Levillain | 624279f | 2014-12-04 11:54:28 +0000 | [diff] [blame] | 444 | void cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 445 | void cvttsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version. |
Roland Levillain | 4c0b61f | 2014-12-05 12:06:01 +0000 | [diff] [blame] | 446 | void cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 447 | |
| 448 | void cvtdq2pd(XmmRegister dst, XmmRegister src); |
| 449 | |
| 450 | void comiss(XmmRegister a, XmmRegister b); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 451 | void comiss(XmmRegister a, const Address& b); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 452 | void comisd(XmmRegister a, XmmRegister b); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 453 | void comisd(XmmRegister a, const Address& b); |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 454 | void ucomiss(XmmRegister a, XmmRegister b); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 455 | void ucomiss(XmmRegister a, const Address& b); |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 456 | void ucomisd(XmmRegister a, XmmRegister b); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 457 | void ucomisd(XmmRegister a, const Address& b); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 458 | |
Mark Mendell | fb8d279 | 2015-03-31 22:16:59 -0400 | [diff] [blame] | 459 | void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm); |
| 460 | void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm); |
| 461 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 462 | void sqrtsd(XmmRegister dst, XmmRegister src); |
| 463 | void sqrtss(XmmRegister dst, XmmRegister src); |
| 464 | |
| 465 | void xorpd(XmmRegister dst, const Address& src); |
| 466 | void xorpd(XmmRegister dst, XmmRegister src); |
| 467 | void xorps(XmmRegister dst, const Address& src); |
| 468 | void xorps(XmmRegister dst, XmmRegister src); |
| 469 | |
| 470 | void andpd(XmmRegister dst, const Address& src); |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 471 | void andpd(XmmRegister dst, XmmRegister src); |
| 472 | void andps(XmmRegister dst, XmmRegister src); |
| 473 | |
| 474 | void orpd(XmmRegister dst, XmmRegister src); |
| 475 | void orps(XmmRegister dst, XmmRegister src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 476 | |
| 477 | void flds(const Address& src); |
| 478 | void fstps(const Address& dst); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 479 | void fsts(const Address& dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 480 | |
| 481 | void fldl(const Address& src); |
| 482 | void fstpl(const Address& dst); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 483 | void fstl(const Address& dst); |
| 484 | |
| 485 | void fstsw(); |
| 486 | |
| 487 | void fucompp(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 488 | |
| 489 | void fnstcw(const Address& dst); |
| 490 | void fldcw(const Address& src); |
| 491 | |
| 492 | void fistpl(const Address& dst); |
| 493 | void fistps(const Address& dst); |
| 494 | void fildl(const Address& src); |
Roland Levillain | 0a18601 | 2015-04-13 17:00:20 +0100 | [diff] [blame] | 495 | void filds(const Address& src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 496 | |
| 497 | void fincstp(); |
| 498 | void ffree(const Immediate& index); |
| 499 | |
| 500 | void fsin(); |
| 501 | void fcos(); |
| 502 | void fptan(); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 503 | void fprem(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 504 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 505 | void xchgl(CpuRegister dst, CpuRegister src); |
Nicolas Geoffray | ecb2f9b | 2014-06-13 08:59:59 +0000 | [diff] [blame] | 506 | void xchgq(CpuRegister dst, CpuRegister src); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 507 | void xchgl(CpuRegister reg, const Address& address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 508 | |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 509 | void cmpw(const Address& address, const Immediate& imm); |
| 510 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 511 | void cmpl(CpuRegister reg, const Immediate& imm); |
| 512 | void cmpl(CpuRegister reg0, CpuRegister reg1); |
| 513 | void cmpl(CpuRegister reg, const Address& address); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 514 | void cmpl(const Address& address, CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 515 | void cmpl(const Address& address, const Immediate& imm); |
| 516 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 517 | void cmpq(CpuRegister reg0, CpuRegister reg1); |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 518 | void cmpq(CpuRegister reg0, const Immediate& imm); |
| 519 | void cmpq(CpuRegister reg0, const Address& address); |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 520 | void cmpq(const Address& address, const Immediate& imm); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 521 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 522 | void testl(CpuRegister reg1, CpuRegister reg2); |
Calin Juravle | cd6dffe | 2015-01-08 17:35:35 +0000 | [diff] [blame] | 523 | void testl(CpuRegister reg, const Address& address); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 524 | void testl(CpuRegister reg, const Immediate& imm); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 525 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 526 | void testq(CpuRegister reg1, CpuRegister reg2); |
Nicolas Geoffray | f12feb8 | 2014-07-17 18:32:41 +0100 | [diff] [blame] | 527 | void testq(CpuRegister reg, const Address& address); |
| 528 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 529 | void andl(CpuRegister dst, const Immediate& imm); |
| 530 | void andl(CpuRegister dst, CpuRegister src); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 531 | void andl(CpuRegister reg, const Address& address); |
Nicolas Geoffray | 412f10c | 2014-06-19 10:00:34 +0100 | [diff] [blame] | 532 | void andq(CpuRegister dst, const Immediate& imm); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 533 | void andq(CpuRegister dst, CpuRegister src); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 534 | void andq(CpuRegister reg, const Address& address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 535 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 536 | void orl(CpuRegister dst, const Immediate& imm); |
| 537 | void orl(CpuRegister dst, CpuRegister src); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 538 | void orl(CpuRegister reg, const Address& address); |
| 539 | void orq(CpuRegister dst, CpuRegister src); |
Mark Mendell | 3f6c7f6 | 2015-03-13 13:47:53 -0400 | [diff] [blame] | 540 | void orq(CpuRegister dst, const Immediate& imm); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 541 | void orq(CpuRegister reg, const Address& address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 542 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 543 | void xorl(CpuRegister dst, CpuRegister src); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 544 | void xorl(CpuRegister dst, const Immediate& imm); |
| 545 | void xorl(CpuRegister reg, const Address& address); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 546 | void xorq(CpuRegister dst, const Immediate& imm); |
Nicolas Geoffray | 412f10c | 2014-06-19 10:00:34 +0100 | [diff] [blame] | 547 | void xorq(CpuRegister dst, CpuRegister src); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 548 | void xorq(CpuRegister reg, const Address& address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 549 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 550 | void addl(CpuRegister dst, CpuRegister src); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 551 | void addl(CpuRegister reg, const Immediate& imm); |
| 552 | void addl(CpuRegister reg, const Address& address); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 553 | void addl(const Address& address, CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 554 | void addl(const Address& address, const Immediate& imm); |
| 555 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 556 | void addq(CpuRegister reg, const Immediate& imm); |
| 557 | void addq(CpuRegister dst, CpuRegister src); |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 558 | void addq(CpuRegister dst, const Address& address); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 559 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 560 | void subl(CpuRegister dst, CpuRegister src); |
| 561 | void subl(CpuRegister reg, const Immediate& imm); |
| 562 | void subl(CpuRegister reg, const Address& address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 563 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 564 | void subq(CpuRegister reg, const Immediate& imm); |
| 565 | void subq(CpuRegister dst, CpuRegister src); |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 566 | void subq(CpuRegister dst, const Address& address); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 567 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 568 | void cdq(); |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 569 | void cqo(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 570 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 571 | void idivl(CpuRegister reg); |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 572 | void idivq(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 573 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 574 | void imull(CpuRegister dst, CpuRegister src); |
| 575 | void imull(CpuRegister reg, const Immediate& imm); |
Mark Mendell | 4a2aa4a | 2015-07-27 16:13:10 -0400 | [diff] [blame] | 576 | void imull(CpuRegister dst, CpuRegister src, const Immediate& imm); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 577 | void imull(CpuRegister reg, const Address& address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 578 | |
Guillaume Sanchez | 0f88e87 | 2015-03-30 17:55:45 +0100 | [diff] [blame] | 579 | void imulq(CpuRegister src); |
Calin Juravle | 34bacdf | 2014-10-07 20:23:36 +0100 | [diff] [blame] | 580 | void imulq(CpuRegister dst, CpuRegister src); |
| 581 | void imulq(CpuRegister reg, const Immediate& imm); |
| 582 | void imulq(CpuRegister reg, const Address& address); |
Mark Mendell | 3f6c7f6 | 2015-03-13 13:47:53 -0400 | [diff] [blame] | 583 | void imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm); |
Calin Juravle | 34bacdf | 2014-10-07 20:23:36 +0100 | [diff] [blame] | 584 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 585 | void imull(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 586 | void imull(const Address& address); |
| 587 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 588 | void mull(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 589 | void mull(const Address& address); |
| 590 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 591 | void shll(CpuRegister reg, const Immediate& imm); |
| 592 | void shll(CpuRegister operand, CpuRegister shifter); |
| 593 | void shrl(CpuRegister reg, const Immediate& imm); |
| 594 | void shrl(CpuRegister operand, CpuRegister shifter); |
| 595 | void sarl(CpuRegister reg, const Immediate& imm); |
| 596 | void sarl(CpuRegister operand, CpuRegister shifter); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 597 | |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 598 | void shlq(CpuRegister reg, const Immediate& imm); |
| 599 | void shlq(CpuRegister operand, CpuRegister shifter); |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 600 | void shrq(CpuRegister reg, const Immediate& imm); |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 601 | void shrq(CpuRegister operand, CpuRegister shifter); |
| 602 | void sarq(CpuRegister reg, const Immediate& imm); |
| 603 | void sarq(CpuRegister operand, CpuRegister shifter); |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 604 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 605 | void negl(CpuRegister reg); |
Roland Levillain | 2e07b4f | 2014-10-23 18:12:09 +0100 | [diff] [blame] | 606 | void negq(CpuRegister reg); |
Roland Levillain | 7056643 | 2014-10-24 16:20:17 +0100 | [diff] [blame] | 607 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 608 | void notl(CpuRegister reg); |
Roland Levillain | 7056643 | 2014-10-24 16:20:17 +0100 | [diff] [blame] | 609 | void notq(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 610 | |
| 611 | void enter(const Immediate& imm); |
| 612 | void leave(); |
| 613 | |
| 614 | void ret(); |
| 615 | void ret(const Immediate& imm); |
| 616 | |
| 617 | void nop(); |
| 618 | void int3(); |
| 619 | void hlt(); |
| 620 | |
| 621 | void j(Condition condition, Label* label); |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 622 | void j(Condition condition, NearLabel* label); |
| 623 | void jrcxz(NearLabel* label); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 624 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 625 | void jmp(CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 626 | void jmp(const Address& address); |
| 627 | void jmp(Label* label); |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 628 | void jmp(NearLabel* label); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 629 | |
| 630 | X86_64Assembler* lock(); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 631 | void cmpxchgl(const Address& address, CpuRegister reg); |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 632 | void cmpxchgq(const Address& address, CpuRegister reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 633 | |
| 634 | void mfence(); |
| 635 | |
| 636 | X86_64Assembler* gs(); |
| 637 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 638 | void setcc(Condition condition, CpuRegister dst); |
| 639 | |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 640 | void bswapl(CpuRegister dst); |
| 641 | void bswapq(CpuRegister dst); |
| 642 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 643 | void bsfl(CpuRegister dst, CpuRegister src); |
| 644 | void bsfl(CpuRegister dst, const Address& src); |
| 645 | void bsfq(CpuRegister dst, CpuRegister src); |
| 646 | void bsfq(CpuRegister dst, const Address& src); |
| 647 | |
Mark Mendell | 8ae3ffb | 2015-08-12 21:16:41 -0400 | [diff] [blame] | 648 | void bsrl(CpuRegister dst, CpuRegister src); |
| 649 | void bsrl(CpuRegister dst, const Address& src); |
| 650 | void bsrq(CpuRegister dst, CpuRegister src); |
| 651 | void bsrq(CpuRegister dst, const Address& src); |
| 652 | |
Aart Bik | 3f67e69 | 2016-01-15 14:35:12 -0800 | [diff] [blame] | 653 | void popcntl(CpuRegister dst, CpuRegister src); |
| 654 | void popcntl(CpuRegister dst, const Address& src); |
| 655 | void popcntq(CpuRegister dst, CpuRegister src); |
| 656 | void popcntq(CpuRegister dst, const Address& src); |
| 657 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 658 | void rorl(CpuRegister reg, const Immediate& imm); |
| 659 | void rorl(CpuRegister operand, CpuRegister shifter); |
| 660 | void roll(CpuRegister reg, const Immediate& imm); |
| 661 | void roll(CpuRegister operand, CpuRegister shifter); |
| 662 | |
| 663 | void rorq(CpuRegister reg, const Immediate& imm); |
| 664 | void rorq(CpuRegister operand, CpuRegister shifter); |
| 665 | void rolq(CpuRegister reg, const Immediate& imm); |
| 666 | void rolq(CpuRegister operand, CpuRegister shifter); |
| 667 | |
Andreas Gampe | 21030dd | 2015-05-07 14:46:15 -0700 | [diff] [blame] | 668 | void repne_scasw(); |
agicsaki | 71311f8 | 2015-07-27 11:34:13 -0700 | [diff] [blame] | 669 | void repe_cmpsw(); |
agicsaki | 970abfb | 2015-07-31 10:31:14 -0700 | [diff] [blame] | 670 | void repe_cmpsl(); |
agicsaki | 3fd0e6a | 2015-08-03 20:14:29 -0700 | [diff] [blame] | 671 | void repe_cmpsq(); |
Mark Mendell | b9c4bbe | 2015-07-01 14:26:52 -0400 | [diff] [blame] | 672 | void rep_movsw(); |
Andreas Gampe | 21030dd | 2015-05-07 14:46:15 -0700 | [diff] [blame] | 673 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 674 | // |
| 675 | // Macros for High-level operations. |
| 676 | // |
| 677 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 678 | void AddImmediate(CpuRegister reg, const Immediate& imm); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 679 | |
| 680 | void LoadDoubleConstant(XmmRegister dst, double value); |
| 681 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 682 | void LockCmpxchgl(const Address& address, CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 683 | lock()->cmpxchgl(address, reg); |
| 684 | } |
| 685 | |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 686 | void LockCmpxchgq(const Address& address, CpuRegister reg) { |
| 687 | lock()->cmpxchgq(address, reg); |
| 688 | } |
| 689 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 690 | // |
| 691 | // Misc. functionality |
| 692 | // |
| 693 | int PreferredLoopAlignment() { return 16; } |
| 694 | void Align(int alignment, int offset); |
Andreas Gampe | 85b62f2 | 2015-09-09 13:15:38 -0700 | [diff] [blame] | 695 | void Bind(Label* label) OVERRIDE; |
| 696 | void Jump(Label* label) OVERRIDE { |
| 697 | jmp(label); |
| 698 | } |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 699 | void Bind(NearLabel* label); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 700 | |
| 701 | // |
| 702 | // Overridden common assembler high-level functionality |
| 703 | // |
| 704 | |
| 705 | // Emit code that will create an activation on the stack |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 706 | void BuildFrame(size_t frame_size, ManagedRegister method_reg, |
| 707 | const std::vector<ManagedRegister>& callee_save_regs, |
| 708 | const ManagedRegisterEntrySpills& entry_spills) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 709 | |
| 710 | // Emit code that will remove an activation from the stack |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 711 | void RemoveFrame(size_t frame_size, const std::vector<ManagedRegister>& callee_save_regs) |
| 712 | OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 713 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 714 | void IncreaseFrameSize(size_t adjust) OVERRIDE; |
| 715 | void DecreaseFrameSize(size_t adjust) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 716 | |
| 717 | // Store routines |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 718 | void Store(FrameOffset offs, ManagedRegister src, size_t size) OVERRIDE; |
| 719 | void StoreRef(FrameOffset dest, ManagedRegister src) OVERRIDE; |
| 720 | void StoreRawPtr(FrameOffset dest, ManagedRegister src) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 721 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 722 | void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 723 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 724 | void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch) |
| 725 | OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 726 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 727 | void StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, |
| 728 | ManagedRegister scratch) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 729 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 730 | void StoreStackPointerToThread64(ThreadOffset<8> thr_offs) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 731 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 732 | void StoreSpanning(FrameOffset dest, ManagedRegister src, FrameOffset in_off, |
| 733 | ManagedRegister scratch) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 734 | |
| 735 | // Load routines |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 736 | void Load(ManagedRegister dest, FrameOffset src, size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 737 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 738 | void LoadFromThread64(ManagedRegister dest, ThreadOffset<8> src, size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 739 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 740 | void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 741 | |
Mathieu Chartier | e401d14 | 2015-04-22 13:56:20 -0700 | [diff] [blame] | 742 | void LoadRef(ManagedRegister dest, ManagedRegister base, MemberOffset offs, |
Roland Levillain | 4d02711 | 2015-07-01 15:41:14 +0100 | [diff] [blame] | 743 | bool unpoison_reference) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 744 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 745 | void LoadRawPtr(ManagedRegister dest, ManagedRegister base, Offset offs) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 746 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 747 | void LoadRawPtrFromThread64(ManagedRegister dest, ThreadOffset<8> offs) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 748 | |
| 749 | // Copying routines |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 750 | void Move(ManagedRegister dest, ManagedRegister src, size_t size); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 751 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 752 | void CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs, |
| 753 | ManagedRegister scratch) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 754 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 755 | void CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, ManagedRegister scratch) |
| 756 | OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 757 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 758 | void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister scratch) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 759 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 760 | void Copy(FrameOffset dest, FrameOffset src, ManagedRegister scratch, size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 761 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 762 | void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister scratch, |
| 763 | size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 764 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 765 | void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, ManagedRegister scratch, |
| 766 | size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 767 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 768 | void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister scratch, |
| 769 | size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 770 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 771 | void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset, |
| 772 | ManagedRegister scratch, size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 773 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 774 | void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset, |
| 775 | ManagedRegister scratch, size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 776 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 777 | void MemoryBarrier(ManagedRegister) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 778 | |
| 779 | // Sign extension |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 780 | void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 781 | |
| 782 | // Zero extension |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 783 | void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 784 | |
| 785 | // Exploit fast access in managed code to Thread::Current() |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 786 | void GetCurrentThread(ManagedRegister tr) OVERRIDE; |
| 787 | void GetCurrentThread(FrameOffset dest_offset, ManagedRegister scratch) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 788 | |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 789 | // Set up out_reg to hold a Object** into the handle scope, or to be null if the |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 790 | // value is null and null_allowed. in_reg holds a possibly stale reference |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 791 | // that can be used to avoid loading the handle scope entry to see if the value is |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 792 | // null. |
| 793 | void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, |
| 794 | ManagedRegister in_reg, bool null_allowed) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 795 | |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 796 | // Set up out_off to hold a Object** into the handle scope, or to be null if the |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 797 | // value is null and null_allowed. |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 798 | void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, |
| 799 | ManagedRegister scratch, bool null_allowed) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 800 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 801 | // src holds a handle scope entry (Object**) load this into dst |
| 802 | virtual void LoadReferenceFromHandleScope(ManagedRegister dst, |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 803 | ManagedRegister src); |
| 804 | |
| 805 | // Heap::VerifyObject on src. In some cases (such as a reference to this) we |
| 806 | // know that src may not be null. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 807 | void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE; |
| 808 | void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 809 | |
| 810 | // Call to address held at [base+offset] |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 811 | void Call(ManagedRegister base, Offset offset, ManagedRegister scratch) OVERRIDE; |
| 812 | void Call(FrameOffset base, Offset offset, ManagedRegister scratch) OVERRIDE; |
| 813 | void CallFromThread64(ThreadOffset<8> offset, ManagedRegister scratch) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 814 | |
| 815 | // Generate code to check if Thread::Current()->exception_ is non-null |
| 816 | // and branch to a ExceptionSlowPath if it is. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 817 | void ExceptionPoll(ManagedRegister scratch, size_t stack_adjust) OVERRIDE; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 818 | |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 819 | // Add a double to the constant area, returning the offset into |
| 820 | // the constant area where the literal resides. |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 821 | size_t AddDouble(double v) { return constant_area_.AddDouble(v); } |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 822 | |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 823 | // Add a float to the constant area, returning the offset into |
| 824 | // the constant area where the literal resides. |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 825 | size_t AddFloat(float v) { return constant_area_.AddFloat(v); } |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 826 | |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 827 | // Add an int32_t to the constant area, returning the offset into |
| 828 | // the constant area where the literal resides. |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 829 | size_t AddInt32(int32_t v) { |
| 830 | return constant_area_.AddInt32(v); |
| 831 | } |
| 832 | |
| 833 | // Add an int32_t to the end of the constant area, returning the offset into |
| 834 | // the constant area where the literal resides. |
| 835 | size_t AppendInt32(int32_t v) { |
| 836 | return constant_area_.AppendInt32(v); |
| 837 | } |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 838 | |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 839 | // Add an int64_t to the constant area, returning the offset into |
| 840 | // the constant area where the literal resides. |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 841 | size_t AddInt64(int64_t v) { return constant_area_.AddInt64(v); } |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 842 | |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 843 | // Add the contents of the constant area to the assembler buffer. |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 844 | void AddConstantArea(); |
| 845 | |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 846 | // Is the constant area empty? Return true if there are no literals in the constant area. |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 847 | bool IsConstantAreaEmpty() const { return constant_area_.GetSize() == 0; } |
| 848 | |
Mark Mendell | 9c86b48 | 2015-09-18 13:36:07 -0400 | [diff] [blame] | 849 | // Return the current size of the constant area. |
| 850 | size_t ConstantAreaSize() const { return constant_area_.GetSize(); } |
| 851 | |
Roland Levillain | 4d02711 | 2015-07-01 15:41:14 +0100 | [diff] [blame] | 852 | // |
| 853 | // Heap poisoning. |
| 854 | // |
| 855 | |
| 856 | // Poison a heap reference contained in `reg`. |
| 857 | void PoisonHeapReference(CpuRegister reg) { negl(reg); } |
| 858 | // Unpoison a heap reference contained in `reg`. |
| 859 | void UnpoisonHeapReference(CpuRegister reg) { negl(reg); } |
| 860 | // Unpoison a heap reference contained in `reg` if heap poisoning is enabled. |
| 861 | void MaybeUnpoisonHeapReference(CpuRegister reg) { |
| 862 | if (kPoisonHeapReferences) { |
| 863 | UnpoisonHeapReference(reg); |
| 864 | } |
| 865 | } |
| 866 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 867 | private: |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 868 | void EmitUint8(uint8_t value); |
| 869 | void EmitInt32(int32_t value); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 870 | void EmitInt64(int64_t value); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 871 | void EmitRegisterOperand(uint8_t rm, uint8_t reg); |
| 872 | void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg); |
| 873 | void EmitFixup(AssemblerFixup* fixup); |
| 874 | void EmitOperandSizeOverride(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 875 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 876 | void EmitOperand(uint8_t rm, const Operand& operand); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 877 | void EmitImmediate(const Immediate& imm); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 878 | void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 879 | void EmitLabel(Label* label, int instruction_size); |
| 880 | void EmitLabelLink(Label* label); |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 881 | void EmitLabelLink(NearLabel* label); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 882 | |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 883 | void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm); |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 884 | void EmitGenericShift(bool wide, int rm, CpuRegister operand, CpuRegister shifter); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 885 | |
| 886 | // If any input is not false, output the necessary rex prefix. |
| 887 | void EmitOptionalRex(bool force, bool w, bool r, bool x, bool b); |
| 888 | |
| 889 | // Emit a rex prefix byte if necessary for reg. ie if reg is a register in the range R8 to R15. |
| 890 | void EmitOptionalRex32(CpuRegister reg); |
| 891 | void EmitOptionalRex32(CpuRegister dst, CpuRegister src); |
| 892 | void EmitOptionalRex32(XmmRegister dst, XmmRegister src); |
| 893 | void EmitOptionalRex32(CpuRegister dst, XmmRegister src); |
| 894 | void EmitOptionalRex32(XmmRegister dst, CpuRegister src); |
| 895 | void EmitOptionalRex32(const Operand& operand); |
| 896 | void EmitOptionalRex32(CpuRegister dst, const Operand& operand); |
| 897 | void EmitOptionalRex32(XmmRegister dst, const Operand& operand); |
| 898 | |
| 899 | // Emit a REX.W prefix plus necessary register bit encodings. |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 900 | void EmitRex64(); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 901 | void EmitRex64(CpuRegister reg); |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 902 | void EmitRex64(const Operand& operand); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 903 | void EmitRex64(CpuRegister dst, CpuRegister src); |
| 904 | void EmitRex64(CpuRegister dst, const Operand& operand); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 905 | void EmitRex64(XmmRegister dst, const Operand& operand); |
Nicolas Geoffray | 102cbed | 2014-10-15 18:31:05 +0100 | [diff] [blame] | 906 | void EmitRex64(XmmRegister dst, CpuRegister src); |
Roland Levillain | 624279f | 2014-12-04 11:54:28 +0000 | [diff] [blame] | 907 | void EmitRex64(CpuRegister dst, XmmRegister src); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 908 | |
| 909 | // Emit a REX prefix to normalize byte registers plus necessary register bit encodings. |
| 910 | void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src); |
| 911 | void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 912 | |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 913 | ConstantArea constant_area_; |
| 914 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 915 | DISALLOW_COPY_AND_ASSIGN(X86_64Assembler); |
| 916 | }; |
| 917 | |
| 918 | inline void X86_64Assembler::EmitUint8(uint8_t value) { |
| 919 | buffer_.Emit<uint8_t>(value); |
| 920 | } |
| 921 | |
| 922 | inline void X86_64Assembler::EmitInt32(int32_t value) { |
| 923 | buffer_.Emit<int32_t>(value); |
| 924 | } |
| 925 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 926 | inline void X86_64Assembler::EmitInt64(int64_t value) { |
Roland Levillain | 55dcfb5 | 2014-10-24 18:09:09 +0100 | [diff] [blame] | 927 | // Write this 64-bit value as two 32-bit words for alignment reasons |
| 928 | // (this is essentially when running on ARM, which does not allow |
| 929 | // 64-bit unaligned accesses). We assume little-endianness here. |
| 930 | EmitInt32(Low32Bits(value)); |
| 931 | EmitInt32(High32Bits(value)); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 932 | } |
| 933 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 934 | inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 935 | CHECK_GE(rm, 0); |
| 936 | CHECK_LT(rm, 8); |
Nicolas Geoffray | 102cbed | 2014-10-15 18:31:05 +0100 | [diff] [blame] | 937 | buffer_.Emit<uint8_t>((0xC0 | (reg & 7)) + (rm << 3)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 938 | } |
| 939 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 940 | inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) { |
| 941 | EmitRegisterOperand(rm, static_cast<uint8_t>(reg.AsFloatRegister())); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 942 | } |
| 943 | |
| 944 | inline void X86_64Assembler::EmitFixup(AssemblerFixup* fixup) { |
| 945 | buffer_.EmitFixup(fixup); |
| 946 | } |
| 947 | |
| 948 | inline void X86_64Assembler::EmitOperandSizeOverride() { |
| 949 | EmitUint8(0x66); |
| 950 | } |
| 951 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 952 | } // namespace x86_64 |
| 953 | } // namespace art |
| 954 | |
| 955 | #endif // ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_ |