Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 1 | // Copyright 2011 Google Inc. All Rights Reserved. |
| 2 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 3 | #include "assembler_arm.h" |
| 4 | |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 5 | #include "logging.h" |
| 6 | #include "offsets.h" |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 7 | #include "thread.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 8 | #include "utils.h" |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 9 | |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 10 | namespace art { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 11 | namespace arm { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 12 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 13 | // Instruction encoding bits. |
| 14 | enum { |
| 15 | H = 1 << 5, // halfword (or byte) |
| 16 | L = 1 << 20, // load (or store) |
| 17 | S = 1 << 20, // set condition code (or leave unchanged) |
| 18 | W = 1 << 21, // writeback base register (or leave unchanged) |
| 19 | A = 1 << 21, // accumulate in multiply instruction (or not) |
| 20 | B = 1 << 22, // unsigned byte (or word) |
| 21 | N = 1 << 22, // long (or short) |
| 22 | U = 1 << 23, // positive (or negative) offset/index |
| 23 | P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing) |
| 24 | I = 1 << 25, // immediate shifter operand (or not) |
| 25 | |
| 26 | B0 = 1, |
| 27 | B1 = 1 << 1, |
| 28 | B2 = 1 << 2, |
| 29 | B3 = 1 << 3, |
| 30 | B4 = 1 << 4, |
| 31 | B5 = 1 << 5, |
| 32 | B6 = 1 << 6, |
| 33 | B7 = 1 << 7, |
| 34 | B8 = 1 << 8, |
| 35 | B9 = 1 << 9, |
| 36 | B10 = 1 << 10, |
| 37 | B11 = 1 << 11, |
| 38 | B12 = 1 << 12, |
| 39 | B16 = 1 << 16, |
| 40 | B17 = 1 << 17, |
| 41 | B18 = 1 << 18, |
| 42 | B19 = 1 << 19, |
| 43 | B20 = 1 << 20, |
| 44 | B21 = 1 << 21, |
| 45 | B22 = 1 << 22, |
| 46 | B23 = 1 << 23, |
| 47 | B24 = 1 << 24, |
| 48 | B25 = 1 << 25, |
| 49 | B26 = 1 << 26, |
| 50 | B27 = 1 << 27, |
| 51 | |
| 52 | // Instruction bit masks. |
| 53 | RdMask = 15 << 12, // in str instruction |
| 54 | CondMask = 15 << 28, |
| 55 | CoprocessorMask = 15 << 8, |
| 56 | OpCodeMask = 15 << 21, // in data-processing instructions |
| 57 | Imm24Mask = (1 << 24) - 1, |
| 58 | Off12Mask = (1 << 12) - 1, |
| 59 | |
| 60 | // ldrex/strex register field encodings. |
| 61 | kLdExRnShift = 16, |
| 62 | kLdExRtShift = 12, |
| 63 | kStrExRnShift = 16, |
| 64 | kStrExRdShift = 12, |
| 65 | kStrExRtShift = 0, |
| 66 | }; |
| 67 | |
| 68 | |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 69 | static const char* kRegisterNames[] = { |
| 70 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", |
| 71 | "fp", "ip", "sp", "lr", "pc" |
| 72 | }; |
| 73 | std::ostream& operator<<(std::ostream& os, const Register& rhs) { |
| 74 | if (rhs >= R0 && rhs <= PC) { |
| 75 | os << kRegisterNames[rhs]; |
| 76 | } else { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 77 | os << "Register[" << static_cast<int>(rhs) << "]"; |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 78 | } |
| 79 | return os; |
| 80 | } |
| 81 | |
| 82 | |
| 83 | std::ostream& operator<<(std::ostream& os, const SRegister& rhs) { |
| 84 | if (rhs >= S0 && rhs < kNumberOfSRegisters) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 85 | os << "s" << static_cast<int>(rhs); |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 86 | } else { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 87 | os << "SRegister[" << static_cast<int>(rhs) << "]"; |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 88 | } |
| 89 | return os; |
| 90 | } |
| 91 | |
| 92 | |
| 93 | std::ostream& operator<<(std::ostream& os, const DRegister& rhs) { |
| 94 | if (rhs >= D0 && rhs < kNumberOfDRegisters) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 95 | os << "d" << static_cast<int>(rhs); |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 96 | } else { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 97 | os << "DRegister[" << static_cast<int>(rhs) << "]"; |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 98 | } |
| 99 | return os; |
| 100 | } |
| 101 | |
| 102 | |
| 103 | static const char* kConditionNames[] = { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 104 | "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", |
| 105 | "LE", "AL", |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 106 | }; |
| 107 | std::ostream& operator<<(std::ostream& os, const Condition& rhs) { |
| 108 | if (rhs >= EQ && rhs <= AL) { |
| 109 | os << kConditionNames[rhs]; |
| 110 | } else { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 111 | os << "Condition[" << static_cast<int>(rhs) << "]"; |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 112 | } |
| 113 | return os; |
| 114 | } |
| 115 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 116 | void ArmAssembler::Emit(int32_t value) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 117 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 118 | buffer_.Emit<int32_t>(value); |
| 119 | } |
| 120 | |
| 121 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 122 | void ArmAssembler::EmitType01(Condition cond, |
| 123 | int type, |
| 124 | Opcode opcode, |
| 125 | int set_cc, |
| 126 | Register rn, |
| 127 | Register rd, |
| 128 | ShifterOperand so) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 129 | CHECK_NE(rd, kNoRegister); |
| 130 | CHECK_NE(cond, kNoCondition); |
| 131 | int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
| 132 | type << kTypeShift | |
| 133 | static_cast<int32_t>(opcode) << kOpcodeShift | |
| 134 | set_cc << kSShift | |
| 135 | static_cast<int32_t>(rn) << kRnShift | |
| 136 | static_cast<int32_t>(rd) << kRdShift | |
| 137 | so.encoding(); |
| 138 | Emit(encoding); |
| 139 | } |
| 140 | |
| 141 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 142 | void ArmAssembler::EmitType5(Condition cond, int offset, bool link) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 143 | CHECK_NE(cond, kNoCondition); |
| 144 | int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
| 145 | 5 << kTypeShift | |
| 146 | (link ? 1 : 0) << kLinkShift; |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 147 | Emit(ArmAssembler::EncodeBranchOffset(offset, encoding)); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 151 | void ArmAssembler::EmitMemOp(Condition cond, |
| 152 | bool load, |
| 153 | bool byte, |
| 154 | Register rd, |
| 155 | Address ad) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 156 | CHECK_NE(rd, kNoRegister); |
| 157 | CHECK_NE(cond, kNoCondition); |
| 158 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 159 | B26 | |
| 160 | (load ? L : 0) | |
| 161 | (byte ? B : 0) | |
| 162 | (static_cast<int32_t>(rd) << kRdShift) | |
| 163 | ad.encoding(); |
| 164 | Emit(encoding); |
| 165 | } |
| 166 | |
| 167 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 168 | void ArmAssembler::EmitMemOpAddressMode3(Condition cond, |
| 169 | int32_t mode, |
| 170 | Register rd, |
| 171 | Address ad) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 172 | CHECK_NE(rd, kNoRegister); |
| 173 | CHECK_NE(cond, kNoCondition); |
| 174 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 175 | B22 | |
| 176 | mode | |
| 177 | (static_cast<int32_t>(rd) << kRdShift) | |
| 178 | ad.encoding3(); |
| 179 | Emit(encoding); |
| 180 | } |
| 181 | |
| 182 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 183 | void ArmAssembler::EmitMultiMemOp(Condition cond, |
| 184 | BlockAddressMode am, |
| 185 | bool load, |
| 186 | Register base, |
| 187 | RegList regs) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 188 | CHECK_NE(base, kNoRegister); |
| 189 | CHECK_NE(cond, kNoCondition); |
| 190 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 191 | B27 | |
| 192 | am | |
| 193 | (load ? L : 0) | |
| 194 | (static_cast<int32_t>(base) << kRnShift) | |
| 195 | regs; |
| 196 | Emit(encoding); |
| 197 | } |
| 198 | |
| 199 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 200 | void ArmAssembler::EmitShiftImmediate(Condition cond, |
| 201 | Shift opcode, |
| 202 | Register rd, |
| 203 | Register rm, |
| 204 | ShifterOperand so) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 205 | CHECK_NE(cond, kNoCondition); |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 206 | CHECK_EQ(so.type(), 1U); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 207 | int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
| 208 | static_cast<int32_t>(MOV) << kOpcodeShift | |
| 209 | static_cast<int32_t>(rd) << kRdShift | |
| 210 | so.encoding() << kShiftImmShift | |
| 211 | static_cast<int32_t>(opcode) << kShiftShift | |
| 212 | static_cast<int32_t>(rm); |
| 213 | Emit(encoding); |
| 214 | } |
| 215 | |
| 216 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 217 | void ArmAssembler::EmitShiftRegister(Condition cond, |
| 218 | Shift opcode, |
| 219 | Register rd, |
| 220 | Register rm, |
| 221 | ShifterOperand so) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 222 | CHECK_NE(cond, kNoCondition); |
Elliott Hughes | 1f359b0 | 2011-07-17 14:27:17 -0700 | [diff] [blame] | 223 | CHECK_EQ(so.type(), 0U); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 224 | int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
| 225 | static_cast<int32_t>(MOV) << kOpcodeShift | |
| 226 | static_cast<int32_t>(rd) << kRdShift | |
| 227 | so.encoding() << kShiftRegisterShift | |
| 228 | static_cast<int32_t>(opcode) << kShiftShift | |
| 229 | B4 | |
| 230 | static_cast<int32_t>(rm); |
| 231 | Emit(encoding); |
| 232 | } |
| 233 | |
| 234 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 235 | void ArmAssembler::EmitBranch(Condition cond, Label* label, bool link) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 236 | if (label->IsBound()) { |
| 237 | EmitType5(cond, label->Position() - buffer_.Size(), link); |
| 238 | } else { |
| 239 | int position = buffer_.Size(); |
| 240 | // Use the offset field of the branch instruction for linking the sites. |
| 241 | EmitType5(cond, label->position_, link); |
| 242 | label->LinkTo(position); |
| 243 | } |
| 244 | } |
| 245 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 246 | void ArmAssembler::and_(Register rd, Register rn, ShifterOperand so, |
| 247 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 248 | EmitType01(cond, so.type(), AND, 0, rn, rd, so); |
| 249 | } |
| 250 | |
| 251 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 252 | void ArmAssembler::eor(Register rd, Register rn, ShifterOperand so, |
| 253 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 254 | EmitType01(cond, so.type(), EOR, 0, rn, rd, so); |
| 255 | } |
| 256 | |
| 257 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 258 | void ArmAssembler::sub(Register rd, Register rn, ShifterOperand so, |
| 259 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 260 | EmitType01(cond, so.type(), SUB, 0, rn, rd, so); |
| 261 | } |
| 262 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 263 | void ArmAssembler::rsb(Register rd, Register rn, ShifterOperand so, |
| 264 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 265 | EmitType01(cond, so.type(), RSB, 0, rn, rd, so); |
| 266 | } |
| 267 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 268 | void ArmAssembler::rsbs(Register rd, Register rn, ShifterOperand so, |
| 269 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 270 | EmitType01(cond, so.type(), RSB, 1, rn, rd, so); |
| 271 | } |
| 272 | |
| 273 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 274 | void ArmAssembler::add(Register rd, Register rn, ShifterOperand so, |
| 275 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 276 | EmitType01(cond, so.type(), ADD, 0, rn, rd, so); |
| 277 | } |
| 278 | |
| 279 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 280 | void ArmAssembler::adds(Register rd, Register rn, ShifterOperand so, |
| 281 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 282 | EmitType01(cond, so.type(), ADD, 1, rn, rd, so); |
| 283 | } |
| 284 | |
| 285 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 286 | void ArmAssembler::subs(Register rd, Register rn, ShifterOperand so, |
| 287 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 288 | EmitType01(cond, so.type(), SUB, 1, rn, rd, so); |
| 289 | } |
| 290 | |
| 291 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 292 | void ArmAssembler::adc(Register rd, Register rn, ShifterOperand so, |
| 293 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 294 | EmitType01(cond, so.type(), ADC, 0, rn, rd, so); |
| 295 | } |
| 296 | |
| 297 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 298 | void ArmAssembler::sbc(Register rd, Register rn, ShifterOperand so, |
| 299 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 300 | EmitType01(cond, so.type(), SBC, 0, rn, rd, so); |
| 301 | } |
| 302 | |
| 303 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 304 | void ArmAssembler::rsc(Register rd, Register rn, ShifterOperand so, |
| 305 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 306 | EmitType01(cond, so.type(), RSC, 0, rn, rd, so); |
| 307 | } |
| 308 | |
| 309 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 310 | void ArmAssembler::tst(Register rn, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 311 | CHECK_NE(rn, PC); // Reserve tst pc instruction for exception handler marker. |
| 312 | EmitType01(cond, so.type(), TST, 1, rn, R0, so); |
| 313 | } |
| 314 | |
| 315 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 316 | void ArmAssembler::teq(Register rn, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 317 | CHECK_NE(rn, PC); // Reserve teq pc instruction for exception handler marker. |
| 318 | EmitType01(cond, so.type(), TEQ, 1, rn, R0, so); |
| 319 | } |
| 320 | |
| 321 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 322 | void ArmAssembler::cmp(Register rn, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 323 | EmitType01(cond, so.type(), CMP, 1, rn, R0, so); |
| 324 | } |
| 325 | |
| 326 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 327 | void ArmAssembler::cmn(Register rn, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 328 | EmitType01(cond, so.type(), CMN, 1, rn, R0, so); |
| 329 | } |
| 330 | |
| 331 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 332 | void ArmAssembler::orr(Register rd, Register rn, |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 333 | ShifterOperand so, Condition cond) { |
| 334 | EmitType01(cond, so.type(), ORR, 0, rn, rd, so); |
| 335 | } |
| 336 | |
| 337 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 338 | void ArmAssembler::orrs(Register rd, Register rn, |
| 339 | ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 340 | EmitType01(cond, so.type(), ORR, 1, rn, rd, so); |
| 341 | } |
| 342 | |
| 343 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 344 | void ArmAssembler::mov(Register rd, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 345 | EmitType01(cond, so.type(), MOV, 0, R0, rd, so); |
| 346 | } |
| 347 | |
| 348 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 349 | void ArmAssembler::movs(Register rd, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 350 | EmitType01(cond, so.type(), MOV, 1, R0, rd, so); |
| 351 | } |
| 352 | |
| 353 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 354 | void ArmAssembler::bic(Register rd, Register rn, ShifterOperand so, |
| 355 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 356 | EmitType01(cond, so.type(), BIC, 0, rn, rd, so); |
| 357 | } |
| 358 | |
| 359 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 360 | void ArmAssembler::mvn(Register rd, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 361 | EmitType01(cond, so.type(), MVN, 0, R0, rd, so); |
| 362 | } |
| 363 | |
| 364 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 365 | void ArmAssembler::mvns(Register rd, ShifterOperand so, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 366 | EmitType01(cond, so.type(), MVN, 1, R0, rd, so); |
| 367 | } |
| 368 | |
| 369 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 370 | void ArmAssembler::clz(Register rd, Register rm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 371 | CHECK_NE(rd, kNoRegister); |
| 372 | CHECK_NE(rm, kNoRegister); |
| 373 | CHECK_NE(cond, kNoCondition); |
| 374 | CHECK_NE(rd, PC); |
| 375 | CHECK_NE(rm, PC); |
| 376 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 377 | B24 | B22 | B21 | (0xf << 16) | |
| 378 | (static_cast<int32_t>(rd) << kRdShift) | |
| 379 | (0xf << 8) | B4 | static_cast<int32_t>(rm); |
| 380 | Emit(encoding); |
| 381 | } |
| 382 | |
| 383 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 384 | void ArmAssembler::movw(Register rd, uint16_t imm16, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 385 | CHECK_NE(cond, kNoCondition); |
| 386 | int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
| 387 | B25 | B24 | ((imm16 >> 12) << 16) | |
| 388 | static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); |
| 389 | Emit(encoding); |
| 390 | } |
| 391 | |
| 392 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 393 | void ArmAssembler::movt(Register rd, uint16_t imm16, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 394 | CHECK_NE(cond, kNoCondition); |
| 395 | int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
| 396 | B25 | B24 | B22 | ((imm16 >> 12) << 16) | |
| 397 | static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); |
| 398 | Emit(encoding); |
| 399 | } |
| 400 | |
| 401 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 402 | void ArmAssembler::EmitMulOp(Condition cond, int32_t opcode, |
| 403 | Register rd, Register rn, |
| 404 | Register rm, Register rs) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 405 | CHECK_NE(rd, kNoRegister); |
| 406 | CHECK_NE(rn, kNoRegister); |
| 407 | CHECK_NE(rm, kNoRegister); |
| 408 | CHECK_NE(rs, kNoRegister); |
| 409 | CHECK_NE(cond, kNoCondition); |
| 410 | int32_t encoding = opcode | |
| 411 | (static_cast<int32_t>(cond) << kConditionShift) | |
| 412 | (static_cast<int32_t>(rn) << kRnShift) | |
| 413 | (static_cast<int32_t>(rd) << kRdShift) | |
| 414 | (static_cast<int32_t>(rs) << kRsShift) | |
| 415 | B7 | B4 | |
| 416 | (static_cast<int32_t>(rm) << kRmShift); |
| 417 | Emit(encoding); |
| 418 | } |
| 419 | |
| 420 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 421 | void ArmAssembler::mul(Register rd, Register rn, Register rm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 422 | // Assembler registers rd, rn, rm are encoded as rn, rm, rs. |
| 423 | EmitMulOp(cond, 0, R0, rd, rn, rm); |
| 424 | } |
| 425 | |
| 426 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 427 | void ArmAssembler::mla(Register rd, Register rn, Register rm, Register ra, |
| 428 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 429 | // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. |
| 430 | EmitMulOp(cond, B21, ra, rd, rn, rm); |
| 431 | } |
| 432 | |
| 433 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 434 | void ArmAssembler::mls(Register rd, Register rn, Register rm, Register ra, |
| 435 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 436 | // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. |
| 437 | EmitMulOp(cond, B22 | B21, ra, rd, rn, rm); |
| 438 | } |
| 439 | |
| 440 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 441 | void ArmAssembler::umull(Register rd_lo, Register rd_hi, Register rn, |
| 442 | Register rm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 443 | // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. |
| 444 | EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm); |
| 445 | } |
| 446 | |
| 447 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 448 | void ArmAssembler::ldr(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 449 | EmitMemOp(cond, true, false, rd, ad); |
| 450 | } |
| 451 | |
| 452 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 453 | void ArmAssembler::str(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 454 | EmitMemOp(cond, false, false, rd, ad); |
| 455 | } |
| 456 | |
| 457 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 458 | void ArmAssembler::ldrb(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 459 | EmitMemOp(cond, true, true, rd, ad); |
| 460 | } |
| 461 | |
| 462 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 463 | void ArmAssembler::strb(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 464 | EmitMemOp(cond, false, true, rd, ad); |
| 465 | } |
| 466 | |
| 467 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 468 | void ArmAssembler::ldrh(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 469 | EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad); |
| 470 | } |
| 471 | |
| 472 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 473 | void ArmAssembler::strh(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 474 | EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad); |
| 475 | } |
| 476 | |
| 477 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 478 | void ArmAssembler::ldrsb(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 479 | EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad); |
| 480 | } |
| 481 | |
| 482 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 483 | void ArmAssembler::ldrsh(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 484 | EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad); |
| 485 | } |
| 486 | |
| 487 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 488 | void ArmAssembler::ldrd(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 489 | CHECK_EQ(rd % 2, 0); |
| 490 | EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad); |
| 491 | } |
| 492 | |
| 493 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 494 | void ArmAssembler::strd(Register rd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 495 | CHECK_EQ(rd % 2, 0); |
| 496 | EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad); |
| 497 | } |
| 498 | |
| 499 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 500 | void ArmAssembler::ldm(BlockAddressMode am, |
| 501 | Register base, |
| 502 | RegList regs, |
| 503 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 504 | EmitMultiMemOp(cond, am, true, base, regs); |
| 505 | } |
| 506 | |
| 507 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 508 | void ArmAssembler::stm(BlockAddressMode am, |
| 509 | Register base, |
| 510 | RegList regs, |
| 511 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 512 | EmitMultiMemOp(cond, am, false, base, regs); |
| 513 | } |
| 514 | |
| 515 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 516 | void ArmAssembler::ldrex(Register rt, Register rn, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 517 | CHECK_NE(rn, kNoRegister); |
| 518 | CHECK_NE(rt, kNoRegister); |
| 519 | CHECK_NE(cond, kNoCondition); |
| 520 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 521 | B24 | |
| 522 | B23 | |
| 523 | L | |
| 524 | (static_cast<int32_t>(rn) << kLdExRnShift) | |
| 525 | (static_cast<int32_t>(rt) << kLdExRtShift) | |
| 526 | B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0; |
| 527 | Emit(encoding); |
| 528 | } |
| 529 | |
| 530 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 531 | void ArmAssembler::strex(Register rd, |
| 532 | Register rt, |
| 533 | Register rn, |
| 534 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 535 | CHECK_NE(rn, kNoRegister); |
| 536 | CHECK_NE(rd, kNoRegister); |
| 537 | CHECK_NE(rt, kNoRegister); |
| 538 | CHECK_NE(cond, kNoCondition); |
| 539 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 540 | B24 | |
| 541 | B23 | |
| 542 | (static_cast<int32_t>(rn) << kStrExRnShift) | |
| 543 | (static_cast<int32_t>(rd) << kStrExRdShift) | |
| 544 | B11 | B10 | B9 | B8 | B7 | B4 | |
| 545 | (static_cast<int32_t>(rt) << kStrExRtShift); |
| 546 | Emit(encoding); |
| 547 | } |
| 548 | |
| 549 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 550 | void ArmAssembler::clrex() { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 551 | int32_t encoding = (kSpecialCondition << kConditionShift) | |
| 552 | B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf; |
| 553 | Emit(encoding); |
| 554 | } |
| 555 | |
| 556 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 557 | void ArmAssembler::nop(Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 558 | CHECK_NE(cond, kNoCondition); |
| 559 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 560 | B25 | B24 | B21 | (0xf << 12); |
| 561 | Emit(encoding); |
| 562 | } |
| 563 | |
| 564 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 565 | void ArmAssembler::vmovsr(SRegister sn, Register rt, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 566 | CHECK_NE(sn, kNoSRegister); |
| 567 | CHECK_NE(rt, kNoRegister); |
| 568 | CHECK_NE(rt, SP); |
| 569 | CHECK_NE(rt, PC); |
| 570 | CHECK_NE(cond, kNoCondition); |
| 571 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 572 | B27 | B26 | B25 | |
| 573 | ((static_cast<int32_t>(sn) >> 1)*B16) | |
| 574 | (static_cast<int32_t>(rt)*B12) | B11 | B9 | |
| 575 | ((static_cast<int32_t>(sn) & 1)*B7) | B4; |
| 576 | Emit(encoding); |
| 577 | } |
| 578 | |
| 579 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 580 | void ArmAssembler::vmovrs(Register rt, SRegister sn, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 581 | CHECK_NE(sn, kNoSRegister); |
| 582 | CHECK_NE(rt, kNoRegister); |
| 583 | CHECK_NE(rt, SP); |
| 584 | CHECK_NE(rt, PC); |
| 585 | CHECK_NE(cond, kNoCondition); |
| 586 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 587 | B27 | B26 | B25 | B20 | |
| 588 | ((static_cast<int32_t>(sn) >> 1)*B16) | |
| 589 | (static_cast<int32_t>(rt)*B12) | B11 | B9 | |
| 590 | ((static_cast<int32_t>(sn) & 1)*B7) | B4; |
| 591 | Emit(encoding); |
| 592 | } |
| 593 | |
| 594 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 595 | void ArmAssembler::vmovsrr(SRegister sm, Register rt, Register rt2, |
| 596 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 597 | CHECK_NE(sm, kNoSRegister); |
| 598 | CHECK_NE(sm, S31); |
| 599 | CHECK_NE(rt, kNoRegister); |
| 600 | CHECK_NE(rt, SP); |
| 601 | CHECK_NE(rt, PC); |
| 602 | CHECK_NE(rt2, kNoRegister); |
| 603 | CHECK_NE(rt2, SP); |
| 604 | CHECK_NE(rt2, PC); |
| 605 | CHECK_NE(cond, kNoCondition); |
| 606 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 607 | B27 | B26 | B22 | |
| 608 | (static_cast<int32_t>(rt2)*B16) | |
| 609 | (static_cast<int32_t>(rt)*B12) | B11 | B9 | |
| 610 | ((static_cast<int32_t>(sm) & 1)*B5) | B4 | |
| 611 | (static_cast<int32_t>(sm) >> 1); |
| 612 | Emit(encoding); |
| 613 | } |
| 614 | |
| 615 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 616 | void ArmAssembler::vmovrrs(Register rt, Register rt2, SRegister sm, |
| 617 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 618 | CHECK_NE(sm, kNoSRegister); |
| 619 | CHECK_NE(sm, S31); |
| 620 | CHECK_NE(rt, kNoRegister); |
| 621 | CHECK_NE(rt, SP); |
| 622 | CHECK_NE(rt, PC); |
| 623 | CHECK_NE(rt2, kNoRegister); |
| 624 | CHECK_NE(rt2, SP); |
| 625 | CHECK_NE(rt2, PC); |
| 626 | CHECK_NE(rt, rt2); |
| 627 | CHECK_NE(cond, kNoCondition); |
| 628 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 629 | B27 | B26 | B22 | B20 | |
| 630 | (static_cast<int32_t>(rt2)*B16) | |
| 631 | (static_cast<int32_t>(rt)*B12) | B11 | B9 | |
| 632 | ((static_cast<int32_t>(sm) & 1)*B5) | B4 | |
| 633 | (static_cast<int32_t>(sm) >> 1); |
| 634 | Emit(encoding); |
| 635 | } |
| 636 | |
| 637 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 638 | void ArmAssembler::vmovdrr(DRegister dm, Register rt, Register rt2, |
| 639 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 640 | CHECK_NE(dm, kNoDRegister); |
| 641 | CHECK_NE(rt, kNoRegister); |
| 642 | CHECK_NE(rt, SP); |
| 643 | CHECK_NE(rt, PC); |
| 644 | CHECK_NE(rt2, kNoRegister); |
| 645 | CHECK_NE(rt2, SP); |
| 646 | CHECK_NE(rt2, PC); |
| 647 | CHECK_NE(cond, kNoCondition); |
| 648 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 649 | B27 | B26 | B22 | |
| 650 | (static_cast<int32_t>(rt2)*B16) | |
| 651 | (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | |
| 652 | ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | |
| 653 | (static_cast<int32_t>(dm) & 0xf); |
| 654 | Emit(encoding); |
| 655 | } |
| 656 | |
| 657 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 658 | void ArmAssembler::vmovrrd(Register rt, Register rt2, DRegister dm, |
| 659 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 660 | CHECK_NE(dm, kNoDRegister); |
| 661 | CHECK_NE(rt, kNoRegister); |
| 662 | CHECK_NE(rt, SP); |
| 663 | CHECK_NE(rt, PC); |
| 664 | CHECK_NE(rt2, kNoRegister); |
| 665 | CHECK_NE(rt2, SP); |
| 666 | CHECK_NE(rt2, PC); |
| 667 | CHECK_NE(rt, rt2); |
| 668 | CHECK_NE(cond, kNoCondition); |
| 669 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 670 | B27 | B26 | B22 | B20 | |
| 671 | (static_cast<int32_t>(rt2)*B16) | |
| 672 | (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 | |
| 673 | ((static_cast<int32_t>(dm) >> 4)*B5) | B4 | |
| 674 | (static_cast<int32_t>(dm) & 0xf); |
| 675 | Emit(encoding); |
| 676 | } |
| 677 | |
| 678 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 679 | void ArmAssembler::vldrs(SRegister sd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 680 | CHECK_NE(sd, kNoSRegister); |
| 681 | CHECK_NE(cond, kNoCondition); |
| 682 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 683 | B27 | B26 | B24 | B20 | |
| 684 | ((static_cast<int32_t>(sd) & 1)*B22) | |
| 685 | ((static_cast<int32_t>(sd) >> 1)*B12) | |
| 686 | B11 | B9 | ad.vencoding(); |
| 687 | Emit(encoding); |
| 688 | } |
| 689 | |
| 690 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 691 | void ArmAssembler::vstrs(SRegister sd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 692 | CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC); |
| 693 | CHECK_NE(sd, kNoSRegister); |
| 694 | CHECK_NE(cond, kNoCondition); |
| 695 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 696 | B27 | B26 | B24 | |
| 697 | ((static_cast<int32_t>(sd) & 1)*B22) | |
| 698 | ((static_cast<int32_t>(sd) >> 1)*B12) | |
| 699 | B11 | B9 | ad.vencoding(); |
| 700 | Emit(encoding); |
| 701 | } |
| 702 | |
| 703 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 704 | void ArmAssembler::vldrd(DRegister dd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 705 | CHECK_NE(dd, kNoDRegister); |
| 706 | CHECK_NE(cond, kNoCondition); |
| 707 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 708 | B27 | B26 | B24 | B20 | |
| 709 | ((static_cast<int32_t>(dd) >> 4)*B22) | |
| 710 | ((static_cast<int32_t>(dd) & 0xf)*B12) | |
| 711 | B11 | B9 | B8 | ad.vencoding(); |
| 712 | Emit(encoding); |
| 713 | } |
| 714 | |
| 715 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 716 | void ArmAssembler::vstrd(DRegister dd, Address ad, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 717 | CHECK_NE(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)), PC); |
| 718 | CHECK_NE(dd, kNoDRegister); |
| 719 | CHECK_NE(cond, kNoCondition); |
| 720 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 721 | B27 | B26 | B24 | |
| 722 | ((static_cast<int32_t>(dd) >> 4)*B22) | |
| 723 | ((static_cast<int32_t>(dd) & 0xf)*B12) | |
| 724 | B11 | B9 | B8 | ad.vencoding(); |
| 725 | Emit(encoding); |
| 726 | } |
| 727 | |
| 728 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 729 | void ArmAssembler::EmitVFPsss(Condition cond, int32_t opcode, |
| 730 | SRegister sd, SRegister sn, SRegister sm) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 731 | CHECK_NE(sd, kNoSRegister); |
| 732 | CHECK_NE(sn, kNoSRegister); |
| 733 | CHECK_NE(sm, kNoSRegister); |
| 734 | CHECK_NE(cond, kNoCondition); |
| 735 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 736 | B27 | B26 | B25 | B11 | B9 | opcode | |
| 737 | ((static_cast<int32_t>(sd) & 1)*B22) | |
| 738 | ((static_cast<int32_t>(sn) >> 1)*B16) | |
| 739 | ((static_cast<int32_t>(sd) >> 1)*B12) | |
| 740 | ((static_cast<int32_t>(sn) & 1)*B7) | |
| 741 | ((static_cast<int32_t>(sm) & 1)*B5) | |
| 742 | (static_cast<int32_t>(sm) >> 1); |
| 743 | Emit(encoding); |
| 744 | } |
| 745 | |
| 746 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 747 | void ArmAssembler::EmitVFPddd(Condition cond, int32_t opcode, |
| 748 | DRegister dd, DRegister dn, DRegister dm) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 749 | CHECK_NE(dd, kNoDRegister); |
| 750 | CHECK_NE(dn, kNoDRegister); |
| 751 | CHECK_NE(dm, kNoDRegister); |
| 752 | CHECK_NE(cond, kNoCondition); |
| 753 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 754 | B27 | B26 | B25 | B11 | B9 | B8 | opcode | |
| 755 | ((static_cast<int32_t>(dd) >> 4)*B22) | |
| 756 | ((static_cast<int32_t>(dn) & 0xf)*B16) | |
| 757 | ((static_cast<int32_t>(dd) & 0xf)*B12) | |
| 758 | ((static_cast<int32_t>(dn) >> 4)*B7) | |
| 759 | ((static_cast<int32_t>(dm) >> 4)*B5) | |
| 760 | (static_cast<int32_t>(dm) & 0xf); |
| 761 | Emit(encoding); |
| 762 | } |
| 763 | |
| 764 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 765 | void ArmAssembler::vmovs(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 766 | EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm); |
| 767 | } |
| 768 | |
| 769 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 770 | void ArmAssembler::vmovd(DRegister dd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 771 | EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm); |
| 772 | } |
| 773 | |
| 774 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 775 | bool ArmAssembler::vmovs(SRegister sd, float s_imm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 776 | uint32_t imm32 = bit_cast<uint32_t, float>(s_imm); |
| 777 | if (((imm32 & ((1 << 19) - 1)) == 0) && |
| 778 | ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) || |
| 779 | (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) { |
| 780 | uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) | |
| 781 | ((imm32 >> 19) & ((1 << 6) -1)); |
| 782 | EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf), |
| 783 | sd, S0, S0); |
| 784 | return true; |
| 785 | } |
| 786 | return false; |
| 787 | } |
| 788 | |
| 789 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 790 | bool ArmAssembler::vmovd(DRegister dd, double d_imm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 791 | uint64_t imm64 = bit_cast<uint64_t, double>(d_imm); |
| 792 | if (((imm64 & ((1LL << 48) - 1)) == 0) && |
| 793 | ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) || |
| 794 | (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) { |
| 795 | uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) | |
| 796 | ((imm64 >> 48) & ((1 << 6) -1)); |
| 797 | EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf), |
| 798 | dd, D0, D0); |
| 799 | return true; |
| 800 | } |
| 801 | return false; |
| 802 | } |
| 803 | |
| 804 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 805 | void ArmAssembler::vadds(SRegister sd, SRegister sn, SRegister sm, |
| 806 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 807 | EmitVFPsss(cond, B21 | B20, sd, sn, sm); |
| 808 | } |
| 809 | |
| 810 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 811 | void ArmAssembler::vaddd(DRegister dd, DRegister dn, DRegister dm, |
| 812 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 813 | EmitVFPddd(cond, B21 | B20, dd, dn, dm); |
| 814 | } |
| 815 | |
| 816 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 817 | void ArmAssembler::vsubs(SRegister sd, SRegister sn, SRegister sm, |
| 818 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 819 | EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm); |
| 820 | } |
| 821 | |
| 822 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 823 | void ArmAssembler::vsubd(DRegister dd, DRegister dn, DRegister dm, |
| 824 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 825 | EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm); |
| 826 | } |
| 827 | |
| 828 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 829 | void ArmAssembler::vmuls(SRegister sd, SRegister sn, SRegister sm, |
| 830 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 831 | EmitVFPsss(cond, B21, sd, sn, sm); |
| 832 | } |
| 833 | |
| 834 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 835 | void ArmAssembler::vmuld(DRegister dd, DRegister dn, DRegister dm, |
| 836 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 837 | EmitVFPddd(cond, B21, dd, dn, dm); |
| 838 | } |
| 839 | |
| 840 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 841 | void ArmAssembler::vmlas(SRegister sd, SRegister sn, SRegister sm, |
| 842 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 843 | EmitVFPsss(cond, 0, sd, sn, sm); |
| 844 | } |
| 845 | |
| 846 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 847 | void ArmAssembler::vmlad(DRegister dd, DRegister dn, DRegister dm, |
| 848 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 849 | EmitVFPddd(cond, 0, dd, dn, dm); |
| 850 | } |
| 851 | |
| 852 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 853 | void ArmAssembler::vmlss(SRegister sd, SRegister sn, SRegister sm, |
| 854 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 855 | EmitVFPsss(cond, B6, sd, sn, sm); |
| 856 | } |
| 857 | |
| 858 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 859 | void ArmAssembler::vmlsd(DRegister dd, DRegister dn, DRegister dm, |
| 860 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 861 | EmitVFPddd(cond, B6, dd, dn, dm); |
| 862 | } |
| 863 | |
| 864 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 865 | void ArmAssembler::vdivs(SRegister sd, SRegister sn, SRegister sm, |
| 866 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 867 | EmitVFPsss(cond, B23, sd, sn, sm); |
| 868 | } |
| 869 | |
| 870 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 871 | void ArmAssembler::vdivd(DRegister dd, DRegister dn, DRegister dm, |
| 872 | Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 873 | EmitVFPddd(cond, B23, dd, dn, dm); |
| 874 | } |
| 875 | |
| 876 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 877 | void ArmAssembler::vabss(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 878 | EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm); |
| 879 | } |
| 880 | |
| 881 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 882 | void ArmAssembler::vabsd(DRegister dd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 883 | EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm); |
| 884 | } |
| 885 | |
| 886 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 887 | void ArmAssembler::vnegs(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 888 | EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm); |
| 889 | } |
| 890 | |
| 891 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 892 | void ArmAssembler::vnegd(DRegister dd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 893 | EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm); |
| 894 | } |
| 895 | |
| 896 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 897 | void ArmAssembler::vsqrts(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 898 | EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm); |
| 899 | } |
| 900 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 901 | void ArmAssembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 902 | EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm); |
| 903 | } |
| 904 | |
| 905 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 906 | void ArmAssembler::EmitVFPsd(Condition cond, int32_t opcode, |
| 907 | SRegister sd, DRegister dm) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 908 | CHECK_NE(sd, kNoSRegister); |
| 909 | CHECK_NE(dm, kNoDRegister); |
| 910 | CHECK_NE(cond, kNoCondition); |
| 911 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 912 | B27 | B26 | B25 | B11 | B9 | opcode | |
| 913 | ((static_cast<int32_t>(sd) & 1)*B22) | |
| 914 | ((static_cast<int32_t>(sd) >> 1)*B12) | |
| 915 | ((static_cast<int32_t>(dm) >> 4)*B5) | |
| 916 | (static_cast<int32_t>(dm) & 0xf); |
| 917 | Emit(encoding); |
| 918 | } |
| 919 | |
| 920 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 921 | void ArmAssembler::EmitVFPds(Condition cond, int32_t opcode, |
| 922 | DRegister dd, SRegister sm) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 923 | CHECK_NE(dd, kNoDRegister); |
| 924 | CHECK_NE(sm, kNoSRegister); |
| 925 | CHECK_NE(cond, kNoCondition); |
| 926 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 927 | B27 | B26 | B25 | B11 | B9 | opcode | |
| 928 | ((static_cast<int32_t>(dd) >> 4)*B22) | |
| 929 | ((static_cast<int32_t>(dd) & 0xf)*B12) | |
| 930 | ((static_cast<int32_t>(sm) & 1)*B5) | |
| 931 | (static_cast<int32_t>(sm) >> 1); |
| 932 | Emit(encoding); |
| 933 | } |
| 934 | |
| 935 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 936 | void ArmAssembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 937 | EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm); |
| 938 | } |
| 939 | |
| 940 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 941 | void ArmAssembler::vcvtds(DRegister dd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 942 | EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm); |
| 943 | } |
| 944 | |
| 945 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 946 | void ArmAssembler::vcvtis(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 947 | EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm); |
| 948 | } |
| 949 | |
| 950 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 951 | void ArmAssembler::vcvtid(SRegister sd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 952 | EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm); |
| 953 | } |
| 954 | |
| 955 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 956 | void ArmAssembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 957 | EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm); |
| 958 | } |
| 959 | |
| 960 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 961 | void ArmAssembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 962 | EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm); |
| 963 | } |
| 964 | |
| 965 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 966 | void ArmAssembler::vcvtus(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 967 | EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm); |
| 968 | } |
| 969 | |
| 970 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 971 | void ArmAssembler::vcvtud(SRegister sd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 972 | EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm); |
| 973 | } |
| 974 | |
| 975 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 976 | void ArmAssembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 977 | EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm); |
| 978 | } |
| 979 | |
| 980 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 981 | void ArmAssembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 982 | EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm); |
| 983 | } |
| 984 | |
| 985 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 986 | void ArmAssembler::vcmps(SRegister sd, SRegister sm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 987 | EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm); |
| 988 | } |
| 989 | |
| 990 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 991 | void ArmAssembler::vcmpd(DRegister dd, DRegister dm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 992 | EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm); |
| 993 | } |
| 994 | |
| 995 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 996 | void ArmAssembler::vcmpsz(SRegister sd, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 997 | EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0); |
| 998 | } |
| 999 | |
| 1000 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1001 | void ArmAssembler::vcmpdz(DRegister dd, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1002 | EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0); |
| 1003 | } |
| 1004 | |
| 1005 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1006 | void ArmAssembler::vmstat(Condition cond) { // VMRS APSR_nzcv, FPSCR |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1007 | CHECK_NE(cond, kNoCondition); |
| 1008 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 1009 | B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | |
| 1010 | (static_cast<int32_t>(PC)*B12) | |
| 1011 | B11 | B9 | B4; |
| 1012 | Emit(encoding); |
| 1013 | } |
| 1014 | |
| 1015 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1016 | void ArmAssembler::svc(uint32_t imm24) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1017 | CHECK(IsUint(24, imm24)); |
| 1018 | int32_t encoding = (AL << kConditionShift) | B27 | B26 | B25 | B24 | imm24; |
| 1019 | Emit(encoding); |
| 1020 | } |
| 1021 | |
| 1022 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1023 | void ArmAssembler::bkpt(uint16_t imm16) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1024 | int32_t encoding = (AL << kConditionShift) | B24 | B21 | |
| 1025 | ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf); |
| 1026 | Emit(encoding); |
| 1027 | } |
| 1028 | |
| 1029 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1030 | void ArmAssembler::b(Label* label, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1031 | EmitBranch(cond, label, false); |
| 1032 | } |
| 1033 | |
| 1034 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1035 | void ArmAssembler::bl(Label* label, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1036 | EmitBranch(cond, label, true); |
| 1037 | } |
| 1038 | |
| 1039 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1040 | void ArmAssembler::blx(Register rm, Condition cond) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1041 | CHECK_NE(rm, kNoRegister); |
| 1042 | CHECK_NE(cond, kNoCondition); |
| 1043 | int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
| 1044 | B24 | B21 | (0xfff << 8) | B5 | B4 | |
| 1045 | (static_cast<int32_t>(rm) << kRmShift); |
| 1046 | Emit(encoding); |
| 1047 | } |
| 1048 | |
| 1049 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1050 | void ArmAssembler::MarkExceptionHandler(Label* label) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1051 | EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0)); |
| 1052 | Label l; |
| 1053 | b(&l); |
| 1054 | EmitBranch(AL, label, false); |
| 1055 | Bind(&l); |
| 1056 | } |
| 1057 | |
| 1058 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1059 | void ArmAssembler::Bind(Label* label) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1060 | CHECK(!label->IsBound()); |
| 1061 | int bound_pc = buffer_.Size(); |
| 1062 | while (label->IsLinked()) { |
| 1063 | int32_t position = label->Position(); |
| 1064 | int32_t next = buffer_.Load<int32_t>(position); |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1065 | int32_t encoded = ArmAssembler::EncodeBranchOffset(bound_pc - position, next); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1066 | buffer_.Store<int32_t>(position, encoded); |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1067 | label->position_ = ArmAssembler::DecodeBranchOffset(next); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1068 | } |
| 1069 | label->BindTo(bound_pc); |
| 1070 | } |
| 1071 | |
| 1072 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1073 | void ArmAssembler::EncodeUint32InTstInstructions(uint32_t data) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1074 | // TODO: Consider using movw ip, <16 bits>. |
| 1075 | while (!IsUint(8, data)) { |
| 1076 | tst(R0, ShifterOperand(data & 0xFF), VS); |
| 1077 | data >>= 8; |
| 1078 | } |
| 1079 | tst(R0, ShifterOperand(data), MI); |
| 1080 | } |
| 1081 | |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1082 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1083 | int32_t ArmAssembler::EncodeBranchOffset(int offset, int32_t inst) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1084 | // The offset is off by 8 due to the way the ARM CPUs read PC. |
| 1085 | offset -= 8; |
| 1086 | CHECK(IsAligned(offset, 4)); |
| 1087 | CHECK(IsInt(CountOneBits(kBranchOffsetMask), offset)); |
| 1088 | |
| 1089 | // Properly preserve only the bits supported in the instruction. |
| 1090 | offset >>= 2; |
| 1091 | offset &= kBranchOffsetMask; |
| 1092 | return (inst & ~kBranchOffsetMask) | offset; |
| 1093 | } |
| 1094 | |
| 1095 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1096 | int ArmAssembler::DecodeBranchOffset(int32_t inst) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 1097 | // Sign-extend, left-shift by 2, then add 8. |
| 1098 | return ((((inst & kBranchOffsetMask) << 8) >> 6) + 8); |
| 1099 | } |
| 1100 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1101 | void ArmAssembler::AddConstant(Register rd, int32_t value, Condition cond) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1102 | AddConstant(rd, rd, value, cond); |
| 1103 | } |
| 1104 | |
| 1105 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1106 | void ArmAssembler::AddConstant(Register rd, Register rn, int32_t value, |
| 1107 | Condition cond) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1108 | if (value == 0) { |
| 1109 | if (rd != rn) { |
| 1110 | mov(rd, ShifterOperand(rn), cond); |
| 1111 | } |
| 1112 | return; |
| 1113 | } |
| 1114 | // We prefer to select the shorter code sequence rather than selecting add for |
| 1115 | // positive values and sub for negatives ones, which would slightly improve |
| 1116 | // the readability of generated code for some constants. |
| 1117 | ShifterOperand shifter_op; |
| 1118 | if (ShifterOperand::CanHold(value, &shifter_op)) { |
| 1119 | add(rd, rn, shifter_op, cond); |
| 1120 | } else if (ShifterOperand::CanHold(-value, &shifter_op)) { |
| 1121 | sub(rd, rn, shifter_op, cond); |
| 1122 | } else { |
| 1123 | CHECK(rn != IP); |
| 1124 | if (ShifterOperand::CanHold(~value, &shifter_op)) { |
| 1125 | mvn(IP, shifter_op, cond); |
| 1126 | add(rd, rn, ShifterOperand(IP), cond); |
| 1127 | } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) { |
| 1128 | mvn(IP, shifter_op, cond); |
| 1129 | sub(rd, rn, ShifterOperand(IP), cond); |
| 1130 | } else { |
| 1131 | movw(IP, Low16Bits(value), cond); |
| 1132 | uint16_t value_high = High16Bits(value); |
| 1133 | if (value_high != 0) { |
| 1134 | movt(IP, value_high, cond); |
| 1135 | } |
| 1136 | add(rd, rn, ShifterOperand(IP), cond); |
| 1137 | } |
| 1138 | } |
| 1139 | } |
| 1140 | |
| 1141 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1142 | void ArmAssembler::AddConstantSetFlags(Register rd, Register rn, int32_t value, |
| 1143 | Condition cond) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1144 | ShifterOperand shifter_op; |
| 1145 | if (ShifterOperand::CanHold(value, &shifter_op)) { |
| 1146 | adds(rd, rn, shifter_op, cond); |
| 1147 | } else if (ShifterOperand::CanHold(-value, &shifter_op)) { |
| 1148 | subs(rd, rn, shifter_op, cond); |
| 1149 | } else { |
| 1150 | CHECK(rn != IP); |
| 1151 | if (ShifterOperand::CanHold(~value, &shifter_op)) { |
| 1152 | mvn(IP, shifter_op, cond); |
| 1153 | adds(rd, rn, ShifterOperand(IP), cond); |
| 1154 | } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) { |
| 1155 | mvn(IP, shifter_op, cond); |
| 1156 | subs(rd, rn, ShifterOperand(IP), cond); |
| 1157 | } else { |
| 1158 | movw(IP, Low16Bits(value), cond); |
| 1159 | uint16_t value_high = High16Bits(value); |
| 1160 | if (value_high != 0) { |
| 1161 | movt(IP, value_high, cond); |
| 1162 | } |
| 1163 | adds(rd, rn, ShifterOperand(IP), cond); |
| 1164 | } |
| 1165 | } |
| 1166 | } |
| 1167 | |
| 1168 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1169 | void ArmAssembler::LoadImmediate(Register rd, int32_t value, Condition cond) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1170 | ShifterOperand shifter_op; |
| 1171 | if (ShifterOperand::CanHold(value, &shifter_op)) { |
| 1172 | mov(rd, shifter_op, cond); |
| 1173 | } else if (ShifterOperand::CanHold(~value, &shifter_op)) { |
| 1174 | mvn(rd, shifter_op, cond); |
| 1175 | } else { |
| 1176 | movw(rd, Low16Bits(value), cond); |
| 1177 | uint16_t value_high = High16Bits(value); |
| 1178 | if (value_high != 0) { |
| 1179 | movt(rd, value_high, cond); |
| 1180 | } |
| 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | |
| 1185 | bool Address::CanHoldLoadOffset(LoadOperandType type, int offset) { |
| 1186 | switch (type) { |
| 1187 | case kLoadSignedByte: |
| 1188 | case kLoadSignedHalfword: |
| 1189 | case kLoadUnsignedHalfword: |
| 1190 | case kLoadWordPair: |
| 1191 | return IsAbsoluteUint(8, offset); // Addressing mode 3. |
| 1192 | case kLoadUnsignedByte: |
| 1193 | case kLoadWord: |
| 1194 | return IsAbsoluteUint(12, offset); // Addressing mode 2. |
| 1195 | case kLoadSWord: |
| 1196 | case kLoadDWord: |
| 1197 | return IsAbsoluteUint(10, offset); // VFP addressing mode. |
| 1198 | default: |
| 1199 | LOG(FATAL) << "UNREACHABLE"; |
| 1200 | return false; |
| 1201 | } |
| 1202 | } |
| 1203 | |
| 1204 | |
| 1205 | bool Address::CanHoldStoreOffset(StoreOperandType type, int offset) { |
| 1206 | switch (type) { |
| 1207 | case kStoreHalfword: |
| 1208 | case kStoreWordPair: |
| 1209 | return IsAbsoluteUint(8, offset); // Addressing mode 3. |
| 1210 | case kStoreByte: |
| 1211 | case kStoreWord: |
| 1212 | return IsAbsoluteUint(12, offset); // Addressing mode 2. |
| 1213 | case kStoreSWord: |
| 1214 | case kStoreDWord: |
| 1215 | return IsAbsoluteUint(10, offset); // VFP addressing mode. |
| 1216 | default: |
| 1217 | LOG(FATAL) << "UNREACHABLE"; |
| 1218 | return false; |
| 1219 | } |
| 1220 | } |
| 1221 | |
| 1222 | |
| 1223 | // Implementation note: this method must emit at most one instruction when |
| 1224 | // Address::CanHoldLoadOffset. |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1225 | void ArmAssembler::LoadFromOffset(LoadOperandType type, |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1226 | Register reg, |
| 1227 | Register base, |
| 1228 | int32_t offset, |
| 1229 | Condition cond) { |
| 1230 | if (!Address::CanHoldLoadOffset(type, offset)) { |
| 1231 | CHECK(base != IP); |
| 1232 | LoadImmediate(IP, offset, cond); |
| 1233 | add(IP, IP, ShifterOperand(base), cond); |
| 1234 | base = IP; |
| 1235 | offset = 0; |
| 1236 | } |
| 1237 | CHECK(Address::CanHoldLoadOffset(type, offset)); |
| 1238 | switch (type) { |
| 1239 | case kLoadSignedByte: |
| 1240 | ldrsb(reg, Address(base, offset), cond); |
| 1241 | break; |
| 1242 | case kLoadUnsignedByte: |
| 1243 | ldrb(reg, Address(base, offset), cond); |
| 1244 | break; |
| 1245 | case kLoadSignedHalfword: |
| 1246 | ldrsh(reg, Address(base, offset), cond); |
| 1247 | break; |
| 1248 | case kLoadUnsignedHalfword: |
| 1249 | ldrh(reg, Address(base, offset), cond); |
| 1250 | break; |
| 1251 | case kLoadWord: |
| 1252 | ldr(reg, Address(base, offset), cond); |
| 1253 | break; |
| 1254 | case kLoadWordPair: |
| 1255 | ldrd(reg, Address(base, offset), cond); |
| 1256 | break; |
| 1257 | default: |
| 1258 | LOG(FATAL) << "UNREACHABLE"; |
| 1259 | } |
| 1260 | } |
| 1261 | |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1262 | // Implementation note: this method must emit at most one instruction when |
| 1263 | // Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset. |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1264 | void ArmAssembler::LoadSFromOffset(SRegister reg, |
| 1265 | Register base, |
| 1266 | int32_t offset, |
| 1267 | Condition cond) { |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1268 | if (!Address::CanHoldLoadOffset(kLoadSWord, offset)) { |
| 1269 | CHECK_NE(base, IP); |
| 1270 | LoadImmediate(IP, offset, cond); |
| 1271 | add(IP, IP, ShifterOperand(base), cond); |
| 1272 | base = IP; |
| 1273 | offset = 0; |
| 1274 | } |
| 1275 | CHECK(Address::CanHoldLoadOffset(kLoadSWord, offset)); |
| 1276 | vldrs(reg, Address(base, offset), cond); |
| 1277 | } |
| 1278 | |
| 1279 | // Implementation note: this method must emit at most one instruction when |
| 1280 | // Address::CanHoldLoadOffset, as expected by JIT::GuardedLoadFromOffset. |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1281 | void ArmAssembler::LoadDFromOffset(DRegister reg, |
| 1282 | Register base, |
| 1283 | int32_t offset, |
| 1284 | Condition cond) { |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1285 | if (!Address::CanHoldLoadOffset(kLoadDWord, offset)) { |
| 1286 | CHECK_NE(base, IP); |
| 1287 | LoadImmediate(IP, offset, cond); |
| 1288 | add(IP, IP, ShifterOperand(base), cond); |
| 1289 | base = IP; |
| 1290 | offset = 0; |
| 1291 | } |
| 1292 | CHECK(Address::CanHoldLoadOffset(kLoadDWord, offset)); |
| 1293 | vldrd(reg, Address(base, offset), cond); |
| 1294 | } |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1295 | |
| 1296 | // Implementation note: this method must emit at most one instruction when |
| 1297 | // Address::CanHoldStoreOffset. |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1298 | void ArmAssembler::StoreToOffset(StoreOperandType type, |
| 1299 | Register reg, |
| 1300 | Register base, |
| 1301 | int32_t offset, |
| 1302 | Condition cond) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1303 | if (!Address::CanHoldStoreOffset(type, offset)) { |
| 1304 | CHECK(reg != IP); |
| 1305 | CHECK(base != IP); |
| 1306 | LoadImmediate(IP, offset, cond); |
| 1307 | add(IP, IP, ShifterOperand(base), cond); |
| 1308 | base = IP; |
| 1309 | offset = 0; |
| 1310 | } |
| 1311 | CHECK(Address::CanHoldStoreOffset(type, offset)); |
| 1312 | switch (type) { |
| 1313 | case kStoreByte: |
| 1314 | strb(reg, Address(base, offset), cond); |
| 1315 | break; |
| 1316 | case kStoreHalfword: |
| 1317 | strh(reg, Address(base, offset), cond); |
| 1318 | break; |
| 1319 | case kStoreWord: |
| 1320 | str(reg, Address(base, offset), cond); |
| 1321 | break; |
| 1322 | case kStoreWordPair: |
| 1323 | strd(reg, Address(base, offset), cond); |
| 1324 | break; |
| 1325 | default: |
| 1326 | LOG(FATAL) << "UNREACHABLE"; |
| 1327 | } |
| 1328 | } |
| 1329 | |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1330 | // Implementation note: this method must emit at most one instruction when |
| 1331 | // Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreToOffset. |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1332 | void ArmAssembler::StoreSToOffset(SRegister reg, |
| 1333 | Register base, |
| 1334 | int32_t offset, |
| 1335 | Condition cond) { |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1336 | if (!Address::CanHoldStoreOffset(kStoreSWord, offset)) { |
| 1337 | CHECK_NE(base, IP); |
| 1338 | LoadImmediate(IP, offset, cond); |
| 1339 | add(IP, IP, ShifterOperand(base), cond); |
| 1340 | base = IP; |
| 1341 | offset = 0; |
| 1342 | } |
| 1343 | CHECK(Address::CanHoldStoreOffset(kStoreSWord, offset)); |
| 1344 | vstrs(reg, Address(base, offset), cond); |
| 1345 | } |
| 1346 | |
| 1347 | // Implementation note: this method must emit at most one instruction when |
| 1348 | // Address::CanHoldStoreOffset, as expected by JIT::GuardedStoreSToOffset. |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1349 | void ArmAssembler::StoreDToOffset(DRegister reg, |
| 1350 | Register base, |
| 1351 | int32_t offset, |
| 1352 | Condition cond) { |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1353 | if (!Address::CanHoldStoreOffset(kStoreDWord, offset)) { |
| 1354 | CHECK_NE(base, IP); |
| 1355 | LoadImmediate(IP, offset, cond); |
| 1356 | add(IP, IP, ShifterOperand(base), cond); |
| 1357 | base = IP; |
| 1358 | offset = 0; |
| 1359 | } |
| 1360 | CHECK(Address::CanHoldStoreOffset(kStoreDWord, offset)); |
| 1361 | vstrd(reg, Address(base, offset), cond); |
| 1362 | } |
| 1363 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1364 | void ArmAssembler::Push(Register rd, Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1365 | str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond); |
| 1366 | } |
| 1367 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1368 | void ArmAssembler::Pop(Register rd, Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1369 | ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond); |
| 1370 | } |
| 1371 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1372 | void ArmAssembler::PushList(RegList regs, Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1373 | stm(DB_W, SP, regs, cond); |
| 1374 | } |
| 1375 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1376 | void ArmAssembler::PopList(RegList regs, Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1377 | ldm(IA_W, SP, regs, cond); |
| 1378 | } |
| 1379 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1380 | void ArmAssembler::Mov(Register rd, Register rm, Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1381 | if (rd != rm) { |
| 1382 | mov(rd, ShifterOperand(rm), cond); |
| 1383 | } |
| 1384 | } |
| 1385 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1386 | void ArmAssembler::Lsl(Register rd, Register rm, uint32_t shift_imm, |
| 1387 | Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1388 | CHECK_NE(shift_imm, 0u); // Do not use Lsl if no shift is wanted. |
| 1389 | mov(rd, ShifterOperand(rm, LSL, shift_imm), cond); |
| 1390 | } |
| 1391 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1392 | void ArmAssembler::Lsr(Register rd, Register rm, uint32_t shift_imm, |
| 1393 | Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1394 | CHECK_NE(shift_imm, 0u); // Do not use Lsr if no shift is wanted. |
| 1395 | if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. |
| 1396 | mov(rd, ShifterOperand(rm, LSR, shift_imm), cond); |
| 1397 | } |
| 1398 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1399 | void ArmAssembler::Asr(Register rd, Register rm, uint32_t shift_imm, |
| 1400 | Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1401 | CHECK_NE(shift_imm, 0u); // Do not use Asr if no shift is wanted. |
| 1402 | if (shift_imm == 32) shift_imm = 0; // Comply to UAL syntax. |
| 1403 | mov(rd, ShifterOperand(rm, ASR, shift_imm), cond); |
| 1404 | } |
| 1405 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1406 | void ArmAssembler::Ror(Register rd, Register rm, uint32_t shift_imm, |
| 1407 | Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1408 | CHECK_NE(shift_imm, 0u); // Use Rrx instruction. |
| 1409 | mov(rd, ShifterOperand(rm, ROR, shift_imm), cond); |
| 1410 | } |
| 1411 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1412 | void ArmAssembler::Rrx(Register rd, Register rm, Condition cond) { |
Carl Shapiro | 9b9ba28 | 2011-08-14 15:30:39 -0700 | [diff] [blame] | 1413 | mov(rd, ShifterOperand(rm, ROR, 0), cond); |
| 1414 | } |
| 1415 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1416 | void ArmAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1417 | const std::vector<ManagedRegister>& callee_save_regs) { |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 1418 | CHECK(IsAligned(frame_size, kStackAlignment)); |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1419 | CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister()); |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1420 | |
| 1421 | // Push callee saves and link register |
| 1422 | RegList push_list = 1 << LR; |
| 1423 | size_t pushed_values = 1; |
| 1424 | for (size_t i = 0; i < callee_save_regs.size(); i++) { |
| 1425 | Register reg = callee_save_regs.at(i).AsArm().AsCoreRegister(); |
| 1426 | push_list |= 1 << reg; |
| 1427 | pushed_values++; |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 1428 | } |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1429 | PushList(push_list); |
| 1430 | |
| 1431 | // Increase frame to required size |
| 1432 | CHECK_GT(frame_size, pushed_values * kPointerSize); // Must be at least space to push Method* |
| 1433 | size_t adjust = frame_size - (pushed_values * kPointerSize); |
| 1434 | IncreaseFrameSize(adjust); |
| 1435 | |
| 1436 | // Write out Method* |
| 1437 | StoreToOffset(kStoreWord, R0, SP, 0); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1438 | } |
| 1439 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1440 | void ArmAssembler::RemoveFrame(size_t frame_size, |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1441 | const std::vector<ManagedRegister>& callee_save_regs) { |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 1442 | CHECK(IsAligned(frame_size, kStackAlignment)); |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1443 | // Compute callee saves to pop and PC |
| 1444 | RegList pop_list = 1 << PC; |
| 1445 | size_t pop_values = 1; |
| 1446 | for (size_t i = 0; i < callee_save_regs.size(); i++) { |
| 1447 | Register reg = callee_save_regs.at(i).AsArm().AsCoreRegister(); |
| 1448 | pop_list |= 1 << reg; |
| 1449 | pop_values++; |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 1450 | } |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1451 | |
| 1452 | // Decrease frame to start of callee saves |
| 1453 | CHECK_GT(frame_size, pop_values * kPointerSize); |
| 1454 | size_t adjust = frame_size - (pop_values * kPointerSize); |
| 1455 | DecreaseFrameSize(adjust); |
| 1456 | |
| 1457 | // Pop callee saves and PC |
| 1458 | PopList(pop_list); |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 1459 | } |
| 1460 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1461 | void ArmAssembler::IncreaseFrameSize(size_t adjust) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1462 | AddConstant(SP, -adjust); |
| 1463 | } |
| 1464 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1465 | void ArmAssembler::DecreaseFrameSize(size_t adjust) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1466 | AddConstant(SP, adjust); |
| 1467 | } |
| 1468 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1469 | void ArmAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) { |
| 1470 | ArmManagedRegister src = msrc.AsArm(); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1471 | if (src.IsNoRegister()) { |
| 1472 | CHECK_EQ(0u, size); |
| 1473 | } else if (src.IsCoreRegister()) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1474 | CHECK_EQ(4u, size); |
| 1475 | StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1476 | } else if (src.IsRegisterPair()) { |
| 1477 | CHECK_EQ(8u, size); |
| 1478 | StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value()); |
| 1479 | StoreToOffset(kStoreWord, src.AsRegisterPairHigh(), |
| 1480 | SP, dest.Int32Value() + 4); |
| 1481 | } else if (src.IsSRegister()) { |
| 1482 | StoreSToOffset(src.AsSRegister(), SP, dest.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1483 | } else { |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1484 | CHECK(src.IsDRegister()); |
| 1485 | StoreDToOffset(src.AsDRegister(), SP, dest.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1486 | } |
| 1487 | } |
| 1488 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1489 | void ArmAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) { |
| 1490 | ArmManagedRegister src = msrc.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1491 | CHECK(src.IsCoreRegister()); |
| 1492 | StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); |
| 1493 | } |
| 1494 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1495 | void ArmAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) { |
| 1496 | ArmManagedRegister src = msrc.AsArm(); |
Ian Rogers | df20fe0 | 2011-07-20 20:34:16 -0700 | [diff] [blame] | 1497 | CHECK(src.IsCoreRegister()); |
| 1498 | StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); |
| 1499 | } |
| 1500 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1501 | void ArmAssembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc, |
| 1502 | FrameOffset in_off, ManagedRegister mscratch) { |
| 1503 | ArmManagedRegister src = msrc.AsArm(); |
| 1504 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | 7a99c11 | 2011-09-07 12:48:27 -0700 | [diff] [blame] | 1505 | StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); |
| 1506 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value()); |
| 1507 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4); |
| 1508 | } |
| 1509 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1510 | void ArmAssembler::CopyRef(FrameOffset dest, FrameOffset src, |
| 1511 | ManagedRegister mscratch) { |
| 1512 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1513 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value()); |
| 1514 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); |
| 1515 | } |
| 1516 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1517 | void ArmAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, |
| 1518 | MemberOffset offs) { |
| 1519 | ArmManagedRegister dest = mdest.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1520 | CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()); |
| 1521 | LoadFromOffset(kLoadWord, dest.AsCoreRegister(), |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1522 | base.AsArm().AsCoreRegister(), offs.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1523 | } |
| 1524 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1525 | void ArmAssembler::LoadRef(ManagedRegister mdest, FrameOffset src) { |
| 1526 | ArmManagedRegister dest = mdest.AsArm(); |
| 1527 | CHECK(dest.IsCoreRegister()); |
| 1528 | LoadFromOffset(kLoadWord, dest.AsCoreRegister(), |
| 1529 | SP, src.Int32Value()); |
| 1530 | } |
| 1531 | |
| 1532 | void ArmAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, |
Ian Rogers | a04d397 | 2011-08-17 11:33:44 -0700 | [diff] [blame] | 1533 | Offset offs) { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1534 | ArmManagedRegister dest = mdest.AsArm(); |
Ian Rogers | a04d397 | 2011-08-17 11:33:44 -0700 | [diff] [blame] | 1535 | CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()); |
| 1536 | LoadFromOffset(kLoadWord, dest.AsCoreRegister(), |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1537 | base.AsArm().AsCoreRegister(), offs.Int32Value()); |
Ian Rogers | a04d397 | 2011-08-17 11:33:44 -0700 | [diff] [blame] | 1538 | } |
| 1539 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1540 | void ArmAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, |
| 1541 | ManagedRegister mscratch) { |
| 1542 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1543 | CHECK(scratch.IsCoreRegister()); |
| 1544 | LoadImmediate(scratch.AsCoreRegister(), imm); |
| 1545 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); |
| 1546 | } |
| 1547 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1548 | void ArmAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm, |
| 1549 | ManagedRegister mscratch) { |
| 1550 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1551 | CHECK(scratch.IsCoreRegister()); |
| 1552 | LoadImmediate(scratch.AsCoreRegister(), imm); |
| 1553 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), TR, dest.Int32Value()); |
| 1554 | } |
| 1555 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1556 | void ArmAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) { |
| 1557 | ArmManagedRegister dest = mdest.AsArm(); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1558 | if (dest.IsNoRegister()) { |
| 1559 | CHECK_EQ(0u, size); |
| 1560 | } else if (dest.IsCoreRegister()) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1561 | CHECK_EQ(4u, size); |
| 1562 | LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value()); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1563 | } else if (dest.IsRegisterPair()) { |
| 1564 | CHECK_EQ(8u, size); |
| 1565 | LoadFromOffset(kLoadWord, dest.AsRegisterPairLow(), SP, src.Int32Value()); |
| 1566 | LoadFromOffset(kLoadWord, dest.AsRegisterPairHigh(), |
| 1567 | SP, src.Int32Value() + 4); |
| 1568 | } else if (dest.IsSRegister()) { |
| 1569 | LoadSFromOffset(dest.AsSRegister(), SP, src.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1570 | } else { |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1571 | CHECK(dest.IsDRegister()); |
| 1572 | LoadDFromOffset(dest.AsDRegister(), SP, src.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1573 | } |
| 1574 | } |
| 1575 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1576 | void ArmAssembler::LoadRawPtrFromThread(ManagedRegister mdest, |
| 1577 | ThreadOffset offs) { |
| 1578 | ArmManagedRegister dest = mdest.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1579 | CHECK(dest.IsCoreRegister()); |
| 1580 | LoadFromOffset(kLoadWord, dest.AsCoreRegister(), |
| 1581 | TR, offs.Int32Value()); |
| 1582 | } |
| 1583 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1584 | void ArmAssembler::CopyRawPtrFromThread(FrameOffset fr_offs, |
| 1585 | ThreadOffset thr_offs, |
| 1586 | ManagedRegister mscratch) { |
| 1587 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1588 | CHECK(scratch.IsCoreRegister()); |
| 1589 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1590 | TR, thr_offs.Int32Value()); |
| 1591 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), |
| 1592 | SP, fr_offs.Int32Value()); |
| 1593 | } |
| 1594 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1595 | void ArmAssembler::CopyRawPtrToThread(ThreadOffset thr_offs, |
| 1596 | FrameOffset fr_offs, |
| 1597 | ManagedRegister mscratch) { |
| 1598 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1599 | CHECK(scratch.IsCoreRegister()); |
| 1600 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1601 | SP, fr_offs.Int32Value()); |
| 1602 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), |
| 1603 | TR, thr_offs.Int32Value()); |
| 1604 | } |
| 1605 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1606 | void ArmAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs, |
| 1607 | FrameOffset fr_offs, |
| 1608 | ManagedRegister mscratch) { |
| 1609 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1610 | CHECK(scratch.IsCoreRegister()); |
| 1611 | AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value(), AL); |
| 1612 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), |
| 1613 | TR, thr_offs.Int32Value()); |
| 1614 | } |
| 1615 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1616 | void ArmAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) { |
Ian Rogers | 45a76cb | 2011-07-21 22:00:15 -0700 | [diff] [blame] | 1617 | StoreToOffset(kStoreWord, SP, TR, thr_offs.Int32Value()); |
| 1618 | } |
| 1619 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1620 | void ArmAssembler::Move(ManagedRegister mdest, ManagedRegister msrc) { |
| 1621 | ArmManagedRegister dest = mdest.AsArm(); |
| 1622 | ArmManagedRegister src = msrc.AsArm(); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1623 | if (!dest.Equals(src)) { |
| 1624 | if (dest.IsCoreRegister()) { |
| 1625 | CHECK(src.IsCoreRegister()); |
| 1626 | mov(dest.AsCoreRegister(), ShifterOperand(src.AsCoreRegister())); |
Ian Rogers | 7a99c11 | 2011-09-07 12:48:27 -0700 | [diff] [blame] | 1627 | } else if (dest.IsDRegister()) { |
| 1628 | CHECK(src.IsDRegister()); |
| 1629 | vmovd(dest.AsDRegister(), src.AsDRegister()); |
| 1630 | } else if (dest.IsSRegister()) { |
| 1631 | CHECK(src.IsSRegister()); |
| 1632 | vmovs(dest.AsSRegister(), src.AsSRegister()); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1633 | } else { |
Ian Rogers | 7a99c11 | 2011-09-07 12:48:27 -0700 | [diff] [blame] | 1634 | CHECK(dest.IsRegisterPair()); |
| 1635 | CHECK(src.IsRegisterPair()); |
| 1636 | // Ensure that the first move doesn't clobber the input of the second |
| 1637 | if (src.AsRegisterPairHigh() != dest.AsRegisterPairLow()) { |
| 1638 | mov(dest.AsRegisterPairLow(), ShifterOperand(src.AsRegisterPairLow())); |
| 1639 | mov(dest.AsRegisterPairHigh(), ShifterOperand(src.AsRegisterPairHigh())); |
| 1640 | } else { |
| 1641 | mov(dest.AsRegisterPairHigh(), ShifterOperand(src.AsRegisterPairHigh())); |
| 1642 | mov(dest.AsRegisterPairLow(), ShifterOperand(src.AsRegisterPairLow())); |
| 1643 | } |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1644 | } |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1645 | } |
| 1646 | } |
| 1647 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1648 | void ArmAssembler::Copy(FrameOffset dest, FrameOffset src, |
| 1649 | ManagedRegister mscratch, size_t size) { |
| 1650 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1651 | CHECK(scratch.IsCoreRegister()); |
Shih-wei Liao | 5381cf9 | 2011-07-27 00:28:04 -0700 | [diff] [blame] | 1652 | CHECK(size == 4 || size == 8); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1653 | if (size == 4) { |
| 1654 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1655 | SP, src.Int32Value()); |
| 1656 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), |
| 1657 | SP, dest.Int32Value()); |
Shih-wei Liao | 5381cf9 | 2011-07-27 00:28:04 -0700 | [diff] [blame] | 1658 | } else if (size == 8) { |
| 1659 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1660 | SP, src.Int32Value()); |
| 1661 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), |
| 1662 | SP, dest.Int32Value()); |
| 1663 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1664 | SP, src.Int32Value() + 4); |
| 1665 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), |
| 1666 | SP, dest.Int32Value() + 4); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1667 | } |
| 1668 | } |
| 1669 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1670 | void ArmAssembler::CreateSirtEntry(ManagedRegister mout_reg, |
| 1671 | FrameOffset sirt_offset, |
| 1672 | ManagedRegister min_reg, bool null_allowed) { |
| 1673 | ArmManagedRegister out_reg = mout_reg.AsArm(); |
| 1674 | ArmManagedRegister in_reg = min_reg.AsArm(); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1675 | CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1676 | CHECK(out_reg.IsCoreRegister()); |
| 1677 | if (null_allowed) { |
Ian Rogers | 408f79a | 2011-08-23 18:22:33 -0700 | [diff] [blame] | 1678 | // Null values get a SIRT entry value of 0. Otherwise, the SIRT entry is |
| 1679 | // the address in the SIRT holding the reference. |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1680 | // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1681 | if (in_reg.IsNoRegister()) { |
| 1682 | LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(), |
Ian Rogers | 408f79a | 2011-08-23 18:22:33 -0700 | [diff] [blame] | 1683 | SP, sirt_offset.Int32Value()); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1684 | in_reg = out_reg; |
| 1685 | } |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1686 | cmp(in_reg.AsCoreRegister(), ShifterOperand(0)); |
| 1687 | if (!out_reg.Equals(in_reg)) { |
| 1688 | LoadImmediate(out_reg.AsCoreRegister(), 0, EQ); |
| 1689 | } |
Ian Rogers | 408f79a | 2011-08-23 18:22:33 -0700 | [diff] [blame] | 1690 | AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value(), NE); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1691 | } else { |
Ian Rogers | 408f79a | 2011-08-23 18:22:33 -0700 | [diff] [blame] | 1692 | AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value(), AL); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1693 | } |
| 1694 | } |
| 1695 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1696 | void ArmAssembler::CreateSirtEntry(FrameOffset out_off, |
| 1697 | FrameOffset sirt_offset, |
| 1698 | ManagedRegister mscratch, |
| 1699 | bool null_allowed) { |
| 1700 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1701 | CHECK(scratch.IsCoreRegister()); |
| 1702 | if (null_allowed) { |
| 1703 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, |
Ian Rogers | 408f79a | 2011-08-23 18:22:33 -0700 | [diff] [blame] | 1704 | sirt_offset.Int32Value()); |
| 1705 | // Null values get a SIRT entry value of 0. Otherwise, the sirt entry is |
| 1706 | // the address in the SIRT holding the reference. |
| 1707 | // e.g. scratch = (scratch == 0) ? 0 : (SP+sirt_offset) |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1708 | cmp(scratch.AsCoreRegister(), ShifterOperand(0)); |
Ian Rogers | 408f79a | 2011-08-23 18:22:33 -0700 | [diff] [blame] | 1709 | AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), NE); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1710 | } else { |
Ian Rogers | 408f79a | 2011-08-23 18:22:33 -0700 | [diff] [blame] | 1711 | AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value(), AL); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1712 | } |
| 1713 | StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, out_off.Int32Value()); |
| 1714 | } |
| 1715 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1716 | void ArmAssembler::LoadReferenceFromSirt(ManagedRegister mout_reg, |
| 1717 | ManagedRegister min_reg) { |
| 1718 | ArmManagedRegister out_reg = mout_reg.AsArm(); |
| 1719 | ArmManagedRegister in_reg = min_reg.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1720 | CHECK(out_reg.IsCoreRegister()); |
| 1721 | CHECK(in_reg.IsCoreRegister()); |
| 1722 | Label null_arg; |
| 1723 | if (!out_reg.Equals(in_reg)) { |
| 1724 | LoadImmediate(out_reg.AsCoreRegister(), 0, EQ); |
| 1725 | } |
| 1726 | cmp(in_reg.AsCoreRegister(), ShifterOperand(0)); |
Ian Rogers | df20fe0 | 2011-07-20 20:34:16 -0700 | [diff] [blame] | 1727 | LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(), |
| 1728 | in_reg.AsCoreRegister(), 0, NE); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1729 | } |
| 1730 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1731 | void ArmAssembler::VerifyObject(ManagedRegister src, bool could_be_null) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1732 | // TODO: not validating references |
| 1733 | } |
| 1734 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1735 | void ArmAssembler::VerifyObject(FrameOffset src, bool could_be_null) { |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1736 | // TODO: not validating references |
| 1737 | } |
| 1738 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1739 | void ArmAssembler::Call(ManagedRegister mbase, Offset offset, |
| 1740 | ManagedRegister mscratch) { |
| 1741 | ArmManagedRegister base = mbase.AsArm(); |
| 1742 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 1743 | CHECK(base.IsCoreRegister()); |
| 1744 | CHECK(scratch.IsCoreRegister()); |
| 1745 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1746 | base.AsCoreRegister(), offset.Int32Value()); |
| 1747 | blx(scratch.AsCoreRegister()); |
| 1748 | // TODO: place reference map on call |
| 1749 | } |
| 1750 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1751 | void ArmAssembler::Call(FrameOffset base, Offset offset, |
| 1752 | ManagedRegister mscratch) { |
| 1753 | ArmManagedRegister scratch = mscratch.AsArm(); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1754 | CHECK(scratch.IsCoreRegister()); |
| 1755 | // Call *(*(SP + base) + offset) |
| 1756 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1757 | SP, base.Int32Value()); |
| 1758 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1759 | scratch.AsCoreRegister(), offset.Int32Value()); |
| 1760 | blx(scratch.AsCoreRegister()); |
| 1761 | // TODO: place reference map on call |
| 1762 | } |
| 1763 | |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1764 | void ArmAssembler::Call(ThreadOffset offset, ManagedRegister scratch) { |
| 1765 | UNIMPLEMENTED(FATAL); |
| 1766 | } |
| 1767 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1768 | void ArmAssembler::GetCurrentThread(ManagedRegister tr) { |
| 1769 | mov(tr.AsArm().AsCoreRegister(), ShifterOperand(TR)); |
Shih-wei Liao | 668512a | 2011-09-01 14:18:34 -0700 | [diff] [blame] | 1770 | } |
| 1771 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1772 | void ArmAssembler::GetCurrentThread(FrameOffset offset, |
| 1773 | ManagedRegister scratch) { |
Shih-wei Liao | 668512a | 2011-09-01 14:18:34 -0700 | [diff] [blame] | 1774 | StoreToOffset(kStoreWord, TR, SP, offset.Int32Value(), AL); |
| 1775 | } |
| 1776 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1777 | void ArmAssembler::SuspendPoll(ManagedRegister mscratch, |
| 1778 | ManagedRegister return_reg, |
| 1779 | FrameOffset return_save_location, |
| 1780 | size_t return_size) { |
| 1781 | ArmManagedRegister scratch = mscratch.AsArm(); |
| 1782 | ArmSuspendCountSlowPath* slow = |
| 1783 | new ArmSuspendCountSlowPath(return_reg.AsArm(), return_save_location, |
| 1784 | return_size); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1785 | buffer_.EnqueueSlowPath(slow); |
| 1786 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1787 | TR, Thread::SuspendCountOffset().Int32Value()); |
| 1788 | cmp(scratch.AsCoreRegister(), ShifterOperand(0)); |
| 1789 | b(slow->Entry(), NE); |
| 1790 | Bind(slow->Continuation()); |
| 1791 | } |
| 1792 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1793 | void ArmSuspendCountSlowPath::Emit(Assembler* sasm) { |
| 1794 | ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm); |
| 1795 | #define __ sp_asm-> |
| 1796 | __ Bind(&entry_); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1797 | // Save return value |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1798 | __ Store(return_save_location_, return_register_, return_size_); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1799 | // Pass top of stack as argument |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1800 | __ mov(R0, ShifterOperand(SP)); |
| 1801 | __ LoadFromOffset(kLoadWord, R12, TR, |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1802 | Thread::SuspendCountEntryPointOffset().Int32Value()); |
| 1803 | // Note: assume that link register will be spilled/filled on method entry/exit |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1804 | __ blx(R12); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1805 | // Reload return value |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1806 | __ Load(return_register_, return_save_location_, return_size_); |
| 1807 | __ b(&continuation_); |
| 1808 | #undef __ |
Ian Rogers | 45a76cb | 2011-07-21 22:00:15 -0700 | [diff] [blame] | 1809 | } |
| 1810 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1811 | void ArmAssembler::ExceptionPoll(ManagedRegister mscratch) { |
| 1812 | ArmManagedRegister scratch = mscratch.AsArm(); |
Ian Rogers | 67375ac | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1813 | ArmExceptionSlowPath* slow = new ArmExceptionSlowPath(scratch); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1814 | buffer_.EnqueueSlowPath(slow); |
| 1815 | LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), |
| 1816 | TR, Thread::ExceptionOffset().Int32Value()); |
| 1817 | cmp(scratch.AsCoreRegister(), ShifterOperand(0)); |
| 1818 | b(slow->Entry(), NE); |
Carl Shapiro | e2d373e | 2011-07-25 15:20:06 -0700 | [diff] [blame] | 1819 | } |
| 1820 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1821 | void ArmExceptionSlowPath::Emit(Assembler* sasm) { |
| 1822 | ArmAssembler* sp_asm = down_cast<ArmAssembler*>(sasm); |
| 1823 | #define __ sp_asm-> |
| 1824 | __ Bind(&entry_); |
Ian Rogers | 67375ac | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1825 | |
| 1826 | // Pass exception object as argument |
| 1827 | // Don't care about preserving R0 as this call won't return |
| 1828 | __ mov(R0, ShifterOperand(scratch_.AsCoreRegister())); |
| 1829 | // Set up call to Thread::Current()->pDeliverException |
| 1830 | __ LoadFromOffset(kLoadWord, R12, TR, OFFSETOF_MEMBER(Thread, pDeliverException)); |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1831 | __ blx(R12); |
Ian Rogers | 67375ac | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 1832 | // Call never returns |
| 1833 | __ bkpt(0); |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1834 | #undef __ |
Ian Rogers | 45a76cb | 2011-07-21 22:00:15 -0700 | [diff] [blame] | 1835 | } |
| 1836 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 1837 | } // namespace arm |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 1838 | } // namespace art |