Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "assembler_mips64.h" |
| 18 | |
| 19 | #include "base/casts.h" |
| 20 | #include "entrypoints/quick/quick_entrypoints.h" |
| 21 | #include "memory_region.h" |
| 22 | #include "thread.h" |
| 23 | |
| 24 | namespace art { |
| 25 | namespace mips64 { |
| 26 | |
| 27 | void Mips64Assembler::Emit(int32_t value) { |
| 28 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 29 | buffer_.Emit<int32_t>(value); |
| 30 | } |
| 31 | |
| 32 | void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, |
| 33 | int shamt, int funct) { |
| 34 | CHECK_NE(rs, kNoGpuRegister); |
| 35 | CHECK_NE(rt, kNoGpuRegister); |
| 36 | CHECK_NE(rd, kNoGpuRegister); |
| 37 | int32_t encoding = opcode << kOpcodeShift | |
| 38 | static_cast<int32_t>(rs) << kRsShift | |
| 39 | static_cast<int32_t>(rt) << kRtShift | |
| 40 | static_cast<int32_t>(rd) << kRdShift | |
| 41 | shamt << kShamtShift | |
| 42 | funct; |
| 43 | Emit(encoding); |
| 44 | } |
| 45 | |
| 46 | void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { |
| 47 | CHECK_NE(rs, kNoGpuRegister); |
| 48 | CHECK_NE(rt, kNoGpuRegister); |
| 49 | int32_t encoding = opcode << kOpcodeShift | |
| 50 | static_cast<int32_t>(rs) << kRsShift | |
| 51 | static_cast<int32_t>(rt) << kRtShift | |
| 52 | imm; |
| 53 | Emit(encoding); |
| 54 | } |
| 55 | |
| 56 | void Mips64Assembler::EmitJ(int opcode, int address) { |
| 57 | int32_t encoding = opcode << kOpcodeShift | |
| 58 | address; |
| 59 | Emit(encoding); |
| 60 | } |
| 61 | |
| 62 | void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, |
| 63 | int funct) { |
| 64 | CHECK_NE(ft, kNoFpuRegister); |
| 65 | CHECK_NE(fs, kNoFpuRegister); |
| 66 | CHECK_NE(fd, kNoFpuRegister); |
| 67 | int32_t encoding = opcode << kOpcodeShift | |
| 68 | fmt << kFmtShift | |
| 69 | static_cast<int32_t>(ft) << kFtShift | |
| 70 | static_cast<int32_t>(fs) << kFsShift | |
| 71 | static_cast<int32_t>(fd) << kFdShift | |
| 72 | funct; |
| 73 | Emit(encoding); |
| 74 | } |
| 75 | |
| 76 | void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm) { |
| 77 | CHECK_NE(rt, kNoFpuRegister); |
| 78 | int32_t encoding = opcode << kOpcodeShift | |
| 79 | fmt << kFmtShift | |
| 80 | static_cast<int32_t>(rt) << kRtShift | |
| 81 | imm; |
| 82 | Emit(encoding); |
| 83 | } |
| 84 | |
| 85 | void Mips64Assembler::EmitBranch(GpuRegister rt, GpuRegister rs, Label* label, bool equal) { |
| 86 | int offset; |
| 87 | if (label->IsBound()) { |
| 88 | offset = label->Position() - buffer_.Size(); |
| 89 | } else { |
| 90 | // Use the offset field of the branch instruction for linking the sites. |
| 91 | offset = label->position_; |
| 92 | label->LinkTo(buffer_.Size()); |
| 93 | } |
| 94 | if (equal) { |
| 95 | Beq(rt, rs, (offset >> 2) & kBranchOffsetMask); |
| 96 | } else { |
| 97 | Bne(rt, rs, (offset >> 2) & kBranchOffsetMask); |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | void Mips64Assembler::EmitJump(Label* label, bool link) { |
| 102 | int offset; |
| 103 | if (label->IsBound()) { |
| 104 | offset = label->Position() - buffer_.Size(); |
| 105 | } else { |
| 106 | // Use the offset field of the jump instruction for linking the sites. |
| 107 | offset = label->position_; |
| 108 | label->LinkTo(buffer_.Size()); |
| 109 | } |
| 110 | if (link) { |
| 111 | Jal((offset >> 2) & kJumpOffsetMask); |
| 112 | } else { |
| 113 | J((offset >> 2) & kJumpOffsetMask); |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | int32_t Mips64Assembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) { |
| 118 | CHECK_ALIGNED(offset, 4); |
| 119 | CHECK(IsInt(POPCOUNT(kBranchOffsetMask), offset)) << offset; |
| 120 | |
| 121 | // Properly preserve only the bits supported in the instruction. |
| 122 | offset >>= 2; |
| 123 | if (is_jump) { |
| 124 | offset &= kJumpOffsetMask; |
| 125 | return (inst & ~kJumpOffsetMask) | offset; |
| 126 | } else { |
| 127 | offset &= kBranchOffsetMask; |
| 128 | return (inst & ~kBranchOffsetMask) | offset; |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | int Mips64Assembler::DecodeBranchOffset(int32_t inst, bool is_jump) { |
| 133 | // Sign-extend, then left-shift by 2. |
| 134 | if (is_jump) { |
| 135 | return (((inst & kJumpOffsetMask) << 6) >> 4); |
| 136 | } else { |
| 137 | return (((inst & kBranchOffsetMask) << 16) >> 14); |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | void Mips64Assembler::Bind(Label* label, bool is_jump) { |
| 142 | CHECK(!label->IsBound()); |
| 143 | int bound_pc = buffer_.Size(); |
| 144 | while (label->IsLinked()) { |
| 145 | int32_t position = label->Position(); |
| 146 | int32_t next = buffer_.Load<int32_t>(position); |
| 147 | int32_t offset = is_jump ? bound_pc - position : bound_pc - position - 4; |
| 148 | int32_t encoded = Mips64Assembler::EncodeBranchOffset(offset, next, is_jump); |
| 149 | buffer_.Store<int32_t>(position, encoded); |
| 150 | label->position_ = Mips64Assembler::DecodeBranchOffset(next, is_jump); |
| 151 | } |
| 152 | label->BindTo(bound_pc); |
| 153 | } |
| 154 | |
| 155 | void Mips64Assembler::Add(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 156 | EmitR(0, rs, rt, rd, 0, 0x20); |
| 157 | } |
| 158 | |
| 159 | void Mips64Assembler::Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 160 | EmitI(0x8, rs, rt, imm16); |
| 161 | } |
| 162 | |
| 163 | void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 164 | EmitR(0, rs, rt, rd, 0, 0x21); |
| 165 | } |
| 166 | |
| 167 | void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 168 | EmitI(0x9, rs, rt, imm16); |
| 169 | } |
| 170 | |
| 171 | void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 172 | EmitI(0x19, rs, rt, imm16); |
| 173 | } |
| 174 | |
| 175 | void Mips64Assembler::Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 176 | EmitR(0, rs, rt, rd, 0, 0x22); |
| 177 | } |
| 178 | |
| 179 | void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 180 | EmitR(0, rs, rt, rd, 0, 0x23); |
| 181 | } |
| 182 | |
| 183 | void Mips64Assembler::Mult(GpuRegister rs, GpuRegister rt) { |
| 184 | EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x18); |
| 185 | } |
| 186 | |
| 187 | void Mips64Assembler::Multu(GpuRegister rs, GpuRegister rt) { |
| 188 | EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x19); |
| 189 | } |
| 190 | |
| 191 | void Mips64Assembler::Div(GpuRegister rs, GpuRegister rt) { |
| 192 | EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1a); |
| 193 | } |
| 194 | |
| 195 | void Mips64Assembler::Divu(GpuRegister rs, GpuRegister rt) { |
| 196 | EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1b); |
| 197 | } |
| 198 | |
| 199 | void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 200 | EmitR(0, rs, rt, rd, 0, 0x24); |
| 201 | } |
| 202 | |
| 203 | void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 204 | EmitI(0xc, rs, rt, imm16); |
| 205 | } |
| 206 | |
| 207 | void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 208 | EmitR(0, rs, rt, rd, 0, 0x25); |
| 209 | } |
| 210 | |
| 211 | void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 212 | EmitI(0xd, rs, rt, imm16); |
| 213 | } |
| 214 | |
| 215 | void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 216 | EmitR(0, rs, rt, rd, 0, 0x26); |
| 217 | } |
| 218 | |
| 219 | void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 220 | EmitI(0xe, rs, rt, imm16); |
| 221 | } |
| 222 | |
| 223 | void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 224 | EmitR(0, rs, rt, rd, 0, 0x27); |
| 225 | } |
| 226 | |
| 227 | void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rs, int shamt) { |
| 228 | EmitR(0, rs, static_cast<GpuRegister>(0), rd, shamt, 0x00); |
| 229 | } |
| 230 | |
| 231 | void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rs, int shamt) { |
| 232 | EmitR(0, rs, static_cast<GpuRegister>(0), rd, shamt, 0x02); |
| 233 | } |
| 234 | |
| 235 | void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rs, int shamt) { |
| 236 | EmitR(0, rs, static_cast<GpuRegister>(0), rd, shamt, 0x03); |
| 237 | } |
| 238 | |
| 239 | void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 240 | EmitR(0, rs, rt, rd, 0, 0x04); |
| 241 | } |
| 242 | |
| 243 | void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 244 | EmitR(0, rs, rt, rd, 0, 0x06); |
| 245 | } |
| 246 | |
| 247 | void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 248 | EmitR(0, rs, rt, rd, 0, 0x07); |
| 249 | } |
| 250 | |
| 251 | void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 252 | EmitI(0x20, rs, rt, imm16); |
| 253 | } |
| 254 | |
| 255 | void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 256 | EmitI(0x21, rs, rt, imm16); |
| 257 | } |
| 258 | |
| 259 | void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 260 | EmitI(0x23, rs, rt, imm16); |
| 261 | } |
| 262 | |
| 263 | void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 264 | EmitI(0x37, rs, rt, imm16); |
| 265 | } |
| 266 | |
| 267 | void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 268 | EmitI(0x24, rs, rt, imm16); |
| 269 | } |
| 270 | |
| 271 | void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 272 | EmitI(0x25, rs, rt, imm16); |
| 273 | } |
| 274 | |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 275 | void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 276 | EmitI(0x27, rs, rt, imm16); |
| 277 | } |
| 278 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 279 | void Mips64Assembler::Lui(GpuRegister rt, uint16_t imm16) { |
| 280 | EmitI(0xf, static_cast<GpuRegister>(0), rt, imm16); |
| 281 | } |
| 282 | |
| 283 | void Mips64Assembler::Mfhi(GpuRegister rd) { |
| 284 | EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x10); |
| 285 | } |
| 286 | |
| 287 | void Mips64Assembler::Mflo(GpuRegister rd) { |
| 288 | EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x12); |
| 289 | } |
| 290 | |
| 291 | void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 292 | EmitI(0x28, rs, rt, imm16); |
| 293 | } |
| 294 | |
| 295 | void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 296 | EmitI(0x29, rs, rt, imm16); |
| 297 | } |
| 298 | |
| 299 | void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 300 | EmitI(0x2b, rs, rt, imm16); |
| 301 | } |
| 302 | |
| 303 | void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 304 | EmitI(0x3f, rs, rt, imm16); |
| 305 | } |
| 306 | |
| 307 | void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 308 | EmitR(0, rs, rt, rd, 0, 0x2a); |
| 309 | } |
| 310 | |
| 311 | void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 312 | EmitR(0, rs, rt, rd, 0, 0x2b); |
| 313 | } |
| 314 | |
| 315 | void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 316 | EmitI(0xa, rs, rt, imm16); |
| 317 | } |
| 318 | |
| 319 | void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 320 | EmitI(0xb, rs, rt, imm16); |
| 321 | } |
| 322 | |
| 323 | void Mips64Assembler::Beq(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 324 | EmitI(0x4, rs, rt, imm16); |
| 325 | Nop(); |
| 326 | } |
| 327 | |
| 328 | void Mips64Assembler::Bne(GpuRegister rt, GpuRegister rs, uint16_t imm16) { |
| 329 | EmitI(0x5, rs, rt, imm16); |
| 330 | Nop(); |
| 331 | } |
| 332 | |
| 333 | void Mips64Assembler::J(uint32_t address) { |
| 334 | EmitJ(0x2, address); |
| 335 | Nop(); |
| 336 | } |
| 337 | |
| 338 | void Mips64Assembler::Jal(uint32_t address) { |
| 339 | EmitJ(0x2, address); |
| 340 | Nop(); |
| 341 | } |
| 342 | |
| 343 | void Mips64Assembler::Jr(GpuRegister rs) { |
| 344 | EmitR(0, rs, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), 0, 0x09); // Jalr zero, rs |
| 345 | Nop(); |
| 346 | } |
| 347 | |
| 348 | void Mips64Assembler::Jalr(GpuRegister rs) { |
| 349 | EmitR(0, rs, static_cast<GpuRegister>(0), RA, 0, 0x09); |
| 350 | Nop(); |
| 351 | } |
| 352 | |
| 353 | void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 354 | EmitFR(0x11, 0x10, ft, fs, fd, 0x0); |
| 355 | } |
| 356 | |
| 357 | void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 358 | EmitFR(0x11, 0x10, ft, fs, fd, 0x1); |
| 359 | } |
| 360 | |
| 361 | void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 362 | EmitFR(0x11, 0x10, ft, fs, fd, 0x2); |
| 363 | } |
| 364 | |
| 365 | void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 366 | EmitFR(0x11, 0x10, ft, fs, fd, 0x3); |
| 367 | } |
| 368 | |
| 369 | void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 370 | EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), |
| 371 | static_cast<FpuRegister>(fd), 0x0); |
| 372 | } |
| 373 | |
| 374 | void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 375 | EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), |
| 376 | static_cast<FpuRegister>(fd), 0x1); |
| 377 | } |
| 378 | |
| 379 | void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 380 | EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), |
| 381 | static_cast<FpuRegister>(fd), 0x2); |
| 382 | } |
| 383 | |
| 384 | void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { |
| 385 | EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), |
| 386 | static_cast<FpuRegister>(fd), 0x3); |
| 387 | } |
| 388 | |
| 389 | void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) { |
| 390 | EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6); |
| 391 | } |
| 392 | |
| 393 | void Mips64Assembler::MovD(FpuRegister fd, FpuRegister fs) { |
| 394 | EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), static_cast<FpuRegister>(fs), |
| 395 | static_cast<FpuRegister>(fd), 0x6); |
| 396 | } |
| 397 | |
| 398 | void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) { |
| 399 | EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); |
| 400 | } |
| 401 | |
| 402 | void Mips64Assembler::Mtc1(FpuRegister ft, GpuRegister rs) { |
| 403 | EmitFR(0x11, 0x04, ft, static_cast<FpuRegister>(rs), static_cast<FpuRegister>(0), 0x0); |
| 404 | } |
| 405 | |
| 406 | void Mips64Assembler::Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { |
| 407 | EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16); |
| 408 | } |
| 409 | |
| 410 | void Mips64Assembler::Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { |
| 411 | EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16); |
| 412 | } |
| 413 | |
| 414 | void Mips64Assembler::Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { |
| 415 | EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16); |
| 416 | } |
| 417 | |
| 418 | void Mips64Assembler::Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { |
| 419 | EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16); |
| 420 | } |
| 421 | |
| 422 | void Mips64Assembler::Break() { |
| 423 | EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), |
| 424 | static_cast<GpuRegister>(0), 0, 0xD); |
| 425 | } |
| 426 | |
| 427 | void Mips64Assembler::Nop() { |
| 428 | EmitR(0x0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), |
| 429 | static_cast<GpuRegister>(0), 0, 0x0); |
| 430 | } |
| 431 | |
| 432 | void Mips64Assembler::Move(GpuRegister rt, GpuRegister rs) { |
| 433 | EmitI(0x19, rs, rt, 0); // Daddiu |
| 434 | } |
| 435 | |
| 436 | void Mips64Assembler::Clear(GpuRegister rt) { |
| 437 | EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rt, 0, 0x20); |
| 438 | } |
| 439 | |
| 440 | void Mips64Assembler::Not(GpuRegister rt, GpuRegister rs) { |
| 441 | EmitR(0, static_cast<GpuRegister>(0), rs, rt, 0, 0x27); |
| 442 | } |
| 443 | |
| 444 | void Mips64Assembler::Mul(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 445 | Mult(rs, rt); |
| 446 | Mflo(rd); |
| 447 | } |
| 448 | |
| 449 | void Mips64Assembler::Div(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 450 | Div(rs, rt); |
| 451 | Mflo(rd); |
| 452 | } |
| 453 | |
| 454 | void Mips64Assembler::Rem(GpuRegister rd, GpuRegister rs, GpuRegister rt) { |
| 455 | Div(rs, rt); |
| 456 | Mfhi(rd); |
| 457 | } |
| 458 | |
| 459 | void Mips64Assembler::AddConstant64(GpuRegister rt, GpuRegister rs, int32_t value) { |
| 460 | CHECK((value >= -32768) && (value <= 32766)); |
| 461 | Daddiu(rt, rs, value); |
| 462 | } |
| 463 | |
| 464 | void Mips64Assembler::LoadImmediate64(GpuRegister rt, int32_t value) { |
| 465 | CHECK((value >= -32768) && (value <= 32766)); |
| 466 | Daddiu(rt, ZERO, value); |
| 467 | } |
| 468 | |
| 469 | void Mips64Assembler::LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, |
| 470 | int32_t offset) { |
| 471 | switch (type) { |
| 472 | case kLoadSignedByte: |
| 473 | Lb(reg, base, offset); |
| 474 | break; |
| 475 | case kLoadUnsignedByte: |
| 476 | Lbu(reg, base, offset); |
| 477 | break; |
| 478 | case kLoadSignedHalfword: |
| 479 | Lh(reg, base, offset); |
| 480 | break; |
| 481 | case kLoadUnsignedHalfword: |
| 482 | Lhu(reg, base, offset); |
| 483 | break; |
| 484 | case kLoadWord: |
| 485 | Lw(reg, base, offset); |
| 486 | break; |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 487 | case kLoadUnsignedWord: |
| 488 | Lwu(reg, base, offset); |
| 489 | break; |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 490 | case kLoadDoubleword: |
| 491 | // TODO: alignment issues ??? |
| 492 | Ld(reg, base, offset); |
| 493 | break; |
| 494 | default: |
| 495 | LOG(FATAL) << "UNREACHABLE"; |
| 496 | } |
| 497 | } |
| 498 | |
| 499 | void Mips64Assembler::LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, |
| 500 | int32_t offset) { |
| 501 | CHECK((offset >= -32768) && (offset <= 32766)); |
| 502 | switch (type) { |
| 503 | case kLoadWord: |
| 504 | Lwc1(reg, base, offset); |
| 505 | break; |
| 506 | case kLoadDoubleword: |
| 507 | // TODO: alignment issues ??? |
| 508 | Ldc1(reg, base, offset); |
| 509 | break; |
| 510 | default: |
| 511 | LOG(FATAL) << "UNREACHABLE"; |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | void Mips64Assembler::EmitLoad(ManagedRegister m_dst, GpuRegister src_register, int32_t src_offset, |
| 516 | size_t size) { |
| 517 | Mips64ManagedRegister dst = m_dst.AsMips64(); |
| 518 | if (dst.IsNoRegister()) { |
| 519 | CHECK_EQ(0u, size) << dst; |
| 520 | } else if (dst.IsGpuRegister()) { |
| 521 | if (size == 4) { |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 522 | LoadFromOffset(kLoadWord, dst.AsGpuRegister(), src_register, src_offset); |
| 523 | } else if (size == 8) { |
| 524 | CHECK_EQ(8u, size) << dst; |
| 525 | LoadFromOffset(kLoadDoubleword, dst.AsGpuRegister(), src_register, src_offset); |
| 526 | } else { |
| 527 | UNIMPLEMENTED(FATAL) << "We only support Load() of size 4 and 8"; |
| 528 | } |
| 529 | } else if (dst.IsFpuRegister()) { |
| 530 | if (size == 4) { |
| 531 | CHECK_EQ(4u, size) << dst; |
| 532 | LoadFpuFromOffset(kLoadWord, dst.AsFpuRegister(), src_register, src_offset); |
| 533 | } else if (size == 8) { |
| 534 | CHECK_EQ(8u, size) << dst; |
| 535 | LoadFpuFromOffset(kLoadDoubleword, dst.AsFpuRegister(), src_register, src_offset); |
| 536 | } else { |
| 537 | UNIMPLEMENTED(FATAL) << "We only support Load() of size 4 and 8"; |
| 538 | } |
| 539 | } |
| 540 | } |
| 541 | |
| 542 | void Mips64Assembler::StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, |
| 543 | int32_t offset) { |
| 544 | switch (type) { |
| 545 | case kStoreByte: |
| 546 | Sb(reg, base, offset); |
| 547 | break; |
| 548 | case kStoreHalfword: |
| 549 | Sh(reg, base, offset); |
| 550 | break; |
| 551 | case kStoreWord: |
| 552 | Sw(reg, base, offset); |
| 553 | break; |
| 554 | case kStoreDoubleword: |
| 555 | // TODO: alignment issues ??? |
| 556 | Sd(reg, base, offset); |
| 557 | break; |
| 558 | default: |
| 559 | LOG(FATAL) << "UNREACHABLE"; |
| 560 | } |
| 561 | } |
| 562 | |
| 563 | void Mips64Assembler::StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, |
| 564 | int32_t offset) { |
| 565 | switch (type) { |
| 566 | case kStoreWord: |
| 567 | Swc1(reg, base, offset); |
| 568 | break; |
| 569 | case kStoreDoubleword: |
| 570 | Sdc1(reg, base, offset); |
| 571 | break; |
| 572 | default: |
| 573 | LOG(FATAL) << "UNREACHABLE"; |
| 574 | } |
| 575 | } |
| 576 | |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 577 | static dwarf::Reg DWARFReg(GpuRegister reg) { |
| 578 | return dwarf::Reg::Mips64Core(static_cast<int>(reg)); |
| 579 | } |
| 580 | |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 581 | constexpr size_t kFramePointerSize = 8; |
| 582 | |
| 583 | void Mips64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, |
| 584 | const std::vector<ManagedRegister>& callee_save_regs, |
| 585 | const ManagedRegisterEntrySpills& entry_spills) { |
| 586 | CHECK_ALIGNED(frame_size, kStackAlignment); |
| 587 | |
| 588 | // Increase frame to required size. |
| 589 | IncreaseFrameSize(frame_size); |
| 590 | |
| 591 | // Push callee saves and return address |
| 592 | int stack_offset = frame_size - kFramePointerSize; |
| 593 | StoreToOffset(kStoreDoubleword, RA, SP, stack_offset); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 594 | cfi_.RelOffset(DWARFReg(RA), stack_offset); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 595 | for (int i = callee_save_regs.size() - 1; i >= 0; --i) { |
| 596 | stack_offset -= kFramePointerSize; |
| 597 | GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister(); |
| 598 | StoreToOffset(kStoreDoubleword, reg, SP, stack_offset); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 599 | cfi_.RelOffset(DWARFReg(reg), stack_offset); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 600 | } |
| 601 | |
| 602 | // Write out Method*. |
| 603 | StoreToOffset(kStoreWord, method_reg.AsMips64().AsGpuRegister(), SP, 0); |
| 604 | |
| 605 | // Write out entry spills. |
| 606 | int32_t offset = frame_size + sizeof(StackReference<mirror::ArtMethod>); |
| 607 | for (size_t i = 0; i < entry_spills.size(); ++i) { |
| 608 | Mips64ManagedRegister reg = entry_spills.at(i).AsMips64(); |
| 609 | ManagedRegisterSpill spill = entry_spills.at(i); |
| 610 | int32_t size = spill.getSize(); |
| 611 | if (reg.IsNoRegister()) { |
| 612 | // only increment stack offset. |
| 613 | offset += size; |
| 614 | } else if (reg.IsFpuRegister()) { |
| 615 | StoreFpuToOffset((size == 4) ? kStoreWord : kStoreDoubleword, reg.AsFpuRegister(), SP, offset); |
| 616 | offset += size; |
| 617 | } else if (reg.IsGpuRegister()) { |
| 618 | StoreToOffset((size == 4) ? kStoreWord : kStoreDoubleword, reg.AsGpuRegister(), SP, offset); |
| 619 | offset += size; |
| 620 | } |
| 621 | } |
| 622 | } |
| 623 | |
| 624 | void Mips64Assembler::RemoveFrame(size_t frame_size, |
| 625 | const std::vector<ManagedRegister>& callee_save_regs) { |
| 626 | CHECK_ALIGNED(frame_size, kStackAlignment); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 627 | cfi_.RememberState(); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 628 | |
| 629 | // Pop callee saves and return address |
| 630 | int stack_offset = frame_size - (callee_save_regs.size() * kFramePointerSize) - kFramePointerSize; |
| 631 | for (size_t i = 0; i < callee_save_regs.size(); ++i) { |
| 632 | GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister(); |
| 633 | LoadFromOffset(kLoadDoubleword, reg, SP, stack_offset); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 634 | cfi_.Restore(DWARFReg(reg)); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 635 | stack_offset += kFramePointerSize; |
| 636 | } |
| 637 | LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 638 | cfi_.Restore(DWARFReg(RA)); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 639 | |
| 640 | // Decrease frame to required size. |
| 641 | DecreaseFrameSize(frame_size); |
| 642 | |
| 643 | // Then jump to the return address. |
| 644 | Jr(RA); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 645 | |
| 646 | // The CFI should be restored for any code that follows the exit block. |
| 647 | cfi_.RestoreState(); |
| 648 | cfi_.DefCFAOffset(frame_size); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 649 | } |
| 650 | |
| 651 | void Mips64Assembler::IncreaseFrameSize(size_t adjust) { |
| 652 | CHECK_ALIGNED(adjust, kStackAlignment); |
| 653 | AddConstant64(SP, SP, -adjust); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 654 | cfi_.AdjustCFAOffset(adjust); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | void Mips64Assembler::DecreaseFrameSize(size_t adjust) { |
| 658 | CHECK_ALIGNED(adjust, kStackAlignment); |
| 659 | AddConstant64(SP, SP, adjust); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 660 | cfi_.AdjustCFAOffset(-adjust); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 661 | } |
| 662 | |
| 663 | void Mips64Assembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) { |
| 664 | Mips64ManagedRegister src = msrc.AsMips64(); |
| 665 | if (src.IsNoRegister()) { |
| 666 | CHECK_EQ(0u, size); |
| 667 | } else if (src.IsGpuRegister()) { |
| 668 | CHECK(size == 4 || size == 8) << size; |
| 669 | if (size == 8) { |
| 670 | StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); |
| 671 | } else if (size == 4) { |
| 672 | StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value()); |
| 673 | } else { |
| 674 | UNIMPLEMENTED(FATAL) << "We only support Store() of size 4 and 8"; |
| 675 | } |
| 676 | } else if (src.IsFpuRegister()) { |
| 677 | CHECK(size == 4 || size == 8) << size; |
| 678 | if (size == 8) { |
| 679 | StoreFpuToOffset(kStoreDoubleword, src.AsFpuRegister(), SP, dest.Int32Value()); |
| 680 | } else if (size == 4) { |
| 681 | StoreFpuToOffset(kStoreWord, src.AsFpuRegister(), SP, dest.Int32Value()); |
| 682 | } else { |
| 683 | UNIMPLEMENTED(FATAL) << "We only support Store() of size 4 and 8"; |
| 684 | } |
| 685 | } |
| 686 | } |
| 687 | |
| 688 | void Mips64Assembler::StoreRef(FrameOffset dest, ManagedRegister msrc) { |
| 689 | Mips64ManagedRegister src = msrc.AsMips64(); |
| 690 | CHECK(src.IsGpuRegister()); |
| 691 | StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value()); |
| 692 | } |
| 693 | |
| 694 | void Mips64Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) { |
| 695 | Mips64ManagedRegister src = msrc.AsMips64(); |
| 696 | CHECK(src.IsGpuRegister()); |
| 697 | StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); |
| 698 | } |
| 699 | |
| 700 | void Mips64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, |
| 701 | ManagedRegister mscratch) { |
| 702 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 703 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 704 | LoadImmediate64(scratch.AsGpuRegister(), imm); |
| 705 | StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); |
| 706 | } |
| 707 | |
| 708 | void Mips64Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, |
| 709 | ManagedRegister mscratch) { |
| 710 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 711 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 712 | LoadImmediate64(scratch.AsGpuRegister(), imm); |
| 713 | StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, dest.Int32Value()); |
| 714 | } |
| 715 | |
| 716 | void Mips64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, |
| 717 | FrameOffset fr_offs, |
| 718 | ManagedRegister mscratch) { |
| 719 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 720 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 721 | AddConstant64(scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); |
| 722 | StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); |
| 723 | } |
| 724 | |
| 725 | void Mips64Assembler::StoreStackPointerToThread64(ThreadOffset<8> thr_offs) { |
| 726 | StoreToOffset(kStoreDoubleword, SP, S1, thr_offs.Int32Value()); |
| 727 | } |
| 728 | |
| 729 | void Mips64Assembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc, |
| 730 | FrameOffset in_off, ManagedRegister mscratch) { |
| 731 | Mips64ManagedRegister src = msrc.AsMips64(); |
| 732 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 733 | StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); |
| 734 | LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value()); |
| 735 | StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value() + 8); |
| 736 | } |
| 737 | |
| 738 | void Mips64Assembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) { |
| 739 | return EmitLoad(mdest, SP, src.Int32Value(), size); |
| 740 | } |
| 741 | |
| 742 | void Mips64Assembler::LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) { |
| 743 | return EmitLoad(mdest, S1, src.Int32Value(), size); |
| 744 | } |
| 745 | |
| 746 | void Mips64Assembler::LoadRef(ManagedRegister mdest, FrameOffset src) { |
| 747 | Mips64ManagedRegister dest = mdest.AsMips64(); |
| 748 | CHECK(dest.IsGpuRegister()); |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 749 | LoadFromOffset(kLoadUnsignedWord, dest.AsGpuRegister(), SP, src.Int32Value()); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 750 | } |
| 751 | |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 752 | void Mips64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs) { |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 753 | Mips64ManagedRegister dest = mdest.AsMips64(); |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 754 | CHECK(dest.IsGpuRegister() && base.AsMips64().IsGpuRegister()); |
| 755 | LoadFromOffset(kLoadUnsignedWord, dest.AsGpuRegister(), |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 756 | base.AsMips64().AsGpuRegister(), offs.Int32Value()); |
| 757 | if (kPoisonHeapReferences) { |
| 758 | Subu(dest.AsGpuRegister(), ZERO, dest.AsGpuRegister()); |
| 759 | } |
| 760 | } |
| 761 | |
| 762 | void Mips64Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, |
| 763 | Offset offs) { |
| 764 | Mips64ManagedRegister dest = mdest.AsMips64(); |
| 765 | CHECK(dest.IsGpuRegister() && dest.IsGpuRegister()) << dest; |
| 766 | LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), |
| 767 | base.AsMips64().AsGpuRegister(), offs.Int32Value()); |
| 768 | } |
| 769 | |
| 770 | void Mips64Assembler::LoadRawPtrFromThread64(ManagedRegister mdest, |
| 771 | ThreadOffset<8> offs) { |
| 772 | Mips64ManagedRegister dest = mdest.AsMips64(); |
| 773 | CHECK(dest.IsGpuRegister()); |
| 774 | LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value()); |
| 775 | } |
| 776 | |
| 777 | void Mips64Assembler::SignExtend(ManagedRegister /*mreg*/, size_t /*size*/) { |
| 778 | UNIMPLEMENTED(FATAL) << "no sign extension necessary for mips"; |
| 779 | } |
| 780 | |
| 781 | void Mips64Assembler::ZeroExtend(ManagedRegister /*mreg*/, size_t /*size*/) { |
| 782 | UNIMPLEMENTED(FATAL) << "no zero extension necessary for mips"; |
| 783 | } |
| 784 | |
| 785 | void Mips64Assembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) { |
| 786 | Mips64ManagedRegister dest = mdest.AsMips64(); |
| 787 | Mips64ManagedRegister src = msrc.AsMips64(); |
| 788 | if (!dest.Equals(src)) { |
| 789 | if (dest.IsGpuRegister()) { |
| 790 | CHECK(src.IsGpuRegister()) << src; |
| 791 | Move(dest.AsGpuRegister(), src.AsGpuRegister()); |
| 792 | } else if (dest.IsFpuRegister()) { |
| 793 | CHECK(src.IsFpuRegister()) << src; |
| 794 | if (size == 4) { |
| 795 | MovS(dest.AsFpuRegister(), src.AsFpuRegister()); |
| 796 | } else if (size == 8) { |
| 797 | MovD(dest.AsFpuRegister(), src.AsFpuRegister()); |
| 798 | } else { |
| 799 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 800 | } |
| 801 | } |
| 802 | } |
| 803 | } |
| 804 | |
| 805 | void Mips64Assembler::CopyRef(FrameOffset dest, FrameOffset src, |
| 806 | ManagedRegister mscratch) { |
| 807 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 808 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 809 | LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); |
| 810 | StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); |
| 811 | } |
| 812 | |
| 813 | void Mips64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs, |
| 814 | ThreadOffset<8> thr_offs, |
| 815 | ManagedRegister mscratch) { |
| 816 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 817 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 818 | LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); |
| 819 | StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); |
| 820 | } |
| 821 | |
| 822 | void Mips64Assembler::CopyRawPtrToThread64(ThreadOffset<8> thr_offs, |
| 823 | FrameOffset fr_offs, |
| 824 | ManagedRegister mscratch) { |
| 825 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 826 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 827 | LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), |
| 828 | SP, fr_offs.Int32Value()); |
| 829 | StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), |
| 830 | S1, thr_offs.Int32Value()); |
| 831 | } |
| 832 | |
| 833 | void Mips64Assembler::Copy(FrameOffset dest, FrameOffset src, |
| 834 | ManagedRegister mscratch, size_t size) { |
| 835 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 836 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 837 | CHECK(size == 4 || size == 8) << size; |
| 838 | if (size == 4) { |
| 839 | LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); |
| 840 | StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); |
| 841 | } else if (size == 8) { |
| 842 | LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, src.Int32Value()); |
| 843 | StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value()); |
| 844 | } else { |
| 845 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | void Mips64Assembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, |
| 850 | ManagedRegister mscratch, size_t size) { |
| 851 | GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); |
| 852 | CHECK(size == 4 || size == 8) << size; |
| 853 | if (size == 4) { |
| 854 | LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(), |
| 855 | src_offset.Int32Value()); |
| 856 | StoreToOffset(kStoreWord, scratch, SP, dest.Int32Value()); |
| 857 | } else if (size == 8) { |
| 858 | LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(), |
| 859 | src_offset.Int32Value()); |
| 860 | StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value()); |
| 861 | } else { |
| 862 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 863 | } |
| 864 | } |
| 865 | |
| 866 | void Mips64Assembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, |
| 867 | ManagedRegister mscratch, size_t size) { |
| 868 | GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); |
| 869 | CHECK(size == 4 || size == 8) << size; |
| 870 | if (size == 4) { |
| 871 | LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value()); |
| 872 | StoreToOffset(kStoreWord, scratch, dest_base.AsMips64().AsGpuRegister(), |
| 873 | dest_offset.Int32Value()); |
| 874 | } else if (size == 8) { |
| 875 | LoadFromOffset(kLoadDoubleword, scratch, SP, src.Int32Value()); |
| 876 | StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(), |
| 877 | dest_offset.Int32Value()); |
| 878 | } else { |
| 879 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 880 | } |
| 881 | } |
| 882 | |
| 883 | void Mips64Assembler::Copy(FrameOffset /*dest*/, FrameOffset /*src_base*/, Offset /*src_offset*/, |
| 884 | ManagedRegister /*mscratch*/, size_t /*size*/) { |
| 885 | UNIMPLEMENTED(FATAL) << "no mips64 implementation"; |
| 886 | } |
| 887 | |
| 888 | void Mips64Assembler::Copy(ManagedRegister dest, Offset dest_offset, |
| 889 | ManagedRegister src, Offset src_offset, |
| 890 | ManagedRegister mscratch, size_t size) { |
| 891 | GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); |
| 892 | CHECK(size == 4 || size == 8) << size; |
| 893 | if (size == 4) { |
| 894 | LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value()); |
| 895 | StoreToOffset(kStoreWord, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value()); |
| 896 | } else if (size == 8) { |
| 897 | LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(), |
| 898 | src_offset.Int32Value()); |
| 899 | StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), |
| 900 | dest_offset.Int32Value()); |
| 901 | } else { |
| 902 | UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; |
| 903 | } |
| 904 | } |
| 905 | |
| 906 | void Mips64Assembler::Copy(FrameOffset /*dest*/, Offset /*dest_offset*/, FrameOffset /*src*/, Offset |
| 907 | /*src_offset*/, |
| 908 | ManagedRegister /*mscratch*/, size_t /*size*/) { |
| 909 | UNIMPLEMENTED(FATAL) << "no mips64 implementation"; |
| 910 | } |
| 911 | |
| 912 | void Mips64Assembler::MemoryBarrier(ManagedRegister) { |
| 913 | UNIMPLEMENTED(FATAL) << "no mips64 implementation"; |
| 914 | } |
| 915 | |
| 916 | void Mips64Assembler::CreateHandleScopeEntry(ManagedRegister mout_reg, |
| 917 | FrameOffset handle_scope_offset, |
| 918 | ManagedRegister min_reg, bool null_allowed) { |
| 919 | Mips64ManagedRegister out_reg = mout_reg.AsMips64(); |
| 920 | Mips64ManagedRegister in_reg = min_reg.AsMips64(); |
| 921 | CHECK(in_reg.IsNoRegister() || in_reg.IsGpuRegister()) << in_reg; |
| 922 | CHECK(out_reg.IsGpuRegister()) << out_reg; |
| 923 | if (null_allowed) { |
| 924 | Label null_arg; |
| 925 | // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is |
| 926 | // the address in the handle scope holding the reference. |
| 927 | // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) |
| 928 | if (in_reg.IsNoRegister()) { |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 929 | LoadFromOffset(kLoadUnsignedWord, out_reg.AsGpuRegister(), |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 930 | SP, handle_scope_offset.Int32Value()); |
| 931 | in_reg = out_reg; |
| 932 | } |
| 933 | if (!out_reg.Equals(in_reg)) { |
| 934 | LoadImmediate64(out_reg.AsGpuRegister(), 0); |
| 935 | } |
| 936 | EmitBranch(in_reg.AsGpuRegister(), ZERO, &null_arg, true); |
| 937 | AddConstant64(out_reg.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); |
| 938 | Bind(&null_arg, false); |
| 939 | } else { |
| 940 | AddConstant64(out_reg.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); |
| 941 | } |
| 942 | } |
| 943 | |
| 944 | void Mips64Assembler::CreateHandleScopeEntry(FrameOffset out_off, |
| 945 | FrameOffset handle_scope_offset, |
| 946 | ManagedRegister mscratch, |
| 947 | bool null_allowed) { |
| 948 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 949 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 950 | if (null_allowed) { |
| 951 | Label null_arg; |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 952 | LoadFromOffset(kLoadUnsignedWord, scratch.AsGpuRegister(), SP, |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 953 | handle_scope_offset.Int32Value()); |
| 954 | // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is |
| 955 | // the address in the handle scope holding the reference. |
| 956 | // e.g. scratch = (scratch == 0) ? 0 : (SP+handle_scope_offset) |
| 957 | EmitBranch(scratch.AsGpuRegister(), ZERO, &null_arg, true); |
| 958 | AddConstant64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); |
| 959 | Bind(&null_arg, false); |
| 960 | } else { |
| 961 | AddConstant64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); |
| 962 | } |
| 963 | StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, out_off.Int32Value()); |
| 964 | } |
| 965 | |
| 966 | // Given a handle scope entry, load the associated reference. |
| 967 | void Mips64Assembler::LoadReferenceFromHandleScope(ManagedRegister mout_reg, |
| 968 | ManagedRegister min_reg) { |
| 969 | Mips64ManagedRegister out_reg = mout_reg.AsMips64(); |
| 970 | Mips64ManagedRegister in_reg = min_reg.AsMips64(); |
| 971 | CHECK(out_reg.IsGpuRegister()) << out_reg; |
| 972 | CHECK(in_reg.IsGpuRegister()) << in_reg; |
| 973 | Label null_arg; |
| 974 | if (!out_reg.Equals(in_reg)) { |
| 975 | LoadImmediate64(out_reg.AsGpuRegister(), 0); |
| 976 | } |
| 977 | EmitBranch(in_reg.AsGpuRegister(), ZERO, &null_arg, true); |
| 978 | LoadFromOffset(kLoadDoubleword, out_reg.AsGpuRegister(), |
| 979 | in_reg.AsGpuRegister(), 0); |
| 980 | Bind(&null_arg, false); |
| 981 | } |
| 982 | |
| 983 | void Mips64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) { |
| 984 | // TODO: not validating references |
| 985 | } |
| 986 | |
| 987 | void Mips64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) { |
| 988 | // TODO: not validating references |
| 989 | } |
| 990 | |
| 991 | void Mips64Assembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister mscratch) { |
| 992 | Mips64ManagedRegister base = mbase.AsMips64(); |
| 993 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 994 | CHECK(base.IsGpuRegister()) << base; |
| 995 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 996 | LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), |
| 997 | base.AsGpuRegister(), offset.Int32Value()); |
| 998 | Jalr(scratch.AsGpuRegister()); |
| 999 | // TODO: place reference map on call |
| 1000 | } |
| 1001 | |
| 1002 | void Mips64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) { |
| 1003 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 1004 | CHECK(scratch.IsGpuRegister()) << scratch; |
| 1005 | // Call *(*(SP + base) + offset) |
Douglas Leung | d90957f | 2015-04-30 19:22:49 -0700 | [diff] [blame] | 1006 | LoadFromOffset(kLoadUnsignedWord, scratch.AsGpuRegister(), |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1007 | SP, base.Int32Value()); |
| 1008 | LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), |
| 1009 | scratch.AsGpuRegister(), offset.Int32Value()); |
| 1010 | Jalr(scratch.AsGpuRegister()); |
| 1011 | // TODO: place reference map on call |
| 1012 | } |
| 1013 | |
| 1014 | void Mips64Assembler::CallFromThread64(ThreadOffset<8> /*offset*/, ManagedRegister /*mscratch*/) { |
| 1015 | UNIMPLEMENTED(FATAL) << "no mips64 implementation"; |
| 1016 | } |
| 1017 | |
| 1018 | void Mips64Assembler::GetCurrentThread(ManagedRegister tr) { |
| 1019 | Move(tr.AsMips64().AsGpuRegister(), S1); |
| 1020 | } |
| 1021 | |
| 1022 | void Mips64Assembler::GetCurrentThread(FrameOffset offset, |
| 1023 | ManagedRegister /*mscratch*/) { |
| 1024 | StoreToOffset(kStoreDoubleword, S1, SP, offset.Int32Value()); |
| 1025 | } |
| 1026 | |
| 1027 | void Mips64Assembler::ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) { |
| 1028 | Mips64ManagedRegister scratch = mscratch.AsMips64(); |
| 1029 | Mips64ExceptionSlowPath* slow = new Mips64ExceptionSlowPath(scratch, stack_adjust); |
| 1030 | buffer_.EnqueueSlowPath(slow); |
| 1031 | LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), |
| 1032 | S1, Thread::ExceptionOffset<8>().Int32Value()); |
| 1033 | EmitBranch(scratch.AsGpuRegister(), ZERO, slow->Entry(), false); |
| 1034 | } |
| 1035 | |
| 1036 | void Mips64ExceptionSlowPath::Emit(Assembler* sasm) { |
| 1037 | Mips64Assembler* sp_asm = down_cast<Mips64Assembler*>(sasm); |
| 1038 | #define __ sp_asm-> |
| 1039 | __ Bind(&entry_, false); |
| 1040 | if (stack_adjust_ != 0) { // Fix up the frame. |
| 1041 | __ DecreaseFrameSize(stack_adjust_); |
| 1042 | } |
| 1043 | // Pass exception object as argument |
| 1044 | // Don't care about preserving A0 as this call won't return |
| 1045 | __ Move(A0, scratch_.AsGpuRegister()); |
| 1046 | // Set up call to Thread::Current()->pDeliverException |
| 1047 | __ LoadFromOffset(kLoadDoubleword, T9, S1, |
Goran Jakovljevic | 75c40d4 | 2015-04-03 15:45:21 +0200 | [diff] [blame] | 1048 | QUICK_ENTRYPOINT_OFFSET(8, pDeliverException).Int32Value()); |
Andreas Gampe | 57b3429 | 2015-01-14 15:45:59 -0800 | [diff] [blame] | 1049 | __ Jr(T9); |
| 1050 | // Call never returns |
| 1051 | __ Break(); |
| 1052 | #undef __ |
| 1053 | } |
| 1054 | |
| 1055 | } // namespace mips64 |
| 1056 | } // namespace art |