Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "assembler_x86_64.h" |
| 18 | |
| 19 | #include "base/casts.h" |
| 20 | #include "entrypoints/quick/quick_entrypoints.h" |
| 21 | #include "memory_region.h" |
| 22 | #include "thread.h" |
| 23 | |
| 24 | namespace art { |
| 25 | namespace x86_64 { |
| 26 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 27 | std::ostream& operator<<(std::ostream& os, const CpuRegister& reg) { |
| 28 | return os << reg.AsRegister(); |
| 29 | } |
| 30 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 31 | std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 32 | return os << reg.AsFloatRegister(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 33 | } |
| 34 | |
| 35 | std::ostream& operator<<(std::ostream& os, const X87Register& reg) { |
| 36 | return os << "ST" << static_cast<int>(reg); |
| 37 | } |
| 38 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 39 | void X86_64Assembler::call(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 40 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 41 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 42 | EmitUint8(0xFF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 43 | EmitRegisterOperand(2, reg.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 44 | } |
| 45 | |
| 46 | |
| 47 | void X86_64Assembler::call(const Address& address) { |
| 48 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 49 | EmitOptionalRex32(address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 50 | EmitUint8(0xFF); |
| 51 | EmitOperand(2, address); |
| 52 | } |
| 53 | |
| 54 | |
| 55 | void X86_64Assembler::call(Label* label) { |
| 56 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 57 | EmitUint8(0xE8); |
| 58 | static const int kSize = 5; |
Nicolas Geoffray | 1cf9528 | 2014-12-12 19:22:03 +0000 | [diff] [blame] | 59 | // Offset by one because we already have emitted the opcode. |
| 60 | EmitLabel(label, kSize - 1); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 61 | } |
| 62 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 63 | void X86_64Assembler::pushq(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 64 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 65 | EmitOptionalRex32(reg); |
| 66 | EmitUint8(0x50 + reg.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | |
| 70 | void X86_64Assembler::pushq(const Address& address) { |
| 71 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 72 | EmitOptionalRex32(address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 73 | EmitUint8(0xFF); |
| 74 | EmitOperand(6, address); |
| 75 | } |
| 76 | |
| 77 | |
| 78 | void X86_64Assembler::pushq(const Immediate& imm) { |
| 79 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 80 | CHECK(imm.is_int32()); // pushq only supports 32b immediate. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 81 | if (imm.is_int8()) { |
| 82 | EmitUint8(0x6A); |
| 83 | EmitUint8(imm.value() & 0xFF); |
| 84 | } else { |
| 85 | EmitUint8(0x68); |
| 86 | EmitImmediate(imm); |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 91 | void X86_64Assembler::popq(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 92 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 93 | EmitOptionalRex32(reg); |
| 94 | EmitUint8(0x58 + reg.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | |
| 98 | void X86_64Assembler::popq(const Address& address) { |
| 99 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 100 | EmitOptionalRex32(address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 101 | EmitUint8(0x8F); |
| 102 | EmitOperand(0, address); |
| 103 | } |
| 104 | |
| 105 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 106 | void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 107 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 108 | if (imm.is_int32()) { |
| 109 | // 32 bit. Note: sign-extends. |
| 110 | EmitRex64(dst); |
| 111 | EmitUint8(0xC7); |
| 112 | EmitRegisterOperand(0, dst.LowBits()); |
| 113 | EmitInt32(static_cast<int32_t>(imm.value())); |
| 114 | } else { |
| 115 | EmitRex64(dst); |
| 116 | EmitUint8(0xB8 + dst.LowBits()); |
| 117 | EmitInt64(imm.value()); |
| 118 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 122 | void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { |
Roland Levillain | 946e143 | 2014-11-11 17:35:19 +0000 | [diff] [blame] | 123 | CHECK(imm.is_int32()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 124 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 125 | EmitOptionalRex32(dst); |
| 126 | EmitUint8(0xB8 + dst.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 127 | EmitImmediate(imm); |
| 128 | } |
| 129 | |
| 130 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 131 | void X86_64Assembler::movq(const Address& dst, const Immediate& imm) { |
| 132 | CHECK(imm.is_int32()); |
| 133 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 134 | EmitRex64(dst); |
| 135 | EmitUint8(0xC7); |
| 136 | EmitOperand(0, dst); |
| 137 | EmitImmediate(imm); |
| 138 | } |
| 139 | |
| 140 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 141 | void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 142 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 143 | // 0x89 is movq r/m64 <- r64, with op1 in r/m and op2 in reg: so reverse EmitRex64 |
| 144 | EmitRex64(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 145 | EmitUint8(0x89); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 146 | EmitRegisterOperand(src.LowBits(), dst.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 150 | void X86_64Assembler::movl(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 151 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 152 | EmitOptionalRex32(dst, src); |
Nicolas Geoffray | ecb2f9b | 2014-06-13 08:59:59 +0000 | [diff] [blame] | 153 | EmitUint8(0x8B); |
| 154 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 158 | void X86_64Assembler::movq(CpuRegister dst, const Address& src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 159 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 160 | EmitRex64(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 161 | EmitUint8(0x8B); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 162 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 166 | void X86_64Assembler::movl(CpuRegister dst, const Address& src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 167 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 168 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 169 | EmitUint8(0x8B); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 170 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 174 | void X86_64Assembler::movq(const Address& dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 175 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 176 | EmitRex64(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 177 | EmitUint8(0x89); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 178 | EmitOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 182 | void X86_64Assembler::movl(const Address& dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 183 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 184 | EmitOptionalRex32(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 185 | EmitUint8(0x89); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 186 | EmitOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 187 | } |
| 188 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 189 | void X86_64Assembler::movl(const Address& dst, const Immediate& imm) { |
| 190 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 191 | EmitOptionalRex32(dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 192 | EmitUint8(0xC7); |
| 193 | EmitOperand(0, dst); |
| 194 | EmitImmediate(imm); |
| 195 | } |
| 196 | |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 197 | |
| 198 | void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src) { |
| 199 | cmov(c, dst, src, true); |
| 200 | } |
| 201 | |
| 202 | void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit) { |
| 203 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 204 | EmitOptionalRex(false, is64bit, dst.NeedsRex(), false, src.NeedsRex()); |
| 205 | EmitUint8(0x0F); |
| 206 | EmitUint8(0x40 + c); |
| 207 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
| 208 | } |
| 209 | |
| 210 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 211 | void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 212 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 213 | EmitOptionalByteRegNormalizingRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 214 | EmitUint8(0x0F); |
| 215 | EmitUint8(0xB6); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 216 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 217 | } |
| 218 | |
| 219 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 220 | void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 221 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Chao-ying Fu | d23840d | 2015-04-07 16:03:04 -0700 | [diff] [blame] | 222 | // Byte register is only in the source register form, so we don't use |
| 223 | // EmitOptionalByteRegNormalizingRex32(dst, src); |
| 224 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 225 | EmitUint8(0x0F); |
| 226 | EmitUint8(0xB6); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 227 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 231 | void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 232 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 233 | EmitOptionalByteRegNormalizingRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 234 | EmitUint8(0x0F); |
| 235 | EmitUint8(0xBE); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 236 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 240 | void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 241 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Chao-ying Fu | d23840d | 2015-04-07 16:03:04 -0700 | [diff] [blame] | 242 | // Byte register is only in the source register form, so we don't use |
| 243 | // EmitOptionalByteRegNormalizingRex32(dst, src); |
| 244 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 245 | EmitUint8(0x0F); |
| 246 | EmitUint8(0xBE); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 247 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 251 | void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 252 | LOG(FATAL) << "Use movzxb or movsxb instead."; |
| 253 | } |
| 254 | |
| 255 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 256 | void X86_64Assembler::movb(const Address& dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 257 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 258 | EmitOptionalByteRegNormalizingRex32(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 259 | EmitUint8(0x88); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 260 | EmitOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | |
| 264 | void X86_64Assembler::movb(const Address& dst, const Immediate& imm) { |
| 265 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 266 | EmitOptionalRex32(dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 267 | EmitUint8(0xC6); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 268 | EmitOperand(Register::RAX, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 269 | CHECK(imm.is_int8()); |
| 270 | EmitUint8(imm.value() & 0xFF); |
| 271 | } |
| 272 | |
| 273 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 274 | void X86_64Assembler::movzxw(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 275 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 276 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 277 | EmitUint8(0x0F); |
| 278 | EmitUint8(0xB7); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 279 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 283 | void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 284 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 285 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 286 | EmitUint8(0x0F); |
| 287 | EmitUint8(0xB7); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 288 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 292 | void X86_64Assembler::movsxw(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 293 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 294 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 295 | EmitUint8(0x0F); |
| 296 | EmitUint8(0xBF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 297 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 301 | void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 302 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 303 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 304 | EmitUint8(0x0F); |
| 305 | EmitUint8(0xBF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 306 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 307 | } |
| 308 | |
| 309 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 310 | void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 311 | LOG(FATAL) << "Use movzxw or movsxw instead."; |
| 312 | } |
| 313 | |
| 314 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 315 | void X86_64Assembler::movw(const Address& dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 316 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 317 | EmitOperandSizeOverride(); |
Nicolas Geoffray | e4ded41 | 2014-08-05 22:52:45 +0100 | [diff] [blame] | 318 | EmitOptionalRex32(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 319 | EmitUint8(0x89); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 320 | EmitOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 324 | void X86_64Assembler::movw(const Address& dst, const Immediate& imm) { |
| 325 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 326 | EmitOperandSizeOverride(); |
| 327 | EmitOptionalRex32(dst); |
| 328 | EmitUint8(0xC7); |
| 329 | EmitOperand(Register::RAX, dst); |
Nicolas Geoffray | b6e7206 | 2014-10-07 14:54:48 +0100 | [diff] [blame] | 330 | CHECK(imm.is_uint16() || imm.is_int16()); |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 331 | EmitUint8(imm.value() & 0xFF); |
| 332 | EmitUint8(imm.value() >> 8); |
| 333 | } |
| 334 | |
| 335 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 336 | void X86_64Assembler::leaq(CpuRegister dst, const Address& src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 337 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 338 | EmitRex64(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 339 | EmitUint8(0x8D); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 340 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | |
Nicolas Geoffray | 748f140 | 2015-01-27 08:17:54 +0000 | [diff] [blame] | 344 | void X86_64Assembler::leal(CpuRegister dst, const Address& src) { |
| 345 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 346 | EmitOptionalRex32(dst, src); |
| 347 | EmitUint8(0x8D); |
| 348 | EmitOperand(dst.LowBits(), src); |
| 349 | } |
| 350 | |
| 351 | |
Nicolas Geoffray | 7fb49da | 2014-10-06 09:12:41 +0100 | [diff] [blame] | 352 | void X86_64Assembler::movaps(XmmRegister dst, XmmRegister src) { |
| 353 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 354 | EmitOptionalRex32(dst, src); |
| 355 | EmitUint8(0x0F); |
| 356 | EmitUint8(0x28); |
Nicolas Geoffray | 102cbed | 2014-10-15 18:31:05 +0100 | [diff] [blame] | 357 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Nicolas Geoffray | 7fb49da | 2014-10-06 09:12:41 +0100 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 361 | void X86_64Assembler::movss(XmmRegister dst, const Address& src) { |
| 362 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 363 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 364 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 365 | EmitUint8(0x0F); |
| 366 | EmitUint8(0x10); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 367 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | |
| 371 | void X86_64Assembler::movss(const Address& dst, XmmRegister src) { |
| 372 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 373 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 374 | EmitOptionalRex32(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 375 | EmitUint8(0x0F); |
| 376 | EmitUint8(0x11); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 377 | EmitOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 378 | } |
| 379 | |
| 380 | |
| 381 | void X86_64Assembler::movss(XmmRegister dst, XmmRegister src) { |
| 382 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 383 | EmitUint8(0xF3); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 384 | EmitOptionalRex32(src, dst); // Movss is MR encoding instead of the usual RM. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 385 | EmitUint8(0x0F); |
| 386 | EmitUint8(0x11); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 387 | EmitXmmRegisterOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | |
Roland Levillain | dff1f28 | 2014-11-05 14:15:05 +0000 | [diff] [blame] | 391 | void X86_64Assembler::movsxd(CpuRegister dst, CpuRegister src) { |
| 392 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Nicolas Geoffray | 57a88d4 | 2014-11-10 15:09:21 +0000 | [diff] [blame] | 393 | EmitRex64(dst, src); |
Roland Levillain | dff1f28 | 2014-11-05 14:15:05 +0000 | [diff] [blame] | 394 | EmitUint8(0x63); |
| 395 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
| 396 | } |
| 397 | |
| 398 | |
| 399 | void X86_64Assembler::movsxd(CpuRegister dst, const Address& src) { |
| 400 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 7fd8b59 | 2015-04-22 10:46:07 -0400 | [diff] [blame] | 401 | EmitRex64(dst, src); |
Roland Levillain | dff1f28 | 2014-11-05 14:15:05 +0000 | [diff] [blame] | 402 | EmitUint8(0x63); |
| 403 | EmitOperand(dst.LowBits(), src); |
| 404 | } |
| 405 | |
| 406 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 407 | void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) { |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 408 | movd(dst, src, true); |
| 409 | } |
| 410 | |
| 411 | void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) { |
| 412 | movd(dst, src, true); |
| 413 | } |
| 414 | |
| 415 | void X86_64Assembler::movd(XmmRegister dst, CpuRegister src, bool is64bit) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 416 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 417 | EmitUint8(0x66); |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 418 | EmitOptionalRex(false, is64bit, dst.NeedsRex(), false, src.NeedsRex()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 419 | EmitUint8(0x0F); |
| 420 | EmitUint8(0x6E); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 421 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 422 | } |
| 423 | |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 424 | void X86_64Assembler::movd(CpuRegister dst, XmmRegister src, bool is64bit) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 425 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 426 | EmitUint8(0x66); |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 427 | EmitOptionalRex(false, is64bit, src.NeedsRex(), false, dst.NeedsRex()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 428 | EmitUint8(0x0F); |
| 429 | EmitUint8(0x7E); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 430 | EmitOperand(src.LowBits(), Operand(dst)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | |
| 434 | void X86_64Assembler::addss(XmmRegister dst, XmmRegister src) { |
| 435 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 436 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 437 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 438 | EmitUint8(0x0F); |
| 439 | EmitUint8(0x58); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 440 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 441 | } |
| 442 | |
| 443 | |
| 444 | void X86_64Assembler::addss(XmmRegister dst, const Address& src) { |
| 445 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 446 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 447 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 448 | EmitUint8(0x0F); |
| 449 | EmitUint8(0x58); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 450 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 451 | } |
| 452 | |
| 453 | |
| 454 | void X86_64Assembler::subss(XmmRegister dst, XmmRegister src) { |
| 455 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 456 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 457 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 458 | EmitUint8(0x0F); |
| 459 | EmitUint8(0x5C); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 460 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 461 | } |
| 462 | |
| 463 | |
| 464 | void X86_64Assembler::subss(XmmRegister dst, const Address& src) { |
| 465 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 466 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 467 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 468 | EmitUint8(0x0F); |
| 469 | EmitUint8(0x5C); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 470 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 471 | } |
| 472 | |
| 473 | |
| 474 | void X86_64Assembler::mulss(XmmRegister dst, XmmRegister src) { |
| 475 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 476 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 477 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 478 | EmitUint8(0x0F); |
| 479 | EmitUint8(0x59); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 480 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | |
| 484 | void X86_64Assembler::mulss(XmmRegister dst, const Address& src) { |
| 485 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 486 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 487 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 488 | EmitUint8(0x0F); |
| 489 | EmitUint8(0x59); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 490 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 491 | } |
| 492 | |
| 493 | |
| 494 | void X86_64Assembler::divss(XmmRegister dst, XmmRegister src) { |
| 495 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 496 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 497 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 498 | EmitUint8(0x0F); |
| 499 | EmitUint8(0x5E); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 500 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 501 | } |
| 502 | |
| 503 | |
| 504 | void X86_64Assembler::divss(XmmRegister dst, const Address& src) { |
| 505 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 506 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 507 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 508 | EmitUint8(0x0F); |
| 509 | EmitUint8(0x5E); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 510 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | |
| 514 | void X86_64Assembler::flds(const Address& src) { |
| 515 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 516 | EmitUint8(0xD9); |
| 517 | EmitOperand(0, src); |
| 518 | } |
| 519 | |
| 520 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 521 | void X86_64Assembler::fsts(const Address& dst) { |
| 522 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 523 | EmitUint8(0xD9); |
| 524 | EmitOperand(2, dst); |
| 525 | } |
| 526 | |
| 527 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 528 | void X86_64Assembler::fstps(const Address& dst) { |
| 529 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 530 | EmitUint8(0xD9); |
| 531 | EmitOperand(3, dst); |
| 532 | } |
| 533 | |
| 534 | |
| 535 | void X86_64Assembler::movsd(XmmRegister dst, const Address& src) { |
| 536 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 537 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 538 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 539 | EmitUint8(0x0F); |
| 540 | EmitUint8(0x10); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 541 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | |
| 545 | void X86_64Assembler::movsd(const Address& dst, XmmRegister src) { |
| 546 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 547 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 548 | EmitOptionalRex32(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 549 | EmitUint8(0x0F); |
| 550 | EmitUint8(0x11); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 551 | EmitOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | |
| 555 | void X86_64Assembler::movsd(XmmRegister dst, XmmRegister src) { |
| 556 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 557 | EmitUint8(0xF2); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 558 | EmitOptionalRex32(src, dst); // Movsd is MR encoding instead of the usual RM. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 559 | EmitUint8(0x0F); |
| 560 | EmitUint8(0x11); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 561 | EmitXmmRegisterOperand(src.LowBits(), dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | |
| 565 | void X86_64Assembler::addsd(XmmRegister dst, XmmRegister src) { |
| 566 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 567 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 568 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 569 | EmitUint8(0x0F); |
| 570 | EmitUint8(0x58); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 571 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 572 | } |
| 573 | |
| 574 | |
| 575 | void X86_64Assembler::addsd(XmmRegister dst, const Address& src) { |
| 576 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 577 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 578 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 579 | EmitUint8(0x0F); |
| 580 | EmitUint8(0x58); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 581 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 582 | } |
| 583 | |
| 584 | |
| 585 | void X86_64Assembler::subsd(XmmRegister dst, XmmRegister src) { |
| 586 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 587 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 588 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 589 | EmitUint8(0x0F); |
| 590 | EmitUint8(0x5C); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 591 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 592 | } |
| 593 | |
| 594 | |
| 595 | void X86_64Assembler::subsd(XmmRegister dst, const Address& src) { |
| 596 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 597 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 598 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 599 | EmitUint8(0x0F); |
| 600 | EmitUint8(0x5C); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 601 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 602 | } |
| 603 | |
| 604 | |
| 605 | void X86_64Assembler::mulsd(XmmRegister dst, XmmRegister src) { |
| 606 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 607 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 608 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 609 | EmitUint8(0x0F); |
| 610 | EmitUint8(0x59); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 611 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | |
| 615 | void X86_64Assembler::mulsd(XmmRegister dst, const Address& src) { |
| 616 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 617 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 618 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 619 | EmitUint8(0x0F); |
| 620 | EmitUint8(0x59); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 621 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 622 | } |
| 623 | |
| 624 | |
| 625 | void X86_64Assembler::divsd(XmmRegister dst, XmmRegister src) { |
| 626 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 627 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 628 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 629 | EmitUint8(0x0F); |
| 630 | EmitUint8(0x5E); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 631 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | |
| 635 | void X86_64Assembler::divsd(XmmRegister dst, const Address& src) { |
| 636 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 637 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 638 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 639 | EmitUint8(0x0F); |
| 640 | EmitUint8(0x5E); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 641 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 642 | } |
| 643 | |
| 644 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 645 | void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src) { |
Roland Levillain | 6d0e483 | 2014-11-27 18:31:21 +0000 | [diff] [blame] | 646 | cvtsi2ss(dst, src, false); |
| 647 | } |
| 648 | |
| 649 | |
| 650 | void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 651 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 652 | EmitUint8(0xF3); |
Roland Levillain | 6d0e483 | 2014-11-27 18:31:21 +0000 | [diff] [blame] | 653 | if (is64bit) { |
| 654 | // Emit a REX.W prefix if the operand size is 64 bits. |
| 655 | EmitRex64(dst, src); |
| 656 | } else { |
| 657 | EmitOptionalRex32(dst, src); |
| 658 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 659 | EmitUint8(0x0F); |
| 660 | EmitUint8(0x2A); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 661 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 662 | } |
| 663 | |
| 664 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 665 | void X86_64Assembler::cvtsi2ss(XmmRegister dst, const Address& src, bool is64bit) { |
| 666 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 667 | EmitUint8(0xF3); |
| 668 | if (is64bit) { |
| 669 | // Emit a REX.W prefix if the operand size is 64 bits. |
| 670 | EmitRex64(dst, src); |
| 671 | } else { |
| 672 | EmitOptionalRex32(dst, src); |
| 673 | } |
| 674 | EmitUint8(0x0F); |
| 675 | EmitUint8(0x2A); |
| 676 | EmitOperand(dst.LowBits(), src); |
| 677 | } |
| 678 | |
| 679 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 680 | void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src) { |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 681 | cvtsi2sd(dst, src, false); |
| 682 | } |
| 683 | |
| 684 | |
| 685 | void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 686 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 687 | EmitUint8(0xF2); |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 688 | if (is64bit) { |
| 689 | // Emit a REX.W prefix if the operand size is 64 bits. |
| 690 | EmitRex64(dst, src); |
| 691 | } else { |
| 692 | EmitOptionalRex32(dst, src); |
| 693 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 694 | EmitUint8(0x0F); |
| 695 | EmitUint8(0x2A); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 696 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 697 | } |
| 698 | |
| 699 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 700 | void X86_64Assembler::cvtsi2sd(XmmRegister dst, const Address& src, bool is64bit) { |
| 701 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 702 | EmitUint8(0xF2); |
| 703 | if (is64bit) { |
| 704 | // Emit a REX.W prefix if the operand size is 64 bits. |
| 705 | EmitRex64(dst, src); |
| 706 | } else { |
| 707 | EmitOptionalRex32(dst, src); |
| 708 | } |
| 709 | EmitUint8(0x0F); |
| 710 | EmitUint8(0x2A); |
| 711 | EmitOperand(dst.LowBits(), src); |
| 712 | } |
| 713 | |
| 714 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 715 | void X86_64Assembler::cvtss2si(CpuRegister dst, XmmRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 716 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 717 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 718 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 719 | EmitUint8(0x0F); |
| 720 | EmitUint8(0x2D); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 721 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | |
| 725 | void X86_64Assembler::cvtss2sd(XmmRegister dst, XmmRegister src) { |
| 726 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 727 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 728 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 729 | EmitUint8(0x0F); |
| 730 | EmitUint8(0x5A); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 731 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 732 | } |
| 733 | |
| 734 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 735 | void X86_64Assembler::cvtss2sd(XmmRegister dst, const Address& src) { |
| 736 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 737 | EmitUint8(0xF3); |
| 738 | EmitOptionalRex32(dst, src); |
| 739 | EmitUint8(0x0F); |
| 740 | EmitUint8(0x5A); |
| 741 | EmitOperand(dst.LowBits(), src); |
| 742 | } |
| 743 | |
| 744 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 745 | void X86_64Assembler::cvtsd2si(CpuRegister dst, XmmRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 746 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 747 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 748 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 749 | EmitUint8(0x0F); |
| 750 | EmitUint8(0x2D); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 751 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 752 | } |
| 753 | |
| 754 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 755 | void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) { |
Roland Levillain | 624279f | 2014-12-04 11:54:28 +0000 | [diff] [blame] | 756 | cvttss2si(dst, src, false); |
| 757 | } |
| 758 | |
| 759 | |
| 760 | void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 761 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 762 | EmitUint8(0xF3); |
Roland Levillain | 624279f | 2014-12-04 11:54:28 +0000 | [diff] [blame] | 763 | if (is64bit) { |
| 764 | // Emit a REX.W prefix if the operand size is 64 bits. |
| 765 | EmitRex64(dst, src); |
| 766 | } else { |
| 767 | EmitOptionalRex32(dst, src); |
| 768 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 769 | EmitUint8(0x0F); |
| 770 | EmitUint8(0x2C); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 771 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 775 | void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src) { |
Roland Levillain | 4c0b61f | 2014-12-05 12:06:01 +0000 | [diff] [blame] | 776 | cvttsd2si(dst, src, false); |
| 777 | } |
| 778 | |
| 779 | |
| 780 | void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 781 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 782 | EmitUint8(0xF2); |
Roland Levillain | 4c0b61f | 2014-12-05 12:06:01 +0000 | [diff] [blame] | 783 | if (is64bit) { |
| 784 | // Emit a REX.W prefix if the operand size is 64 bits. |
| 785 | EmitRex64(dst, src); |
| 786 | } else { |
| 787 | EmitOptionalRex32(dst, src); |
| 788 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 789 | EmitUint8(0x0F); |
| 790 | EmitUint8(0x2C); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 791 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 792 | } |
| 793 | |
| 794 | |
| 795 | void X86_64Assembler::cvtsd2ss(XmmRegister dst, XmmRegister src) { |
| 796 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 797 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 798 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 799 | EmitUint8(0x0F); |
| 800 | EmitUint8(0x5A); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 801 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 802 | } |
| 803 | |
| 804 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 805 | void X86_64Assembler::cvtsd2ss(XmmRegister dst, const Address& src) { |
| 806 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 807 | EmitUint8(0xF2); |
| 808 | EmitOptionalRex32(dst, src); |
| 809 | EmitUint8(0x0F); |
| 810 | EmitUint8(0x5A); |
| 811 | EmitOperand(dst.LowBits(), src); |
| 812 | } |
| 813 | |
| 814 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 815 | void X86_64Assembler::cvtdq2pd(XmmRegister dst, XmmRegister src) { |
| 816 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 817 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 818 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 819 | EmitUint8(0x0F); |
| 820 | EmitUint8(0xE6); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 821 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 822 | } |
| 823 | |
| 824 | |
| 825 | void X86_64Assembler::comiss(XmmRegister a, XmmRegister b) { |
| 826 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 827 | EmitOptionalRex32(a, b); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 828 | EmitUint8(0x0F); |
| 829 | EmitUint8(0x2F); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 830 | EmitXmmRegisterOperand(a.LowBits(), b); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 831 | } |
| 832 | |
| 833 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 834 | void X86_64Assembler::comiss(XmmRegister a, const Address& b) { |
| 835 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 836 | EmitOptionalRex32(a, b); |
| 837 | EmitUint8(0x0F); |
| 838 | EmitUint8(0x2F); |
| 839 | EmitOperand(a.LowBits(), b); |
| 840 | } |
| 841 | |
| 842 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 843 | void X86_64Assembler::comisd(XmmRegister a, XmmRegister b) { |
| 844 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 845 | EmitUint8(0x66); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 846 | EmitOptionalRex32(a, b); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 847 | EmitUint8(0x0F); |
| 848 | EmitUint8(0x2F); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 849 | EmitXmmRegisterOperand(a.LowBits(), b); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 850 | } |
| 851 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 852 | |
| 853 | void X86_64Assembler::comisd(XmmRegister a, const Address& b) { |
| 854 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 855 | EmitUint8(0x66); |
| 856 | EmitOptionalRex32(a, b); |
| 857 | EmitUint8(0x0F); |
| 858 | EmitUint8(0x2F); |
| 859 | EmitOperand(a.LowBits(), b); |
| 860 | } |
| 861 | |
| 862 | |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 863 | void X86_64Assembler::ucomiss(XmmRegister a, XmmRegister b) { |
| 864 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 865 | EmitOptionalRex32(a, b); |
| 866 | EmitUint8(0x0F); |
| 867 | EmitUint8(0x2E); |
| 868 | EmitXmmRegisterOperand(a.LowBits(), b); |
| 869 | } |
| 870 | |
| 871 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 872 | void X86_64Assembler::ucomiss(XmmRegister a, const Address& b) { |
| 873 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 874 | EmitOptionalRex32(a, b); |
| 875 | EmitUint8(0x0F); |
| 876 | EmitUint8(0x2E); |
| 877 | EmitOperand(a.LowBits(), b); |
| 878 | } |
| 879 | |
| 880 | |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 881 | void X86_64Assembler::ucomisd(XmmRegister a, XmmRegister b) { |
| 882 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 883 | EmitUint8(0x66); |
| 884 | EmitOptionalRex32(a, b); |
| 885 | EmitUint8(0x0F); |
| 886 | EmitUint8(0x2E); |
| 887 | EmitXmmRegisterOperand(a.LowBits(), b); |
| 888 | } |
| 889 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 890 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 891 | void X86_64Assembler::ucomisd(XmmRegister a, const Address& b) { |
| 892 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 893 | EmitUint8(0x66); |
| 894 | EmitOptionalRex32(a, b); |
| 895 | EmitUint8(0x0F); |
| 896 | EmitUint8(0x2E); |
| 897 | EmitOperand(a.LowBits(), b); |
| 898 | } |
| 899 | |
| 900 | |
Mark Mendell | fb8d279 | 2015-03-31 22:16:59 -0400 | [diff] [blame] | 901 | void X86_64Assembler::roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 902 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 903 | EmitUint8(0x66); |
| 904 | EmitOptionalRex32(dst, src); |
| 905 | EmitUint8(0x0F); |
| 906 | EmitUint8(0x3A); |
| 907 | EmitUint8(0x0B); |
| 908 | EmitXmmRegisterOperand(dst.LowBits(), src); |
| 909 | EmitUint8(imm.value()); |
| 910 | } |
| 911 | |
| 912 | |
| 913 | void X86_64Assembler::roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) { |
| 914 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 915 | EmitUint8(0x66); |
| 916 | EmitOptionalRex32(dst, src); |
| 917 | EmitUint8(0x0F); |
| 918 | EmitUint8(0x3A); |
| 919 | EmitUint8(0x0A); |
| 920 | EmitXmmRegisterOperand(dst.LowBits(), src); |
| 921 | EmitUint8(imm.value()); |
| 922 | } |
| 923 | |
| 924 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 925 | void X86_64Assembler::sqrtsd(XmmRegister dst, XmmRegister src) { |
| 926 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 927 | EmitUint8(0xF2); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 928 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 929 | EmitUint8(0x0F); |
| 930 | EmitUint8(0x51); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 931 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | |
| 935 | void X86_64Assembler::sqrtss(XmmRegister dst, XmmRegister src) { |
| 936 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 937 | EmitUint8(0xF3); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 938 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 939 | EmitUint8(0x0F); |
| 940 | EmitUint8(0x51); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 941 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 942 | } |
| 943 | |
| 944 | |
| 945 | void X86_64Assembler::xorpd(XmmRegister dst, const Address& src) { |
| 946 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 947 | EmitUint8(0x66); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 948 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 949 | EmitUint8(0x0F); |
| 950 | EmitUint8(0x57); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 951 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 952 | } |
| 953 | |
| 954 | |
| 955 | void X86_64Assembler::xorpd(XmmRegister dst, XmmRegister src) { |
| 956 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 957 | EmitUint8(0x66); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 958 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 959 | EmitUint8(0x0F); |
| 960 | EmitUint8(0x57); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 961 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 962 | } |
| 963 | |
| 964 | |
| 965 | void X86_64Assembler::xorps(XmmRegister dst, const Address& src) { |
| 966 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 967 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 968 | EmitUint8(0x0F); |
| 969 | EmitUint8(0x57); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 970 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 971 | } |
| 972 | |
| 973 | |
| 974 | void X86_64Assembler::xorps(XmmRegister dst, XmmRegister src) { |
| 975 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 976 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 977 | EmitUint8(0x0F); |
| 978 | EmitUint8(0x57); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 979 | EmitXmmRegisterOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 980 | } |
| 981 | |
| 982 | |
| 983 | void X86_64Assembler::andpd(XmmRegister dst, const Address& src) { |
| 984 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 985 | EmitUint8(0x66); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 986 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 987 | EmitUint8(0x0F); |
| 988 | EmitUint8(0x54); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 989 | EmitOperand(dst.LowBits(), src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 990 | } |
| 991 | |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 992 | void X86_64Assembler::andpd(XmmRegister dst, XmmRegister src) { |
| 993 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 994 | EmitUint8(0x66); |
| 995 | EmitOptionalRex32(dst, src); |
| 996 | EmitUint8(0x0F); |
| 997 | EmitUint8(0x54); |
| 998 | EmitXmmRegisterOperand(dst.LowBits(), src); |
| 999 | } |
| 1000 | |
| 1001 | void X86_64Assembler::andps(XmmRegister dst, XmmRegister src) { |
| 1002 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1003 | EmitOptionalRex32(dst, src); |
| 1004 | EmitUint8(0x0F); |
| 1005 | EmitUint8(0x54); |
| 1006 | EmitXmmRegisterOperand(dst.LowBits(), src); |
| 1007 | } |
| 1008 | |
| 1009 | void X86_64Assembler::orpd(XmmRegister dst, XmmRegister src) { |
| 1010 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1011 | EmitUint8(0x66); |
| 1012 | EmitOptionalRex32(dst, src); |
| 1013 | EmitUint8(0x0F); |
| 1014 | EmitUint8(0x56); |
| 1015 | EmitXmmRegisterOperand(dst.LowBits(), src); |
| 1016 | } |
| 1017 | |
| 1018 | void X86_64Assembler::orps(XmmRegister dst, XmmRegister src) { |
| 1019 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1020 | EmitOptionalRex32(dst, src); |
| 1021 | EmitUint8(0x0F); |
| 1022 | EmitUint8(0x56); |
| 1023 | EmitXmmRegisterOperand(dst.LowBits(), src); |
| 1024 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1025 | |
| 1026 | void X86_64Assembler::fldl(const Address& src) { |
| 1027 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1028 | EmitUint8(0xDD); |
| 1029 | EmitOperand(0, src); |
| 1030 | } |
| 1031 | |
| 1032 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1033 | void X86_64Assembler::fstl(const Address& dst) { |
| 1034 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1035 | EmitUint8(0xDD); |
| 1036 | EmitOperand(2, dst); |
| 1037 | } |
| 1038 | |
| 1039 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1040 | void X86_64Assembler::fstpl(const Address& dst) { |
| 1041 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1042 | EmitUint8(0xDD); |
| 1043 | EmitOperand(3, dst); |
| 1044 | } |
| 1045 | |
| 1046 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1047 | void X86_64Assembler::fstsw() { |
| 1048 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1049 | EmitUint8(0x9B); |
| 1050 | EmitUint8(0xDF); |
| 1051 | EmitUint8(0xE0); |
| 1052 | } |
| 1053 | |
| 1054 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1055 | void X86_64Assembler::fnstcw(const Address& dst) { |
| 1056 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1057 | EmitUint8(0xD9); |
| 1058 | EmitOperand(7, dst); |
| 1059 | } |
| 1060 | |
| 1061 | |
| 1062 | void X86_64Assembler::fldcw(const Address& src) { |
| 1063 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1064 | EmitUint8(0xD9); |
| 1065 | EmitOperand(5, src); |
| 1066 | } |
| 1067 | |
| 1068 | |
| 1069 | void X86_64Assembler::fistpl(const Address& dst) { |
| 1070 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1071 | EmitUint8(0xDF); |
| 1072 | EmitOperand(7, dst); |
| 1073 | } |
| 1074 | |
| 1075 | |
| 1076 | void X86_64Assembler::fistps(const Address& dst) { |
| 1077 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1078 | EmitUint8(0xDB); |
| 1079 | EmitOperand(3, dst); |
| 1080 | } |
| 1081 | |
| 1082 | |
| 1083 | void X86_64Assembler::fildl(const Address& src) { |
| 1084 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1085 | EmitUint8(0xDF); |
| 1086 | EmitOperand(5, src); |
| 1087 | } |
| 1088 | |
| 1089 | |
Roland Levillain | 0a18601 | 2015-04-13 17:00:20 +0100 | [diff] [blame] | 1090 | void X86_64Assembler::filds(const Address& src) { |
| 1091 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1092 | EmitUint8(0xDB); |
| 1093 | EmitOperand(0, src); |
| 1094 | } |
| 1095 | |
| 1096 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1097 | void X86_64Assembler::fincstp() { |
| 1098 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1099 | EmitUint8(0xD9); |
| 1100 | EmitUint8(0xF7); |
| 1101 | } |
| 1102 | |
| 1103 | |
| 1104 | void X86_64Assembler::ffree(const Immediate& index) { |
| 1105 | CHECK_LT(index.value(), 7); |
| 1106 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1107 | EmitUint8(0xDD); |
| 1108 | EmitUint8(0xC0 + index.value()); |
| 1109 | } |
| 1110 | |
| 1111 | |
| 1112 | void X86_64Assembler::fsin() { |
| 1113 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1114 | EmitUint8(0xD9); |
| 1115 | EmitUint8(0xFE); |
| 1116 | } |
| 1117 | |
| 1118 | |
| 1119 | void X86_64Assembler::fcos() { |
| 1120 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1121 | EmitUint8(0xD9); |
| 1122 | EmitUint8(0xFF); |
| 1123 | } |
| 1124 | |
| 1125 | |
| 1126 | void X86_64Assembler::fptan() { |
| 1127 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1128 | EmitUint8(0xD9); |
| 1129 | EmitUint8(0xF2); |
| 1130 | } |
| 1131 | |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 1132 | void X86_64Assembler::fucompp() { |
| 1133 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1134 | EmitUint8(0xDA); |
| 1135 | EmitUint8(0xE9); |
| 1136 | } |
| 1137 | |
| 1138 | |
| 1139 | void X86_64Assembler::fprem() { |
| 1140 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1141 | EmitUint8(0xD9); |
| 1142 | EmitUint8(0xF8); |
| 1143 | } |
| 1144 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1145 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1146 | void X86_64Assembler::xchgl(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1147 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1148 | // There is a short version for rax. |
| 1149 | // It's a bit awkward, as CpuRegister has a const field, so assignment and thus swapping doesn't |
| 1150 | // work. |
| 1151 | const bool src_rax = src.AsRegister() == RAX; |
| 1152 | const bool dst_rax = dst.AsRegister() == RAX; |
| 1153 | if (src_rax || dst_rax) { |
| 1154 | EmitOptionalRex32(src_rax ? dst : src); |
| 1155 | EmitUint8(0x90 + (src_rax ? dst.LowBits() : src.LowBits())); |
| 1156 | return; |
| 1157 | } |
| 1158 | |
| 1159 | // General case. |
| 1160 | EmitOptionalRex32(src, dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1161 | EmitUint8(0x87); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1162 | EmitRegisterOperand(src.LowBits(), dst.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1163 | } |
| 1164 | |
Nicolas Geoffray | ecb2f9b | 2014-06-13 08:59:59 +0000 | [diff] [blame] | 1165 | |
| 1166 | void X86_64Assembler::xchgq(CpuRegister dst, CpuRegister src) { |
| 1167 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1168 | // There is a short version for rax. |
| 1169 | // It's a bit awkward, as CpuRegister has a const field, so assignment and thus swapping doesn't |
| 1170 | // work. |
| 1171 | const bool src_rax = src.AsRegister() == RAX; |
| 1172 | const bool dst_rax = dst.AsRegister() == RAX; |
| 1173 | if (src_rax || dst_rax) { |
| 1174 | // If src == target, emit a nop instead. |
| 1175 | if (src_rax && dst_rax) { |
| 1176 | EmitUint8(0x90); |
| 1177 | } else { |
| 1178 | EmitRex64(src_rax ? dst : src); |
| 1179 | EmitUint8(0x90 + (src_rax ? dst.LowBits() : src.LowBits())); |
| 1180 | } |
| 1181 | return; |
| 1182 | } |
| 1183 | |
| 1184 | // General case. |
| 1185 | EmitRex64(src, dst); |
Nicolas Geoffray | ecb2f9b | 2014-06-13 08:59:59 +0000 | [diff] [blame] | 1186 | EmitUint8(0x87); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1187 | EmitRegisterOperand(src.LowBits(), dst.LowBits()); |
Nicolas Geoffray | ecb2f9b | 2014-06-13 08:59:59 +0000 | [diff] [blame] | 1188 | } |
| 1189 | |
| 1190 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1191 | void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1192 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1193 | EmitOptionalRex32(reg, address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1194 | EmitUint8(0x87); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1195 | EmitOperand(reg.LowBits(), address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1196 | } |
| 1197 | |
| 1198 | |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 1199 | void X86_64Assembler::cmpw(const Address& address, const Immediate& imm) { |
| 1200 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1201 | EmitOptionalRex32(address); |
| 1202 | EmitUint8(0x66); |
| 1203 | EmitComplex(7, address, imm); |
| 1204 | } |
| 1205 | |
| 1206 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1207 | void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1208 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1209 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1210 | EmitComplex(7, Operand(reg), imm); |
| 1211 | } |
| 1212 | |
| 1213 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1214 | void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1215 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1216 | EmitOptionalRex32(reg0, reg1); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1217 | EmitUint8(0x3B); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1218 | EmitOperand(reg0.LowBits(), Operand(reg1)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1219 | } |
| 1220 | |
| 1221 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1222 | void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1223 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1224 | EmitOptionalRex32(reg, address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1225 | EmitUint8(0x3B); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1226 | EmitOperand(reg.LowBits(), address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1227 | } |
| 1228 | |
| 1229 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 1230 | void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) { |
| 1231 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1232 | EmitOptionalRex32(reg, address); |
| 1233 | EmitUint8(0x39); |
| 1234 | EmitOperand(reg.LowBits(), address); |
| 1235 | } |
| 1236 | |
| 1237 | |
| 1238 | void X86_64Assembler::cmpl(const Address& address, const Immediate& imm) { |
| 1239 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1240 | EmitOptionalRex32(address); |
| 1241 | EmitComplex(7, address, imm); |
| 1242 | } |
| 1243 | |
| 1244 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 1245 | void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) { |
| 1246 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1247 | EmitRex64(reg0, reg1); |
| 1248 | EmitUint8(0x3B); |
| 1249 | EmitOperand(reg0.LowBits(), Operand(reg1)); |
| 1250 | } |
| 1251 | |
| 1252 | |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 1253 | void X86_64Assembler::cmpq(CpuRegister reg, const Immediate& imm) { |
| 1254 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1255 | CHECK(imm.is_int32()); // cmpq only supports 32b immediate. |
| 1256 | EmitRex64(reg); |
| 1257 | EmitComplex(7, Operand(reg), imm); |
| 1258 | } |
| 1259 | |
| 1260 | |
| 1261 | void X86_64Assembler::cmpq(CpuRegister reg, const Address& address) { |
| 1262 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 1263 | EmitRex64(reg, address); |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 1264 | EmitUint8(0x3B); |
| 1265 | EmitOperand(reg.LowBits(), address); |
| 1266 | } |
| 1267 | |
| 1268 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 1269 | void X86_64Assembler::cmpq(const Address& address, const Immediate& imm) { |
| 1270 | CHECK(imm.is_int32()); // cmpq only supports 32b immediate. |
| 1271 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1272 | EmitRex64(address); |
| 1273 | EmitComplex(7, address, imm); |
| 1274 | } |
| 1275 | |
| 1276 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1277 | void X86_64Assembler::addl(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1278 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1279 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1280 | EmitUint8(0x03); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1281 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1282 | } |
| 1283 | |
| 1284 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1285 | void X86_64Assembler::addl(CpuRegister reg, const Address& address) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1286 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1287 | EmitOptionalRex32(reg, address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1288 | EmitUint8(0x03); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1289 | EmitOperand(reg.LowBits(), address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1290 | } |
| 1291 | |
| 1292 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1293 | void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1294 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1295 | EmitOptionalRex32(reg1, reg2); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1296 | EmitUint8(0x85); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1297 | EmitRegisterOperand(reg1.LowBits(), reg2.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1298 | } |
| 1299 | |
| 1300 | |
Calin Juravle | cd6dffe | 2015-01-08 17:35:35 +0000 | [diff] [blame] | 1301 | void X86_64Assembler::testl(CpuRegister reg, const Address& address) { |
| 1302 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1303 | EmitOptionalRex32(reg, address); |
| 1304 | EmitUint8(0x85); |
| 1305 | EmitOperand(reg.LowBits(), address); |
| 1306 | } |
| 1307 | |
| 1308 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1309 | void X86_64Assembler::testl(CpuRegister reg, const Immediate& immediate) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1310 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1311 | // For registers that have a byte variant (RAX, RBX, RCX, and RDX) |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1312 | // we only test the byte CpuRegister to keep the encoding short. |
| 1313 | if (immediate.is_uint8() && reg.AsRegister() < 4) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1314 | // Use zero-extended 8-bit immediate. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1315 | if (reg.AsRegister() == RAX) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1316 | EmitUint8(0xA8); |
| 1317 | } else { |
| 1318 | EmitUint8(0xF6); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1319 | EmitUint8(0xC0 + reg.AsRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1320 | } |
| 1321 | EmitUint8(immediate.value() & 0xFF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1322 | } else if (reg.AsRegister() == RAX) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1323 | // Use short form if the destination is RAX. |
| 1324 | EmitUint8(0xA9); |
| 1325 | EmitImmediate(immediate); |
| 1326 | } else { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1327 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1328 | EmitUint8(0xF7); |
| 1329 | EmitOperand(0, Operand(reg)); |
| 1330 | EmitImmediate(immediate); |
| 1331 | } |
| 1332 | } |
| 1333 | |
| 1334 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 1335 | void X86_64Assembler::testq(CpuRegister reg1, CpuRegister reg2) { |
| 1336 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1337 | EmitRex64(reg1, reg2); |
| 1338 | EmitUint8(0x85); |
| 1339 | EmitRegisterOperand(reg1.LowBits(), reg2.LowBits()); |
| 1340 | } |
| 1341 | |
| 1342 | |
Nicolas Geoffray | f12feb8 | 2014-07-17 18:32:41 +0100 | [diff] [blame] | 1343 | void X86_64Assembler::testq(CpuRegister reg, const Address& address) { |
| 1344 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 7fd8b59 | 2015-04-22 10:46:07 -0400 | [diff] [blame] | 1345 | EmitRex64(reg, address); |
Nicolas Geoffray | f12feb8 | 2014-07-17 18:32:41 +0100 | [diff] [blame] | 1346 | EmitUint8(0x85); |
| 1347 | EmitOperand(reg.LowBits(), address); |
| 1348 | } |
| 1349 | |
| 1350 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1351 | void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1352 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1353 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1354 | EmitUint8(0x23); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1355 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1356 | } |
| 1357 | |
| 1358 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1359 | void X86_64Assembler::andl(CpuRegister reg, const Address& address) { |
| 1360 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1361 | EmitOptionalRex32(reg, address); |
| 1362 | EmitUint8(0x23); |
| 1363 | EmitOperand(reg.LowBits(), address); |
| 1364 | } |
| 1365 | |
| 1366 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1367 | void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1368 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1369 | EmitOptionalRex32(dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1370 | EmitComplex(4, Operand(dst), imm); |
| 1371 | } |
| 1372 | |
| 1373 | |
Nicolas Geoffray | 412f10c | 2014-06-19 10:00:34 +0100 | [diff] [blame] | 1374 | void X86_64Assembler::andq(CpuRegister reg, const Immediate& imm) { |
| 1375 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1376 | CHECK(imm.is_int32()); // andq only supports 32b immediate. |
| 1377 | EmitRex64(reg); |
| 1378 | EmitComplex(4, Operand(reg), imm); |
| 1379 | } |
| 1380 | |
| 1381 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1382 | void X86_64Assembler::andq(CpuRegister dst, CpuRegister src) { |
| 1383 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1384 | EmitRex64(dst, src); |
| 1385 | EmitUint8(0x23); |
| 1386 | EmitOperand(dst.LowBits(), Operand(src)); |
| 1387 | } |
| 1388 | |
| 1389 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 1390 | void X86_64Assembler::andq(CpuRegister dst, const Address& src) { |
| 1391 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1392 | EmitRex64(dst, src); |
| 1393 | EmitUint8(0x23); |
| 1394 | EmitOperand(dst.LowBits(), src); |
| 1395 | } |
| 1396 | |
| 1397 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1398 | void X86_64Assembler::orl(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1399 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1400 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1401 | EmitUint8(0x0B); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1402 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1403 | } |
| 1404 | |
| 1405 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1406 | void X86_64Assembler::orl(CpuRegister reg, const Address& address) { |
| 1407 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1408 | EmitOptionalRex32(reg, address); |
| 1409 | EmitUint8(0x0B); |
| 1410 | EmitOperand(reg.LowBits(), address); |
| 1411 | } |
| 1412 | |
| 1413 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1414 | void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1415 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1416 | EmitOptionalRex32(dst); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1417 | EmitComplex(1, Operand(dst), imm); |
| 1418 | } |
| 1419 | |
| 1420 | |
Mark Mendell | 3f6c7f6 | 2015-03-13 13:47:53 -0400 | [diff] [blame] | 1421 | void X86_64Assembler::orq(CpuRegister dst, const Immediate& imm) { |
| 1422 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1423 | CHECK(imm.is_int32()); // orq only supports 32b immediate. |
| 1424 | EmitRex64(dst); |
| 1425 | EmitComplex(1, Operand(dst), imm); |
| 1426 | } |
| 1427 | |
| 1428 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1429 | void X86_64Assembler::orq(CpuRegister dst, CpuRegister src) { |
| 1430 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1431 | EmitRex64(dst, src); |
| 1432 | EmitUint8(0x0B); |
| 1433 | EmitOperand(dst.LowBits(), Operand(src)); |
| 1434 | } |
| 1435 | |
| 1436 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 1437 | void X86_64Assembler::orq(CpuRegister dst, const Address& src) { |
| 1438 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1439 | EmitRex64(dst, src); |
| 1440 | EmitUint8(0x0B); |
| 1441 | EmitOperand(dst.LowBits(), src); |
| 1442 | } |
| 1443 | |
| 1444 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1445 | void X86_64Assembler::xorl(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1446 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1447 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1448 | EmitUint8(0x33); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1449 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1450 | } |
| 1451 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 1452 | |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 1453 | void X86_64Assembler::xorl(CpuRegister reg, const Address& address) { |
| 1454 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1455 | EmitOptionalRex32(reg, address); |
| 1456 | EmitUint8(0x33); |
| 1457 | EmitOperand(reg.LowBits(), address); |
| 1458 | } |
| 1459 | |
| 1460 | |
| 1461 | void X86_64Assembler::xorl(CpuRegister dst, const Immediate& imm) { |
| 1462 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1463 | EmitOptionalRex32(dst); |
| 1464 | EmitComplex(6, Operand(dst), imm); |
| 1465 | } |
| 1466 | |
| 1467 | |
Nicolas Geoffray | 412f10c | 2014-06-19 10:00:34 +0100 | [diff] [blame] | 1468 | void X86_64Assembler::xorq(CpuRegister dst, CpuRegister src) { |
| 1469 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1470 | EmitRex64(dst, src); |
| 1471 | EmitUint8(0x33); |
| 1472 | EmitOperand(dst.LowBits(), Operand(src)); |
| 1473 | } |
| 1474 | |
| 1475 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 1476 | void X86_64Assembler::xorq(CpuRegister dst, const Immediate& imm) { |
| 1477 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1478 | CHECK(imm.is_int32()); // xorq only supports 32b immediate. |
| 1479 | EmitRex64(dst); |
| 1480 | EmitComplex(6, Operand(dst), imm); |
| 1481 | } |
| 1482 | |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 1483 | void X86_64Assembler::xorq(CpuRegister dst, const Address& src) { |
| 1484 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1485 | EmitRex64(dst, src); |
| 1486 | EmitUint8(0x33); |
| 1487 | EmitOperand(dst.LowBits(), src); |
| 1488 | } |
| 1489 | |
| 1490 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1491 | #if 0 |
| 1492 | void X86_64Assembler::rex(bool force, bool w, Register* r, Register* x, Register* b) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1493 | // REX.WRXB |
| 1494 | // W - 64-bit operand |
| 1495 | // R - MODRM.reg |
| 1496 | // X - SIB.index |
| 1497 | // B - MODRM.rm/SIB.base |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1498 | uint8_t rex = force ? 0x40 : 0; |
| 1499 | if (w) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1500 | rex |= 0x48; // REX.W000 |
| 1501 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1502 | if (r != nullptr && *r >= Register::R8 && *r < Register::kNumberOfCpuRegisters) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1503 | rex |= 0x44; // REX.0R00 |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1504 | *r = static_cast<Register>(*r - 8); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1505 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1506 | if (x != nullptr && *x >= Register::R8 && *x < Register::kNumberOfCpuRegisters) { |
| 1507 | rex |= 0x42; // REX.00X0 |
| 1508 | *x = static_cast<Register>(*x - 8); |
| 1509 | } |
| 1510 | if (b != nullptr && *b >= Register::R8 && *b < Register::kNumberOfCpuRegisters) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1511 | rex |= 0x41; // REX.000B |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1512 | *b = static_cast<Register>(*b - 8); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1513 | } |
| 1514 | if (rex != 0) { |
| 1515 | EmitUint8(rex); |
| 1516 | } |
| 1517 | } |
| 1518 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1519 | void X86_64Assembler::rex_reg_mem(bool force, bool w, Register* dst, const Address& mem) { |
| 1520 | // REX.WRXB |
| 1521 | // W - 64-bit operand |
| 1522 | // R - MODRM.reg |
| 1523 | // X - SIB.index |
| 1524 | // B - MODRM.rm/SIB.base |
| 1525 | uint8_t rex = mem->rex(); |
| 1526 | if (force) { |
| 1527 | rex |= 0x40; // REX.0000 |
| 1528 | } |
| 1529 | if (w) { |
| 1530 | rex |= 0x48; // REX.W000 |
| 1531 | } |
| 1532 | if (dst != nullptr && *dst >= Register::R8 && *dst < Register::kNumberOfCpuRegisters) { |
| 1533 | rex |= 0x44; // REX.0R00 |
| 1534 | *dst = static_cast<Register>(*dst - 8); |
| 1535 | } |
| 1536 | if (rex != 0) { |
| 1537 | EmitUint8(rex); |
| 1538 | } |
| 1539 | } |
| 1540 | |
| 1541 | void rex_mem_reg(bool force, bool w, Address* mem, Register* src); |
| 1542 | #endif |
| 1543 | |
| 1544 | void X86_64Assembler::addl(CpuRegister reg, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1545 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1546 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1547 | EmitComplex(0, Operand(reg), imm); |
| 1548 | } |
| 1549 | |
| 1550 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1551 | void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1552 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 1553 | CHECK(imm.is_int32()); // addq only supports 32b immediate. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1554 | EmitRex64(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1555 | EmitComplex(0, Operand(reg), imm); |
| 1556 | } |
| 1557 | |
| 1558 | |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 1559 | void X86_64Assembler::addq(CpuRegister dst, const Address& address) { |
| 1560 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 7fd8b59 | 2015-04-22 10:46:07 -0400 | [diff] [blame] | 1561 | EmitRex64(dst, address); |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 1562 | EmitUint8(0x03); |
| 1563 | EmitOperand(dst.LowBits(), address); |
| 1564 | } |
| 1565 | |
| 1566 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 1567 | void X86_64Assembler::addq(CpuRegister dst, CpuRegister src) { |
| 1568 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1569 | // 0x01 is addq r/m64 <- r/m64 + r64, with op1 in r/m and op2 in reg: so reverse EmitRex64 |
| 1570 | EmitRex64(src, dst); |
| 1571 | EmitUint8(0x01); |
| 1572 | EmitRegisterOperand(src.LowBits(), dst.LowBits()); |
| 1573 | } |
| 1574 | |
| 1575 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1576 | void X86_64Assembler::addl(const Address& address, CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1577 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1578 | EmitOptionalRex32(reg, address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1579 | EmitUint8(0x01); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1580 | EmitOperand(reg.LowBits(), address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1581 | } |
| 1582 | |
| 1583 | |
| 1584 | void X86_64Assembler::addl(const Address& address, const Immediate& imm) { |
| 1585 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1586 | EmitOptionalRex32(address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1587 | EmitComplex(0, address, imm); |
| 1588 | } |
| 1589 | |
| 1590 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1591 | void X86_64Assembler::subl(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1592 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1593 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1594 | EmitUint8(0x2B); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1595 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1596 | } |
| 1597 | |
| 1598 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1599 | void X86_64Assembler::subl(CpuRegister reg, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1600 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1601 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1602 | EmitComplex(5, Operand(reg), imm); |
| 1603 | } |
| 1604 | |
| 1605 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 1606 | void X86_64Assembler::subq(CpuRegister reg, const Immediate& imm) { |
| 1607 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1608 | CHECK(imm.is_int32()); // subq only supports 32b immediate. |
| 1609 | EmitRex64(reg); |
| 1610 | EmitComplex(5, Operand(reg), imm); |
| 1611 | } |
| 1612 | |
| 1613 | |
| 1614 | void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) { |
| 1615 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1616 | EmitRex64(dst, src); |
| 1617 | EmitUint8(0x2B); |
| 1618 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
| 1619 | } |
| 1620 | |
| 1621 | |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 1622 | void X86_64Assembler::subq(CpuRegister reg, const Address& address) { |
| 1623 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 7fd8b59 | 2015-04-22 10:46:07 -0400 | [diff] [blame] | 1624 | EmitRex64(reg, address); |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 1625 | EmitUint8(0x2B); |
| 1626 | EmitOperand(reg.LowBits() & 7, address); |
| 1627 | } |
| 1628 | |
| 1629 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1630 | void X86_64Assembler::subl(CpuRegister reg, const Address& address) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1631 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1632 | EmitOptionalRex32(reg, address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1633 | EmitUint8(0x2B); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1634 | EmitOperand(reg.LowBits(), address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1635 | } |
| 1636 | |
| 1637 | |
| 1638 | void X86_64Assembler::cdq() { |
| 1639 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1640 | EmitUint8(0x99); |
| 1641 | } |
| 1642 | |
| 1643 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 1644 | void X86_64Assembler::cqo() { |
| 1645 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1646 | EmitRex64(); |
| 1647 | EmitUint8(0x99); |
| 1648 | } |
| 1649 | |
| 1650 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1651 | void X86_64Assembler::idivl(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1652 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1653 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1654 | EmitUint8(0xF7); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1655 | EmitUint8(0xF8 | reg.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1656 | } |
| 1657 | |
| 1658 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 1659 | void X86_64Assembler::idivq(CpuRegister reg) { |
| 1660 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1661 | EmitRex64(reg); |
| 1662 | EmitUint8(0xF7); |
| 1663 | EmitUint8(0xF8 | reg.LowBits()); |
| 1664 | } |
| 1665 | |
| 1666 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1667 | void X86_64Assembler::imull(CpuRegister dst, CpuRegister src) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1668 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1669 | EmitOptionalRex32(dst, src); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1670 | EmitUint8(0x0F); |
| 1671 | EmitUint8(0xAF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1672 | EmitOperand(dst.LowBits(), Operand(src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1673 | } |
| 1674 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1675 | void X86_64Assembler::imull(CpuRegister reg, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1676 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1677 | CHECK(imm.is_int32()); // imull only supports 32b immediate. |
| 1678 | |
Nicolas Geoffray | b5de00f | 2014-10-24 15:43:49 +0100 | [diff] [blame] | 1679 | EmitOptionalRex32(reg, reg); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1680 | |
| 1681 | // See whether imm can be represented as a sign-extended 8bit value. |
| 1682 | int32_t v32 = static_cast<int32_t>(imm.value()); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 1683 | if (IsInt<8>(v32)) { |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1684 | // Sign-extension works. |
| 1685 | EmitUint8(0x6B); |
| 1686 | EmitOperand(reg.LowBits(), Operand(reg)); |
| 1687 | EmitUint8(static_cast<uint8_t>(v32 & 0xFF)); |
| 1688 | } else { |
| 1689 | // Not representable, use full immediate. |
| 1690 | EmitUint8(0x69); |
| 1691 | EmitOperand(reg.LowBits(), Operand(reg)); |
| 1692 | EmitImmediate(imm); |
| 1693 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1694 | } |
| 1695 | |
| 1696 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1697 | void X86_64Assembler::imull(CpuRegister reg, const Address& address) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1698 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1699 | EmitOptionalRex32(reg, address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1700 | EmitUint8(0x0F); |
| 1701 | EmitUint8(0xAF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1702 | EmitOperand(reg.LowBits(), address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1703 | } |
| 1704 | |
| 1705 | |
Calin Juravle | 34bacdf | 2014-10-07 20:23:36 +0100 | [diff] [blame] | 1706 | void X86_64Assembler::imulq(CpuRegister dst, CpuRegister src) { |
| 1707 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1708 | EmitRex64(dst, src); |
| 1709 | EmitUint8(0x0F); |
| 1710 | EmitUint8(0xAF); |
| 1711 | EmitRegisterOperand(dst.LowBits(), src.LowBits()); |
| 1712 | } |
| 1713 | |
| 1714 | |
| 1715 | void X86_64Assembler::imulq(CpuRegister reg, const Immediate& imm) { |
Mark Mendell | 3f6c7f6 | 2015-03-13 13:47:53 -0400 | [diff] [blame] | 1716 | imulq(reg, reg, imm); |
| 1717 | } |
| 1718 | |
| 1719 | void X86_64Assembler::imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) { |
Calin Juravle | 34bacdf | 2014-10-07 20:23:36 +0100 | [diff] [blame] | 1720 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1721 | CHECK(imm.is_int32()); // imulq only supports 32b immediate. |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1722 | |
Mark Mendell | 3f6c7f6 | 2015-03-13 13:47:53 -0400 | [diff] [blame] | 1723 | EmitRex64(dst, reg); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1724 | |
| 1725 | // See whether imm can be represented as a sign-extended 8bit value. |
| 1726 | int64_t v64 = imm.value(); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 1727 | if (IsInt<8>(v64)) { |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1728 | // Sign-extension works. |
| 1729 | EmitUint8(0x6B); |
Mark Mendell | 3f6c7f6 | 2015-03-13 13:47:53 -0400 | [diff] [blame] | 1730 | EmitOperand(dst.LowBits(), Operand(reg)); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1731 | EmitUint8(static_cast<uint8_t>(v64 & 0xFF)); |
| 1732 | } else { |
| 1733 | // Not representable, use full immediate. |
| 1734 | EmitUint8(0x69); |
Mark Mendell | 3f6c7f6 | 2015-03-13 13:47:53 -0400 | [diff] [blame] | 1735 | EmitOperand(dst.LowBits(), Operand(reg)); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 1736 | EmitImmediate(imm); |
| 1737 | } |
Calin Juravle | 34bacdf | 2014-10-07 20:23:36 +0100 | [diff] [blame] | 1738 | } |
| 1739 | |
Calin Juravle | 34bacdf | 2014-10-07 20:23:36 +0100 | [diff] [blame] | 1740 | void X86_64Assembler::imulq(CpuRegister reg, const Address& address) { |
| 1741 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1742 | EmitRex64(reg, address); |
| 1743 | EmitUint8(0x0F); |
| 1744 | EmitUint8(0xAF); |
| 1745 | EmitOperand(reg.LowBits(), address); |
| 1746 | } |
| 1747 | |
| 1748 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1749 | void X86_64Assembler::imull(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1750 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1751 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1752 | EmitUint8(0xF7); |
| 1753 | EmitOperand(5, Operand(reg)); |
| 1754 | } |
| 1755 | |
| 1756 | |
Guillaume Sanchez | 0f88e87 | 2015-03-30 17:55:45 +0100 | [diff] [blame] | 1757 | void X86_64Assembler::imulq(CpuRegister reg) { |
| 1758 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1759 | EmitRex64(reg); |
| 1760 | EmitUint8(0xF7); |
| 1761 | EmitOperand(5, Operand(reg)); |
| 1762 | } |
| 1763 | |
| 1764 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1765 | void X86_64Assembler::imull(const Address& address) { |
| 1766 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1767 | EmitOptionalRex32(address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1768 | EmitUint8(0xF7); |
| 1769 | EmitOperand(5, address); |
| 1770 | } |
| 1771 | |
| 1772 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1773 | void X86_64Assembler::mull(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1774 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1775 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1776 | EmitUint8(0xF7); |
| 1777 | EmitOperand(4, Operand(reg)); |
| 1778 | } |
| 1779 | |
| 1780 | |
| 1781 | void X86_64Assembler::mull(const Address& address) { |
| 1782 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1783 | EmitOptionalRex32(address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1784 | EmitUint8(0xF7); |
| 1785 | EmitOperand(4, address); |
| 1786 | } |
| 1787 | |
| 1788 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1789 | void X86_64Assembler::shll(CpuRegister reg, const Immediate& imm) { |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 1790 | EmitGenericShift(false, 4, reg, imm); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1791 | } |
| 1792 | |
| 1793 | |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1794 | void X86_64Assembler::shlq(CpuRegister reg, const Immediate& imm) { |
| 1795 | EmitGenericShift(true, 4, reg, imm); |
| 1796 | } |
| 1797 | |
| 1798 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1799 | void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1800 | EmitGenericShift(false, 4, operand, shifter); |
| 1801 | } |
| 1802 | |
| 1803 | |
| 1804 | void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) { |
| 1805 | EmitGenericShift(true, 4, operand, shifter); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1806 | } |
| 1807 | |
| 1808 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1809 | void X86_64Assembler::shrl(CpuRegister reg, const Immediate& imm) { |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 1810 | EmitGenericShift(false, 5, reg, imm); |
| 1811 | } |
| 1812 | |
| 1813 | |
| 1814 | void X86_64Assembler::shrq(CpuRegister reg, const Immediate& imm) { |
| 1815 | EmitGenericShift(true, 5, reg, imm); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1816 | } |
| 1817 | |
| 1818 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1819 | void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) { |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1820 | EmitGenericShift(false, 5, operand, shifter); |
| 1821 | } |
| 1822 | |
| 1823 | |
| 1824 | void X86_64Assembler::shrq(CpuRegister operand, CpuRegister shifter) { |
| 1825 | EmitGenericShift(true, 5, operand, shifter); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1826 | } |
| 1827 | |
| 1828 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1829 | void X86_64Assembler::sarl(CpuRegister reg, const Immediate& imm) { |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 1830 | EmitGenericShift(false, 7, reg, imm); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1831 | } |
| 1832 | |
| 1833 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1834 | void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) { |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 1835 | EmitGenericShift(false, 7, operand, shifter); |
| 1836 | } |
| 1837 | |
| 1838 | |
| 1839 | void X86_64Assembler::sarq(CpuRegister reg, const Immediate& imm) { |
| 1840 | EmitGenericShift(true, 7, reg, imm); |
| 1841 | } |
| 1842 | |
| 1843 | |
| 1844 | void X86_64Assembler::sarq(CpuRegister operand, CpuRegister shifter) { |
| 1845 | EmitGenericShift(true, 7, operand, shifter); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1846 | } |
| 1847 | |
| 1848 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1849 | void X86_64Assembler::negl(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1850 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1851 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1852 | EmitUint8(0xF7); |
| 1853 | EmitOperand(3, Operand(reg)); |
| 1854 | } |
| 1855 | |
Roland Levillain | 7056643 | 2014-10-24 16:20:17 +0100 | [diff] [blame] | 1856 | |
Roland Levillain | 2e07b4f | 2014-10-23 18:12:09 +0100 | [diff] [blame] | 1857 | void X86_64Assembler::negq(CpuRegister reg) { |
| 1858 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1859 | EmitRex64(reg); |
| 1860 | EmitUint8(0xF7); |
| 1861 | EmitOperand(3, Operand(reg)); |
| 1862 | } |
| 1863 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1864 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1865 | void X86_64Assembler::notl(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1866 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1867 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1868 | EmitUint8(0xF7); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1869 | EmitUint8(0xD0 | reg.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1870 | } |
| 1871 | |
| 1872 | |
Roland Levillain | 7056643 | 2014-10-24 16:20:17 +0100 | [diff] [blame] | 1873 | void X86_64Assembler::notq(CpuRegister reg) { |
| 1874 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1875 | EmitRex64(reg); |
| 1876 | EmitUint8(0xF7); |
| 1877 | EmitOperand(2, Operand(reg)); |
| 1878 | } |
| 1879 | |
| 1880 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1881 | void X86_64Assembler::enter(const Immediate& imm) { |
| 1882 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1883 | EmitUint8(0xC8); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 1884 | CHECK(imm.is_uint16()) << imm.value(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1885 | EmitUint8(imm.value() & 0xFF); |
| 1886 | EmitUint8((imm.value() >> 8) & 0xFF); |
| 1887 | EmitUint8(0x00); |
| 1888 | } |
| 1889 | |
| 1890 | |
| 1891 | void X86_64Assembler::leave() { |
| 1892 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1893 | EmitUint8(0xC9); |
| 1894 | } |
| 1895 | |
| 1896 | |
| 1897 | void X86_64Assembler::ret() { |
| 1898 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1899 | EmitUint8(0xC3); |
| 1900 | } |
| 1901 | |
| 1902 | |
| 1903 | void X86_64Assembler::ret(const Immediate& imm) { |
| 1904 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1905 | EmitUint8(0xC2); |
| 1906 | CHECK(imm.is_uint16()); |
| 1907 | EmitUint8(imm.value() & 0xFF); |
| 1908 | EmitUint8((imm.value() >> 8) & 0xFF); |
| 1909 | } |
| 1910 | |
| 1911 | |
| 1912 | |
| 1913 | void X86_64Assembler::nop() { |
| 1914 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1915 | EmitUint8(0x90); |
| 1916 | } |
| 1917 | |
| 1918 | |
| 1919 | void X86_64Assembler::int3() { |
| 1920 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1921 | EmitUint8(0xCC); |
| 1922 | } |
| 1923 | |
| 1924 | |
| 1925 | void X86_64Assembler::hlt() { |
| 1926 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1927 | EmitUint8(0xF4); |
| 1928 | } |
| 1929 | |
| 1930 | |
| 1931 | void X86_64Assembler::j(Condition condition, Label* label) { |
| 1932 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1933 | if (label->IsBound()) { |
| 1934 | static const int kShortSize = 2; |
| 1935 | static const int kLongSize = 6; |
| 1936 | int offset = label->Position() - buffer_.Size(); |
| 1937 | CHECK_LE(offset, 0); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 1938 | if (IsInt<8>(offset - kShortSize)) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1939 | EmitUint8(0x70 + condition); |
| 1940 | EmitUint8((offset - kShortSize) & 0xFF); |
| 1941 | } else { |
| 1942 | EmitUint8(0x0F); |
| 1943 | EmitUint8(0x80 + condition); |
| 1944 | EmitInt32(offset - kLongSize); |
| 1945 | } |
| 1946 | } else { |
| 1947 | EmitUint8(0x0F); |
| 1948 | EmitUint8(0x80 + condition); |
| 1949 | EmitLabelLink(label); |
| 1950 | } |
| 1951 | } |
| 1952 | |
| 1953 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1954 | void X86_64Assembler::jmp(CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1955 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1956 | EmitOptionalRex32(reg); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1957 | EmitUint8(0xFF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1958 | EmitRegisterOperand(4, reg.LowBits()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1959 | } |
| 1960 | |
| 1961 | void X86_64Assembler::jmp(const Address& address) { |
| 1962 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1963 | EmitOptionalRex32(address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1964 | EmitUint8(0xFF); |
| 1965 | EmitOperand(4, address); |
| 1966 | } |
| 1967 | |
| 1968 | void X86_64Assembler::jmp(Label* label) { |
| 1969 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1970 | if (label->IsBound()) { |
| 1971 | static const int kShortSize = 2; |
| 1972 | static const int kLongSize = 5; |
| 1973 | int offset = label->Position() - buffer_.Size(); |
| 1974 | CHECK_LE(offset, 0); |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 1975 | if (IsInt<8>(offset - kShortSize)) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1976 | EmitUint8(0xEB); |
| 1977 | EmitUint8((offset - kShortSize) & 0xFF); |
| 1978 | } else { |
| 1979 | EmitUint8(0xE9); |
| 1980 | EmitInt32(offset - kLongSize); |
| 1981 | } |
| 1982 | } else { |
| 1983 | EmitUint8(0xE9); |
| 1984 | EmitLabelLink(label); |
| 1985 | } |
| 1986 | } |
| 1987 | |
| 1988 | |
| 1989 | X86_64Assembler* X86_64Assembler::lock() { |
| 1990 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 1991 | EmitUint8(0xF0); |
| 1992 | return this; |
| 1993 | } |
| 1994 | |
| 1995 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1996 | void X86_64Assembler::cmpxchgl(const Address& address, CpuRegister reg) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1997 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 1998 | EmitOptionalRex32(reg, address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 1999 | EmitUint8(0x0F); |
| 2000 | EmitUint8(0xB1); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2001 | EmitOperand(reg.LowBits(), address); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2002 | } |
| 2003 | |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 2004 | |
| 2005 | void X86_64Assembler::cmpxchgq(const Address& address, CpuRegister reg) { |
| 2006 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2007 | EmitRex64(reg, address); |
| 2008 | EmitUint8(0x0F); |
| 2009 | EmitUint8(0xB1); |
| 2010 | EmitOperand(reg.LowBits(), address); |
| 2011 | } |
| 2012 | |
| 2013 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2014 | void X86_64Assembler::mfence() { |
| 2015 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2016 | EmitUint8(0x0F); |
| 2017 | EmitUint8(0xAE); |
| 2018 | EmitUint8(0xF0); |
| 2019 | } |
| 2020 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 2021 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2022 | X86_64Assembler* X86_64Assembler::gs() { |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 2023 | // TODO: gs is a prefix and not an instruction |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2024 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2025 | EmitUint8(0x65); |
| 2026 | return this; |
| 2027 | } |
| 2028 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 2029 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2030 | void X86_64Assembler::AddImmediate(CpuRegister reg, const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2031 | int value = imm.value(); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2032 | if (value != 0) { |
| 2033 | if (value > 0) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2034 | addl(reg, imm); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2035 | } else { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2036 | subl(reg, Immediate(value)); |
| 2037 | } |
| 2038 | } |
| 2039 | } |
| 2040 | |
| 2041 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 2042 | void X86_64Assembler::setcc(Condition condition, CpuRegister dst) { |
| 2043 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2044 | // RSP, RBP, RDI, RSI need rex prefix (else the pattern encodes ah/bh/ch/dh). |
| 2045 | if (dst.NeedsRex() || dst.AsRegister() > 3) { |
| 2046 | EmitOptionalRex(true, false, false, false, dst.NeedsRex()); |
| 2047 | } |
| 2048 | EmitUint8(0x0F); |
| 2049 | EmitUint8(0x90 + condition); |
| 2050 | EmitUint8(0xC0 + dst.LowBits()); |
| 2051 | } |
| 2052 | |
Andreas Gampe | 71fb52f | 2014-12-29 17:43:08 -0800 | [diff] [blame] | 2053 | void X86_64Assembler::bswapl(CpuRegister dst) { |
| 2054 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2055 | EmitOptionalRex(false, false, false, false, dst.NeedsRex()); |
| 2056 | EmitUint8(0x0F); |
| 2057 | EmitUint8(0xC8 + dst.LowBits()); |
| 2058 | } |
| 2059 | |
| 2060 | void X86_64Assembler::bswapq(CpuRegister dst) { |
| 2061 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2062 | EmitOptionalRex(false, true, false, false, dst.NeedsRex()); |
| 2063 | EmitUint8(0x0F); |
| 2064 | EmitUint8(0xC8 + dst.LowBits()); |
| 2065 | } |
| 2066 | |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 2067 | |
Andreas Gampe | 21030dd | 2015-05-07 14:46:15 -0700 | [diff] [blame] | 2068 | void X86_64Assembler::repne_scasw() { |
| 2069 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2070 | EmitUint8(0x66); |
| 2071 | EmitUint8(0xF2); |
| 2072 | EmitUint8(0xAF); |
| 2073 | } |
| 2074 | |
| 2075 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2076 | void X86_64Assembler::LoadDoubleConstant(XmmRegister dst, double value) { |
| 2077 | // TODO: Need to have a code constants table. |
| 2078 | int64_t constant = bit_cast<int64_t, double>(value); |
| 2079 | pushq(Immediate(High32Bits(constant))); |
| 2080 | pushq(Immediate(Low32Bits(constant))); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2081 | movsd(dst, Address(CpuRegister(RSP), 0)); |
Ian Rogers | 1373595 | 2014-10-08 12:43:28 -0700 | [diff] [blame] | 2082 | addq(CpuRegister(RSP), Immediate(2 * sizeof(intptr_t))); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2083 | } |
| 2084 | |
| 2085 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2086 | void X86_64Assembler::Align(int alignment, int offset) { |
| 2087 | CHECK(IsPowerOfTwo(alignment)); |
| 2088 | // Emit nop instruction until the real position is aligned. |
| 2089 | while (((offset + buffer_.GetPosition()) & (alignment-1)) != 0) { |
| 2090 | nop(); |
| 2091 | } |
| 2092 | } |
| 2093 | |
| 2094 | |
| 2095 | void X86_64Assembler::Bind(Label* label) { |
| 2096 | int bound = buffer_.Size(); |
| 2097 | CHECK(!label->IsBound()); // Labels can only be bound once. |
| 2098 | while (label->IsLinked()) { |
| 2099 | int position = label->LinkPosition(); |
| 2100 | int next = buffer_.Load<int32_t>(position); |
| 2101 | buffer_.Store<int32_t>(position, bound - (position + 4)); |
| 2102 | label->position_ = next; |
| 2103 | } |
| 2104 | label->BindTo(bound); |
| 2105 | } |
| 2106 | |
| 2107 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2108 | void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2109 | CHECK_GE(reg_or_opcode, 0); |
| 2110 | CHECK_LT(reg_or_opcode, 8); |
| 2111 | const int length = operand.length_; |
| 2112 | CHECK_GT(length, 0); |
| 2113 | // Emit the ModRM byte updated with the given reg value. |
| 2114 | CHECK_EQ(operand.encoding_[0] & 0x38, 0); |
| 2115 | EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3)); |
| 2116 | // Emit the rest of the encoded operand. |
| 2117 | for (int i = 1; i < length; i++) { |
| 2118 | EmitUint8(operand.encoding_[i]); |
| 2119 | } |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 2120 | AssemblerFixup* fixup = operand.GetFixup(); |
| 2121 | if (fixup != nullptr) { |
| 2122 | EmitFixup(fixup); |
| 2123 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2124 | } |
| 2125 | |
| 2126 | |
| 2127 | void X86_64Assembler::EmitImmediate(const Immediate& imm) { |
Andreas Gampe | 5a4fa82 | 2014-03-31 16:50:12 -0700 | [diff] [blame] | 2128 | if (imm.is_int32()) { |
| 2129 | EmitInt32(static_cast<int32_t>(imm.value())); |
| 2130 | } else { |
| 2131 | EmitInt64(imm.value()); |
| 2132 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2133 | } |
| 2134 | |
| 2135 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2136 | void X86_64Assembler::EmitComplex(uint8_t reg_or_opcode, |
| 2137 | const Operand& operand, |
| 2138 | const Immediate& immediate) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2139 | CHECK_GE(reg_or_opcode, 0); |
| 2140 | CHECK_LT(reg_or_opcode, 8); |
| 2141 | if (immediate.is_int8()) { |
| 2142 | // Use sign-extended 8-bit immediate. |
| 2143 | EmitUint8(0x83); |
| 2144 | EmitOperand(reg_or_opcode, operand); |
| 2145 | EmitUint8(immediate.value() & 0xFF); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2146 | } else if (operand.IsRegister(CpuRegister(RAX))) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2147 | // Use short form if the destination is eax. |
| 2148 | EmitUint8(0x05 + (reg_or_opcode << 3)); |
| 2149 | EmitImmediate(immediate); |
| 2150 | } else { |
| 2151 | EmitUint8(0x81); |
| 2152 | EmitOperand(reg_or_opcode, operand); |
| 2153 | EmitImmediate(immediate); |
| 2154 | } |
| 2155 | } |
| 2156 | |
| 2157 | |
| 2158 | void X86_64Assembler::EmitLabel(Label* label, int instruction_size) { |
| 2159 | if (label->IsBound()) { |
| 2160 | int offset = label->Position() - buffer_.Size(); |
| 2161 | CHECK_LE(offset, 0); |
| 2162 | EmitInt32(offset - instruction_size); |
| 2163 | } else { |
| 2164 | EmitLabelLink(label); |
| 2165 | } |
| 2166 | } |
| 2167 | |
| 2168 | |
| 2169 | void X86_64Assembler::EmitLabelLink(Label* label) { |
| 2170 | CHECK(!label->IsBound()); |
| 2171 | int position = buffer_.Size(); |
| 2172 | EmitInt32(label->position_); |
| 2173 | label->LinkTo(position); |
| 2174 | } |
| 2175 | |
| 2176 | |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 2177 | void X86_64Assembler::EmitGenericShift(bool wide, |
| 2178 | int reg_or_opcode, |
| 2179 | CpuRegister reg, |
| 2180 | const Immediate& imm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2181 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2182 | CHECK(imm.is_int8()); |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 2183 | if (wide) { |
| 2184 | EmitRex64(reg); |
Andreas Gampe | 851df20 | 2014-11-12 14:05:46 -0800 | [diff] [blame] | 2185 | } else { |
| 2186 | EmitOptionalRex32(reg); |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 2187 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2188 | if (imm.value() == 1) { |
| 2189 | EmitUint8(0xD1); |
| 2190 | EmitOperand(reg_or_opcode, Operand(reg)); |
| 2191 | } else { |
| 2192 | EmitUint8(0xC1); |
| 2193 | EmitOperand(reg_or_opcode, Operand(reg)); |
| 2194 | EmitUint8(imm.value() & 0xFF); |
| 2195 | } |
| 2196 | } |
| 2197 | |
| 2198 | |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 2199 | void X86_64Assembler::EmitGenericShift(bool wide, |
| 2200 | int reg_or_opcode, |
Nicolas Geoffray | 1a43dd7 | 2014-07-17 15:15:34 +0100 | [diff] [blame] | 2201 | CpuRegister operand, |
| 2202 | CpuRegister shifter) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2203 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2204 | CHECK_EQ(shifter.AsRegister(), RCX); |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 2205 | if (wide) { |
| 2206 | EmitRex64(operand); |
| 2207 | } else { |
| 2208 | EmitOptionalRex32(operand); |
| 2209 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2210 | EmitUint8(0xD3); |
| 2211 | EmitOperand(reg_or_opcode, Operand(operand)); |
| 2212 | } |
| 2213 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2214 | void X86_64Assembler::EmitOptionalRex(bool force, bool w, bool r, bool x, bool b) { |
| 2215 | // REX.WRXB |
| 2216 | // W - 64-bit operand |
| 2217 | // R - MODRM.reg |
| 2218 | // X - SIB.index |
| 2219 | // B - MODRM.rm/SIB.base |
| 2220 | uint8_t rex = force ? 0x40 : 0; |
| 2221 | if (w) { |
| 2222 | rex |= 0x48; // REX.W000 |
| 2223 | } |
| 2224 | if (r) { |
| 2225 | rex |= 0x44; // REX.0R00 |
| 2226 | } |
| 2227 | if (x) { |
| 2228 | rex |= 0x42; // REX.00X0 |
| 2229 | } |
| 2230 | if (b) { |
| 2231 | rex |= 0x41; // REX.000B |
| 2232 | } |
| 2233 | if (rex != 0) { |
| 2234 | EmitUint8(rex); |
| 2235 | } |
| 2236 | } |
| 2237 | |
| 2238 | void X86_64Assembler::EmitOptionalRex32(CpuRegister reg) { |
Vladimir Kostyukov | fba52f1 | 2014-04-15 15:41:47 +0700 | [diff] [blame] | 2239 | EmitOptionalRex(false, false, false, false, reg.NeedsRex()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2240 | } |
| 2241 | |
| 2242 | void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) { |
| 2243 | EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex()); |
| 2244 | } |
| 2245 | |
| 2246 | void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, XmmRegister src) { |
| 2247 | EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex()); |
| 2248 | } |
| 2249 | |
| 2250 | void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, XmmRegister src) { |
| 2251 | EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex()); |
| 2252 | } |
| 2253 | |
| 2254 | void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, CpuRegister src) { |
| 2255 | EmitOptionalRex(false, false, dst.NeedsRex(), false, src.NeedsRex()); |
| 2256 | } |
| 2257 | |
| 2258 | void X86_64Assembler::EmitOptionalRex32(const Operand& operand) { |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2259 | uint8_t rex = operand.rex(); |
| 2260 | if (rex != 0) { |
| 2261 | EmitUint8(rex); |
| 2262 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2263 | } |
| 2264 | |
| 2265 | void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) { |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2266 | uint8_t rex = operand.rex(); |
| 2267 | if (dst.NeedsRex()) { |
| 2268 | rex |= 0x44; // REX.0R00 |
| 2269 | } |
| 2270 | if (rex != 0) { |
| 2271 | EmitUint8(rex); |
| 2272 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2273 | } |
| 2274 | |
| 2275 | void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) { |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2276 | uint8_t rex = operand.rex(); |
| 2277 | if (dst.NeedsRex()) { |
| 2278 | rex |= 0x44; // REX.0R00 |
| 2279 | } |
| 2280 | if (rex != 0) { |
| 2281 | EmitUint8(rex); |
| 2282 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2283 | } |
| 2284 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 2285 | void X86_64Assembler::EmitRex64() { |
| 2286 | EmitOptionalRex(false, true, false, false, false); |
| 2287 | } |
| 2288 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2289 | void X86_64Assembler::EmitRex64(CpuRegister reg) { |
Vladimir Kostyukov | fba52f1 | 2014-04-15 15:41:47 +0700 | [diff] [blame] | 2290 | EmitOptionalRex(false, true, false, false, reg.NeedsRex()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2291 | } |
Vladimir Kostyukov | fba52f1 | 2014-04-15 15:41:47 +0700 | [diff] [blame] | 2292 | |
Calin Juravle | d6fb6cf | 2014-11-11 19:07:44 +0000 | [diff] [blame] | 2293 | void X86_64Assembler::EmitRex64(const Operand& operand) { |
| 2294 | uint8_t rex = operand.rex(); |
| 2295 | rex |= 0x48; // REX.W000 |
| 2296 | EmitUint8(rex); |
| 2297 | } |
| 2298 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2299 | void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) { |
| 2300 | EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex()); |
| 2301 | } |
| 2302 | |
Nicolas Geoffray | 102cbed | 2014-10-15 18:31:05 +0100 | [diff] [blame] | 2303 | void X86_64Assembler::EmitRex64(XmmRegister dst, CpuRegister src) { |
| 2304 | EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex()); |
| 2305 | } |
| 2306 | |
Roland Levillain | 624279f | 2014-12-04 11:54:28 +0000 | [diff] [blame] | 2307 | void X86_64Assembler::EmitRex64(CpuRegister dst, XmmRegister src) { |
| 2308 | EmitOptionalRex(false, true, dst.NeedsRex(), false, src.NeedsRex()); |
| 2309 | } |
| 2310 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2311 | void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) { |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2312 | uint8_t rex = 0x48 | operand.rex(); // REX.W000 |
| 2313 | if (dst.NeedsRex()) { |
| 2314 | rex |= 0x44; // REX.0R00 |
| 2315 | } |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 2316 | EmitUint8(rex); |
| 2317 | } |
| 2318 | |
| 2319 | void X86_64Assembler::EmitRex64(XmmRegister dst, const Operand& operand) { |
| 2320 | uint8_t rex = 0x48 | operand.rex(); // REX.W000 |
| 2321 | if (dst.NeedsRex()) { |
| 2322 | rex |= 0x44; // REX.0R00 |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2323 | } |
Mark Mendell | 40741f3 | 2015-04-20 22:10:34 -0400 | [diff] [blame] | 2324 | EmitUint8(rex); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2325 | } |
| 2326 | |
| 2327 | void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) { |
Chao-ying Fu | d23840d | 2015-04-07 16:03:04 -0700 | [diff] [blame] | 2328 | // For src, SPL, BPL, SIL, DIL need the rex prefix. |
| 2329 | bool force = src.AsRegister() > 3; |
| 2330 | EmitOptionalRex(force, false, dst.NeedsRex(), false, src.NeedsRex()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2331 | } |
| 2332 | |
| 2333 | void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) { |
Chao-ying Fu | d23840d | 2015-04-07 16:03:04 -0700 | [diff] [blame] | 2334 | uint8_t rex = operand.rex(); |
| 2335 | // For dst, SPL, BPL, SIL, DIL need the rex prefix. |
| 2336 | bool force = dst.AsRegister() > 3; |
| 2337 | if (force) { |
| 2338 | rex |= 0x40; // REX.0000 |
| 2339 | } |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2340 | if (dst.NeedsRex()) { |
| 2341 | rex |= 0x44; // REX.0R00 |
| 2342 | } |
| 2343 | if (rex != 0) { |
| 2344 | EmitUint8(rex); |
| 2345 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2346 | } |
| 2347 | |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2348 | static dwarf::Reg DWARFReg(Register reg) { |
| 2349 | return dwarf::Reg::X86_64Core(static_cast<int>(reg)); |
| 2350 | } |
| 2351 | static dwarf::Reg DWARFReg(FloatRegister reg) { |
| 2352 | return dwarf::Reg::X86_64Fp(static_cast<int>(reg)); |
| 2353 | } |
| 2354 | |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2355 | constexpr size_t kFramePointerSize = 8; |
| 2356 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2357 | void X86_64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, |
Ian Rogers | 790a6b7 | 2014-04-01 10:36:00 -0700 | [diff] [blame] | 2358 | const std::vector<ManagedRegister>& spill_regs, |
| 2359 | const ManagedRegisterEntrySpills& entry_spills) { |
David Srbecky | 8c57831 | 2015-04-07 19:46:22 +0100 | [diff] [blame] | 2360 | DCHECK_EQ(buffer_.Size(), 0U); // Nothing emitted yet. |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2361 | cfi_.SetCurrentCFAOffset(8); // Return address on stack. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2362 | CHECK_ALIGNED(frame_size, kStackAlignment); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2363 | int gpr_count = 0; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2364 | for (int i = spill_regs.size() - 1; i >= 0; --i) { |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2365 | x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); |
| 2366 | if (spill.IsCpuRegister()) { |
| 2367 | pushq(spill.AsCpuRegister()); |
| 2368 | gpr_count++; |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2369 | cfi_.AdjustCFAOffset(kFramePointerSize); |
| 2370 | cfi_.RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2371 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2372 | } |
David Srbecky | 8c57831 | 2015-04-07 19:46:22 +0100 | [diff] [blame] | 2373 | // return address then method on stack. |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2374 | int64_t rest_of_frame = static_cast<int64_t>(frame_size) |
| 2375 | - (gpr_count * kFramePointerSize) |
| 2376 | - kFramePointerSize /*return address*/; |
| 2377 | subq(CpuRegister(RSP), Immediate(rest_of_frame)); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2378 | cfi_.AdjustCFAOffset(rest_of_frame); |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 2379 | |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2380 | // spill xmms |
| 2381 | int64_t offset = rest_of_frame; |
| 2382 | for (int i = spill_regs.size() - 1; i >= 0; --i) { |
| 2383 | x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); |
| 2384 | if (spill.IsXmmRegister()) { |
| 2385 | offset -= sizeof(double); |
| 2386 | movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister()); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2387 | cfi_.RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2388 | } |
| 2389 | } |
Andreas Gampe | cf4035a | 2014-05-28 22:43:01 -0700 | [diff] [blame] | 2390 | |
| 2391 | DCHECK_EQ(4U, sizeof(StackReference<mirror::ArtMethod>)); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2392 | |
Andreas Gampe | cf4035a | 2014-05-28 22:43:01 -0700 | [diff] [blame] | 2393 | movl(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2394 | |
| 2395 | for (size_t i = 0; i < entry_spills.size(); ++i) { |
| 2396 | ManagedRegisterSpill spill = entry_spills.at(i); |
| 2397 | if (spill.AsX86_64().IsCpuRegister()) { |
| 2398 | if (spill.getSize() == 8) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2399 | movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), |
| 2400 | spill.AsX86_64().AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2401 | } else { |
| 2402 | CHECK_EQ(spill.getSize(), 4); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2403 | movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2404 | } |
| 2405 | } else { |
| 2406 | if (spill.getSize() == 8) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2407 | movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2408 | } else { |
| 2409 | CHECK_EQ(spill.getSize(), 4); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2410 | movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2411 | } |
| 2412 | } |
| 2413 | } |
| 2414 | } |
| 2415 | |
| 2416 | void X86_64Assembler::RemoveFrame(size_t frame_size, |
| 2417 | const std::vector<ManagedRegister>& spill_regs) { |
| 2418 | CHECK_ALIGNED(frame_size, kStackAlignment); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2419 | cfi_.RememberState(); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2420 | int gpr_count = 0; |
| 2421 | // unspill xmms |
| 2422 | int64_t offset = static_cast<int64_t>(frame_size) - (spill_regs.size() * kFramePointerSize) - 2 * kFramePointerSize; |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2423 | for (size_t i = 0; i < spill_regs.size(); ++i) { |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2424 | x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); |
| 2425 | if (spill.IsXmmRegister()) { |
| 2426 | offset += sizeof(double); |
| 2427 | movsd(spill.AsXmmRegister(), Address(CpuRegister(RSP), offset)); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2428 | cfi_.Restore(DWARFReg(spill.AsXmmRegister().AsFloatRegister())); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2429 | } else { |
| 2430 | gpr_count++; |
| 2431 | } |
| 2432 | } |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2433 | int adjust = static_cast<int>(frame_size) - (gpr_count * kFramePointerSize) - kFramePointerSize; |
| 2434 | addq(CpuRegister(RSP), Immediate(adjust)); |
| 2435 | cfi_.AdjustCFAOffset(-adjust); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2436 | for (size_t i = 0; i < spill_regs.size(); ++i) { |
| 2437 | x86_64::X86_64ManagedRegister spill = spill_regs.at(i).AsX86_64(); |
| 2438 | if (spill.IsCpuRegister()) { |
| 2439 | popq(spill.AsCpuRegister()); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2440 | cfi_.AdjustCFAOffset(-static_cast<int>(kFramePointerSize)); |
| 2441 | cfi_.Restore(DWARFReg(spill.AsCpuRegister().AsRegister())); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 2442 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2443 | } |
| 2444 | ret(); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2445 | // The CFI should be restored for any code that follows the exit block. |
| 2446 | cfi_.RestoreState(); |
| 2447 | cfi_.DefCFAOffset(frame_size); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2448 | } |
| 2449 | |
| 2450 | void X86_64Assembler::IncreaseFrameSize(size_t adjust) { |
| 2451 | CHECK_ALIGNED(adjust, kStackAlignment); |
avignate | 5408b6b | 2014-06-04 17:59:44 +0700 | [diff] [blame] | 2452 | addq(CpuRegister(RSP), Immediate(-static_cast<int64_t>(adjust))); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2453 | cfi_.AdjustCFAOffset(adjust); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2454 | } |
| 2455 | |
| 2456 | void X86_64Assembler::DecreaseFrameSize(size_t adjust) { |
| 2457 | CHECK_ALIGNED(adjust, kStackAlignment); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2458 | addq(CpuRegister(RSP), Immediate(adjust)); |
David Srbecky | dd97393 | 2015-04-07 20:29:48 +0100 | [diff] [blame] | 2459 | cfi_.AdjustCFAOffset(-adjust); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2460 | } |
| 2461 | |
| 2462 | void X86_64Assembler::Store(FrameOffset offs, ManagedRegister msrc, size_t size) { |
| 2463 | X86_64ManagedRegister src = msrc.AsX86_64(); |
| 2464 | if (src.IsNoRegister()) { |
| 2465 | CHECK_EQ(0u, size); |
| 2466 | } else if (src.IsCpuRegister()) { |
| 2467 | if (size == 4) { |
| 2468 | CHECK_EQ(4u, size); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2469 | movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2470 | } else { |
| 2471 | CHECK_EQ(8u, size); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2472 | movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2473 | } |
| 2474 | } else if (src.IsRegisterPair()) { |
| 2475 | CHECK_EQ(0u, size); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2476 | movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow()); |
| 2477 | movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)), |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2478 | src.AsRegisterPairHigh()); |
| 2479 | } else if (src.IsX87Register()) { |
| 2480 | if (size == 4) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2481 | fstps(Address(CpuRegister(RSP), offs)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2482 | } else { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2483 | fstpl(Address(CpuRegister(RSP), offs)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2484 | } |
| 2485 | } else { |
| 2486 | CHECK(src.IsXmmRegister()); |
| 2487 | if (size == 4) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2488 | movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2489 | } else { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2490 | movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2491 | } |
| 2492 | } |
| 2493 | } |
| 2494 | |
| 2495 | void X86_64Assembler::StoreRef(FrameOffset dest, ManagedRegister msrc) { |
| 2496 | X86_64ManagedRegister src = msrc.AsX86_64(); |
| 2497 | CHECK(src.IsCpuRegister()); |
Andreas Gampe | cf4035a | 2014-05-28 22:43:01 -0700 | [diff] [blame] | 2498 | movl(Address(CpuRegister(RSP), dest), src.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2499 | } |
| 2500 | |
| 2501 | void X86_64Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) { |
| 2502 | X86_64ManagedRegister src = msrc.AsX86_64(); |
| 2503 | CHECK(src.IsCpuRegister()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2504 | movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2505 | } |
| 2506 | |
| 2507 | void X86_64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2508 | ManagedRegister) { |
| 2509 | movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq? |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2510 | } |
| 2511 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2512 | void X86_64Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, |
| 2513 | ManagedRegister) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2514 | gs()->movl(Address::Absolute(dest, true), Immediate(imm)); // TODO(64) movq? |
| 2515 | } |
| 2516 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2517 | void X86_64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, |
| 2518 | FrameOffset fr_offs, |
| 2519 | ManagedRegister mscratch) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2520 | X86_64ManagedRegister scratch = mscratch.AsX86_64(); |
| 2521 | CHECK(scratch.IsCpuRegister()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2522 | leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2523 | gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister()); |
| 2524 | } |
| 2525 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2526 | void X86_64Assembler::StoreStackPointerToThread64(ThreadOffset<8> thr_offs) { |
| 2527 | gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2528 | } |
| 2529 | |
| 2530 | void X86_64Assembler::StoreSpanning(FrameOffset /*dst*/, ManagedRegister /*src*/, |
| 2531 | FrameOffset /*in_off*/, ManagedRegister /*scratch*/) { |
| 2532 | UNIMPLEMENTED(FATAL); // this case only currently exists for ARM |
| 2533 | } |
| 2534 | |
| 2535 | void X86_64Assembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) { |
| 2536 | X86_64ManagedRegister dest = mdest.AsX86_64(); |
| 2537 | if (dest.IsNoRegister()) { |
| 2538 | CHECK_EQ(0u, size); |
| 2539 | } else if (dest.IsCpuRegister()) { |
| 2540 | if (size == 4) { |
| 2541 | CHECK_EQ(4u, size); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2542 | movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2543 | } else { |
| 2544 | CHECK_EQ(8u, size); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2545 | movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2546 | } |
| 2547 | } else if (dest.IsRegisterPair()) { |
| 2548 | CHECK_EQ(0u, size); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2549 | movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src)); |
| 2550 | movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4))); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2551 | } else if (dest.IsX87Register()) { |
| 2552 | if (size == 4) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2553 | flds(Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2554 | } else { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2555 | fldl(Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2556 | } |
| 2557 | } else { |
| 2558 | CHECK(dest.IsXmmRegister()); |
| 2559 | if (size == 4) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2560 | movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2561 | } else { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2562 | movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2563 | } |
| 2564 | } |
| 2565 | } |
| 2566 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2567 | void X86_64Assembler::LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2568 | X86_64ManagedRegister dest = mdest.AsX86_64(); |
| 2569 | if (dest.IsNoRegister()) { |
| 2570 | CHECK_EQ(0u, size); |
| 2571 | } else if (dest.IsCpuRegister()) { |
| 2572 | CHECK_EQ(4u, size); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2573 | gs()->movl(dest.AsCpuRegister(), Address::Absolute(src, true)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2574 | } else if (dest.IsRegisterPair()) { |
| 2575 | CHECK_EQ(8u, size); |
| 2576 | gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2577 | } else if (dest.IsX87Register()) { |
| 2578 | if (size == 4) { |
| 2579 | gs()->flds(Address::Absolute(src, true)); |
| 2580 | } else { |
| 2581 | gs()->fldl(Address::Absolute(src, true)); |
| 2582 | } |
| 2583 | } else { |
| 2584 | CHECK(dest.IsXmmRegister()); |
| 2585 | if (size == 4) { |
| 2586 | gs()->movss(dest.AsXmmRegister(), Address::Absolute(src, true)); |
| 2587 | } else { |
| 2588 | gs()->movsd(dest.AsXmmRegister(), Address::Absolute(src, true)); |
| 2589 | } |
| 2590 | } |
| 2591 | } |
| 2592 | |
| 2593 | void X86_64Assembler::LoadRef(ManagedRegister mdest, FrameOffset src) { |
| 2594 | X86_64ManagedRegister dest = mdest.AsX86_64(); |
| 2595 | CHECK(dest.IsCpuRegister()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2596 | movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2597 | } |
| 2598 | |
| 2599 | void X86_64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base, |
| 2600 | MemberOffset offs) { |
| 2601 | X86_64ManagedRegister dest = mdest.AsX86_64(); |
| 2602 | CHECK(dest.IsCpuRegister() && dest.IsCpuRegister()); |
Hiroshi Yamauchi | f889267 | 2014-09-30 10:56:14 -0700 | [diff] [blame] | 2603 | movl(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs)); |
Hiroshi Yamauchi | b88f0b1 | 2014-09-26 14:55:38 -0700 | [diff] [blame] | 2604 | if (kPoisonHeapReferences) { |
| 2605 | negl(dest.AsCpuRegister()); |
| 2606 | } |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2607 | } |
| 2608 | |
| 2609 | void X86_64Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, |
| 2610 | Offset offs) { |
| 2611 | X86_64ManagedRegister dest = mdest.AsX86_64(); |
| 2612 | CHECK(dest.IsCpuRegister() && dest.IsCpuRegister()); |
| 2613 | movq(dest.AsCpuRegister(), Address(base.AsX86_64().AsCpuRegister(), offs)); |
| 2614 | } |
| 2615 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2616 | void X86_64Assembler::LoadRawPtrFromThread64(ManagedRegister mdest, ThreadOffset<8> offs) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2617 | X86_64ManagedRegister dest = mdest.AsX86_64(); |
| 2618 | CHECK(dest.IsCpuRegister()); |
| 2619 | gs()->movq(dest.AsCpuRegister(), Address::Absolute(offs, true)); |
| 2620 | } |
| 2621 | |
| 2622 | void X86_64Assembler::SignExtend(ManagedRegister mreg, size_t size) { |
| 2623 | X86_64ManagedRegister reg = mreg.AsX86_64(); |
| 2624 | CHECK(size == 1 || size == 2) << size; |
| 2625 | CHECK(reg.IsCpuRegister()) << reg; |
| 2626 | if (size == 1) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2627 | movsxb(reg.AsCpuRegister(), reg.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2628 | } else { |
| 2629 | movsxw(reg.AsCpuRegister(), reg.AsCpuRegister()); |
| 2630 | } |
| 2631 | } |
| 2632 | |
| 2633 | void X86_64Assembler::ZeroExtend(ManagedRegister mreg, size_t size) { |
| 2634 | X86_64ManagedRegister reg = mreg.AsX86_64(); |
| 2635 | CHECK(size == 1 || size == 2) << size; |
| 2636 | CHECK(reg.IsCpuRegister()) << reg; |
| 2637 | if (size == 1) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2638 | movzxb(reg.AsCpuRegister(), reg.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2639 | } else { |
| 2640 | movzxw(reg.AsCpuRegister(), reg.AsCpuRegister()); |
| 2641 | } |
| 2642 | } |
| 2643 | |
| 2644 | void X86_64Assembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) { |
| 2645 | X86_64ManagedRegister dest = mdest.AsX86_64(); |
| 2646 | X86_64ManagedRegister src = msrc.AsX86_64(); |
| 2647 | if (!dest.Equals(src)) { |
| 2648 | if (dest.IsCpuRegister() && src.IsCpuRegister()) { |
| 2649 | movq(dest.AsCpuRegister(), src.AsCpuRegister()); |
| 2650 | } else if (src.IsX87Register() && dest.IsXmmRegister()) { |
| 2651 | // Pass via stack and pop X87 register |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2652 | subl(CpuRegister(RSP), Immediate(16)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2653 | if (size == 4) { |
| 2654 | CHECK_EQ(src.AsX87Register(), ST0); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2655 | fstps(Address(CpuRegister(RSP), 0)); |
| 2656 | movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2657 | } else { |
| 2658 | CHECK_EQ(src.AsX87Register(), ST0); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2659 | fstpl(Address(CpuRegister(RSP), 0)); |
| 2660 | movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2661 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2662 | addq(CpuRegister(RSP), Immediate(16)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2663 | } else { |
| 2664 | // TODO: x87, SSE |
| 2665 | UNIMPLEMENTED(FATAL) << ": Move " << dest << ", " << src; |
| 2666 | } |
| 2667 | } |
| 2668 | } |
| 2669 | |
| 2670 | void X86_64Assembler::CopyRef(FrameOffset dest, FrameOffset src, |
| 2671 | ManagedRegister mscratch) { |
| 2672 | X86_64ManagedRegister scratch = mscratch.AsX86_64(); |
| 2673 | CHECK(scratch.IsCpuRegister()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2674 | movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src)); |
| 2675 | movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2676 | } |
| 2677 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2678 | void X86_64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs, |
| 2679 | ThreadOffset<8> thr_offs, |
| 2680 | ManagedRegister mscratch) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2681 | X86_64ManagedRegister scratch = mscratch.AsX86_64(); |
| 2682 | CHECK(scratch.IsCpuRegister()); |
| 2683 | gs()->movq(scratch.AsCpuRegister(), Address::Absolute(thr_offs, true)); |
| 2684 | Store(fr_offs, scratch, 8); |
| 2685 | } |
| 2686 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2687 | void X86_64Assembler::CopyRawPtrToThread64(ThreadOffset<8> thr_offs, |
| 2688 | FrameOffset fr_offs, |
| 2689 | ManagedRegister mscratch) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2690 | X86_64ManagedRegister scratch = mscratch.AsX86_64(); |
| 2691 | CHECK(scratch.IsCpuRegister()); |
| 2692 | Load(scratch, fr_offs, 8); |
| 2693 | gs()->movq(Address::Absolute(thr_offs, true), scratch.AsCpuRegister()); |
| 2694 | } |
| 2695 | |
| 2696 | void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src, |
| 2697 | ManagedRegister mscratch, |
| 2698 | size_t size) { |
| 2699 | X86_64ManagedRegister scratch = mscratch.AsX86_64(); |
| 2700 | if (scratch.IsCpuRegister() && size == 8) { |
| 2701 | Load(scratch, src, 4); |
| 2702 | Store(dest, scratch, 4); |
| 2703 | Load(scratch, FrameOffset(src.Int32Value() + 4), 4); |
| 2704 | Store(FrameOffset(dest.Int32Value() + 4), scratch, 4); |
| 2705 | } else { |
| 2706 | Load(scratch, src, size); |
| 2707 | Store(dest, scratch, size); |
| 2708 | } |
| 2709 | } |
| 2710 | |
| 2711 | void X86_64Assembler::Copy(FrameOffset /*dst*/, ManagedRegister /*src_base*/, Offset /*src_offset*/, |
| 2712 | ManagedRegister /*scratch*/, size_t /*size*/) { |
| 2713 | UNIMPLEMENTED(FATAL); |
| 2714 | } |
| 2715 | |
| 2716 | void X86_64Assembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, |
| 2717 | ManagedRegister scratch, size_t size) { |
| 2718 | CHECK(scratch.IsNoRegister()); |
| 2719 | CHECK_EQ(size, 4u); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2720 | pushq(Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2721 | popq(Address(dest_base.AsX86_64().AsCpuRegister(), dest_offset)); |
| 2722 | } |
| 2723 | |
| 2724 | void X86_64Assembler::Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, |
| 2725 | ManagedRegister mscratch, size_t size) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2726 | CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2727 | CHECK_EQ(size, 4u); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2728 | movq(scratch, Address(CpuRegister(RSP), src_base)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2729 | movq(scratch, Address(scratch, src_offset)); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2730 | movq(Address(CpuRegister(RSP), dest), scratch); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2731 | } |
| 2732 | |
| 2733 | void X86_64Assembler::Copy(ManagedRegister dest, Offset dest_offset, |
| 2734 | ManagedRegister src, Offset src_offset, |
| 2735 | ManagedRegister scratch, size_t size) { |
| 2736 | CHECK_EQ(size, 4u); |
| 2737 | CHECK(scratch.IsNoRegister()); |
| 2738 | pushq(Address(src.AsX86_64().AsCpuRegister(), src_offset)); |
| 2739 | popq(Address(dest.AsX86_64().AsCpuRegister(), dest_offset)); |
| 2740 | } |
| 2741 | |
| 2742 | void X86_64Assembler::Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset, |
| 2743 | ManagedRegister mscratch, size_t size) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2744 | CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2745 | CHECK_EQ(size, 4u); |
| 2746 | CHECK_EQ(dest.Int32Value(), src.Int32Value()); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2747 | movq(scratch, Address(CpuRegister(RSP), src)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2748 | pushq(Address(scratch, src_offset)); |
| 2749 | popq(Address(scratch, dest_offset)); |
| 2750 | } |
| 2751 | |
| 2752 | void X86_64Assembler::MemoryBarrier(ManagedRegister) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2753 | mfence(); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2754 | } |
| 2755 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2756 | void X86_64Assembler::CreateHandleScopeEntry(ManagedRegister mout_reg, |
| 2757 | FrameOffset handle_scope_offset, |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2758 | ManagedRegister min_reg, bool null_allowed) { |
| 2759 | X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); |
| 2760 | X86_64ManagedRegister in_reg = min_reg.AsX86_64(); |
| 2761 | if (in_reg.IsNoRegister()) { // TODO(64): && null_allowed |
Mathieu Chartier | 2cebb24 | 2015-04-21 16:50:40 -0700 | [diff] [blame] | 2762 | // Use out_reg as indicator of null. |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2763 | in_reg = out_reg; |
| 2764 | // TODO: movzwl |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2765 | movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2766 | } |
| 2767 | CHECK(in_reg.IsCpuRegister()); |
| 2768 | CHECK(out_reg.IsCpuRegister()); |
| 2769 | VerifyObject(in_reg, null_allowed); |
| 2770 | if (null_allowed) { |
| 2771 | Label null_arg; |
| 2772 | if (!out_reg.Equals(in_reg)) { |
| 2773 | xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); |
| 2774 | } |
| 2775 | testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); |
| 2776 | j(kZero, &null_arg); |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2777 | leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2778 | Bind(&null_arg); |
| 2779 | } else { |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2780 | leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2781 | } |
| 2782 | } |
| 2783 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2784 | void X86_64Assembler::CreateHandleScopeEntry(FrameOffset out_off, |
| 2785 | FrameOffset handle_scope_offset, |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2786 | ManagedRegister mscratch, |
| 2787 | bool null_allowed) { |
| 2788 | X86_64ManagedRegister scratch = mscratch.AsX86_64(); |
| 2789 | CHECK(scratch.IsCpuRegister()); |
| 2790 | if (null_allowed) { |
| 2791 | Label null_arg; |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2792 | movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2793 | testl(scratch.AsCpuRegister(), scratch.AsCpuRegister()); |
| 2794 | j(kZero, &null_arg); |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2795 | leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2796 | Bind(&null_arg); |
| 2797 | } else { |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2798 | leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2799 | } |
| 2800 | Store(out_off, scratch, 8); |
| 2801 | } |
| 2802 | |
Mathieu Chartier | eb8167a | 2014-05-07 15:43:14 -0700 | [diff] [blame] | 2803 | // Given a handle scope entry, load the associated reference. |
| 2804 | void X86_64Assembler::LoadReferenceFromHandleScope(ManagedRegister mout_reg, |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2805 | ManagedRegister min_reg) { |
| 2806 | X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); |
| 2807 | X86_64ManagedRegister in_reg = min_reg.AsX86_64(); |
| 2808 | CHECK(out_reg.IsCpuRegister()); |
| 2809 | CHECK(in_reg.IsCpuRegister()); |
| 2810 | Label null_arg; |
| 2811 | if (!out_reg.Equals(in_reg)) { |
| 2812 | xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); |
| 2813 | } |
| 2814 | testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); |
| 2815 | j(kZero, &null_arg); |
| 2816 | movq(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0)); |
| 2817 | Bind(&null_arg); |
| 2818 | } |
| 2819 | |
| 2820 | void X86_64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) { |
| 2821 | // TODO: not validating references |
| 2822 | } |
| 2823 | |
| 2824 | void X86_64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) { |
| 2825 | // TODO: not validating references |
| 2826 | } |
| 2827 | |
| 2828 | void X86_64Assembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister) { |
| 2829 | X86_64ManagedRegister base = mbase.AsX86_64(); |
| 2830 | CHECK(base.IsCpuRegister()); |
| 2831 | call(Address(base.AsCpuRegister(), offset.Int32Value())); |
| 2832 | // TODO: place reference map on call |
| 2833 | } |
| 2834 | |
| 2835 | void X86_64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2836 | CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister(); |
Andreas Gampe | cf4035a | 2014-05-28 22:43:01 -0700 | [diff] [blame] | 2837 | movl(scratch, Address(CpuRegister(RSP), base)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2838 | call(Address(scratch, offset)); |
| 2839 | } |
| 2840 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2841 | void X86_64Assembler::CallFromThread64(ThreadOffset<8> offset, ManagedRegister /*mscratch*/) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2842 | gs()->call(Address::Absolute(offset, true)); |
| 2843 | } |
| 2844 | |
| 2845 | void X86_64Assembler::GetCurrentThread(ManagedRegister tr) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2846 | gs()->movq(tr.AsX86_64().AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2847 | } |
| 2848 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2849 | void X86_64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister mscratch) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2850 | X86_64ManagedRegister scratch = mscratch.AsX86_64(); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2851 | gs()->movq(scratch.AsCpuRegister(), Address::Absolute(Thread::SelfOffset<8>(), true)); |
| 2852 | movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister()); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2853 | } |
| 2854 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2855 | // Slowpath entered when Thread::Current()->_exception is non-null |
| 2856 | class X86_64ExceptionSlowPath FINAL : public SlowPath { |
| 2857 | public: |
| 2858 | explicit X86_64ExceptionSlowPath(size_t stack_adjust) : stack_adjust_(stack_adjust) {} |
| 2859 | virtual void Emit(Assembler *sp_asm) OVERRIDE; |
| 2860 | private: |
| 2861 | const size_t stack_adjust_; |
| 2862 | }; |
| 2863 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2864 | void X86_64Assembler::ExceptionPoll(ManagedRegister /*scratch*/, size_t stack_adjust) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2865 | X86_64ExceptionSlowPath* slow = new X86_64ExceptionSlowPath(stack_adjust); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2866 | buffer_.EnqueueSlowPath(slow); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2867 | gs()->cmpl(Address::Absolute(Thread::ExceptionOffset<8>(), true), Immediate(0)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2868 | j(kNotEqual, slow->Entry()); |
| 2869 | } |
| 2870 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2871 | void X86_64ExceptionSlowPath::Emit(Assembler *sasm) { |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2872 | X86_64Assembler* sp_asm = down_cast<X86_64Assembler*>(sasm); |
| 2873 | #define __ sp_asm-> |
| 2874 | __ Bind(&entry_); |
| 2875 | // Note: the return value is dead |
| 2876 | if (stack_adjust_ != 0) { // Fix up the frame. |
| 2877 | __ DecreaseFrameSize(stack_adjust_); |
| 2878 | } |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 2879 | // Pass exception as argument in RDI |
| 2880 | __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true)); |
| 2881 | __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), true)); |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2882 | // this call should never return |
| 2883 | __ int3(); |
| 2884 | #undef __ |
| 2885 | } |
| 2886 | |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 2887 | void X86_64Assembler::AddConstantArea() { |
| 2888 | const std::vector<int32_t>& area = constant_area_.GetBuffer(); |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 2889 | for (size_t i = 0, e = area.size(); i < e; i++) { |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 2890 | AssemblerBuffer::EnsureCapacity ensured(&buffer_); |
| 2891 | EmitInt32(area[i]); |
| 2892 | } |
| 2893 | } |
| 2894 | |
| 2895 | int ConstantArea::AddInt32(int32_t v) { |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 2896 | for (size_t i = 0, e = buffer_.size(); i < e; i++) { |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 2897 | if (v == buffer_[i]) { |
| 2898 | return i * elem_size_; |
| 2899 | } |
| 2900 | } |
| 2901 | |
| 2902 | // Didn't match anything. |
| 2903 | int result = buffer_.size() * elem_size_; |
| 2904 | buffer_.push_back(v); |
| 2905 | return result; |
| 2906 | } |
| 2907 | |
| 2908 | int ConstantArea::AddInt64(int64_t v) { |
| 2909 | int32_t v_low = v; |
| 2910 | int32_t v_high = v >> 32; |
| 2911 | if (buffer_.size() > 1) { |
| 2912 | // Ensure we don't pass the end of the buffer. |
Mark Mendell | 39dcf55 | 2015-04-09 20:42:42 -0400 | [diff] [blame] | 2913 | for (size_t i = 0, e = buffer_.size() - 1; i < e; i++) { |
| 2914 | if (v_low == buffer_[i] && v_high == buffer_[i + 1]) { |
Mark Mendell | f55c3e0 | 2015-03-26 21:07:46 -0400 | [diff] [blame] | 2915 | return i * elem_size_; |
| 2916 | } |
| 2917 | } |
| 2918 | } |
| 2919 | |
| 2920 | // Didn't match anything. |
| 2921 | int result = buffer_.size() * elem_size_; |
| 2922 | buffer_.push_back(v_low); |
| 2923 | buffer_.push_back(v_high); |
| 2924 | return result; |
| 2925 | } |
| 2926 | |
| 2927 | int ConstantArea::AddDouble(double v) { |
| 2928 | // Treat the value as a 64-bit integer value. |
| 2929 | return AddInt64(bit_cast<int64_t, double>(v)); |
| 2930 | } |
| 2931 | |
| 2932 | int ConstantArea::AddFloat(float v) { |
| 2933 | // Treat the value as a 32-bit integer value. |
| 2934 | return AddInt32(bit_cast<int32_t, float>(v)); |
| 2935 | } |
| 2936 | |
Dmitry Petrochenko | fca8220 | 2014-03-21 11:21:37 +0700 | [diff] [blame] | 2937 | } // namespace x86_64 |
| 2938 | } // namespace art |