Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_mips.h" |
Ian Rogers | 107c31e | 2014-01-23 20:55:29 -0800 | [diff] [blame] | 18 | |
| 19 | #include <inttypes.h> |
| 20 | |
| 21 | #include <string> |
| 22 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 23 | #include "dex/compiler_internals.h" |
| 24 | #include "dex/quick/mir_to_lir-inl.h" |
| 25 | #include "mips_lir.h" |
| 26 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | namespace art { |
| 28 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 29 | static constexpr RegStorage core_regs_arr[] = |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 30 | {rs_rZERO, rs_rAT, rs_rV0, rs_rV1, rs_rA0, rs_rA1, rs_rA2, rs_rA3, rs_rT0, rs_rT1, rs_rT2, |
| 31 | rs_rT3, rs_rT4, rs_rT5, rs_rT6, rs_rT7, rs_rS0, rs_rS1, rs_rS2, rs_rS3, rs_rS4, rs_rS5, |
| 32 | rs_rS6, rs_rS7, rs_rT8, rs_rT9, rs_rK0, rs_rK1, rs_rGP, rs_rSP, rs_rFP, rs_rRA}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 33 | static constexpr RegStorage sp_regs_arr[] = |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 34 | {rs_rF0, rs_rF1, rs_rF2, rs_rF3, rs_rF4, rs_rF5, rs_rF6, rs_rF7, rs_rF8, rs_rF9, rs_rF10, |
| 35 | rs_rF11, rs_rF12, rs_rF13, rs_rF14, rs_rF15}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 36 | static constexpr RegStorage dp_regs_arr[] = |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 37 | {rs_rD0, rs_rD1, rs_rD2, rs_rD3, rs_rD4, rs_rD5, rs_rD6, rs_rD7}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 38 | static constexpr RegStorage reserved_regs_arr[] = |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 39 | {rs_rZERO, rs_rAT, rs_rS0, rs_rS1, rs_rK0, rs_rK1, rs_rGP, rs_rSP, rs_rRA}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 40 | static constexpr RegStorage core_temps_arr[] = |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 41 | {rs_rV0, rs_rV1, rs_rA0, rs_rA1, rs_rA2, rs_rA3, rs_rT0, rs_rT1, rs_rT2, rs_rT3, rs_rT4, |
| 42 | rs_rT5, rs_rT6, rs_rT7, rs_rT8}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 43 | static constexpr RegStorage sp_temps_arr[] = |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 44 | {rs_rF0, rs_rF1, rs_rF2, rs_rF3, rs_rF4, rs_rF5, rs_rF6, rs_rF7, rs_rF8, rs_rF9, rs_rF10, |
| 45 | rs_rF11, rs_rF12, rs_rF13, rs_rF14, rs_rF15}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 46 | static constexpr RegStorage dp_temps_arr[] = |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 47 | {rs_rD0, rs_rD1, rs_rD2, rs_rD3, rs_rD4, rs_rD5, rs_rD6, rs_rD7}; |
| 48 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 49 | static constexpr ArrayRef<const RegStorage> empty_pool; |
| 50 | static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr); |
| 51 | static constexpr ArrayRef<const RegStorage> sp_regs(sp_regs_arr); |
| 52 | static constexpr ArrayRef<const RegStorage> dp_regs(dp_regs_arr); |
| 53 | static constexpr ArrayRef<const RegStorage> reserved_regs(reserved_regs_arr); |
| 54 | static constexpr ArrayRef<const RegStorage> core_temps(core_temps_arr); |
| 55 | static constexpr ArrayRef<const RegStorage> sp_temps(sp_temps_arr); |
| 56 | static constexpr ArrayRef<const RegStorage> dp_temps(dp_temps_arr); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 57 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 58 | RegLocation MipsMir2Lir::LocCReturn() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 59 | return mips_loc_c_return; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 60 | } |
| 61 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 62 | RegLocation MipsMir2Lir::LocCReturnRef() { |
| 63 | return mips_loc_c_return; |
| 64 | } |
| 65 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 66 | RegLocation MipsMir2Lir::LocCReturnWide() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 67 | return mips_loc_c_return_wide; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 68 | } |
| 69 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 70 | RegLocation MipsMir2Lir::LocCReturnFloat() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 71 | return mips_loc_c_return_float; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 72 | } |
| 73 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 74 | RegLocation MipsMir2Lir::LocCReturnDouble() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 75 | return mips_loc_c_return_double; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 76 | } |
| 77 | |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 78 | // Convert k64BitSolo into k64BitPair |
| 79 | RegStorage MipsMir2Lir::Solo64ToPair64(RegStorage reg) { |
| 80 | DCHECK(reg.IsDouble()); |
| 81 | int reg_num = (reg.GetRegNum() & ~1) | RegStorage::kFloatingPoint; |
| 82 | return RegStorage(RegStorage::k64BitPair, reg_num, reg_num + 1); |
| 83 | } |
| 84 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 85 | // Return a target-dependent special register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 86 | RegStorage MipsMir2Lir::TargetReg(SpecialTargetRegister reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 87 | RegStorage res_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 88 | switch (reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 89 | case kSelf: res_reg = rs_rMIPS_SELF; break; |
| 90 | case kSuspend: res_reg = rs_rMIPS_SUSPEND; break; |
| 91 | case kLr: res_reg = rs_rMIPS_LR; break; |
| 92 | case kPc: res_reg = rs_rMIPS_PC; break; |
| 93 | case kSp: res_reg = rs_rMIPS_SP; break; |
| 94 | case kArg0: res_reg = rs_rMIPS_ARG0; break; |
| 95 | case kArg1: res_reg = rs_rMIPS_ARG1; break; |
| 96 | case kArg2: res_reg = rs_rMIPS_ARG2; break; |
| 97 | case kArg3: res_reg = rs_rMIPS_ARG3; break; |
| 98 | case kFArg0: res_reg = rs_rMIPS_FARG0; break; |
| 99 | case kFArg1: res_reg = rs_rMIPS_FARG1; break; |
| 100 | case kFArg2: res_reg = rs_rMIPS_FARG2; break; |
| 101 | case kFArg3: res_reg = rs_rMIPS_FARG3; break; |
| 102 | case kRet0: res_reg = rs_rMIPS_RET0; break; |
| 103 | case kRet1: res_reg = rs_rMIPS_RET1; break; |
| 104 | case kInvokeTgt: res_reg = rs_rMIPS_INVOKE_TGT; break; |
| 105 | case kHiddenArg: res_reg = rs_rT0; break; |
| 106 | case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break; |
| 107 | case kCount: res_reg = rs_rMIPS_COUNT; break; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 108 | default: res_reg = RegStorage::InvalidReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 109 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 110 | return res_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 111 | } |
| 112 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 113 | RegStorage MipsMir2Lir::GetArgMappingToPhysicalReg(int arg_num) { |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 114 | // For the 32-bit internal ABI, the first 3 arguments are passed in registers. |
| 115 | switch (arg_num) { |
| 116 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 117 | return rs_rMIPS_ARG1; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 118 | case 1: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 119 | return rs_rMIPS_ARG2; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 120 | case 2: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 121 | return rs_rMIPS_ARG3; |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 122 | default: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 123 | return RegStorage::InvalidReg(); |
Razvan A Lupusoru | 3bc0174 | 2014-02-06 13:18:43 -0800 | [diff] [blame] | 124 | } |
| 125 | } |
| 126 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 127 | /* |
| 128 | * Decode the register id. |
| 129 | */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 130 | ResourceMask MipsMir2Lir::GetRegMaskCommon(const RegStorage& reg) const { |
| 131 | return reg.IsDouble() |
| 132 | /* Each double register is equal to a pair of single-precision FP registers */ |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 133 | #if (FR_BIT == 0) |
| 134 | ? ResourceMask::TwoBits((reg.GetRegNum() & ~1) + kMipsFPReg0) |
| 135 | #else |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 136 | ? ResourceMask::TwoBits(reg.GetRegNum() * 2 + kMipsFPReg0) |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 137 | #endif |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 138 | : ResourceMask::Bit(reg.IsSingle() ? reg.GetRegNum() + kMipsFPReg0 : reg.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 141 | ResourceMask MipsMir2Lir::GetPCUseDefEncoding() const { |
| 142 | return ResourceMask::Bit(kMipsRegPC); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 146 | void MipsMir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 147 | ResourceMask* use_mask, ResourceMask* def_mask) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 148 | DCHECK_EQ(cu_->instruction_set, kMips); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 149 | DCHECK(!lir->flags.use_def_invalid); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 150 | |
| 151 | // Mips-specific resource map setup here. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 152 | if (flags & REG_DEF_SP) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 153 | def_mask->SetBit(kMipsRegSP); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | if (flags & REG_USE_SP) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 157 | use_mask->SetBit(kMipsRegSP); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | if (flags & REG_DEF_LR) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 161 | def_mask->SetBit(kMipsRegLR); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 162 | } |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 163 | |
| 164 | if (flags & REG_DEF_HI) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 165 | def_mask->SetBit(kMipsRegHI); |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | if (flags & REG_DEF_LO) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 169 | def_mask->SetBit(kMipsRegLO); |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | if (flags & REG_USE_HI) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 173 | use_mask->SetBit(kMipsRegHI); |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | if (flags & REG_USE_LO) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 177 | use_mask->SetBit(kMipsRegLO); |
buzbee | 9da5c10 | 2014-03-28 12:59:18 -0700 | [diff] [blame] | 178 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /* For dumping instructions */ |
| 182 | #define MIPS_REG_COUNT 32 |
| 183 | static const char *mips_reg_name[MIPS_REG_COUNT] = { |
| 184 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 185 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 186 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 187 | "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" |
| 188 | }; |
| 189 | |
| 190 | /* |
| 191 | * Interpret a format string and build a string no longer than size |
| 192 | * See format key in Assemble.c. |
| 193 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 194 | std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 195 | std::string buf; |
| 196 | int i; |
| 197 | const char *fmt_end = &fmt[strlen(fmt)]; |
| 198 | char tbuf[256]; |
| 199 | char nc; |
| 200 | while (fmt < fmt_end) { |
| 201 | int operand; |
| 202 | if (*fmt == '!') { |
| 203 | fmt++; |
| 204 | DCHECK_LT(fmt, fmt_end); |
| 205 | nc = *fmt++; |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 206 | if (nc == '!') { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 207 | strcpy(tbuf, "!"); |
| 208 | } else { |
| 209 | DCHECK_LT(fmt, fmt_end); |
| 210 | DCHECK_LT(static_cast<unsigned>(nc-'0'), 4u); |
| 211 | operand = lir->operands[nc-'0']; |
| 212 | switch (*fmt++) { |
| 213 | case 'b': |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 214 | strcpy(tbuf, "0000"); |
Brian Carlstrom | 38f85e4 | 2013-07-18 14:45:22 -0700 | [diff] [blame] | 215 | for (i = 3; i >= 0; i--) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 216 | tbuf[i] += operand & 1; |
| 217 | operand >>= 1; |
| 218 | } |
| 219 | break; |
| 220 | case 's': |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 221 | snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 222 | break; |
| 223 | case 'S': |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 224 | DCHECK_EQ(RegStorage::RegNum(operand) & 1, 0); |
| 225 | snprintf(tbuf, arraysize(tbuf), "$f%d", RegStorage::RegNum(operand)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 226 | break; |
| 227 | case 'h': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 228 | snprintf(tbuf, arraysize(tbuf), "%04x", operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 229 | break; |
| 230 | case 'M': |
| 231 | case 'd': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 232 | snprintf(tbuf, arraysize(tbuf), "%d", operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 233 | break; |
| 234 | case 'D': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 235 | snprintf(tbuf, arraysize(tbuf), "%d", operand+1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 236 | break; |
| 237 | case 'E': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 238 | snprintf(tbuf, arraysize(tbuf), "%d", operand*4); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 239 | break; |
| 240 | case 'F': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 241 | snprintf(tbuf, arraysize(tbuf), "%d", operand*2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 242 | break; |
| 243 | case 't': |
Ian Rogers | 107c31e | 2014-01-23 20:55:29 -0800 | [diff] [blame] | 244 | snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", |
| 245 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 + (operand << 1), |
| 246 | lir->target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 247 | break; |
| 248 | case 'T': |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 249 | snprintf(tbuf, arraysize(tbuf), "0x%08x", operand << 2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 250 | break; |
| 251 | case 'u': { |
| 252 | int offset_1 = lir->operands[0]; |
| 253 | int offset_2 = NEXT_LIR(lir)->operands[0]; |
| 254 | uintptr_t target = |
| 255 | (((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) & ~3) + |
| 256 | (offset_1 << 21 >> 9) + (offset_2 << 1)) & 0xfffffffc; |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 257 | snprintf(tbuf, arraysize(tbuf), "%p", reinterpret_cast<void*>(target)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 258 | break; |
| 259 | } |
| 260 | |
| 261 | /* Nothing to print for BLX_2 */ |
| 262 | case 'v': |
| 263 | strcpy(tbuf, "see above"); |
| 264 | break; |
| 265 | case 'r': |
| 266 | DCHECK(operand >= 0 && operand < MIPS_REG_COUNT); |
| 267 | strcpy(tbuf, mips_reg_name[operand]); |
| 268 | break; |
| 269 | case 'N': |
| 270 | // Placeholder for delay slot handling |
| 271 | strcpy(tbuf, "; nop"); |
| 272 | break; |
| 273 | default: |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 274 | strcpy(tbuf, "DecodeError"); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 275 | break; |
| 276 | } |
| 277 | buf += tbuf; |
| 278 | } |
| 279 | } else { |
| 280 | buf += *fmt++; |
| 281 | } |
| 282 | } |
| 283 | return buf; |
| 284 | } |
| 285 | |
| 286 | // FIXME: need to redo resource maps for MIPS - fix this at that time |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 287 | void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, const ResourceMask& mask, const char *prefix) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 288 | char buf[256]; |
| 289 | buf[0] = 0; |
| 290 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 291 | if (mask.Equals(kEncodeAll)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 292 | strcpy(buf, "all"); |
| 293 | } else { |
| 294 | char num[8]; |
| 295 | int i; |
| 296 | |
| 297 | for (i = 0; i < kMipsRegEnd; i++) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 298 | if (mask.HasBit(i)) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 299 | snprintf(num, arraysize(num), "%d ", i); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 300 | strcat(buf, num); |
| 301 | } |
| 302 | } |
| 303 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 304 | if (mask.HasBit(ResourceMask::kCCode)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 305 | strcat(buf, "cc "); |
| 306 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 307 | if (mask.HasBit(ResourceMask::kFPStatus)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 308 | strcat(buf, "fpcc "); |
| 309 | } |
| 310 | /* Memory bits */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 311 | if (mips_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 312 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 313 | DECODE_ALIAS_INFO_REG(mips_lir->flags.alias_info), |
| 314 | DECODE_ALIAS_INFO_WIDE(mips_lir->flags.alias_info) ? "(+1)" : ""); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 315 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 316 | if (mask.HasBit(ResourceMask::kLiteral)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 317 | strcat(buf, "lit "); |
| 318 | } |
| 319 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 320 | if (mask.HasBit(ResourceMask::kHeapRef)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 321 | strcat(buf, "heap "); |
| 322 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 323 | if (mask.HasBit(ResourceMask::kMustNotAlias)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 324 | strcat(buf, "noalias "); |
| 325 | } |
| 326 | } |
| 327 | if (buf[0]) { |
| 328 | LOG(INFO) << prefix << ": " << buf; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | /* |
| 333 | * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some |
| 334 | * instructions might call out to C/assembly helper functions. Until |
| 335 | * machinery is in place, always spill lr. |
| 336 | */ |
| 337 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 338 | void MipsMir2Lir::AdjustSpillMask() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 339 | core_spill_mask_ |= (1 << rs_rRA.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 340 | num_core_spills_++; |
| 341 | } |
| 342 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 343 | /* Clobber all regs that might be used by an external C call */ |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 344 | void MipsMir2Lir::ClobberCallerSave() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 345 | Clobber(rs_rZERO); |
| 346 | Clobber(rs_rAT); |
| 347 | Clobber(rs_rV0); |
| 348 | Clobber(rs_rV1); |
| 349 | Clobber(rs_rA0); |
| 350 | Clobber(rs_rA1); |
| 351 | Clobber(rs_rA2); |
| 352 | Clobber(rs_rA3); |
| 353 | Clobber(rs_rT0); |
| 354 | Clobber(rs_rT1); |
| 355 | Clobber(rs_rT2); |
| 356 | Clobber(rs_rT3); |
| 357 | Clobber(rs_rT4); |
| 358 | Clobber(rs_rT5); |
| 359 | Clobber(rs_rT6); |
| 360 | Clobber(rs_rT7); |
| 361 | Clobber(rs_rT8); |
| 362 | Clobber(rs_rT9); |
| 363 | Clobber(rs_rK0); |
| 364 | Clobber(rs_rK1); |
| 365 | Clobber(rs_rGP); |
| 366 | Clobber(rs_rFP); |
| 367 | Clobber(rs_rRA); |
| 368 | Clobber(rs_rF0); |
| 369 | Clobber(rs_rF1); |
| 370 | Clobber(rs_rF2); |
| 371 | Clobber(rs_rF3); |
| 372 | Clobber(rs_rF4); |
| 373 | Clobber(rs_rF5); |
| 374 | Clobber(rs_rF6); |
| 375 | Clobber(rs_rF7); |
| 376 | Clobber(rs_rF8); |
| 377 | Clobber(rs_rF9); |
| 378 | Clobber(rs_rF10); |
| 379 | Clobber(rs_rF11); |
| 380 | Clobber(rs_rF12); |
| 381 | Clobber(rs_rF13); |
| 382 | Clobber(rs_rF14); |
| 383 | Clobber(rs_rF15); |
| 384 | Clobber(rs_rD0); |
| 385 | Clobber(rs_rD1); |
| 386 | Clobber(rs_rD2); |
| 387 | Clobber(rs_rD3); |
| 388 | Clobber(rs_rD4); |
| 389 | Clobber(rs_rD5); |
| 390 | Clobber(rs_rD6); |
| 391 | Clobber(rs_rD7); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 392 | } |
| 393 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 394 | RegLocation MipsMir2Lir::GetReturnWideAlt() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 395 | UNIMPLEMENTED(FATAL) << "No GetReturnWideAlt for MIPS"; |
| 396 | RegLocation res = LocCReturnWide(); |
| 397 | return res; |
| 398 | } |
| 399 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 400 | RegLocation MipsMir2Lir::GetReturnAlt() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 401 | UNIMPLEMENTED(FATAL) << "No GetReturnAlt for MIPS"; |
| 402 | RegLocation res = LocCReturn(); |
| 403 | return res; |
| 404 | } |
| 405 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 406 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 407 | void MipsMir2Lir::LockCallTemps() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 408 | LockTemp(rs_rMIPS_ARG0); |
| 409 | LockTemp(rs_rMIPS_ARG1); |
| 410 | LockTemp(rs_rMIPS_ARG2); |
| 411 | LockTemp(rs_rMIPS_ARG3); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 415 | void MipsMir2Lir::FreeCallTemps() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 416 | FreeTemp(rs_rMIPS_ARG0); |
| 417 | FreeTemp(rs_rMIPS_ARG1); |
| 418 | FreeTemp(rs_rMIPS_ARG2); |
| 419 | FreeTemp(rs_rMIPS_ARG3); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 420 | } |
| 421 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 422 | bool MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 423 | #if ANDROID_SMP != 0 |
| 424 | NewLIR1(kMipsSync, 0 /* Only stype currently supported */); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 425 | return true; |
| 426 | #else |
| 427 | return false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 428 | #endif |
| 429 | } |
| 430 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 431 | void MipsMir2Lir::CompilerInitializeRegAlloc() { |
buzbee | b01bf15 | 2014-05-13 15:59:07 -0700 | [diff] [blame] | 432 | reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, empty_pool /* core64 */, sp_regs, |
| 433 | dp_regs, reserved_regs, empty_pool /* reserved64 */, |
| 434 | core_temps, empty_pool /* core64_temps */, sp_temps, |
| 435 | dp_temps); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 436 | |
| 437 | // Target-specific adjustments. |
| 438 | |
| 439 | // Alias single precision floats to appropriate half of overlapping double. |
| 440 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); |
| 441 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 442 | int sp_reg_num = info->GetReg().GetRegNum(); |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 443 | #if (FR_BIT == 0) |
| 444 | int dp_reg_num = sp_reg_num & ~1; |
| 445 | #else |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 446 | int dp_reg_num = sp_reg_num >> 1; |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 447 | #endif |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 448 | RegStorage dp_reg = RegStorage::Solo64(RegStorage::kFloatingPoint | dp_reg_num); |
| 449 | RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); |
| 450 | // Double precision register's master storage should refer to itself. |
| 451 | DCHECK_EQ(dp_reg_info, dp_reg_info->Master()); |
| 452 | // Redirect single precision's master storage to master. |
| 453 | info->SetMaster(dp_reg_info); |
| 454 | // Singles should show a single 32-bit mask bit, at first referring to the low half. |
| 455 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 456 | if (sp_reg_num & 1) { |
| 457 | // For odd singles, change to user the high word of the backing double. |
| 458 | info->SetStorageMask(0x2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 459 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 460 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 461 | |
| 462 | // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. |
| 463 | // TODO: adjust when we roll to hard float calling convention. |
| 464 | reg_pool_->next_core_reg_ = 2; |
| 465 | reg_pool_->next_sp_reg_ = 2; |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 466 | #if (FR_BIT == 0) |
| 467 | reg_pool_->next_dp_reg_ = 2; |
| 468 | #else |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 469 | reg_pool_->next_dp_reg_ = 1; |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 470 | #endif |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 471 | } |
| 472 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 473 | /* |
| 474 | * In the Arm code a it is typical to use the link register |
| 475 | * to hold the target address. However, for Mips we must |
| 476 | * ensure that all branch instructions can be restarted if |
| 477 | * there is a trap in the shadow. Allocate a temp register. |
| 478 | */ |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 479 | RegStorage MipsMir2Lir::LoadHelper(ThreadOffset<4> offset) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 480 | // NOTE: native pointer. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 481 | LoadWordDisp(rs_rMIPS_SELF, offset.Int32Value(), rs_rT9); |
| 482 | return rs_rT9; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 483 | } |
| 484 | |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 485 | RegStorage MipsMir2Lir::LoadHelper(ThreadOffset<8> offset) { |
| 486 | UNIMPLEMENTED(FATAL) << "Should not be called."; |
| 487 | return RegStorage::InvalidReg(); |
| 488 | } |
| 489 | |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 490 | LIR* MipsMir2Lir::CheckSuspendUsingLoad() { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 491 | RegStorage tmp = AllocTemp(); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 492 | // NOTE: native pointer. |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 493 | LoadWordDisp(rs_rMIPS_SELF, Thread::ThreadSuspendTriggerOffset<4>().Int32Value(), tmp); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 494 | LIR *inst = LoadWordDisp(tmp, 0, tmp); |
| 495 | FreeTemp(tmp); |
| 496 | return inst; |
| 497 | } |
| 498 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 499 | void MipsMir2Lir::SpillCoreRegs() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 500 | if (num_core_spills_ == 0) { |
| 501 | return; |
| 502 | } |
| 503 | uint32_t mask = core_spill_mask_; |
| 504 | int offset = num_core_spills_ * 4; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 505 | OpRegImm(kOpSub, rs_rSP, offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 506 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 507 | if (mask & 0x1) { |
| 508 | offset -= 4; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 509 | Store32Disp(rs_rMIPS_SP, offset, RegStorage::Solo32(reg)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 510 | } |
| 511 | } |
| 512 | } |
| 513 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 514 | void MipsMir2Lir::UnSpillCoreRegs() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 515 | if (num_core_spills_ == 0) { |
| 516 | return; |
| 517 | } |
| 518 | uint32_t mask = core_spill_mask_; |
| 519 | int offset = frame_size_; |
| 520 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 521 | if (mask & 0x1) { |
| 522 | offset -= 4; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 523 | Load32Disp(rs_rMIPS_SP, offset, RegStorage::Solo32(reg)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 524 | } |
| 525 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 526 | OpRegImm(kOpAdd, rs_rSP, frame_size_); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 527 | } |
| 528 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 529 | bool MipsMir2Lir::IsUnconditionalBranch(LIR* lir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 530 | return (lir->opcode == kMipsB); |
| 531 | } |
| 532 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 533 | bool MipsMir2Lir::SupportsVolatileLoadStore(OpSize size) { |
| 534 | // No support for 64-bit atomic load/store on mips. |
| 535 | return size != k64 && size != kDouble; |
| 536 | } |
| 537 | |
| 538 | RegisterClass MipsMir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { |
Douglas Leung | 2db3e26 | 2014-06-25 16:02:55 -0700 | [diff] [blame] | 539 | if (UNLIKELY(is_volatile)) { |
| 540 | // On Mips, atomic 64-bit load/store requires an fp register. |
| 541 | // Smaller aligned load/store is atomic for both core and fp registers. |
| 542 | if (size == k64 || size == kDouble) { |
| 543 | return kFPReg; |
| 544 | } |
| 545 | } |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 546 | // TODO: Verify that both core and fp registers are suitable for smaller sizes. |
| 547 | return RegClassBySize(size); |
| 548 | } |
| 549 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 550 | MipsMir2Lir::MipsMir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
| 551 | : Mir2Lir(cu, mir_graph, arena) { |
| 552 | for (int i = 0; i < kMipsLast; i++) { |
| 553 | if (MipsMir2Lir::EncodingMap[i].opcode != i) { |
| 554 | LOG(FATAL) << "Encoding order for " << MipsMir2Lir::EncodingMap[i].name |
| 555 | << " is wrong: expecting " << i << ", seeing " |
| 556 | << static_cast<int>(MipsMir2Lir::EncodingMap[i].opcode); |
| 557 | } |
| 558 | } |
| 559 | } |
| 560 | |
| 561 | Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 562 | ArenaAllocator* const arena) { |
| 563 | return new MipsMir2Lir(cu, mir_graph, arena); |
| 564 | } |
| 565 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 566 | uint64_t MipsMir2Lir::GetTargetInstFlags(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 567 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 568 | return MipsMir2Lir::EncodingMap[opcode].flags; |
| 569 | } |
| 570 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 571 | const char* MipsMir2Lir::GetTargetInstName(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 572 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 573 | return MipsMir2Lir::EncodingMap[opcode].name; |
| 574 | } |
| 575 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 576 | const char* MipsMir2Lir::GetTargetInstFmt(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 577 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 578 | return MipsMir2Lir::EncodingMap[opcode].fmt; |
| 579 | } |
| 580 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 581 | } // namespace art |