Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the X86 ISA */ |
| 18 | |
| 19 | #include "codegen_x86.h" |
| 20 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 21 | #include "dex/reg_storage_eq.h" |
Mingyao Yang | 98d1cc8 | 2014-05-15 17:02:16 -0700 | [diff] [blame] | 22 | #include "mirror/art_method.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 23 | #include "mirror/array.h" |
| 24 | #include "x86_lir.h" |
| 25 | |
| 26 | namespace art { |
| 27 | |
| 28 | /* |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | * Compare two 64-bit values |
| 30 | * x = y return 0 |
| 31 | * x < y return -1 |
| 32 | * x > y return 1 |
| 33 | */ |
| 34 | void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 35 | RegLocation rl_src2) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 36 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 37 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 38 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 39 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 40 | RegStorage temp_reg = AllocTemp(); |
Serguei Katkov | 1c55703 | 2014-06-23 13:23:38 +0700 | [diff] [blame] | 41 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 42 | NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0 |
| 43 | NewLIR2(kX86Set8R, temp_reg.GetReg(), kX86CondL); // temp = (src1 >= src2) ? 0 : 1 |
| 44 | NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg()); |
| 45 | NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
Serguei Katkov | 0498223 | 2014-06-20 18:17:16 +0700 | [diff] [blame] | 46 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 47 | StoreValue(rl_dest, rl_result); |
| 48 | FreeTemp(temp_reg); |
| 49 | return; |
| 50 | } |
| 51 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 52 | FlushAllRegs(); |
| 53 | LockCallTemps(); // Prepare for explicit register usage |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 54 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 55 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 56 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 57 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 58 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 59 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 60 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 61 | NewLIR2(kX86Set8R, rs_r2.GetReg(), kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0 |
| 62 | NewLIR2(kX86Movzx8RR, rs_r2.GetReg(), rs_r2.GetReg()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 63 | OpReg(kOpNeg, rs_r2); // r2 = -r2 |
| 64 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = high | low - sets ZF |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 65 | NewLIR2(kX86Set8R, rs_r0.GetReg(), kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | NewLIR2(kX86Movzx8RR, r0, r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 67 | OpRegReg(kOpOr, rs_r0, rs_r2); // r0 = r0 | r2 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 68 | RegLocation rl_result = LocCReturn(); |
| 69 | StoreValue(rl_dest, rl_result); |
| 70 | } |
| 71 | |
| 72 | X86ConditionCode X86ConditionEncoding(ConditionCode cond) { |
| 73 | switch (cond) { |
| 74 | case kCondEq: return kX86CondEq; |
| 75 | case kCondNe: return kX86CondNe; |
| 76 | case kCondCs: return kX86CondC; |
| 77 | case kCondCc: return kX86CondNc; |
Vladimir Marko | 58af1f9 | 2013-12-19 13:31:15 +0000 | [diff] [blame] | 78 | case kCondUlt: return kX86CondC; |
| 79 | case kCondUge: return kX86CondNc; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 80 | case kCondMi: return kX86CondS; |
| 81 | case kCondPl: return kX86CondNs; |
| 82 | case kCondVs: return kX86CondO; |
| 83 | case kCondVc: return kX86CondNo; |
| 84 | case kCondHi: return kX86CondA; |
| 85 | case kCondLs: return kX86CondBe; |
| 86 | case kCondGe: return kX86CondGe; |
| 87 | case kCondLt: return kX86CondL; |
| 88 | case kCondGt: return kX86CondG; |
| 89 | case kCondLe: return kX86CondLe; |
| 90 | case kCondAl: |
| 91 | case kCondNv: LOG(FATAL) << "Should not reach here"; |
| 92 | } |
| 93 | return kX86CondO; |
| 94 | } |
| 95 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 96 | LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 97 | NewLIR2(src1.Is64Bit() ? kX86Cmp64RR : kX86Cmp32RR, src1.GetReg(), src2.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 98 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 99 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , |
| 100 | cc); |
| 101 | branch->target = target; |
| 102 | return branch; |
| 103 | } |
| 104 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 105 | LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 106 | int check_value, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) { |
| 108 | // TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 109 | NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg.GetReg(), reg.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 110 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 111 | if (reg.Is64Bit()) { |
| 112 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp64RI8 : kX86Cmp64RI, reg.GetReg(), check_value); |
| 113 | } else { |
| 114 | NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); |
| 115 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 116 | } |
| 117 | X86ConditionCode cc = X86ConditionEncoding(cond); |
| 118 | LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ , cc); |
| 119 | branch->target = target; |
| 120 | return branch; |
| 121 | } |
| 122 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 123 | LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { |
| 124 | // If src or dest is a pair, we'll be using low reg. |
| 125 | if (r_dest.IsPair()) { |
| 126 | r_dest = r_dest.GetLow(); |
| 127 | } |
| 128 | if (r_src.IsPair()) { |
| 129 | r_src = r_src.GetLow(); |
| 130 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 131 | if (r_dest.IsFloat() || r_src.IsFloat()) |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 132 | return OpFpRegCopy(r_dest, r_src); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 133 | LIR* res = RawLIR(current_dalvik_offset_, r_dest.Is64Bit() ? kX86Mov64RR : kX86Mov32RR, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 134 | r_dest.GetReg(), r_src.GetReg()); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 135 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 136 | res->flags.is_nop = true; |
| 137 | } |
| 138 | return res; |
| 139 | } |
| 140 | |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 141 | void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { |
| 142 | if (r_dest != r_src) { |
| 143 | LIR *res = OpRegCopyNoInsert(r_dest, r_src); |
| 144 | AppendLIR(res); |
| 145 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 146 | } |
| 147 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 148 | void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 149 | if (r_dest != r_src) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 150 | bool dest_fp = r_dest.IsFloat(); |
| 151 | bool src_fp = r_src.IsFloat(); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 152 | if (dest_fp) { |
| 153 | if (src_fp) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 154 | OpRegCopy(r_dest, r_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 155 | } else { |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 156 | // TODO: Prevent this from happening in the code. The result is often |
| 157 | // unused or could have been loaded more easily from memory. |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 158 | if (!r_src.IsPair()) { |
| 159 | DCHECK(!r_dest.IsPair()); |
| 160 | NewLIR2(kX86MovqxrRR, r_dest.GetReg(), r_src.GetReg()); |
| 161 | } else { |
| 162 | NewLIR2(kX86MovdxrRR, r_dest.GetReg(), r_src.GetLowReg()); |
| 163 | RegStorage r_tmp = AllocTempDouble(); |
| 164 | NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), r_src.GetHighReg()); |
| 165 | NewLIR2(kX86PunpckldqRR, r_dest.GetReg(), r_tmp.GetReg()); |
| 166 | FreeTemp(r_tmp); |
| 167 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 168 | } |
| 169 | } else { |
| 170 | if (src_fp) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 171 | if (!r_dest.IsPair()) { |
| 172 | DCHECK(!r_src.IsPair()); |
| 173 | NewLIR2(kX86MovqrxRR, r_dest.GetReg(), r_src.GetReg()); |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 174 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 175 | NewLIR2(kX86MovdrxRR, r_dest.GetLowReg(), r_src.GetReg()); |
| 176 | RegStorage temp_reg = AllocTempDouble(); |
| 177 | NewLIR2(kX86MovsdRR, temp_reg.GetReg(), r_src.GetReg()); |
| 178 | NewLIR2(kX86PsrlqRI, temp_reg.GetReg(), 32); |
| 179 | NewLIR2(kX86MovdrxRR, r_dest.GetHighReg(), temp_reg.GetReg()); |
| 180 | } |
| 181 | } else { |
| 182 | DCHECK_EQ(r_dest.IsPair(), r_src.IsPair()); |
| 183 | if (!r_src.IsPair()) { |
| 184 | // Just copy the register directly. |
| 185 | OpRegCopy(r_dest, r_src); |
| 186 | } else { |
| 187 | // Handle overlap |
| 188 | if (r_src.GetHighReg() == r_dest.GetLowReg() && |
| 189 | r_src.GetLowReg() == r_dest.GetHighReg()) { |
| 190 | // Deal with cycles. |
| 191 | RegStorage temp_reg = AllocTemp(); |
| 192 | OpRegCopy(temp_reg, r_dest.GetHigh()); |
| 193 | OpRegCopy(r_dest.GetHigh(), r_dest.GetLow()); |
| 194 | OpRegCopy(r_dest.GetLow(), temp_reg); |
| 195 | FreeTemp(temp_reg); |
| 196 | } else if (r_src.GetHighReg() == r_dest.GetLowReg()) { |
| 197 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 198 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 199 | } else { |
| 200 | OpRegCopy(r_dest.GetLow(), r_src.GetLow()); |
| 201 | OpRegCopy(r_dest.GetHigh(), r_src.GetHigh()); |
| 202 | } |
buzbee | 7a11ab0 | 2014-04-28 20:02:38 -0700 | [diff] [blame] | 203 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 204 | } |
| 205 | } |
| 206 | } |
| 207 | } |
| 208 | |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 209 | void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, |
| 210 | int32_t true_val, int32_t false_val, RegStorage rs_dest, |
| 211 | int dest_reg_class) { |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 212 | DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); |
| 213 | DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); |
| 214 | |
| 215 | // We really need this check for correctness, otherwise we will need to do more checks in |
| 216 | // non zero/one case |
| 217 | if (true_val == false_val) { |
| 218 | LoadConstantNoClobber(rs_dest, true_val); |
| 219 | return; |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 220 | } |
| 221 | |
Serguei Katkov | 9ee4519 | 2014-07-17 14:39:03 +0700 | [diff] [blame] | 222 | const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); |
| 223 | |
| 224 | const bool zero_one_case = (true_val == 0 && false_val == 1) || (true_val == 1 && false_val == 0); |
| 225 | if (zero_one_case && IsByteRegister(rs_dest)) { |
| 226 | if (!dest_intersect) { |
| 227 | LoadConstantNoClobber(rs_dest, 0); |
| 228 | } |
| 229 | OpRegReg(kOpCmp, left_op, right_op); |
| 230 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
| 231 | NewLIR2(kX86Set8R, rs_dest.GetReg(), |
| 232 | X86ConditionEncoding(true_val == 1 ? code : FlipComparisonOrder(code))); |
| 233 | if (dest_intersect) { |
| 234 | NewLIR2(rs_dest.Is64Bit() ? kX86Movzx8qRR : kX86Movzx8RR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 235 | } |
| 236 | } else { |
| 237 | // Be careful rs_dest can be changed only after cmp because it can be the same as one of ops |
| 238 | // and it cannot use xor because it makes cc flags to be dirty |
| 239 | RegStorage temp_reg = AllocTypedTemp(false, dest_reg_class, false); |
| 240 | if (temp_reg.Valid()) { |
| 241 | if (false_val == 0 && dest_intersect) { |
| 242 | code = FlipComparisonOrder(code); |
| 243 | std::swap(true_val, false_val); |
| 244 | } |
| 245 | if (!dest_intersect) { |
| 246 | LoadConstantNoClobber(rs_dest, false_val); |
| 247 | } |
| 248 | LoadConstantNoClobber(temp_reg, true_val); |
| 249 | OpRegReg(kOpCmp, left_op, right_op); |
| 250 | if (dest_intersect) { |
| 251 | LoadConstantNoClobber(rs_dest, false_val); |
| 252 | DCHECK(!last_lir_insn_->u.m.def_mask->HasBit(ResourceMask::kCCode)); |
| 253 | } |
| 254 | OpCondRegReg(kOpCmov, code, rs_dest, temp_reg); |
| 255 | FreeTemp(temp_reg); |
| 256 | } else { |
| 257 | // slow path |
| 258 | LIR* cmp_branch = OpCmpBranch(code, left_op, right_op, nullptr); |
| 259 | LoadConstantNoClobber(rs_dest, false_val); |
| 260 | LIR* that_is_it = NewLIR1(kX86Jmp8, 0); |
| 261 | LIR* true_case = NewLIR0(kPseudoTargetLabel); |
| 262 | cmp_branch->target = true_case; |
| 263 | LoadConstantNoClobber(rs_dest, true_val); |
| 264 | LIR* end = NewLIR0(kPseudoTargetLabel); |
| 265 | that_is_it->target = end; |
| 266 | } |
| 267 | } |
Andreas Gampe | 90969af | 2014-07-15 23:02:11 -0700 | [diff] [blame] | 268 | } |
| 269 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 270 | void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 271 | RegLocation rl_result; |
| 272 | RegLocation rl_src = mir_graph_->GetSrc(mir, 0); |
| 273 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 274 | // Avoid using float regs here. |
| 275 | RegisterClass src_reg_class = rl_src.ref ? kRefReg : kCoreReg; |
| 276 | RegisterClass result_reg_class = rl_dest.ref ? kRefReg : kCoreReg; |
| 277 | rl_src = LoadValue(rl_src, src_reg_class); |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 278 | ConditionCode ccode = mir->meta.ccode; |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 279 | |
| 280 | // The kMirOpSelect has two variants, one for constants and one for moves. |
| 281 | const bool is_constant_case = (mir->ssa_rep->num_uses == 1); |
| 282 | |
| 283 | if (is_constant_case) { |
| 284 | int true_val = mir->dalvikInsn.vB; |
| 285 | int false_val = mir->dalvikInsn.vC; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 286 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 287 | |
| 288 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 289 | * For ccode == kCondEq: |
| 290 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 291 | * 1) When the true case is zero and result_reg is not same as src_reg: |
| 292 | * xor result_reg, result_reg |
| 293 | * cmp $0, src_reg |
| 294 | * mov t1, $false_case |
| 295 | * cmovnz result_reg, t1 |
| 296 | * 2) When the false case is zero and result_reg is not same as src_reg: |
| 297 | * xor result_reg, result_reg |
| 298 | * cmp $0, src_reg |
| 299 | * mov t1, $true_case |
| 300 | * cmovz result_reg, t1 |
| 301 | * 3) All other cases (we do compare first to set eflags): |
| 302 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 303 | * mov result_reg, $false_case |
| 304 | * mov t1, $true_case |
| 305 | * cmovz result_reg, t1 |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 306 | */ |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 307 | // FIXME: depending on how you use registers you could get a false != mismatch when dealing |
| 308 | // with different views of the same underlying physical resource (i.e. solo32 vs. solo64). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 309 | const bool result_reg_same_as_src = |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 310 | (rl_src.location == kLocPhysReg && rl_src.reg.GetRegNum() == rl_result.reg.GetRegNum()); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 311 | const bool true_zero_case = (true_val == 0 && false_val != 0 && !result_reg_same_as_src); |
| 312 | const bool false_zero_case = (false_val == 0 && true_val != 0 && !result_reg_same_as_src); |
| 313 | const bool catch_all_case = !(true_zero_case || false_zero_case); |
| 314 | |
| 315 | if (true_zero_case || false_zero_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 316 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | if (true_zero_case || false_zero_case || catch_all_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 320 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | if (catch_all_case) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 324 | OpRegImm(kOpMov, rl_result.reg, false_val); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 325 | } |
| 326 | |
| 327 | if (true_zero_case || false_zero_case || catch_all_case) { |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 328 | ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; |
| 329 | int immediateForTemp = true_zero_case ? false_val : true_val; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 330 | RegStorage temp1_reg = AllocTypedTemp(false, result_reg_class); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 331 | OpRegImm(kOpMov, temp1_reg, immediateForTemp); |
| 332 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 333 | OpCondRegReg(kOpCmov, cc, rl_result.reg, temp1_reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 334 | |
| 335 | FreeTemp(temp1_reg); |
| 336 | } |
| 337 | } else { |
| 338 | RegLocation rl_true = mir_graph_->GetSrc(mir, 1); |
| 339 | RegLocation rl_false = mir_graph_->GetSrc(mir, 2); |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 340 | rl_true = LoadValue(rl_true, result_reg_class); |
| 341 | rl_false = LoadValue(rl_false, result_reg_class); |
| 342 | rl_result = EvalLoc(rl_dest, result_reg_class, true); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 343 | |
| 344 | /* |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 345 | * For ccode == kCondEq: |
| 346 | * |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 347 | * 1) When true case is already in place: |
| 348 | * cmp $0, src_reg |
| 349 | * cmovnz result_reg, false_reg |
| 350 | * 2) When false case is already in place: |
| 351 | * cmp $0, src_reg |
| 352 | * cmovz result_reg, true_reg |
| 353 | * 3) When neither cases are in place: |
| 354 | * cmp $0, src_reg |
Vladimir Marko | a1a7074 | 2014-03-03 10:28:05 +0000 | [diff] [blame] | 355 | * mov result_reg, false_reg |
| 356 | * cmovz result_reg, true_reg |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 357 | */ |
| 358 | |
| 359 | // kMirOpSelect is generated just for conditional cases when comparison is done with zero. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 360 | OpRegImm(kOpCmp, rl_src.reg, 0); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 361 | |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 362 | if (rl_result.reg.GetReg() == rl_true.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 363 | OpCondRegReg(kOpCmov, NegateComparison(ccode), rl_result.reg, rl_false.reg); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 364 | } else if (rl_result.reg.GetReg() == rl_false.reg.GetReg()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 365 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 366 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 367 | OpRegCopy(rl_result.reg, rl_false.reg); |
| 368 | OpCondRegReg(kOpCmov, ccode, rl_result.reg, rl_true.reg); |
Razvan A Lupusoru | e27b3bf | 2014-01-23 09:41:45 -0800 | [diff] [blame] | 369 | } |
| 370 | } |
| 371 | |
| 372 | StoreValue(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 376 | LIR* taken = &block_label_list_[bb->taken]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 377 | RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 378 | RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
Vladimir Marko | a894607 | 2014-01-22 10:30:44 +0000 | [diff] [blame] | 379 | ConditionCode ccode = mir->meta.ccode; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 380 | |
| 381 | if (rl_src1.is_const) { |
| 382 | std::swap(rl_src1, rl_src2); |
| 383 | ccode = FlipComparisonOrder(ccode); |
| 384 | } |
| 385 | if (rl_src2.is_const) { |
| 386 | // Do special compare/branch against simple const operand |
| 387 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 388 | GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); |
| 389 | return; |
| 390 | } |
| 391 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 392 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 393 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 394 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 395 | |
| 396 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
| 397 | OpCondBranch(ccode, taken); |
| 398 | return; |
| 399 | } |
| 400 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 401 | FlushAllRegs(); |
| 402 | LockCallTemps(); // Prepare for explicit register usage |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 403 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_r0, rs_r1); |
| 404 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_r2, rs_r3); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 405 | LoadValueDirectWideFixed(rl_src1, r_tmp1); |
| 406 | LoadValueDirectWideFixed(rl_src2, r_tmp2); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 407 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 408 | // Swap operands and condition code to prevent use of zero flag. |
| 409 | if (ccode == kCondLe || ccode == kCondGt) { |
| 410 | // Compute (r3:r2) = (r3:r2) - (r1:r0) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 411 | OpRegReg(kOpSub, rs_r2, rs_r0); // r2 = r2 - r0 |
| 412 | OpRegReg(kOpSbc, rs_r3, rs_r1); // r3 = r3 - r1 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 413 | } else { |
| 414 | // Compute (r1:r0) = (r1:r0) - (r3:r2) |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 415 | OpRegReg(kOpSub, rs_r0, rs_r2); // r0 = r0 - r2 |
| 416 | OpRegReg(kOpSbc, rs_r1, rs_r3); // r1 = r1 - r3 - CF |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 417 | } |
| 418 | switch (ccode) { |
| 419 | case kCondEq: |
| 420 | case kCondNe: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 421 | OpRegReg(kOpOr, rs_r0, rs_r1); // r0 = r0 | r1 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 422 | break; |
| 423 | case kCondLe: |
| 424 | ccode = kCondGe; |
| 425 | break; |
| 426 | case kCondGt: |
| 427 | ccode = kCondLt; |
| 428 | break; |
| 429 | case kCondLt: |
| 430 | case kCondGe: |
| 431 | break; |
| 432 | default: |
| 433 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 434 | } |
| 435 | OpCondBranch(ccode, taken); |
| 436 | } |
| 437 | |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 438 | void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
| 439 | int64_t val, ConditionCode ccode) { |
| 440 | int32_t val_lo = Low32Bits(val); |
| 441 | int32_t val_hi = High32Bits(val); |
| 442 | LIR* taken = &block_label_list_[bb->taken]; |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 443 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 444 | bool is_equality_test = ccode == kCondEq || ccode == kCondNe; |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 445 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 446 | if (cu_->target64) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 447 | if (is_equality_test && val == 0) { |
| 448 | // We can simplify of comparing for ==, != to 0. |
| 449 | NewLIR2(kX86Test64RR, rl_src1.reg.GetReg(), rl_src1.reg.GetReg()); |
| 450 | } else if (is_equality_test && val_hi == 0 && val_lo > 0) { |
| 451 | OpRegImm(kOpCmp, rl_src1.reg, val_lo); |
| 452 | } else { |
| 453 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 454 | LoadConstantWide(tmp, val); |
| 455 | OpRegReg(kOpCmp, rl_src1.reg, tmp); |
| 456 | FreeTemp(tmp); |
| 457 | } |
| 458 | OpCondBranch(ccode, taken); |
| 459 | return; |
| 460 | } |
| 461 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 462 | if (is_equality_test && val != 0) { |
| 463 | rl_src1 = ForceTempWide(rl_src1); |
| 464 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 465 | RegStorage low_reg = rl_src1.reg.GetLow(); |
| 466 | RegStorage high_reg = rl_src1.reg.GetHigh(); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 467 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 468 | if (is_equality_test) { |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 469 | // We can simplify of comparing for ==, != to 0. |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 470 | if (val == 0) { |
| 471 | if (IsTemp(low_reg)) { |
| 472 | OpRegReg(kOpOr, low_reg, high_reg); |
| 473 | // We have now changed it; ignore the old values. |
| 474 | Clobber(rl_src1.reg); |
| 475 | } else { |
| 476 | RegStorage t_reg = AllocTemp(); |
| 477 | OpRegRegReg(kOpOr, t_reg, low_reg, high_reg); |
| 478 | FreeTemp(t_reg); |
| 479 | } |
| 480 | OpCondBranch(ccode, taken); |
| 481 | return; |
| 482 | } |
| 483 | |
| 484 | // Need to compute the actual value for ==, !=. |
| 485 | OpRegImm(kOpSub, low_reg, val_lo); |
| 486 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 487 | OpRegReg(kOpOr, high_reg, low_reg); |
| 488 | Clobber(rl_src1.reg); |
| 489 | } else if (ccode == kCondLe || ccode == kCondGt) { |
| 490 | // Swap operands and condition code to prevent use of zero flag. |
| 491 | RegStorage tmp = AllocTypedTempWide(false, kCoreReg); |
| 492 | LoadConstantWide(tmp, val); |
| 493 | OpRegReg(kOpSub, tmp.GetLow(), low_reg); |
| 494 | OpRegReg(kOpSbc, tmp.GetHigh(), high_reg); |
| 495 | ccode = (ccode == kCondLe) ? kCondGe : kCondLt; |
| 496 | FreeTemp(tmp); |
| 497 | } else { |
| 498 | // We can use a compare for the low word to set CF. |
| 499 | OpRegImm(kOpCmp, low_reg, val_lo); |
| 500 | if (IsTemp(high_reg)) { |
| 501 | NewLIR2(kX86Sbb32RI, high_reg.GetReg(), val_hi); |
| 502 | // We have now changed it; ignore the old values. |
| 503 | Clobber(rl_src1.reg); |
| 504 | } else { |
| 505 | // mov temp_reg, high_reg; sbb temp_reg, high_constant |
| 506 | RegStorage t_reg = AllocTemp(); |
| 507 | OpRegCopy(t_reg, high_reg); |
| 508 | NewLIR2(kX86Sbb32RI, t_reg.GetReg(), val_hi); |
| 509 | FreeTemp(t_reg); |
| 510 | } |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 511 | } |
| 512 | |
Mark Mendell | 752e205 | 2014-05-01 10:19:04 -0400 | [diff] [blame] | 513 | OpCondBranch(ccode, taken); |
Mark Mendell | 412d4f8 | 2013-12-18 13:32:36 -0800 | [diff] [blame] | 514 | } |
| 515 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 516 | void X86Mir2Lir::CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long) { |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 517 | // It does not make sense to calculate magic and shift for zero divisor. |
| 518 | DCHECK_NE(divisor, 0); |
| 519 | |
| 520 | /* According to H.S.Warren's Hacker's Delight Chapter 10 and |
| 521 | * T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 522 | * The magic number M and shift S can be calculated in the following way: |
| 523 | * Let nc be the most positive value of numerator(n) such that nc = kd - 1, |
| 524 | * where divisor(d) >=2. |
| 525 | * Let nc be the most negative value of numerator(n) such that nc = kd + 1, |
| 526 | * where divisor(d) <= -2. |
| 527 | * Thus nc can be calculated like: |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 528 | * nc = exp + exp % d - 1, where d >= 2 and exp = 2^31 for int or 2^63 for long |
| 529 | * nc = -exp + (exp + 1) % d, where d >= 2 and exp = 2^31 for int or 2^63 for long |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 530 | * |
| 531 | * So the shift p is the smallest p satisfying |
| 532 | * 2^p > nc * (d - 2^p % d), where d >= 2 |
| 533 | * 2^p > nc * (d + 2^p % d), where d <= -2. |
| 534 | * |
| 535 | * the magic number M is calcuated by |
| 536 | * M = (2^p + d - 2^p % d) / d, where d >= 2 |
| 537 | * M = (2^p - d - 2^p % d) / d, where d <= -2. |
| 538 | * |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 539 | * Notice that p is always bigger than or equal to 32/64, so we just return 32-p/64-p as |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 540 | * the shift number S. |
| 541 | */ |
| 542 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 543 | int64_t p = (is_long) ? 63 : 31; |
| 544 | const uint64_t exp = (is_long) ? 0x8000000000000000ULL : 0x80000000U; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 545 | |
| 546 | // Initialize the computations. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 547 | uint64_t abs_d = (divisor >= 0) ? divisor : -divisor; |
| 548 | uint64_t tmp = exp + ((is_long) ? static_cast<uint64_t>(divisor) >> 63 : |
| 549 | static_cast<uint32_t>(divisor) >> 31); |
| 550 | uint64_t abs_nc = tmp - 1 - tmp % abs_d; |
| 551 | uint64_t quotient1 = exp / abs_nc; |
| 552 | uint64_t remainder1 = exp % abs_nc; |
| 553 | uint64_t quotient2 = exp / abs_d; |
| 554 | uint64_t remainder2 = exp % abs_d; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 555 | |
| 556 | /* |
| 557 | * To avoid handling both positive and negative divisor, Hacker's Delight |
| 558 | * introduces a method to handle these 2 cases together to avoid duplication. |
| 559 | */ |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 560 | uint64_t delta; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 561 | do { |
| 562 | p++; |
| 563 | quotient1 = 2 * quotient1; |
| 564 | remainder1 = 2 * remainder1; |
| 565 | if (remainder1 >= abs_nc) { |
| 566 | quotient1++; |
| 567 | remainder1 = remainder1 - abs_nc; |
| 568 | } |
| 569 | quotient2 = 2 * quotient2; |
| 570 | remainder2 = 2 * remainder2; |
| 571 | if (remainder2 >= abs_d) { |
| 572 | quotient2++; |
| 573 | remainder2 = remainder2 - abs_d; |
| 574 | } |
| 575 | delta = abs_d - remainder2; |
| 576 | } while (quotient1 < delta || (quotient1 == delta && remainder1 == 0)); |
| 577 | |
| 578 | magic = (divisor > 0) ? (quotient2 + 1) : (-quotient2 - 1); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 579 | |
| 580 | if (!is_long) { |
| 581 | magic = static_cast<int>(magic); |
| 582 | } |
| 583 | |
| 584 | shift = (is_long) ? p - 64 : p - 32; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 585 | } |
| 586 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 587 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 588 | LOG(FATAL) << "Unexpected use of GenDivRemLit for x86"; |
| 589 | return rl_dest; |
| 590 | } |
| 591 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 592 | RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, |
| 593 | int imm, bool is_div) { |
| 594 | // Use a multiply (and fixup) to perform an int div/rem by a constant. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 595 | RegLocation rl_result; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 596 | |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 597 | if (imm == 1) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 598 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 599 | if (is_div) { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 600 | // x / 1 == x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 601 | LoadValueDirectFixed(rl_src, rl_result.reg); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 602 | } else { |
| 603 | // x % 1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 604 | LoadConstantNoClobber(rl_result.reg, 0); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 605 | } |
| 606 | } else if (imm == -1) { // handle 0x80000000 / -1 special case. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 607 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 608 | if (is_div) { |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 609 | LoadValueDirectFixed(rl_src, rl_result.reg); |
| 610 | OpRegImm(kOpCmp, rl_result.reg, 0x80000000); |
| 611 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 612 | |
| 613 | // for x != MIN_INT, x / -1 == -x. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 614 | NewLIR1(kX86Neg32R, rl_result.reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 615 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 616 | // EAX already contains the right value (0x80000000), |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 617 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 618 | } else { |
| 619 | // x % -1 == 0. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 620 | LoadConstantNoClobber(rl_result.reg, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 621 | } |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 622 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 623 | // Division using shifting. |
| 624 | rl_src = LoadValue(rl_src, kCoreReg); |
| 625 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 626 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 627 | RegStorage rs_temp = AllocTypedTemp(false, kCoreReg); |
| 628 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 629 | } |
| 630 | NewLIR3(kX86Lea32RM, rl_result.reg.GetReg(), rl_src.reg.GetReg(), std::abs(imm) - 1); |
| 631 | NewLIR2(kX86Test32RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 632 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
| 633 | int shift_amount = LowestSetBit(imm); |
| 634 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 635 | if (imm < 0) { |
| 636 | OpReg(kOpNeg, rl_result.reg); |
| 637 | } |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 638 | } else { |
Alexei Zavjalov | 79aa423 | 2014-02-13 13:55:50 +0700 | [diff] [blame] | 639 | CHECK(imm <= -2 || imm >= 2); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 640 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 641 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 642 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 643 | int64_t magic; |
| 644 | int shift; |
| 645 | CalculateMagicAndShift((int64_t)imm, magic, shift, false /* is_long */); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 646 | |
| 647 | /* |
| 648 | * For imm >= 2, |
| 649 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 650 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 651 | * For imm <= -2, |
| 652 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 653 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 654 | * We implement this algorithm in the following way: |
| 655 | * 1. multiply magic number m and numerator n, get the higher 32bit result in EDX |
| 656 | * 2. if imm > 0 and magic < 0, add numerator to EDX |
| 657 | * if imm < 0 and magic > 0, sub numerator from EDX |
| 658 | * 3. if S !=0, SAR S bits for EDX |
| 659 | * 4. add 1 to EDX if EDX < 0 |
| 660 | * 5. Thus, EDX is the quotient |
| 661 | */ |
| 662 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 663 | FlushReg(rs_r0); |
| 664 | Clobber(rs_r0); |
| 665 | LockTemp(rs_r0); |
| 666 | FlushReg(rs_r2); |
| 667 | Clobber(rs_r2); |
| 668 | LockTemp(rs_r2); |
| 669 | |
| 670 | // Assume that the result will be in EDX. |
| 671 | rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r2, INVALID_SREG, INVALID_SREG}; |
| 672 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 673 | // Numerator into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 674 | RegStorage numerator_reg; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 675 | if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { |
| 676 | // We will need the value later. |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 677 | rl_src = LoadValue(rl_src, kCoreReg); |
| 678 | numerator_reg = rl_src.reg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 679 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 680 | } else { |
| 681 | // Only need this once. Just put it into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 682 | LoadValueDirectFixed(rl_src, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 683 | } |
| 684 | |
| 685 | // EDX = magic. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 686 | LoadConstantNoClobber(rs_r2, magic); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 687 | |
| 688 | // EDX:EAX = magic & dividend. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 689 | NewLIR1(kX86Imul32DaR, rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 690 | |
| 691 | if (imm > 0 && magic < 0) { |
| 692 | // Add numerator to EDX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 693 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 694 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 695 | } else if (imm < 0 && magic > 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 696 | DCHECK(numerator_reg.Valid()); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 697 | NewLIR2(kX86Sub32RR, rs_r2.GetReg(), numerator_reg.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 698 | } |
| 699 | |
| 700 | // Do we need the shift? |
| 701 | if (shift != 0) { |
| 702 | // Shift EDX by 'shift' bits. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 703 | NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 704 | } |
| 705 | |
| 706 | // Add 1 to EDX if EDX < 0. |
| 707 | |
| 708 | // Move EDX to EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 709 | OpRegCopy(rs_r0, rs_r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 710 | |
| 711 | // Move sign bit to bit 0, zeroing the rest. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 712 | NewLIR2(kX86Shr32RI, rs_r2.GetReg(), 31); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 713 | |
| 714 | // EDX = EDX + EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 715 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 716 | |
| 717 | // Quotient is in EDX. |
| 718 | if (!is_div) { |
| 719 | // We need to compute the remainder. |
| 720 | // Remainder is divisor - (quotient * imm). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 721 | DCHECK(numerator_reg.Valid()); |
| 722 | OpRegCopy(rs_r0, numerator_reg); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 723 | |
| 724 | // EAX = numerator * imm. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 725 | OpRegRegImm(kOpMul, rs_r2, rs_r2, imm); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 726 | |
| 727 | // EDX -= EAX. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 728 | NewLIR2(kX86Sub32RR, rs_r0.GetReg(), rs_r2.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 729 | |
| 730 | // For this case, return the result in EAX. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 731 | rl_result.reg.SetReg(r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 732 | } |
| 733 | } |
| 734 | |
| 735 | return rl_result; |
| 736 | } |
| 737 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 738 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, |
| 739 | bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 740 | LOG(FATAL) << "Unexpected use of GenDivRem for x86"; |
| 741 | return rl_dest; |
| 742 | } |
| 743 | |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 744 | RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, RegLocation rl_src1, |
| 745 | RegLocation rl_src2, bool is_div, bool check_zero) { |
| 746 | // We have to use fixed registers, so flush all the temps. |
| 747 | FlushAllRegs(); |
| 748 | LockCallTemps(); // Prepare for explicit register usage. |
| 749 | |
| 750 | // Load LHS into EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 751 | LoadValueDirectFixed(rl_src1, rs_r0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 752 | |
| 753 | // Load RHS into EBX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 754 | LoadValueDirectFixed(rl_src2, rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 755 | |
| 756 | // Copy LHS sign bit into EDX. |
| 757 | NewLIR0(kx86Cdq32Da); |
| 758 | |
| 759 | if (check_zero) { |
| 760 | // Handle division by zero case. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 761 | GenDivZeroCheck(rs_r1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | // Have to catch 0x80000000/-1 case, or we will get an exception! |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 765 | OpRegImm(kOpCmp, rs_r1, -1); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 766 | LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 767 | |
| 768 | // RHS is -1. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 769 | OpRegImm(kOpCmp, rs_r0, 0x80000000); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 770 | LIR * minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 771 | |
| 772 | // In 0x80000000/-1 case. |
| 773 | if (!is_div) { |
| 774 | // For DIV, EAX is already right. For REM, we need EDX 0. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 775 | LoadConstantNoClobber(rs_r2, 0); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 776 | } |
| 777 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 778 | |
| 779 | // Expected case. |
| 780 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 781 | minint_branch->target = minus_one_branch->target; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 782 | NewLIR1(kX86Idivmod32DaR, rs_r1.GetReg()); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 783 | done->target = NewLIR0(kPseudoTargetLabel); |
| 784 | |
| 785 | // Result is in EAX for div and EDX for rem. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 786 | RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 787 | if (!is_div) { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 788 | rl_result.reg.SetReg(r2); |
Mark Mendell | 2bf31e6 | 2014-01-23 12:13:40 -0800 | [diff] [blame] | 789 | } |
| 790 | return rl_result; |
| 791 | } |
| 792 | |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 793 | bool X86Mir2Lir::GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 794 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 795 | |
nikolay serdjuk | 4ab6f50 | 2014-08-08 09:55:06 +0700 | [diff] [blame] | 796 | if (is_long && !cu_->target64) { |
| 797 | /* |
| 798 | * We want to implement the following algorithm |
| 799 | * mov eax, low part of arg1 |
| 800 | * mov edx, high part of arg1 |
| 801 | * mov ebx, low part of arg2 |
| 802 | * mov ecx, high part of arg2 |
| 803 | * mov edi, eax |
| 804 | * sub edi, ebx |
| 805 | * mov edi, edx |
| 806 | * sbb edi, ecx |
| 807 | * is_min ? "cmovgel eax, ebx" : "cmovll eax, ebx" |
| 808 | * is_min ? "cmovgel edx, ecx" : "cmovll edx, ecx" |
| 809 | * |
| 810 | * The algorithm above needs 5 registers: a pair for the first operand |
| 811 | * (which later will be used as result), a pair for the second operand |
| 812 | * and a temp register (e.g. 'edi') for intermediate calculations. |
| 813 | * Ideally we have 6 GP caller-save registers in 32-bit mode. They are: |
| 814 | * 'eax', 'ebx', 'ecx', 'edx', 'esi' and 'edi'. So there should be |
| 815 | * always enough registers to operate on. Practically, there is a pair |
| 816 | * of registers 'edi' and 'esi' which holds promoted values and |
| 817 | * sometimes should be treated as 'callee save'. If one of the operands |
| 818 | * is in the promoted registers then we have enough register to |
| 819 | * operate on. Otherwise there is lack of resources and we have to |
| 820 | * save 'edi' before calculations and restore after. |
| 821 | */ |
| 822 | |
| 823 | RegLocation rl_src1 = info->args[0]; |
| 824 | RegLocation rl_src2 = info->args[2]; |
| 825 | RegLocation rl_dest = InlineTargetWide(info); |
| 826 | int res_vreg, src1_vreg, src2_vreg; |
| 827 | |
| 828 | /* |
| 829 | * If the result register is the same as the second element, then we |
| 830 | * need to be careful. The reason is that the first copy will |
| 831 | * inadvertently clobber the second element with the first one thus |
| 832 | * yielding the wrong result. Thus we do a swap in that case. |
| 833 | */ |
| 834 | res_vreg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); |
| 835 | src2_vreg = mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 836 | if (res_vreg == src2_vreg) { |
| 837 | std::swap(rl_src1, rl_src2); |
| 838 | } |
| 839 | |
| 840 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 841 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 842 | |
| 843 | // Pick the first integer as min/max. |
| 844 | OpRegCopyWide(rl_result.reg, rl_src1.reg); |
| 845 | |
| 846 | /* |
| 847 | * If the integers are both in the same register, then there is |
| 848 | * nothing else to do because they are equal and we have already |
| 849 | * moved one into the result. |
| 850 | */ |
| 851 | src1_vreg = mir_graph_->SRegToVReg(rl_src1.s_reg_low); |
| 852 | src2_vreg = mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 853 | if (src1_vreg == src2_vreg) { |
| 854 | StoreValueWide(rl_dest, rl_result); |
| 855 | return true; |
| 856 | } |
| 857 | |
| 858 | // Free registers to make some room for the second operand. |
| 859 | // But don't try to free ourselves or promoted registers. |
| 860 | if (res_vreg != src1_vreg && |
| 861 | IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
| 862 | FreeTemp(rl_src1.reg); |
| 863 | } |
| 864 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 865 | |
| 866 | // Do we have a free register for intermediate calculations? |
| 867 | RegStorage tmp = AllocTemp(false); |
| 868 | if (tmp == RegStorage::InvalidReg()) { |
| 869 | /* |
| 870 | * No, will use 'edi'. |
| 871 | * |
| 872 | * As mentioned above we have 4 temporary and 2 promotable |
| 873 | * caller-save registers. Therefore, we assume that a free |
| 874 | * register can be allocated only if 'esi' and 'edi' are |
| 875 | * already used as operands. If number of promotable registers |
| 876 | * increases from 2 to 4 then our assumption fails and operand |
| 877 | * data is corrupted. |
| 878 | * Let's DCHECK it. |
| 879 | */ |
| 880 | DCHECK(IsTemp(rl_src2.reg.GetLow()) && |
| 881 | IsTemp(rl_src2.reg.GetHigh()) && |
| 882 | IsTemp(rl_result.reg.GetLow()) && |
| 883 | IsTemp(rl_result.reg.GetHigh())); |
| 884 | tmp = rs_rDI; |
| 885 | NewLIR1(kX86Push32R, tmp.GetReg()); |
| 886 | } |
| 887 | |
| 888 | // Now we are ready to do calculations. |
| 889 | OpRegReg(kOpMov, tmp, rl_result.reg.GetLow()); |
| 890 | OpRegReg(kOpSub, tmp, rl_src2.reg.GetLow()); |
| 891 | OpRegReg(kOpMov, tmp, rl_result.reg.GetHigh()); |
| 892 | OpRegReg(kOpSbc, tmp, rl_src2.reg.GetHigh()); |
| 893 | |
| 894 | // Let's put pop 'edi' here to break a bit the dependency chain. |
| 895 | if (tmp == rs_rDI) { |
| 896 | NewLIR1(kX86Pop32R, tmp.GetReg()); |
| 897 | } |
| 898 | |
| 899 | // Conditionally move the other integer into the destination register. |
| 900 | ConditionCode cc = is_min ? kCondGe : kCondLt; |
| 901 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetLow(), rl_src2.reg.GetLow()); |
| 902 | OpCondRegReg(kOpCmov, cc, rl_result.reg.GetHigh(), rl_src2.reg.GetHigh()); |
| 903 | StoreValueWide(rl_dest, rl_result); |
| 904 | return true; |
Serban Constantinescu | 23abec9 | 2014-07-02 16:13:38 +0100 | [diff] [blame] | 905 | } |
| 906 | |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 907 | // Get the two arguments to the invoke and place them in GP registers. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 908 | RegLocation rl_src1 = info->args[0]; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 909 | RegLocation rl_src2 = (is_long) ? info->args[2] : info->args[1]; |
| 910 | rl_src1 = (is_long) ? LoadValueWide(rl_src1, kCoreReg) : LoadValue(rl_src1, kCoreReg); |
| 911 | rl_src2 = (is_long) ? LoadValueWide(rl_src2, kCoreReg) : LoadValue(rl_src2, kCoreReg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 912 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 913 | RegLocation rl_dest = (is_long) ? InlineTargetWide(info) : InlineTarget(info); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 914 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 915 | |
| 916 | /* |
| 917 | * If the result register is the same as the second element, then we need to be careful. |
| 918 | * The reason is that the first copy will inadvertently clobber the second element with |
| 919 | * the first one thus yielding the wrong result. Thus we do a swap in that case. |
| 920 | */ |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 921 | if (rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 922 | std::swap(rl_src1, rl_src2); |
| 923 | } |
| 924 | |
| 925 | // Pick the first integer as min/max. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 926 | OpRegCopy(rl_result.reg, rl_src1.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 927 | |
| 928 | // If the integers are both in the same register, then there is nothing else to do |
| 929 | // because they are equal and we have already moved one into the result. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 930 | if (rl_src1.reg.GetReg() != rl_src2.reg.GetReg()) { |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 931 | // It is possible we didn't pick correctly so do the actual comparison now. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 932 | OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 933 | |
| 934 | // Conditionally move the other integer into the destination register. |
| 935 | ConditionCode condition_code = is_min ? kCondGt : kCondLt; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 936 | OpCondRegReg(kOpCmov, condition_code, rl_result.reg, rl_src2.reg); |
Razvan A Lupusoru | bd288c2 | 2013-12-20 17:27:23 -0800 | [diff] [blame] | 937 | } |
| 938 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 939 | if (is_long) { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 940 | StoreValueWide(rl_dest, rl_result); |
| 941 | } else { |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 942 | StoreValue(rl_dest, rl_result); |
| 943 | } |
| 944 | return true; |
| 945 | } |
| 946 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 947 | bool X86Mir2Lir::GenInlinedPeek(CallInfo* info, OpSize size) { |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 948 | RegLocation rl_src_address = info->args[0]; // long address |
| 949 | RegLocation rl_address; |
| 950 | if (!cu_->target64) { |
| 951 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 952 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 953 | } else { |
| 954 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 955 | } |
| 956 | RegLocation rl_dest = size == k64 ? InlineTargetWide(info) : InlineTarget(info); |
| 957 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 958 | // Unaligned access is allowed on x86. |
| 959 | LoadBaseDisp(rl_address.reg, 0, rl_result.reg, size, kNotVolatile); |
| 960 | if (size == k64) { |
| 961 | StoreValueWide(rl_dest, rl_result); |
| 962 | } else { |
| 963 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 964 | StoreValue(rl_dest, rl_result); |
| 965 | } |
| 966 | return true; |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 967 | } |
| 968 | |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 969 | bool X86Mir2Lir::GenInlinedPoke(CallInfo* info, OpSize size) { |
Alexei Zavjalov | eb24bae | 2014-07-08 16:27:17 +0700 | [diff] [blame] | 970 | RegLocation rl_src_address = info->args[0]; // long address |
| 971 | RegLocation rl_address; |
| 972 | if (!cu_->target64) { |
| 973 | rl_src_address = NarrowRegLoc(rl_src_address); // ignore high half in info->args[0] |
| 974 | rl_address = LoadValue(rl_src_address, kCoreReg); |
| 975 | } else { |
| 976 | rl_address = LoadValueWide(rl_src_address, kCoreReg); |
| 977 | } |
| 978 | RegLocation rl_src_value = info->args[2]; // [size] value |
| 979 | RegLocation rl_value; |
| 980 | if (size == k64) { |
| 981 | // Unaligned access is allowed on x86. |
| 982 | rl_value = LoadValueWide(rl_src_value, kCoreReg); |
| 983 | } else { |
| 984 | DCHECK(size == kSignedByte || size == kSignedHalf || size == k32); |
| 985 | // In 32-bit mode the only EAX..EDX registers can be used with Mov8MR. |
| 986 | if (!cu_->target64 && size == kSignedByte) { |
| 987 | rl_src_value = UpdateLocTyped(rl_src_value, kCoreReg); |
| 988 | if (rl_src_value.location == kLocPhysReg && !IsByteRegister(rl_src_value.reg)) { |
| 989 | RegStorage temp = AllocateByteRegister(); |
| 990 | OpRegCopy(temp, rl_src_value.reg); |
| 991 | rl_value.reg = temp; |
| 992 | } else { |
| 993 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 994 | } |
| 995 | } else { |
| 996 | rl_value = LoadValue(rl_src_value, kCoreReg); |
| 997 | } |
| 998 | } |
| 999 | StoreBaseDisp(rl_address.reg, 0, rl_value.reg, size, kNotVolatile); |
| 1000 | return true; |
Vladimir Marko | e508a20 | 2013-11-04 15:24:22 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1003 | void X86Mir2Lir::OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset) { |
| 1004 | NewLIR5(kX86Lea32RA, r_base.GetReg(), reg1.GetReg(), reg2.GetReg(), scale, offset); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1005 | } |
| 1006 | |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 1007 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<4> offset, int val) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1008 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 1009 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
| 1010 | } |
| 1011 | |
| 1012 | void X86Mir2Lir::OpTlsCmp(ThreadOffset<8> offset, int val) { |
| 1013 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Ian Rogers | 468532e | 2013-08-05 10:56:33 -0700 | [diff] [blame] | 1014 | NewLIR2(kX86Cmp16TI8, offset.Int32Value(), val); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1015 | } |
| 1016 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1017 | static bool IsInReg(X86Mir2Lir *pMir2Lir, const RegLocation &rl, RegStorage reg) { |
| 1018 | return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1019 | } |
| 1020 | |
Vladimir Marko | 1c282e2 | 2013-11-21 14:49:47 +0000 | [diff] [blame] | 1021 | bool X86Mir2Lir::GenInlinedCas(CallInfo* info, bool is_long, bool is_object) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 1022 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1023 | // Unused - RegLocation rl_src_unsafe = info->args[0]; |
| 1024 | RegLocation rl_src_obj = info->args[1]; // Object - known non-null |
| 1025 | RegLocation rl_src_offset = info->args[2]; // long low |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1026 | if (!cu_->target64) { |
| 1027 | rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] |
| 1028 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1029 | RegLocation rl_src_expected = info->args[4]; // int, long or Object |
| 1030 | // If is_long, high half is in info->args[5] |
| 1031 | RegLocation rl_src_new_value = info->args[is_long ? 6 : 5]; // int, long or Object |
| 1032 | // If is_long, high half is in info->args[7] |
| 1033 | |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1034 | if (is_long && cu_->target64) { |
| 1035 | // RAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in RAX. |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1036 | FlushReg(rs_r0q); |
| 1037 | Clobber(rs_r0q); |
| 1038 | LockTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1039 | |
| 1040 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
| 1041 | RegLocation rl_new_value = LoadValueWide(rl_src_new_value, kCoreReg); |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1042 | RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1043 | LoadValueDirectWide(rl_src_expected, rs_r0q); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1044 | NewLIR5(kX86LockCmpxchg64AR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1045 | rl_new_value.reg.GetReg()); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1046 | |
| 1047 | // After a store we need to insert barrier in case of potential load. Since the |
| 1048 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated. |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1049 | GenMemBarrier(kAnyAny); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1050 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1051 | FreeTemp(rs_r0q); |
nikolay serdjuk | c5e4ce1 | 2014-06-10 17:07:10 +0700 | [diff] [blame] | 1052 | } else if (is_long) { |
Yevgeny Rouban | d3a2dfa | 2014-03-18 15:55:16 +0700 | [diff] [blame] | 1053 | // TODO: avoid unnecessary loads of SI and DI when the values are in registers. |
| 1054 | // TODO: CFI support. |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1055 | FlushAllRegs(); |
| 1056 | LockCallTemps(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1057 | RegStorage r_tmp1 = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 1058 | RegStorage r_tmp2 = RegStorage::MakeRegPair(rs_rBX, rs_rCX); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1059 | LoadValueDirectWideFixed(rl_src_expected, r_tmp1); |
| 1060 | LoadValueDirectWideFixed(rl_src_new_value, r_tmp2); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 1061 | // FIXME: needs 64-bit update. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1062 | const bool obj_in_di = IsInReg(this, rl_src_obj, rs_rDI); |
| 1063 | const bool obj_in_si = IsInReg(this, rl_src_obj, rs_rSI); |
| 1064 | DCHECK(!obj_in_si || !obj_in_di); |
| 1065 | const bool off_in_di = IsInReg(this, rl_src_offset, rs_rDI); |
| 1066 | const bool off_in_si = IsInReg(this, rl_src_offset, rs_rSI); |
| 1067 | DCHECK(!off_in_si || !off_in_di); |
| 1068 | // If obj/offset is in a reg, use that reg. Otherwise, use the empty reg. |
| 1069 | RegStorage rs_obj = obj_in_di ? rs_rDI : obj_in_si ? rs_rSI : !off_in_di ? rs_rDI : rs_rSI; |
| 1070 | RegStorage rs_off = off_in_si ? rs_rSI : off_in_di ? rs_rDI : !obj_in_si ? rs_rSI : rs_rDI; |
| 1071 | bool push_di = (!obj_in_di && !off_in_di) && (rs_obj == rs_rDI || rs_off == rs_rDI); |
| 1072 | bool push_si = (!obj_in_si && !off_in_si) && (rs_obj == rs_rSI || rs_off == rs_rSI); |
| 1073 | if (push_di) { |
| 1074 | NewLIR1(kX86Push32R, rs_rDI.GetReg()); |
| 1075 | MarkTemp(rs_rDI); |
| 1076 | LockTemp(rs_rDI); |
| 1077 | } |
| 1078 | if (push_si) { |
| 1079 | NewLIR1(kX86Push32R, rs_rSI.GetReg()); |
| 1080 | MarkTemp(rs_rSI); |
| 1081 | LockTemp(rs_rSI); |
| 1082 | } |
| 1083 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1084 | const size_t push_offset = (push_si ? 4u : 0u) + (push_di ? 4u : 0u); |
| 1085 | if (!obj_in_si && !obj_in_di) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1086 | LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_obj.s_reg_low) + push_offset, rs_obj); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1087 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1088 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1089 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1090 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1091 | } |
| 1092 | if (!off_in_si && !off_in_di) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1093 | LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1094 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1095 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1096 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - push_offset / 4u; |
| 1097 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
| 1098 | } |
| 1099 | NewLIR4(kX86LockCmpxchg64A, rs_obj.GetReg(), rs_off.GetReg(), 0, 0); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1100 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1101 | // After a store we need to insert barrier to prevent reordering with either |
| 1102 | // earlier or later memory accesses. Since |
| 1103 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1104 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1105 | GenMemBarrier(kAnyAny); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1106 | |
| 1107 | if (push_si) { |
| 1108 | FreeTemp(rs_rSI); |
| 1109 | UnmarkTemp(rs_rSI); |
| 1110 | NewLIR1(kX86Pop32R, rs_rSI.GetReg()); |
| 1111 | } |
| 1112 | if (push_di) { |
| 1113 | FreeTemp(rs_rDI); |
| 1114 | UnmarkTemp(rs_rDI); |
| 1115 | NewLIR1(kX86Pop32R, rs_rDI.GetReg()); |
| 1116 | } |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 1117 | FreeCallTemps(); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1118 | } else { |
| 1119 | // EAX must hold expected for CMPXCHG. Neither rl_new_value, nor r_ptr may be in EAX. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1120 | FlushReg(rs_r0); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1121 | Clobber(rs_r0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1122 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1123 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1124 | RegLocation rl_object = LoadValue(rl_src_obj, kRefReg); |
| 1125 | RegLocation rl_new_value = LoadValue(rl_src_new_value); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1126 | |
| 1127 | if (is_object && !mir_graph_->IsConstantNullRef(rl_new_value)) { |
| 1128 | // Mark card for object assuming new value is stored. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1129 | FreeTemp(rs_r0); // Temporarily release EAX for MarkGCCard(). |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1130 | MarkGCCard(rl_new_value.reg, rl_object.reg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1131 | LockTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1132 | } |
| 1133 | |
Chao-ying Fu | 021b60f | 2014-07-09 11:32:31 -0700 | [diff] [blame] | 1134 | RegLocation rl_offset; |
| 1135 | if (cu_->target64) { |
| 1136 | rl_offset = LoadValueWide(rl_src_offset, kCoreReg); |
| 1137 | } else { |
| 1138 | rl_offset = LoadValue(rl_src_offset, kCoreReg); |
| 1139 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1140 | LoadValueDirect(rl_src_expected, rs_r0); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1141 | NewLIR5(kX86LockCmpxchgAR, rl_object.reg.GetReg(), rl_offset.reg.GetReg(), 0, 0, |
| 1142 | rl_new_value.reg.GetReg()); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1143 | |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 1144 | // After a store we need to insert barrier to prevent reordering with either |
| 1145 | // earlier or later memory accesses. Since |
| 1146 | // locked cmpxchg has full barrier semantics, only a scheduling barrier will be generated, |
| 1147 | // and it will be associated with the cmpxchg instruction, preventing both. |
| 1148 | GenMemBarrier(kAnyAny); |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 1149 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1150 | FreeTemp(rs_r0); |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1151 | } |
| 1152 | |
| 1153 | // Convert ZF to boolean |
| 1154 | RegLocation rl_dest = InlineTarget(info); // boolean place for result |
| 1155 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1156 | RegStorage result_reg = rl_result.reg; |
| 1157 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1158 | // For 32-bit, SETcc only works with EAX..EDX. |
| 1159 | if (!IsByteRegister(result_reg)) { |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1160 | result_reg = AllocateByteRegister(); |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 1161 | } |
| 1162 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondZ); |
| 1163 | NewLIR2(kX86Movzx8RR, rl_result.reg.GetReg(), result_reg.GetReg()); |
| 1164 | if (IsTemp(result_reg)) { |
| 1165 | FreeTemp(result_reg); |
| 1166 | } |
Vladimir Marko | c29bb61 | 2013-11-27 16:47:25 +0000 | [diff] [blame] | 1167 | StoreValue(rl_dest, rl_result); |
| 1168 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1169 | } |
| 1170 | |
Yixin Shou | 8c914c0 | 2014-07-28 14:17:09 -0400 | [diff] [blame] | 1171 | void X86Mir2Lir::SwapBits(RegStorage result_reg, int shift, int32_t value) { |
| 1172 | RegStorage r_temp = AllocTemp(); |
| 1173 | OpRegCopy(r_temp, result_reg); |
| 1174 | OpRegImm(kOpLsr, result_reg, shift); |
| 1175 | OpRegImm(kOpAnd, r_temp, value); |
| 1176 | OpRegImm(kOpAnd, result_reg, value); |
| 1177 | OpRegImm(kOpLsl, r_temp, shift); |
| 1178 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1179 | FreeTemp(r_temp); |
| 1180 | } |
| 1181 | |
| 1182 | void X86Mir2Lir::SwapBits64(RegStorage result_reg, int shift, int64_t value) { |
| 1183 | RegStorage r_temp = AllocTempWide(); |
| 1184 | OpRegCopy(r_temp, result_reg); |
| 1185 | OpRegImm(kOpLsr, result_reg, shift); |
| 1186 | RegStorage r_value = AllocTempWide(); |
| 1187 | LoadConstantWide(r_value, value); |
| 1188 | OpRegReg(kOpAnd, r_temp, r_value); |
| 1189 | OpRegReg(kOpAnd, result_reg, r_value); |
| 1190 | OpRegImm(kOpLsl, r_temp, shift); |
| 1191 | OpRegReg(kOpOr, result_reg, r_temp); |
| 1192 | FreeTemp(r_temp); |
| 1193 | FreeTemp(r_value); |
| 1194 | } |
| 1195 | |
| 1196 | bool X86Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) { |
| 1197 | RegLocation rl_src_i = info->args[0]; |
| 1198 | RegLocation rl_i = (size == k64) ? LoadValueWide(rl_src_i, kCoreReg) |
| 1199 | : LoadValue(rl_src_i, kCoreReg); |
| 1200 | RegLocation rl_dest = (size == k64) ? InlineTargetWide(info) : InlineTarget(info); |
| 1201 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1202 | if (size == k64) { |
| 1203 | if (cu_->instruction_set == kX86_64) { |
| 1204 | /* Use one bswap instruction to reverse byte order first and then use 3 rounds of |
| 1205 | swapping bits to reverse bits in a long number x. Using bswap to save instructions |
| 1206 | compared to generic luni implementation which has 5 rounds of swapping bits. |
| 1207 | x = bswap x |
| 1208 | x = (x & 0x5555555555555555) << 1 | (x >> 1) & 0x5555555555555555; |
| 1209 | x = (x & 0x3333333333333333) << 2 | (x >> 2) & 0x3333333333333333; |
| 1210 | x = (x & 0x0F0F0F0F0F0F0F0F) << 4 | (x >> 4) & 0x0F0F0F0F0F0F0F0F; |
| 1211 | */ |
| 1212 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1213 | SwapBits64(rl_result.reg, 1, 0x5555555555555555); |
| 1214 | SwapBits64(rl_result.reg, 2, 0x3333333333333333); |
| 1215 | SwapBits64(rl_result.reg, 4, 0x0f0f0f0f0f0f0f0f); |
| 1216 | StoreValueWide(rl_dest, rl_result); |
| 1217 | return true; |
| 1218 | } |
| 1219 | RegStorage r_i_low = rl_i.reg.GetLow(); |
| 1220 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1221 | // First REV shall clobber rl_result.reg.GetLowReg(), save the value in a temp for the second |
| 1222 | // REV. |
| 1223 | r_i_low = AllocTemp(); |
| 1224 | OpRegCopy(r_i_low, rl_i.reg); |
| 1225 | } |
| 1226 | OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh()); |
| 1227 | OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low); |
| 1228 | if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { |
| 1229 | FreeTemp(r_i_low); |
| 1230 | } |
| 1231 | SwapBits(rl_result.reg.GetLow(), 1, 0x55555555); |
| 1232 | SwapBits(rl_result.reg.GetLow(), 2, 0x33333333); |
| 1233 | SwapBits(rl_result.reg.GetLow(), 4, 0x0f0f0f0f); |
| 1234 | SwapBits(rl_result.reg.GetHigh(), 1, 0x55555555); |
| 1235 | SwapBits(rl_result.reg.GetHigh(), 2, 0x33333333); |
| 1236 | SwapBits(rl_result.reg.GetHigh(), 4, 0x0f0f0f0f); |
| 1237 | StoreValueWide(rl_dest, rl_result); |
| 1238 | } else { |
| 1239 | OpRegReg(kOpRev, rl_result.reg, rl_i.reg); |
| 1240 | SwapBits(rl_result.reg, 1, 0x55555555); |
| 1241 | SwapBits(rl_result.reg, 2, 0x33333333); |
| 1242 | SwapBits(rl_result.reg, 4, 0x0f0f0f0f); |
| 1243 | StoreValue(rl_dest, rl_result); |
| 1244 | } |
| 1245 | return true; |
| 1246 | } |
| 1247 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1248 | LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1249 | CHECK(base_of_code_ != nullptr); |
| 1250 | |
| 1251 | // Address the start of the method |
| 1252 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 1253 | if (rl_method.wide) { |
| 1254 | LoadValueDirectWideFixed(rl_method, reg); |
| 1255 | } else { |
| 1256 | LoadValueDirectFixed(rl_method, reg); |
| 1257 | } |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1258 | store_method_addr_used_ = true; |
| 1259 | |
| 1260 | // Load the proper value from the literal area. |
| 1261 | // We don't know the proper offset for the value, so pick one that will force |
| 1262 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 1263 | // value. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1264 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1265 | LIR *res = RawLIR(current_dalvik_offset_, kX86Mov32RM, reg.GetReg(), reg.GetReg(), 256, |
| 1266 | 0, 0, target); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1267 | res->target = target; |
| 1268 | res->flags.fixup = kFixupLoad; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1269 | store_method_addr_used_ = true; |
| 1270 | return res; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1271 | } |
| 1272 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1273 | LIR* X86Mir2Lir::OpVldm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1274 | LOG(FATAL) << "Unexpected use of OpVldm for x86"; |
| 1275 | return NULL; |
| 1276 | } |
| 1277 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1278 | LIR* X86Mir2Lir::OpVstm(RegStorage r_base, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1279 | LOG(FATAL) << "Unexpected use of OpVstm for x86"; |
| 1280 | return NULL; |
| 1281 | } |
| 1282 | |
| 1283 | void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 1284 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1285 | int first_bit, int second_bit) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1286 | RegStorage t_reg = AllocTemp(); |
| 1287 | OpRegRegImm(kOpLsl, t_reg, rl_src.reg, second_bit - first_bit); |
| 1288 | OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, t_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1289 | FreeTemp(t_reg); |
| 1290 | if (first_bit != 0) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1291 | OpRegRegImm(kOpLsl, rl_result.reg, rl_result.reg, first_bit); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1292 | } |
| 1293 | } |
| 1294 | |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1295 | void X86Mir2Lir::GenDivZeroCheckWide(RegStorage reg) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1296 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1297 | DCHECK(reg.Is64Bit()); |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1298 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1299 | NewLIR2(kX86Cmp64RI8, reg.GetReg(), 0); |
| 1300 | } else { |
| 1301 | DCHECK(reg.IsPair()); |
| 1302 | |
| 1303 | // We are not supposed to clobber the incoming storage, so allocate a temporary. |
| 1304 | RegStorage t_reg = AllocTemp(); |
| 1305 | // Doing an OR is a quick way to check if both registers are zero. This will set the flags. |
| 1306 | OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh()); |
| 1307 | // The temp is no longer needed so free it at this time. |
| 1308 | FreeTemp(t_reg); |
| 1309 | } |
Razvan A Lupusoru | 090dd44 | 2013-12-20 14:35:03 -0800 | [diff] [blame] | 1310 | |
| 1311 | // In case of zero, throw ArithmeticException. |
Mingyao Yang | e643a17 | 2014-04-08 11:02:52 -0700 | [diff] [blame] | 1312 | GenDivZeroCheck(kCondEq); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1313 | } |
| 1314 | |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1315 | void X86Mir2Lir::GenArrayBoundsCheck(RegStorage index, |
| 1316 | RegStorage array_base, |
| 1317 | int len_offset) { |
| 1318 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1319 | public: |
| 1320 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 1321 | RegStorage index, RegStorage array_base, int32_t len_offset) |
| 1322 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 1323 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 1324 | } |
| 1325 | |
| 1326 | void Compile() OVERRIDE { |
| 1327 | m2l_->ResetRegPool(); |
| 1328 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1329 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1330 | |
| 1331 | RegStorage new_index = index_; |
| 1332 | // Move index out of kArg1, either directly to kArg0, or to kArg2. |
Serguei Katkov | 4c7cc15 | 2014-06-24 00:50:02 +0700 | [diff] [blame] | 1333 | // TODO: clean-up to check not a number but with type |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1334 | if (index_ == m2l_->TargetReg(kArg1, kNotWide)) { |
| 1335 | if (array_base_ == m2l_->TargetReg(kArg0, kRef)) { |
| 1336 | m2l_->OpRegCopy(m2l_->TargetReg(kArg2, kNotWide), index_); |
| 1337 | new_index = m2l_->TargetReg(kArg2, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1338 | } else { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1339 | m2l_->OpRegCopy(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1340 | new_index = m2l_->TargetReg(kArg0, kNotWide); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1341 | } |
| 1342 | } |
| 1343 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1344 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1345 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1346 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, new_index, |
| 1347 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1348 | } |
| 1349 | |
| 1350 | private: |
| 1351 | const RegStorage index_; |
| 1352 | const RegStorage array_base_; |
| 1353 | const int32_t len_offset_; |
| 1354 | }; |
| 1355 | |
| 1356 | OpRegMem(kOpCmp, index, array_base, len_offset); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1357 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1358 | LIR* branch = OpCondBranch(kCondUge, nullptr); |
| 1359 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1360 | index, array_base, len_offset)); |
| 1361 | } |
| 1362 | |
| 1363 | void X86Mir2Lir::GenArrayBoundsCheck(int32_t index, |
| 1364 | RegStorage array_base, |
| 1365 | int32_t len_offset) { |
| 1366 | class ArrayBoundsCheckSlowPath : public Mir2Lir::LIRSlowPath { |
| 1367 | public: |
| 1368 | ArrayBoundsCheckSlowPath(Mir2Lir* m2l, LIR* branch, |
| 1369 | int32_t index, RegStorage array_base, int32_t len_offset) |
| 1370 | : LIRSlowPath(m2l, m2l->GetCurrentDexPc(), branch), |
| 1371 | index_(index), array_base_(array_base), len_offset_(len_offset) { |
| 1372 | } |
| 1373 | |
| 1374 | void Compile() OVERRIDE { |
| 1375 | m2l_->ResetRegPool(); |
| 1376 | m2l_->ResetDefTracking(); |
Mingyao Yang | 6ffcfa0 | 2014-04-25 11:06:00 -0700 | [diff] [blame] | 1377 | GenerateTargetLabel(kPseudoThrowTarget); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1378 | |
| 1379 | // Load array length to kArg1. |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 1380 | X86Mir2Lir* x86_m2l = static_cast<X86Mir2Lir*>(m2l_); |
| 1381 | x86_m2l->OpRegMem(kOpMov, m2l_->TargetReg(kArg1, kNotWide), array_base_, len_offset_); |
| 1382 | x86_m2l->LoadConstant(m2l_->TargetReg(kArg0, kNotWide), index_); |
| 1383 | x86_m2l->CallRuntimeHelperRegReg(kQuickThrowArrayBounds, m2l_->TargetReg(kArg0, kNotWide), |
| 1384 | m2l_->TargetReg(kArg1, kNotWide), true); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1385 | } |
| 1386 | |
| 1387 | private: |
| 1388 | const int32_t index_; |
| 1389 | const RegStorage array_base_; |
| 1390 | const int32_t len_offset_; |
| 1391 | }; |
| 1392 | |
| 1393 | NewLIR3(IS_SIMM8(index) ? kX86Cmp32MI8 : kX86Cmp32MI, array_base.GetReg(), len_offset, index); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1394 | MarkPossibleNullPointerException(0); |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 1395 | LIR* branch = OpCondBranch(kCondLs, nullptr); |
| 1396 | AddSlowPath(new (arena_) ArrayBoundsCheckSlowPath(this, branch, |
| 1397 | index, array_base, len_offset)); |
| 1398 | } |
| 1399 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1400 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1401 | LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { |
buzbee | 33ae558 | 2014-06-12 14:56:32 -0700 | [diff] [blame] | 1402 | if (cu_->target64) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 1403 | OpTlsCmp(Thread::ThreadFlagsOffset<8>(), 0); |
| 1404 | } else { |
| 1405 | OpTlsCmp(Thread::ThreadFlagsOffset<4>(), 0); |
| 1406 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1407 | return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target); |
| 1408 | } |
| 1409 | |
| 1410 | // Decrement register and branch on condition |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1411 | LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1412 | OpRegImm(kOpSub, reg, 1); |
Yixin Shou | a0dac3e | 2014-01-23 05:01:22 -0800 | [diff] [blame] | 1413 | return OpCondBranch(c_code, target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1414 | } |
| 1415 | |
buzbee | 11b63d1 | 2013-08-27 07:34:17 -0700 | [diff] [blame] | 1416 | bool X86Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1417 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1418 | LOG(FATAL) << "Unexpected use of smallLiteralDive in x86"; |
| 1419 | return false; |
| 1420 | } |
| 1421 | |
Ian Rogers | e2143c0 | 2014-03-28 08:47:16 -0700 | [diff] [blame] | 1422 | bool X86Mir2Lir::EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { |
| 1423 | LOG(FATAL) << "Unexpected use of easyMultiply in x86"; |
| 1424 | return false; |
| 1425 | } |
| 1426 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1427 | LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1428 | LOG(FATAL) << "Unexpected use of OpIT in x86"; |
| 1429 | return NULL; |
| 1430 | } |
| 1431 | |
Dave Allison | 3da67a5 | 2014-04-02 17:03:45 -0700 | [diff] [blame] | 1432 | void X86Mir2Lir::OpEndIT(LIR* it) { |
| 1433 | LOG(FATAL) << "Unexpected use of OpEndIT in x86"; |
| 1434 | } |
| 1435 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1436 | void X86Mir2Lir::GenImulRegImm(RegStorage dest, RegStorage src, int val) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1437 | switch (val) { |
| 1438 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1439 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1440 | break; |
| 1441 | case 1: |
| 1442 | OpRegCopy(dest, src); |
| 1443 | break; |
| 1444 | default: |
| 1445 | OpRegRegImm(kOpMul, dest, src, val); |
| 1446 | break; |
| 1447 | } |
| 1448 | } |
| 1449 | |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1450 | void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1451 | // All memory accesses below reference dalvik regs. |
| 1452 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1453 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1454 | LIR *m; |
| 1455 | switch (val) { |
| 1456 | case 0: |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1457 | NewLIR2(kX86Xor32RR, dest.GetReg(), dest.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1458 | break; |
| 1459 | case 1: |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1460 | LoadBaseDisp(rs_rX86_SP, displacement, dest, k32, kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1461 | break; |
| 1462 | default: |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1463 | m = NewLIR4(IS_SIMM8(val) ? kX86Imul32RMI8 : kX86Imul32RMI, dest.GetReg(), |
| 1464 | rs_rX86_SP.GetReg(), displacement, val); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1465 | AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); |
| 1466 | break; |
| 1467 | } |
| 1468 | } |
| 1469 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1470 | void X86Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, |
| 1471 | RegLocation rl_src2) { |
| 1472 | if (!cu_->target64) { |
| 1473 | // Some x86 32b ops are fallback. |
| 1474 | switch (opcode) { |
| 1475 | case Instruction::NOT_LONG: |
| 1476 | case Instruction::DIV_LONG: |
| 1477 | case Instruction::DIV_LONG_2ADDR: |
| 1478 | case Instruction::REM_LONG: |
| 1479 | case Instruction::REM_LONG_2ADDR: |
| 1480 | Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1481 | return; |
| 1482 | |
| 1483 | default: |
| 1484 | // Everything else we can handle. |
| 1485 | break; |
| 1486 | } |
| 1487 | } |
| 1488 | |
| 1489 | switch (opcode) { |
| 1490 | case Instruction::NOT_LONG: |
| 1491 | GenNotLong(rl_dest, rl_src2); |
| 1492 | return; |
| 1493 | |
| 1494 | case Instruction::ADD_LONG: |
| 1495 | case Instruction::ADD_LONG_2ADDR: |
| 1496 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1497 | return; |
| 1498 | |
| 1499 | case Instruction::SUB_LONG: |
| 1500 | case Instruction::SUB_LONG_2ADDR: |
| 1501 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, false); |
| 1502 | return; |
| 1503 | |
| 1504 | case Instruction::MUL_LONG: |
| 1505 | case Instruction::MUL_LONG_2ADDR: |
| 1506 | GenMulLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1507 | return; |
| 1508 | |
| 1509 | case Instruction::DIV_LONG: |
| 1510 | case Instruction::DIV_LONG_2ADDR: |
| 1511 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ true); |
| 1512 | return; |
| 1513 | |
| 1514 | case Instruction::REM_LONG: |
| 1515 | case Instruction::REM_LONG_2ADDR: |
| 1516 | GenDivRemLong(opcode, rl_dest, rl_src1, rl_src2, /*is_div*/ false); |
| 1517 | return; |
| 1518 | |
| 1519 | case Instruction::AND_LONG_2ADDR: |
| 1520 | case Instruction::AND_LONG: |
| 1521 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1522 | return; |
| 1523 | |
| 1524 | case Instruction::OR_LONG: |
| 1525 | case Instruction::OR_LONG_2ADDR: |
| 1526 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1527 | return; |
| 1528 | |
| 1529 | case Instruction::XOR_LONG: |
| 1530 | case Instruction::XOR_LONG_2ADDR: |
| 1531 | GenLongArith(rl_dest, rl_src1, rl_src2, opcode, true); |
| 1532 | return; |
| 1533 | |
| 1534 | case Instruction::NEG_LONG: |
| 1535 | GenNegLong(rl_dest, rl_src2); |
| 1536 | return; |
| 1537 | |
| 1538 | default: |
| 1539 | LOG(FATAL) << "Invalid long arith op"; |
| 1540 | return; |
| 1541 | } |
| 1542 | } |
| 1543 | |
| 1544 | bool X86Mir2Lir::GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1545 | // All memory accesses below reference dalvik regs. |
| 1546 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1547 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1548 | if (val == 0) { |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1549 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1550 | if (cu_->target64) { |
| 1551 | OpRegReg(kOpXor, rl_result.reg, rl_result.reg); |
Alexei Zavjalov | d8191d0 | 2014-06-11 18:26:40 +0700 | [diff] [blame] | 1552 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1553 | OpRegReg(kOpXor, rl_result.reg.GetLow(), rl_result.reg.GetLow()); |
| 1554 | OpRegReg(kOpXor, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1555 | } |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1556 | StoreValueWide(rl_dest, rl_result); |
| 1557 | return true; |
| 1558 | } else if (val == 1) { |
| 1559 | StoreValueWide(rl_dest, rl_src1); |
| 1560 | return true; |
| 1561 | } else if (val == 2) { |
| 1562 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src1, rl_src1); |
| 1563 | return true; |
| 1564 | } else if (IsPowerOfTwo(val)) { |
| 1565 | int shift_amount = LowestSetBit(val); |
| 1566 | if (!BadOverlap(rl_src1, rl_dest)) { |
| 1567 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1568 | RegLocation rl_result = GenShiftImmOpLong(Instruction::SHL_LONG, rl_dest, rl_src1, |
| 1569 | shift_amount); |
| 1570 | StoreValueWide(rl_dest, rl_result); |
| 1571 | return true; |
| 1572 | } |
| 1573 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1574 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1575 | // Okay, on 32b just bite the bullet and do it, still better than the general case. |
| 1576 | if (!cu_->target64) { |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1577 | int32_t val_lo = Low32Bits(val); |
| 1578 | int32_t val_hi = High32Bits(val); |
| 1579 | FlushAllRegs(); |
| 1580 | LockCallTemps(); // Prepare for explicit register usage. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1581 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1582 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1583 | int displacement = SRegOffset(rl_src1.s_reg_low); |
| 1584 | |
| 1585 | // ECX <- 1H * 2L |
| 1586 | // EAX <- 1L * 2H |
| 1587 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1588 | GenImulRegImm(rs_r1, rl_src1.reg.GetHigh(), val_lo); |
| 1589 | GenImulRegImm(rs_r0, rl_src1.reg.GetLow(), val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1590 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1591 | GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); |
| 1592 | GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1593 | } |
| 1594 | |
| 1595 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1596 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1597 | |
| 1598 | // EAX <- 2L |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1599 | LoadConstantNoClobber(rs_r0, val_lo); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1600 | |
| 1601 | // EDX:EAX <- 2L * 1L (double precision) |
| 1602 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1603 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1604 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1605 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1606 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1607 | true /* is_load */, true /* is_64bit */); |
| 1608 | } |
| 1609 | |
| 1610 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1611 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1612 | |
| 1613 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1614 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
| 1615 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1616 | StoreValueWide(rl_dest, rl_result); |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1617 | return true; |
| 1618 | } |
| 1619 | return false; |
| 1620 | } |
| 1621 | |
| 1622 | void X86Mir2Lir::GenMulLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
| 1623 | RegLocation rl_src2) { |
| 1624 | if (rl_src1.is_const) { |
| 1625 | std::swap(rl_src1, rl_src2); |
| 1626 | } |
| 1627 | |
| 1628 | if (rl_src2.is_const) { |
| 1629 | if (GenMulLongConst(rl_dest, rl_src1, mir_graph_->ConstantValueWide(rl_src2))) { |
| 1630 | return; |
| 1631 | } |
| 1632 | } |
| 1633 | |
| 1634 | // All memory accesses below reference dalvik regs. |
| 1635 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1636 | |
| 1637 | if (cu_->target64) { |
| 1638 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1639 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1640 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1641 | if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1642 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1643 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
| 1644 | } else if (rl_result.reg.GetReg() != rl_src1.reg.GetReg() && |
| 1645 | rl_result.reg.GetReg() == rl_src2.reg.GetReg()) { |
| 1646 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); |
| 1647 | } else if (rl_result.reg.GetReg() == rl_src1.reg.GetReg() && |
| 1648 | rl_result.reg.GetReg() != rl_src2.reg.GetReg()) { |
| 1649 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1650 | } else { |
| 1651 | OpRegCopy(rl_result.reg, rl_src1.reg); |
| 1652 | NewLIR2(kX86Imul64RR, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); |
| 1653 | } |
| 1654 | StoreValueWide(rl_dest, rl_result); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1655 | return; |
| 1656 | } |
| 1657 | |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 1658 | // Not multiplying by a constant. Do it the hard way |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1659 | // Check for V*V. We can eliminate a multiply in that case, as 2L*1H == 2H*1L. |
| 1660 | bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == |
| 1661 | mir_graph_->SRegToVReg(rl_src2.s_reg_low); |
| 1662 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1663 | FlushAllRegs(); |
| 1664 | LockCallTemps(); // Prepare for explicit register usage. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1665 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
| 1666 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1667 | |
| 1668 | // At this point, the VRs are in their home locations. |
| 1669 | bool src1_in_reg = rl_src1.location == kLocPhysReg; |
| 1670 | bool src2_in_reg = rl_src2.location == kLocPhysReg; |
| 1671 | |
| 1672 | // ECX <- 1H |
| 1673 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1674 | NewLIR2(kX86Mov32RR, rs_r1.GetReg(), rl_src1.reg.GetHighReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1675 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1676 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32, |
| 1677 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1678 | } |
| 1679 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1680 | if (is_square) { |
| 1681 | // Take advantage of the fact that the values are the same. |
| 1682 | // ECX <- ECX * 2L (1H * 2L) |
| 1683 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1684 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1685 | } else { |
| 1686 | int displacement = SRegOffset(rl_src2.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1687 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
| 1688 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1689 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1690 | true /* is_load */, true /* is_64bit */); |
| 1691 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1692 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1693 | // ECX <- 2*ECX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1694 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1695 | } else { |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1696 | // EAX <- 2H |
| 1697 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1698 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetHighReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1699 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1700 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + HIWORD_OFFSET, rs_r0, k32, |
| 1701 | kNotVolatile); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1702 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1703 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1704 | // EAX <- EAX * 1L (2H * 1L) |
| 1705 | if (src1_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1706 | NewLIR2(kX86Imul32RR, rs_r0.GetReg(), rl_src1.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1707 | } else { |
| 1708 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1709 | LIR *m = NewLIR3(kX86Imul32RM, rs_r0.GetReg(), rs_rX86_SP.GetReg(), |
| 1710 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1711 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1712 | true /* is_load */, true /* is_64bit */); |
| 1713 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1714 | |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1715 | // ECX <- ECX * 2L (1H * 2L) |
| 1716 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1717 | NewLIR2(kX86Imul32RR, rs_r1.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1718 | } else { |
| 1719 | int displacement = SRegOffset(rl_src2.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1720 | LIR *m = NewLIR3(kX86Imul32RM, rs_r1.GetReg(), rs_rX86_SP.GetReg(), |
| 1721 | displacement + LOWORD_OFFSET); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1722 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1723 | true /* is_load */, true /* is_64bit */); |
| 1724 | } |
| 1725 | |
| 1726 | // ECX <- ECX + EAX (2H * 1L) + (1H * 2L) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1727 | NewLIR2(kX86Add32RR, rs_r1.GetReg(), rs_r0.GetReg()); |
Mark Mendell | de99bba | 2014-02-14 12:15:02 -0800 | [diff] [blame] | 1728 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1729 | |
| 1730 | // EAX <- 2L |
| 1731 | if (src2_in_reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1732 | NewLIR2(kX86Mov32RR, rs_r0.GetReg(), rl_src2.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1733 | } else { |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 1734 | LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src2.s_reg_low) + LOWORD_OFFSET, rs_r0, k32, |
| 1735 | kNotVolatile); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1736 | } |
| 1737 | |
| 1738 | // EDX:EAX <- 2L * 1L (double precision) |
| 1739 | if (src1_in_reg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1740 | NewLIR1(kX86Mul32DaR, rl_src1.reg.GetLowReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1741 | } else { |
| 1742 | int displacement = SRegOffset(rl_src1.s_reg_low); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1743 | LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1744 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 1745 | true /* is_load */, true /* is_64bit */); |
| 1746 | } |
| 1747 | |
| 1748 | // EDX <- EDX + ECX (add high words) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1749 | NewLIR2(kX86Add32RR, rs_r2.GetReg(), rs_r1.GetReg()); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1750 | |
| 1751 | // Result is EDX:EAX |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 1752 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1753 | RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 1754 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1755 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1756 | |
| 1757 | void X86Mir2Lir::GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, |
| 1758 | Instruction::Code op) { |
| 1759 | DCHECK_EQ(rl_dest.location, kLocPhysReg); |
| 1760 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
| 1761 | if (rl_src.location == kLocPhysReg) { |
| 1762 | // Both operands are in registers. |
Serguei Katkov | ab5545f | 2014-03-25 10:51:15 +0700 | [diff] [blame] | 1763 | // But we must ensure that rl_src is in pair |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1764 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1765 | NewLIR2(x86op, rl_dest.reg.GetReg(), rl_src.reg.GetReg()); |
| 1766 | } else { |
| 1767 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1768 | if (rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()) { |
| 1769 | // The registers are the same, so we would clobber it before the use. |
| 1770 | RegStorage temp_reg = AllocTemp(); |
| 1771 | OpRegCopy(temp_reg, rl_dest.reg); |
| 1772 | rl_src.reg.SetHighReg(temp_reg.GetReg()); |
| 1773 | } |
| 1774 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1775 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1776 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1777 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), rl_src.reg.GetHighReg()); |
| 1778 | FreeTemp(rl_src.reg); // ??? |
| 1779 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1780 | return; |
| 1781 | } |
| 1782 | |
| 1783 | // RHS is in memory. |
| 1784 | DCHECK((rl_src.location == kLocDalvikFrame) || |
| 1785 | (rl_src.location == kLocCompilerTemp)); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1786 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1787 | int displacement = SRegOffset(rl_src.s_reg_low); |
| 1788 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1789 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 1790 | LIR *lir = NewLIR3(x86op, cu_->target64 ? rl_dest.reg.GetReg() : rl_dest.reg.GetLowReg(), |
| 1791 | r_base, displacement + LOWORD_OFFSET); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1792 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 1793 | true /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1794 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1795 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1796 | lir = NewLIR3(x86op, rl_dest.reg.GetHighReg(), r_base, displacement + HIWORD_OFFSET); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1797 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1798 | true /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1799 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1800 | } |
| 1801 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1802 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1803 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1804 | if (rl_dest.location == kLocPhysReg) { |
| 1805 | // Ensure we are in a register pair |
| 1806 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1807 | |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1808 | rl_src = UpdateLocWideTyped(rl_src, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1809 | GenLongRegOrMemOp(rl_result, rl_src, op); |
| 1810 | StoreFinalValueWide(rl_dest, rl_result); |
| 1811 | return; |
| 1812 | } |
| 1813 | |
| 1814 | // It wasn't in registers, so it better be in memory. |
| 1815 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1816 | (rl_dest.location == kLocCompilerTemp)); |
| 1817 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1818 | |
| 1819 | // Operate directly into memory. |
| 1820 | X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 1821 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1822 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 1823 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1824 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1825 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1826 | cu_->target64 ? rl_src.reg.GetReg() : rl_src.reg.GetLowReg()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1827 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 1828 | true /* is_load */, true /* is64bit */); |
| 1829 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1830 | false /* is_load */, true /* is64bit */); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1831 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1832 | x86op = GetOpcode(op, rl_dest, rl_src, true); |
| 1833 | lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, rl_src.reg.GetHighReg()); |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 1834 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1835 | true /* is_load */, true /* is64bit */); |
| 1836 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
| 1837 | false /* is_load */, true /* is64bit */); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1838 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1839 | FreeTemp(rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1840 | } |
| 1841 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1842 | void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src1, |
| 1843 | RegLocation rl_src2, Instruction::Code op, |
| 1844 | bool is_commutative) { |
| 1845 | // Is this really a 2 operand operation? |
| 1846 | switch (op) { |
| 1847 | case Instruction::ADD_LONG_2ADDR: |
| 1848 | case Instruction::SUB_LONG_2ADDR: |
| 1849 | case Instruction::AND_LONG_2ADDR: |
| 1850 | case Instruction::OR_LONG_2ADDR: |
| 1851 | case Instruction::XOR_LONG_2ADDR: |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 1852 | if (GenerateTwoOperandInstructions()) { |
| 1853 | GenLongArith(rl_dest, rl_src2, op); |
| 1854 | return; |
| 1855 | } |
| 1856 | break; |
| 1857 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1858 | default: |
| 1859 | break; |
| 1860 | } |
| 1861 | |
| 1862 | if (rl_dest.location == kLocPhysReg) { |
| 1863 | RegLocation rl_result = LoadValueWide(rl_src1, kCoreReg); |
| 1864 | |
| 1865 | // We are about to clobber the LHS, so it needs to be a temp. |
| 1866 | rl_result = ForceTempWide(rl_result); |
| 1867 | |
| 1868 | // Perform the operation using the RHS. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1869 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1870 | GenLongRegOrMemOp(rl_result, rl_src2, op); |
| 1871 | |
| 1872 | // And now record that the result is in the temp. |
| 1873 | StoreFinalValueWide(rl_dest, rl_result); |
| 1874 | return; |
| 1875 | } |
| 1876 | |
| 1877 | // It wasn't in registers, so it better be in memory. |
| 1878 | DCHECK((rl_dest.location == kLocDalvikFrame) || |
| 1879 | (rl_dest.location == kLocCompilerTemp)); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 1880 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
| 1881 | rl_src2 = UpdateLocWideTyped(rl_src2, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1882 | |
| 1883 | // Get one of the source operands into temporary register. |
| 1884 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1885 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1886 | if (IsTemp(rl_src1.reg)) { |
| 1887 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1888 | } else if (is_commutative) { |
| 1889 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1890 | // We need at least one of them to be a temporary. |
| 1891 | if (!IsTemp(rl_src2.reg)) { |
| 1892 | rl_src1 = ForceTempWide(rl_src1); |
| 1893 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1894 | } else { |
| 1895 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 1896 | StoreFinalValueWide(rl_dest, rl_src2); |
| 1897 | return; |
| 1898 | } |
| 1899 | } else { |
| 1900 | // Need LHS to be the temp. |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1901 | rl_src1 = ForceTempWide(rl_src1); |
Yevgeny Rouban | 91b6ffa | 2014-03-07 14:35:44 +0700 | [diff] [blame] | 1902 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1903 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1904 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1905 | if (IsTemp(rl_src1.reg.GetLow()) && IsTemp(rl_src1.reg.GetHigh())) { |
| 1906 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1907 | } else if (is_commutative) { |
| 1908 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 1909 | // We need at least one of them to be a temporary. |
| 1910 | if (!(IsTemp(rl_src2.reg.GetLow()) && IsTemp(rl_src2.reg.GetHigh()))) { |
| 1911 | rl_src1 = ForceTempWide(rl_src1); |
| 1912 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1913 | } else { |
| 1914 | GenLongRegOrMemOp(rl_src2, rl_src1, op); |
| 1915 | StoreFinalValueWide(rl_dest, rl_src2); |
| 1916 | return; |
| 1917 | } |
| 1918 | } else { |
| 1919 | // Need LHS to be the temp. |
| 1920 | rl_src1 = ForceTempWide(rl_src1); |
| 1921 | GenLongRegOrMemOp(rl_src1, rl_src2, op); |
| 1922 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 1923 | } |
| 1924 | |
| 1925 | StoreFinalValueWide(rl_dest, rl_src1); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1926 | } |
| 1927 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 1928 | void X86Mir2Lir::GenNotLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 1929 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 1930 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1931 | RegLocation rl_result; |
| 1932 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1933 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1934 | OpReg(kOpNot, rl_result.reg); |
| 1935 | StoreValueWide(rl_dest, rl_result); |
| 1936 | } else { |
| 1937 | LOG(FATAL) << "Unexpected use GenNotLong()"; |
| 1938 | } |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 1939 | } |
| 1940 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 1941 | void X86Mir2Lir::GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, |
| 1942 | int64_t imm, bool is_div) { |
| 1943 | if (imm == 0) { |
| 1944 | GenDivZeroException(); |
| 1945 | } else if (imm == 1) { |
| 1946 | if (is_div) { |
| 1947 | // x / 1 == x. |
| 1948 | StoreValueWide(rl_dest, rl_src); |
| 1949 | } else { |
| 1950 | // x % 1 == 0. |
| 1951 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1952 | LoadConstantWide(rl_result.reg, 0); |
| 1953 | StoreValueWide(rl_dest, rl_result); |
| 1954 | } |
| 1955 | } else if (imm == -1) { // handle 0x8000000000000000 / -1 special case. |
| 1956 | if (is_div) { |
| 1957 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1958 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1959 | RegStorage rs_temp = AllocTempWide(); |
| 1960 | |
| 1961 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 1962 | LoadConstantWide(rs_temp, 0x8000000000000000); |
| 1963 | |
| 1964 | // If x == MIN_LONG, return MIN_LONG. |
| 1965 | OpRegReg(kOpCmp, rl_src.reg, rs_temp); |
| 1966 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 1967 | |
| 1968 | // For x != MIN_LONG, x / -1 == -x. |
| 1969 | OpReg(kOpNeg, rl_result.reg); |
| 1970 | |
| 1971 | minint_branch->target = NewLIR0(kPseudoTargetLabel); |
| 1972 | FreeTemp(rs_temp); |
| 1973 | StoreValueWide(rl_dest, rl_result); |
| 1974 | } else { |
| 1975 | // x % -1 == 0. |
| 1976 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1977 | LoadConstantWide(rl_result.reg, 0); |
| 1978 | StoreValueWide(rl_dest, rl_result); |
| 1979 | } |
| 1980 | } else if (is_div && IsPowerOfTwo(std::abs(imm))) { |
| 1981 | // Division using shifting. |
| 1982 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 1983 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 1984 | if (IsSameReg(rl_result.reg, rl_src.reg)) { |
| 1985 | RegStorage rs_temp = AllocTypedTempWide(false, kCoreReg); |
| 1986 | rl_result.reg.SetReg(rs_temp.GetReg()); |
| 1987 | } |
| 1988 | LoadConstantWide(rl_result.reg, std::abs(imm) - 1); |
| 1989 | OpRegReg(kOpAdd, rl_result.reg, rl_src.reg); |
| 1990 | NewLIR2(kX86Test64RR, rl_src.reg.GetReg(), rl_src.reg.GetReg()); |
| 1991 | OpCondRegReg(kOpCmov, kCondPl, rl_result.reg, rl_src.reg); |
| 1992 | int shift_amount = LowestSetBit(imm); |
| 1993 | OpRegImm(kOpAsr, rl_result.reg, shift_amount); |
| 1994 | if (imm < 0) { |
| 1995 | OpReg(kOpNeg, rl_result.reg); |
| 1996 | } |
| 1997 | StoreValueWide(rl_dest, rl_result); |
| 1998 | } else { |
| 1999 | CHECK(imm <= -2 || imm >= 2); |
| 2000 | |
| 2001 | FlushReg(rs_r0q); |
| 2002 | Clobber(rs_r0q); |
| 2003 | LockTemp(rs_r0q); |
| 2004 | FlushReg(rs_r2q); |
| 2005 | Clobber(rs_r2q); |
| 2006 | LockTemp(rs_r2q); |
| 2007 | |
| 2008 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r2q, INVALID_SREG, INVALID_SREG}; |
| 2009 | |
| 2010 | // Use H.S.Warren's Hacker's Delight Chapter 10 and |
| 2011 | // T,Grablund, P.L.Montogomery's Division by invariant integers using multiplication. |
| 2012 | int64_t magic; |
| 2013 | int shift; |
| 2014 | CalculateMagicAndShift(imm, magic, shift, true /* is_long */); |
| 2015 | |
| 2016 | /* |
| 2017 | * For imm >= 2, |
| 2018 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n > 0 |
| 2019 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1, while n < 0. |
| 2020 | * For imm <= -2, |
| 2021 | * int(n/imm) = ceil(n/imm) = floor(M*n/2^S) +1 , while n > 0 |
| 2022 | * int(n/imm) = floor(n/imm) = floor(M*n/2^S), while n < 0. |
| 2023 | * We implement this algorithm in the following way: |
| 2024 | * 1. multiply magic number m and numerator n, get the higher 64bit result in RDX |
| 2025 | * 2. if imm > 0 and magic < 0, add numerator to RDX |
| 2026 | * if imm < 0 and magic > 0, sub numerator from RDX |
| 2027 | * 3. if S !=0, SAR S bits for RDX |
| 2028 | * 4. add 1 to RDX if RDX < 0 |
| 2029 | * 5. Thus, RDX is the quotient |
| 2030 | */ |
| 2031 | |
| 2032 | // Numerator into RAX. |
| 2033 | RegStorage numerator_reg; |
| 2034 | if (!is_div || (imm > 0 && magic < 0) || (imm < 0 && magic > 0)) { |
| 2035 | // We will need the value later. |
| 2036 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2037 | numerator_reg = rl_src.reg; |
| 2038 | OpRegCopyWide(rs_r0q, numerator_reg); |
| 2039 | } else { |
| 2040 | // Only need this once. Just put it into RAX. |
| 2041 | LoadValueDirectWideFixed(rl_src, rs_r0q); |
| 2042 | } |
| 2043 | |
| 2044 | // RDX = magic. |
| 2045 | LoadConstantWide(rs_r2q, magic); |
| 2046 | |
| 2047 | // RDX:RAX = magic & dividend. |
| 2048 | NewLIR1(kX86Imul64DaR, rs_r2q.GetReg()); |
| 2049 | |
| 2050 | if (imm > 0 && magic < 0) { |
| 2051 | // Add numerator to RDX. |
| 2052 | DCHECK(numerator_reg.Valid()); |
| 2053 | OpRegReg(kOpAdd, rs_r2q, numerator_reg); |
| 2054 | } else if (imm < 0 && magic > 0) { |
| 2055 | DCHECK(numerator_reg.Valid()); |
| 2056 | OpRegReg(kOpSub, rs_r2q, numerator_reg); |
| 2057 | } |
| 2058 | |
| 2059 | // Do we need the shift? |
| 2060 | if (shift != 0) { |
| 2061 | // Shift RDX by 'shift' bits. |
| 2062 | OpRegImm(kOpAsr, rs_r2q, shift); |
| 2063 | } |
| 2064 | |
| 2065 | // Move RDX to RAX. |
| 2066 | OpRegCopyWide(rs_r0q, rs_r2q); |
| 2067 | |
| 2068 | // Move sign bit to bit 0, zeroing the rest. |
| 2069 | OpRegImm(kOpLsr, rs_r2q, 63); |
| 2070 | |
| 2071 | // RDX = RDX + RAX. |
| 2072 | OpRegReg(kOpAdd, rs_r2q, rs_r0q); |
| 2073 | |
| 2074 | // Quotient is in RDX. |
| 2075 | if (!is_div) { |
| 2076 | // We need to compute the remainder. |
| 2077 | // Remainder is divisor - (quotient * imm). |
| 2078 | DCHECK(numerator_reg.Valid()); |
| 2079 | OpRegCopyWide(rs_r0q, numerator_reg); |
| 2080 | |
| 2081 | // Imul doesn't support 64-bit imms. |
| 2082 | if (imm > std::numeric_limits<int32_t>::max() || |
| 2083 | imm < std::numeric_limits<int32_t>::min()) { |
| 2084 | RegStorage rs_temp = AllocTempWide(); |
| 2085 | LoadConstantWide(rs_temp, imm); |
| 2086 | |
| 2087 | // RAX = numerator * imm. |
| 2088 | NewLIR2(kX86Imul64RR, rs_r2q.GetReg(), rs_temp.GetReg()); |
| 2089 | |
| 2090 | FreeTemp(rs_temp); |
| 2091 | } else { |
| 2092 | // RAX = numerator * imm. |
| 2093 | int short_imm = static_cast<int>(imm); |
| 2094 | NewLIR3(kX86Imul64RRI, rs_r2q.GetReg(), rs_r2q.GetReg(), short_imm); |
| 2095 | } |
| 2096 | |
| 2097 | // RDX -= RAX. |
| 2098 | OpRegReg(kOpSub, rs_r0q, rs_r2q); |
| 2099 | |
| 2100 | // Store result. |
| 2101 | OpRegCopyWide(rl_result.reg, rs_r0q); |
| 2102 | } else { |
| 2103 | // Store result. |
| 2104 | OpRegCopyWide(rl_result.reg, rs_r2q); |
| 2105 | } |
| 2106 | StoreValueWide(rl_dest, rl_result); |
| 2107 | FreeTemp(rs_r0q); |
| 2108 | FreeTemp(rs_r2q); |
| 2109 | } |
| 2110 | } |
| 2111 | |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2112 | void X86Mir2Lir::GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2113 | RegLocation rl_src2, bool is_div) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2114 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2115 | LOG(FATAL) << "Unexpected use GenDivRemLong()"; |
| 2116 | return; |
| 2117 | } |
| 2118 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2119 | if (rl_src2.is_const) { |
| 2120 | DCHECK(rl_src2.wide); |
| 2121 | int64_t imm = mir_graph_->ConstantValueWide(rl_src2); |
| 2122 | GenDivRemLongLit(rl_dest, rl_src1, imm, is_div); |
| 2123 | return; |
| 2124 | } |
| 2125 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2126 | // We have to use fixed registers, so flush all the temps. |
| 2127 | FlushAllRegs(); |
| 2128 | LockCallTemps(); // Prepare for explicit register usage. |
| 2129 | |
| 2130 | // Load LHS into RAX. |
| 2131 | LoadValueDirectWideFixed(rl_src1, rs_r0q); |
| 2132 | |
| 2133 | // Load RHS into RCX. |
| 2134 | LoadValueDirectWideFixed(rl_src2, rs_r1q); |
| 2135 | |
| 2136 | // Copy LHS sign bit into RDX. |
| 2137 | NewLIR0(kx86Cqo64Da); |
| 2138 | |
| 2139 | // Handle division by zero case. |
| 2140 | GenDivZeroCheckWide(rs_r1q); |
| 2141 | |
| 2142 | // Have to catch 0x8000000000000000/-1 case, or we will get an exception! |
| 2143 | NewLIR2(kX86Cmp64RI8, rs_r1q.GetReg(), -1); |
| 2144 | LIR *minus_one_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 2145 | |
| 2146 | // RHS is -1. |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2147 | LoadConstantWide(rs_r6q, 0x8000000000000000); |
| 2148 | NewLIR2(kX86Cmp64RR, rs_r0q.GetReg(), rs_r6q.GetReg()); |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2149 | LIR *minint_branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2150 | |
| 2151 | // In 0x8000000000000000/-1 case. |
| 2152 | if (!is_div) { |
| 2153 | // For DIV, RAX is already right. For REM, we need RDX 0. |
| 2154 | NewLIR2(kX86Xor64RR, rs_r2q.GetReg(), rs_r2q.GetReg()); |
| 2155 | } |
| 2156 | LIR* done = NewLIR1(kX86Jmp8, 0); |
| 2157 | |
| 2158 | // Expected case. |
| 2159 | minus_one_branch->target = NewLIR0(kPseudoTargetLabel); |
| 2160 | minint_branch->target = minus_one_branch->target; |
| 2161 | NewLIR1(kX86Idivmod64DaR, rs_r1q.GetReg()); |
| 2162 | done->target = NewLIR0(kPseudoTargetLabel); |
| 2163 | |
| 2164 | // Result is in RAX for div and RDX for rem. |
| 2165 | RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r0q, INVALID_SREG, INVALID_SREG}; |
| 2166 | if (!is_div) { |
| 2167 | rl_result.reg.SetReg(r2q); |
| 2168 | } |
| 2169 | |
| 2170 | StoreValueWide(rl_dest, rl_result); |
Serban Constantinescu | ed65c5e | 2014-05-22 15:10:18 +0100 | [diff] [blame] | 2171 | } |
| 2172 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 2173 | void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2174 | rl_src = LoadValueWide(rl_src, kCoreReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2175 | RegLocation rl_result; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2176 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2177 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2178 | OpRegReg(kOpNeg, rl_result.reg, rl_src.reg); |
| 2179 | } else { |
| 2180 | rl_result = ForceTempWide(rl_src); |
| 2181 | if (((rl_dest.location == kLocPhysReg) && (rl_src.location == kLocPhysReg)) && |
| 2182 | ((rl_dest.reg.GetLowReg() == rl_src.reg.GetHighReg()))) { |
| 2183 | // The registers are the same, so we would clobber it before the use. |
| 2184 | RegStorage temp_reg = AllocTemp(); |
| 2185 | OpRegCopy(temp_reg, rl_result.reg); |
| 2186 | rl_result.reg.SetHighReg(temp_reg.GetReg()); |
| 2187 | } |
| 2188 | OpRegReg(kOpNeg, rl_result.reg.GetLow(), rl_result.reg.GetLow()); // rLow = -rLow |
| 2189 | OpRegImm(kOpAdc, rl_result.reg.GetHigh(), 0); // rHigh = rHigh + CF |
| 2190 | OpRegReg(kOpNeg, rl_result.reg.GetHigh(), rl_result.reg.GetHigh()); // rHigh = -rHigh |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2191 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2192 | StoreValueWide(rl_dest, rl_result); |
| 2193 | } |
| 2194 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2195 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 2196 | DCHECK_EQ(kX86, cu_->instruction_set); |
| 2197 | X86OpCode opcode = kX86Bkpt; |
| 2198 | switch (op) { |
| 2199 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2200 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2201 | default: |
| 2202 | LOG(FATAL) << "Bad opcode: " << op; |
| 2203 | break; |
| 2204 | } |
| 2205 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
| 2206 | } |
| 2207 | |
| 2208 | void X86Mir2Lir::OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset) { |
| 2209 | DCHECK_EQ(kX86_64, cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2210 | X86OpCode opcode = kX86Bkpt; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2211 | if (cu_->target64 && r_dest.Is64BitSolo()) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 2212 | switch (op) { |
| 2213 | case kOpCmp: opcode = kX86Cmp64RT; break; |
| 2214 | case kOpMov: opcode = kX86Mov64RT; break; |
| 2215 | default: |
| 2216 | LOG(FATAL) << "Bad opcode(OpRegThreadMem 64): " << op; |
| 2217 | break; |
| 2218 | } |
| 2219 | } else { |
| 2220 | switch (op) { |
| 2221 | case kOpCmp: opcode = kX86Cmp32RT; break; |
| 2222 | case kOpMov: opcode = kX86Mov32RT; break; |
| 2223 | default: |
| 2224 | LOG(FATAL) << "Bad opcode: " << op; |
| 2225 | break; |
| 2226 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2227 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2228 | NewLIR2(opcode, r_dest.GetReg(), thread_offset.Int32Value()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2229 | } |
| 2230 | |
| 2231 | /* |
| 2232 | * Generate array load |
| 2233 | */ |
| 2234 | void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2235 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2236 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2237 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2238 | RegLocation rl_result; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2239 | rl_array = LoadValue(rl_array, kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2240 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2241 | int data_offset; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2242 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2243 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2244 | } else { |
| 2245 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2246 | } |
| 2247 | |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2248 | bool constant_index = rl_index.is_const; |
| 2249 | int32_t constant_index_value = 0; |
| 2250 | if (!constant_index) { |
| 2251 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2252 | } else { |
| 2253 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2254 | // If index is constant, just fold it into the data offset |
| 2255 | data_offset += constant_index_value << scale; |
| 2256 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2257 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2258 | } |
| 2259 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2260 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2261 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2262 | |
| 2263 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2264 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2265 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2266 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2267 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2268 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2269 | } |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2270 | rl_result = EvalLoc(rl_dest, reg_class, true); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 2271 | LoadBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_result.reg, size); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2272 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2273 | StoreValueWide(rl_dest, rl_result); |
| 2274 | } else { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2275 | StoreValue(rl_dest, rl_result); |
| 2276 | } |
| 2277 | } |
| 2278 | |
| 2279 | /* |
| 2280 | * Generate array store |
| 2281 | * |
| 2282 | */ |
| 2283 | void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2284 | RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2285 | RegisterClass reg_class = RegClassBySize(size); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2286 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 2287 | int data_offset; |
| 2288 | |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2289 | if (size == k64 || size == kDouble) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2290 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 2291 | } else { |
| 2292 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 2293 | } |
| 2294 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2295 | rl_array = LoadValue(rl_array, kRefReg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2296 | bool constant_index = rl_index.is_const; |
| 2297 | int32_t constant_index_value = 0; |
| 2298 | if (!constant_index) { |
| 2299 | rl_index = LoadValue(rl_index, kCoreReg); |
| 2300 | } else { |
| 2301 | // If index is constant, just fold it into the data offset |
| 2302 | constant_index_value = mir_graph_->ConstantValue(rl_index); |
| 2303 | data_offset += constant_index_value << scale; |
| 2304 | // treat as non array below |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2305 | rl_index.reg = RegStorage::InvalidReg(); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2306 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2307 | |
| 2308 | /* null object? */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2309 | GenNullCheck(rl_array.reg, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2310 | |
| 2311 | if (!(opt_flags & MIR_IGNORE_RANGE_CHECK)) { |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2312 | if (constant_index) { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2313 | GenArrayBoundsCheck(constant_index_value, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2314 | } else { |
Mingyao Yang | 80365d9 | 2014-04-18 12:10:58 -0700 | [diff] [blame] | 2315 | GenArrayBoundsCheck(rl_index.reg, rl_array.reg, len_offset); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2316 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2317 | } |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2318 | if ((size == k64) || (size == kDouble)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2319 | rl_src = LoadValueWide(rl_src, reg_class); |
| 2320 | } else { |
| 2321 | rl_src = LoadValue(rl_src, reg_class); |
| 2322 | } |
| 2323 | // If the src reg can't be byte accessed, move it to a temp first. |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2324 | if ((size == kSignedByte || size == kUnsignedByte) && !IsByteRegister(rl_src.reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2325 | RegStorage temp = AllocTemp(); |
| 2326 | OpRegCopy(temp, rl_src.reg); |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame^] | 2327 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, temp, size, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2328 | } else { |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame^] | 2329 | StoreBaseIndexedDisp(rl_array.reg, rl_index.reg, scale, data_offset, rl_src.reg, size, opt_flags); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2330 | } |
Ian Rogers | a9a8254 | 2013-10-04 11:17:26 -0700 | [diff] [blame] | 2331 | if (card_mark) { |
Ian Rogers | 773aab1 | 2013-10-14 13:50:10 -0700 | [diff] [blame] | 2332 | // Free rl_index if its a temp. Ensures there are 2 free regs for card mark. |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2333 | if (!constant_index) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2334 | FreeTemp(rl_index.reg); |
Mark Mendell | 343adb5 | 2013-12-18 06:02:17 -0800 | [diff] [blame] | 2335 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2336 | MarkGCCard(rl_src.reg, rl_array.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2337 | } |
| 2338 | } |
| 2339 | |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2340 | RegLocation X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 2341 | RegLocation rl_src, int shift_amount) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2342 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2343 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2344 | OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ |
| 2345 | switch (opcode) { |
| 2346 | case Instruction::SHL_LONG: |
| 2347 | case Instruction::SHL_LONG_2ADDR: |
| 2348 | op = kOpLsl; |
| 2349 | break; |
| 2350 | case Instruction::SHR_LONG: |
| 2351 | case Instruction::SHR_LONG_2ADDR: |
| 2352 | op = kOpAsr; |
| 2353 | break; |
| 2354 | case Instruction::USHR_LONG: |
| 2355 | case Instruction::USHR_LONG_2ADDR: |
| 2356 | op = kOpLsr; |
| 2357 | break; |
| 2358 | default: |
| 2359 | LOG(FATAL) << "Unexpected case"; |
| 2360 | } |
| 2361 | OpRegRegImm(op, rl_result.reg, rl_src.reg, shift_amount); |
| 2362 | } else { |
| 2363 | switch (opcode) { |
| 2364 | case Instruction::SHL_LONG: |
| 2365 | case Instruction::SHL_LONG_2ADDR: |
| 2366 | DCHECK_NE(shift_amount, 1); // Prevent a double store from happening. |
| 2367 | if (shift_amount == 32) { |
| 2368 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2369 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2370 | } else if (shift_amount > 31) { |
| 2371 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetLow()); |
| 2372 | NewLIR2(kX86Sal32RI, rl_result.reg.GetHighReg(), shift_amount - 32); |
| 2373 | LoadConstant(rl_result.reg.GetLow(), 0); |
| 2374 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2375 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2376 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2377 | NewLIR3(kX86Shld32RRI, rl_result.reg.GetHighReg(), rl_result.reg.GetLowReg(), |
| 2378 | shift_amount); |
| 2379 | NewLIR2(kX86Sal32RI, rl_result.reg.GetLowReg(), shift_amount); |
| 2380 | } |
| 2381 | break; |
| 2382 | case Instruction::SHR_LONG: |
| 2383 | case Instruction::SHR_LONG_2ADDR: |
| 2384 | if (shift_amount == 32) { |
| 2385 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2386 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2387 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2388 | } else if (shift_amount > 31) { |
| 2389 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2390 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2391 | NewLIR2(kX86Sar32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2392 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), 31); |
| 2393 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2394 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2395 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2396 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2397 | shift_amount); |
| 2398 | NewLIR2(kX86Sar32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2399 | } |
| 2400 | break; |
| 2401 | case Instruction::USHR_LONG: |
| 2402 | case Instruction::USHR_LONG_2ADDR: |
| 2403 | if (shift_amount == 32) { |
| 2404 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2405 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2406 | } else if (shift_amount > 31) { |
| 2407 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetHigh()); |
| 2408 | NewLIR2(kX86Shr32RI, rl_result.reg.GetLowReg(), shift_amount - 32); |
| 2409 | LoadConstant(rl_result.reg.GetHigh(), 0); |
| 2410 | } else { |
Mark Mendell | b9b9d66 | 2014-06-16 13:03:42 -0400 | [diff] [blame] | 2411 | OpRegCopy(rl_result.reg.GetLow(), rl_src.reg.GetLow()); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2412 | OpRegCopy(rl_result.reg.GetHigh(), rl_src.reg.GetHigh()); |
| 2413 | NewLIR3(kX86Shrd32RRI, rl_result.reg.GetLowReg(), rl_result.reg.GetHighReg(), |
| 2414 | shift_amount); |
| 2415 | NewLIR2(kX86Shr32RI, rl_result.reg.GetHighReg(), shift_amount); |
| 2416 | } |
| 2417 | break; |
| 2418 | default: |
| 2419 | LOG(FATAL) << "Unexpected case"; |
| 2420 | } |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2421 | } |
| 2422 | return rl_result; |
| 2423 | } |
| 2424 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2425 | void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2426 | RegLocation rl_src, RegLocation rl_shift) { |
| 2427 | // Per spec, we only care about low 6 bits of shift amount. |
| 2428 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 2429 | if (shift_amount == 0) { |
| 2430 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2431 | StoreValueWide(rl_dest, rl_src); |
| 2432 | return; |
| 2433 | } else if (shift_amount == 1 && |
| 2434 | (opcode == Instruction::SHL_LONG || opcode == Instruction::SHL_LONG_2ADDR)) { |
| 2435 | // Need to handle this here to avoid calling StoreValueWide twice. |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 2436 | GenArithOpLong(Instruction::ADD_LONG, rl_dest, rl_src, rl_src); |
Mark Mendell | 4708dcd | 2014-01-22 09:05:18 -0800 | [diff] [blame] | 2437 | return; |
| 2438 | } |
| 2439 | if (BadOverlap(rl_src, rl_dest)) { |
| 2440 | GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); |
| 2441 | return; |
| 2442 | } |
| 2443 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 2444 | RegLocation rl_result = GenShiftImmOpLong(opcode, rl_dest, rl_src, shift_amount); |
| 2445 | StoreValueWide(rl_dest, rl_result); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2446 | } |
| 2447 | |
| 2448 | void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 2449 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2450 | bool isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2451 | switch (opcode) { |
| 2452 | case Instruction::ADD_LONG: |
| 2453 | case Instruction::AND_LONG: |
| 2454 | case Instruction::OR_LONG: |
| 2455 | case Instruction::XOR_LONG: |
| 2456 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2457 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2458 | } else { |
| 2459 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2460 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2461 | } |
| 2462 | break; |
| 2463 | case Instruction::SUB_LONG: |
| 2464 | case Instruction::SUB_LONG_2ADDR: |
| 2465 | if (rl_src2.is_const) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2466 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2467 | } else { |
Andreas Gampe | c76c614 | 2014-08-04 16:30:03 -0700 | [diff] [blame] | 2468 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2469 | isConstSuccess = true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2470 | } |
| 2471 | break; |
| 2472 | case Instruction::ADD_LONG_2ADDR: |
| 2473 | case Instruction::OR_LONG_2ADDR: |
| 2474 | case Instruction::XOR_LONG_2ADDR: |
| 2475 | case Instruction::AND_LONG_2ADDR: |
| 2476 | if (rl_src2.is_const) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2477 | if (GenerateTwoOperandInstructions()) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2478 | isConstSuccess = GenLongImm(rl_dest, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2479 | } else { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2480 | isConstSuccess = GenLongLongImm(rl_dest, rl_src1, rl_src2, opcode); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2481 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2482 | } else { |
| 2483 | DCHECK(rl_src1.is_const); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2484 | isConstSuccess = GenLongLongImm(rl_dest, rl_src2, rl_src1, opcode); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2485 | } |
| 2486 | break; |
| 2487 | default: |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2488 | isConstSuccess = false; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2489 | break; |
| 2490 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2491 | |
| 2492 | if (!isConstSuccess) { |
| 2493 | // Default - bail to non-const handler. |
| 2494 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 2495 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2496 | } |
| 2497 | |
| 2498 | bool X86Mir2Lir::IsNoOp(Instruction::Code op, int32_t value) { |
| 2499 | switch (op) { |
| 2500 | case Instruction::AND_LONG_2ADDR: |
| 2501 | case Instruction::AND_LONG: |
| 2502 | return value == -1; |
| 2503 | case Instruction::OR_LONG: |
| 2504 | case Instruction::OR_LONG_2ADDR: |
| 2505 | case Instruction::XOR_LONG: |
| 2506 | case Instruction::XOR_LONG_2ADDR: |
| 2507 | return value == 0; |
| 2508 | default: |
| 2509 | return false; |
| 2510 | } |
| 2511 | } |
| 2512 | |
| 2513 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, |
| 2514 | bool is_high_op) { |
| 2515 | bool rhs_in_mem = rhs.location != kLocPhysReg; |
| 2516 | bool dest_in_mem = dest.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2517 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2518 | DCHECK(!rhs_in_mem || !dest_in_mem); |
| 2519 | switch (op) { |
| 2520 | case Instruction::ADD_LONG: |
| 2521 | case Instruction::ADD_LONG_2ADDR: |
| 2522 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2523 | return is64Bit ? kX86Add64MR : is_high_op ? kX86Adc32MR : kX86Add32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2524 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2525 | return is64Bit ? kX86Add64RM : is_high_op ? kX86Adc32RM : kX86Add32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2526 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2527 | return is64Bit ? kX86Add64RR : is_high_op ? kX86Adc32RR : kX86Add32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2528 | case Instruction::SUB_LONG: |
| 2529 | case Instruction::SUB_LONG_2ADDR: |
| 2530 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2531 | return is64Bit ? kX86Sub64MR : is_high_op ? kX86Sbb32MR : kX86Sub32MR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2532 | } else if (rhs_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2533 | return is64Bit ? kX86Sub64RM : is_high_op ? kX86Sbb32RM : kX86Sub32RM; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2534 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2535 | return is64Bit ? kX86Sub64RR : is_high_op ? kX86Sbb32RR : kX86Sub32RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2536 | case Instruction::AND_LONG_2ADDR: |
| 2537 | case Instruction::AND_LONG: |
| 2538 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2539 | return is64Bit ? kX86And64MR : kX86And32MR; |
| 2540 | } |
| 2541 | if (is64Bit) { |
| 2542 | return rhs_in_mem ? kX86And64RM : kX86And64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2543 | } |
| 2544 | return rhs_in_mem ? kX86And32RM : kX86And32RR; |
| 2545 | case Instruction::OR_LONG: |
| 2546 | case Instruction::OR_LONG_2ADDR: |
| 2547 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2548 | return is64Bit ? kX86Or64MR : kX86Or32MR; |
| 2549 | } |
| 2550 | if (is64Bit) { |
| 2551 | return rhs_in_mem ? kX86Or64RM : kX86Or64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2552 | } |
| 2553 | return rhs_in_mem ? kX86Or32RM : kX86Or32RR; |
| 2554 | case Instruction::XOR_LONG: |
| 2555 | case Instruction::XOR_LONG_2ADDR: |
| 2556 | if (dest_in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2557 | return is64Bit ? kX86Xor64MR : kX86Xor32MR; |
| 2558 | } |
| 2559 | if (is64Bit) { |
| 2560 | return rhs_in_mem ? kX86Xor64RM : kX86Xor64RR; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2561 | } |
| 2562 | return rhs_in_mem ? kX86Xor32RM : kX86Xor32RR; |
| 2563 | default: |
| 2564 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 2565 | return kX86Add32RR; |
| 2566 | } |
| 2567 | } |
| 2568 | |
| 2569 | X86OpCode X86Mir2Lir::GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, |
| 2570 | int32_t value) { |
| 2571 | bool in_mem = loc.location != kLocPhysReg; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2572 | bool is64Bit = cu_->target64; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2573 | bool byte_imm = IS_SIMM8(value); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2574 | DCHECK(in_mem || !loc.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2575 | switch (op) { |
| 2576 | case Instruction::ADD_LONG: |
| 2577 | case Instruction::ADD_LONG_2ADDR: |
| 2578 | if (byte_imm) { |
| 2579 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2580 | return is64Bit ? kX86Add64MI8 : is_high_op ? kX86Adc32MI8 : kX86Add32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2581 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2582 | return is64Bit ? kX86Add64RI8 : is_high_op ? kX86Adc32RI8 : kX86Add32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2583 | } |
| 2584 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2585 | return is64Bit ? kX86Add64MI : is_high_op ? kX86Adc32MI : kX86Add32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2586 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2587 | return is64Bit ? kX86Add64RI : is_high_op ? kX86Adc32RI : kX86Add32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2588 | case Instruction::SUB_LONG: |
| 2589 | case Instruction::SUB_LONG_2ADDR: |
| 2590 | if (byte_imm) { |
| 2591 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2592 | return is64Bit ? kX86Sub64MI8 : is_high_op ? kX86Sbb32MI8 : kX86Sub32MI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2593 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2594 | return is64Bit ? kX86Sub64RI8 : is_high_op ? kX86Sbb32RI8 : kX86Sub32RI8; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2595 | } |
| 2596 | if (in_mem) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2597 | return is64Bit ? kX86Sub64MI : is_high_op ? kX86Sbb32MI : kX86Sub32MI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2598 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2599 | return is64Bit ? kX86Sub64RI : is_high_op ? kX86Sbb32RI : kX86Sub32RI; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2600 | case Instruction::AND_LONG_2ADDR: |
| 2601 | case Instruction::AND_LONG: |
| 2602 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2603 | if (is64Bit) { |
| 2604 | return in_mem ? kX86And64MI8 : kX86And64RI8; |
| 2605 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2606 | return in_mem ? kX86And32MI8 : kX86And32RI8; |
| 2607 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2608 | if (is64Bit) { |
| 2609 | return in_mem ? kX86And64MI : kX86And64RI; |
| 2610 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2611 | return in_mem ? kX86And32MI : kX86And32RI; |
| 2612 | case Instruction::OR_LONG: |
| 2613 | case Instruction::OR_LONG_2ADDR: |
| 2614 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2615 | if (is64Bit) { |
| 2616 | return in_mem ? kX86Or64MI8 : kX86Or64RI8; |
| 2617 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2618 | return in_mem ? kX86Or32MI8 : kX86Or32RI8; |
| 2619 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2620 | if (is64Bit) { |
| 2621 | return in_mem ? kX86Or64MI : kX86Or64RI; |
| 2622 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2623 | return in_mem ? kX86Or32MI : kX86Or32RI; |
| 2624 | case Instruction::XOR_LONG: |
| 2625 | case Instruction::XOR_LONG_2ADDR: |
| 2626 | if (byte_imm) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2627 | if (is64Bit) { |
| 2628 | return in_mem ? kX86Xor64MI8 : kX86Xor64RI8; |
| 2629 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2630 | return in_mem ? kX86Xor32MI8 : kX86Xor32RI8; |
| 2631 | } |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 2632 | if (is64Bit) { |
| 2633 | return in_mem ? kX86Xor64MI : kX86Xor64RI; |
| 2634 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2635 | return in_mem ? kX86Xor32MI : kX86Xor32RI; |
| 2636 | default: |
| 2637 | LOG(FATAL) << "Unexpected opcode: " << op; |
| 2638 | return kX86Add32MI; |
| 2639 | } |
| 2640 | } |
| 2641 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2642 | bool X86Mir2Lir::GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2643 | DCHECK(rl_src.is_const); |
| 2644 | int64_t val = mir_graph_->ConstantValueWide(rl_src); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2645 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2646 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2647 | // We can do with imm only if it fits 32 bit |
| 2648 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2649 | return false; |
| 2650 | } |
| 2651 | |
| 2652 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 2653 | |
| 2654 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2655 | (rl_dest.location == kLocCompilerTemp)) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2656 | int r_base = rs_rX86_SP.GetReg(); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2657 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2658 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2659 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2660 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
| 2661 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val); |
| 2662 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2663 | true /* is_load */, true /* is64bit */); |
| 2664 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
| 2665 | false /* is_load */, true /* is64bit */); |
| 2666 | return true; |
| 2667 | } |
| 2668 | |
| 2669 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2670 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
| 2671 | DCHECK(!rl_result.reg.IsFloat()); |
| 2672 | |
| 2673 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2674 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2675 | |
| 2676 | StoreValueWide(rl_dest, rl_result); |
| 2677 | return true; |
| 2678 | } |
| 2679 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2680 | int32_t val_lo = Low32Bits(val); |
| 2681 | int32_t val_hi = High32Bits(val); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2682 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2683 | |
| 2684 | // Can we just do this into memory? |
| 2685 | if ((rl_dest.location == kLocDalvikFrame) || |
| 2686 | (rl_dest.location == kLocCompilerTemp)) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2687 | int r_base = rs_rX86_SP.GetReg(); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2688 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 2689 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2690 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2691 | if (!IsNoOp(op, val_lo)) { |
| 2692 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2693 | LIR *lir = NewLIR3(x86op, r_base, displacement + LOWORD_OFFSET, val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2694 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2695 | true /* is_load */, true /* is64bit */); |
| 2696 | AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2697 | false /* is_load */, true /* is64bit */); |
| 2698 | } |
| 2699 | if (!IsNoOp(op, val_hi)) { |
| 2700 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2701 | LIR *lir = NewLIR3(x86op, r_base, displacement + HIWORD_OFFSET, val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2702 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Serguei Katkov | 217fe73 | 2014-03-27 14:41:56 +0700 | [diff] [blame] | 2703 | true /* is_load */, true /* is64bit */); |
| 2704 | AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2705 | false /* is_load */, true /* is64bit */); |
| 2706 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2707 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2708 | } |
| 2709 | |
| 2710 | RegLocation rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2711 | DCHECK_EQ(rl_result.location, kLocPhysReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2712 | DCHECK(!rl_result.reg.IsFloat()); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2713 | |
| 2714 | if (!IsNoOp(op, val_lo)) { |
| 2715 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2716 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2717 | } |
| 2718 | if (!IsNoOp(op, val_hi)) { |
| 2719 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2720 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2721 | } |
| 2722 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2723 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2724 | } |
| 2725 | |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2726 | bool X86Mir2Lir::GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2727 | RegLocation rl_src2, Instruction::Code op) { |
| 2728 | DCHECK(rl_src2.is_const); |
| 2729 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2730 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2731 | if (cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2732 | // We can do with imm only if it fits 32 bit |
| 2733 | if (val != (static_cast<int64_t>(static_cast<int32_t>(val)))) { |
| 2734 | return false; |
| 2735 | } |
| 2736 | if (rl_dest.location == kLocPhysReg && |
| 2737 | rl_src1.location == kLocPhysReg && !rl_dest.reg.IsFloat()) { |
| 2738 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val); |
Dmitry Petrochenko | 3157f9a | 2014-06-18 19:11:41 +0700 | [diff] [blame] | 2739 | OpRegCopy(rl_dest.reg, rl_src1.reg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2740 | NewLIR2(x86op, rl_dest.reg.GetReg(), val); |
| 2741 | StoreFinalValueWide(rl_dest, rl_dest); |
| 2742 | return true; |
| 2743 | } |
| 2744 | |
| 2745 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2746 | // We need the values to be in a temporary |
| 2747 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2748 | |
| 2749 | X86OpCode x86op = GetOpcode(op, rl_result, false, val); |
| 2750 | NewLIR2(x86op, rl_result.reg.GetReg(), val); |
| 2751 | |
| 2752 | StoreFinalValueWide(rl_dest, rl_result); |
| 2753 | return true; |
| 2754 | } |
| 2755 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2756 | int32_t val_lo = Low32Bits(val); |
| 2757 | int32_t val_hi = High32Bits(val); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2758 | rl_dest = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 2759 | rl_src1 = UpdateLocWideTyped(rl_src1, kCoreReg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2760 | |
| 2761 | // Can we do this directly into the destination registers? |
| 2762 | if (rl_dest.location == kLocPhysReg && rl_src1.location == kLocPhysReg && |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2763 | rl_dest.reg.GetLowReg() == rl_src1.reg.GetLowReg() && |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2764 | rl_dest.reg.GetHighReg() == rl_src1.reg.GetHighReg() && !rl_dest.reg.IsFloat()) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2765 | if (!IsNoOp(op, val_lo)) { |
| 2766 | X86OpCode x86op = GetOpcode(op, rl_dest, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2767 | NewLIR2(x86op, rl_dest.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2768 | } |
| 2769 | if (!IsNoOp(op, val_hi)) { |
| 2770 | X86OpCode x86op = GetOpcode(op, rl_dest, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2771 | NewLIR2(x86op, rl_dest.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2772 | } |
Maxim Kazantsev | 653f2bf | 2014-02-13 15:11:17 +0700 | [diff] [blame] | 2773 | |
| 2774 | StoreFinalValueWide(rl_dest, rl_dest); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2775 | return true; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2776 | } |
| 2777 | |
| 2778 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 2779 | DCHECK_EQ(rl_src1.location, kLocPhysReg); |
| 2780 | |
| 2781 | // We need the values to be in a temporary |
| 2782 | RegLocation rl_result = ForceTempWide(rl_src1); |
| 2783 | if (!IsNoOp(op, val_lo)) { |
| 2784 | X86OpCode x86op = GetOpcode(op, rl_result, false, val_lo); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2785 | NewLIR2(x86op, rl_result.reg.GetLowReg(), val_lo); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2786 | } |
| 2787 | if (!IsNoOp(op, val_hi)) { |
| 2788 | X86OpCode x86op = GetOpcode(op, rl_result, true, val_hi); |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 2789 | NewLIR2(x86op, rl_result.reg.GetHighReg(), val_hi); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 2790 | } |
| 2791 | |
| 2792 | StoreFinalValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 2793 | return true; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 2794 | } |
| 2795 | |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2796 | // For final classes there are no sub-classes to check and so we can answer the instance-of |
| 2797 | // question with simple comparisons. Use compares to memory and SETEQ to optimize for x86. |
| 2798 | void X86Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, |
| 2799 | RegLocation rl_dest, RegLocation rl_src) { |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 2800 | RegLocation object = LoadValue(rl_src, kRefReg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2801 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2802 | RegStorage result_reg = rl_result.reg; |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2803 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 2804 | // For 32-bit, SETcc only works with EAX..EDX. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2805 | RegStorage object_32reg = object.reg.Is64Bit() ? As32BitReg(object.reg) : object.reg; |
Dmitry Petrochenko | 407f5c1 | 2014-07-01 01:21:38 +0700 | [diff] [blame] | 2806 | if (result_reg.GetRegNum() == object_32reg.GetRegNum() || !IsByteRegister(result_reg)) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2807 | result_reg = AllocateByteRegister(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2808 | } |
| 2809 | |
| 2810 | // Assume that there is no match. |
| 2811 | LoadConstant(result_reg, 0); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2812 | LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2813 | |
Mark Mendell | ade54a2 | 2014-06-09 12:49:55 -0400 | [diff] [blame] | 2814 | // We will use this register to compare to memory below. |
| 2815 | // References are 32 bit in memory, and 64 bit in registers (in 64 bit mode). |
| 2816 | // For this reason, force allocation of a 32 bit register to use, so that the |
| 2817 | // compare to memory will be done using a 32 bit comparision. |
| 2818 | // The LoadRefDisp(s) below will work normally, even in 64 bit mode. |
| 2819 | RegStorage check_class = AllocTemp(); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2820 | |
| 2821 | // If Method* is already in a register, we can save a copy. |
| 2822 | RegLocation rl_method = mir_graph_->GetMethodLoc(); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2823 | int32_t offset_of_type = mirror::Array::DataOffset( |
| 2824 | sizeof(mirror::HeapReference<mirror::Class*>)).Int32Value() + |
| 2825 | (sizeof(mirror::HeapReference<mirror::Class*>) * type_idx); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2826 | |
| 2827 | if (rl_method.location == kLocPhysReg) { |
| 2828 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2829 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2830 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2831 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2832 | LoadRefDisp(rl_method.reg, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2833 | check_class, kNotVolatile); |
| 2834 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2835 | } |
| 2836 | } else { |
| 2837 | LoadCurrMethodDirect(check_class); |
| 2838 | if (use_declaring_class) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2839 | LoadRefDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2840 | check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2841 | } else { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 2842 | LoadRefDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), |
Andreas Gampe | 3c12c51 | 2014-06-24 18:46:29 +0000 | [diff] [blame] | 2843 | check_class, kNotVolatile); |
| 2844 | LoadRefDisp(check_class, offset_of_type, check_class, kNotVolatile); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2845 | } |
| 2846 | } |
| 2847 | |
| 2848 | // Compare the computed class to the class in the object. |
| 2849 | DCHECK_EQ(object.location, kLocPhysReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2850 | OpRegMem(kOpCmp, check_class, object.reg, mirror::Object::ClassOffset().Int32Value()); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2851 | |
| 2852 | // Set the low byte of the result to 0 or 1 from the compare condition code. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2853 | NewLIR2(kX86Set8R, result_reg.GetReg(), kX86CondEq); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2854 | |
| 2855 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 2856 | null_branchover->target = target; |
| 2857 | FreeTemp(check_class); |
| 2858 | if (IsTemp(result_reg)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2859 | OpRegCopy(rl_result.reg, result_reg); |
Mark Mendell | df8ee2e | 2014-01-27 16:37:47 -0800 | [diff] [blame] | 2860 | FreeTemp(result_reg); |
| 2861 | } |
| 2862 | StoreValue(rl_dest, rl_result); |
| 2863 | } |
| 2864 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2865 | void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, |
| 2866 | RegLocation rl_lhs, RegLocation rl_rhs) { |
| 2867 | OpKind op = kOpBkpt; |
| 2868 | bool is_div_rem = false; |
| 2869 | bool unary = false; |
| 2870 | bool shift_op = false; |
| 2871 | bool is_two_addr = false; |
| 2872 | RegLocation rl_result; |
| 2873 | switch (opcode) { |
| 2874 | case Instruction::NEG_INT: |
| 2875 | op = kOpNeg; |
| 2876 | unary = true; |
| 2877 | break; |
| 2878 | case Instruction::NOT_INT: |
| 2879 | op = kOpMvn; |
| 2880 | unary = true; |
| 2881 | break; |
| 2882 | case Instruction::ADD_INT_2ADDR: |
| 2883 | is_two_addr = true; |
| 2884 | // Fallthrough |
| 2885 | case Instruction::ADD_INT: |
| 2886 | op = kOpAdd; |
| 2887 | break; |
| 2888 | case Instruction::SUB_INT_2ADDR: |
| 2889 | is_two_addr = true; |
| 2890 | // Fallthrough |
| 2891 | case Instruction::SUB_INT: |
| 2892 | op = kOpSub; |
| 2893 | break; |
| 2894 | case Instruction::MUL_INT_2ADDR: |
| 2895 | is_two_addr = true; |
| 2896 | // Fallthrough |
| 2897 | case Instruction::MUL_INT: |
| 2898 | op = kOpMul; |
| 2899 | break; |
| 2900 | case Instruction::DIV_INT_2ADDR: |
| 2901 | is_two_addr = true; |
| 2902 | // Fallthrough |
| 2903 | case Instruction::DIV_INT: |
| 2904 | op = kOpDiv; |
| 2905 | is_div_rem = true; |
| 2906 | break; |
| 2907 | /* NOTE: returns in kArg1 */ |
| 2908 | case Instruction::REM_INT_2ADDR: |
| 2909 | is_two_addr = true; |
| 2910 | // Fallthrough |
| 2911 | case Instruction::REM_INT: |
| 2912 | op = kOpRem; |
| 2913 | is_div_rem = true; |
| 2914 | break; |
| 2915 | case Instruction::AND_INT_2ADDR: |
| 2916 | is_two_addr = true; |
| 2917 | // Fallthrough |
| 2918 | case Instruction::AND_INT: |
| 2919 | op = kOpAnd; |
| 2920 | break; |
| 2921 | case Instruction::OR_INT_2ADDR: |
| 2922 | is_two_addr = true; |
| 2923 | // Fallthrough |
| 2924 | case Instruction::OR_INT: |
| 2925 | op = kOpOr; |
| 2926 | break; |
| 2927 | case Instruction::XOR_INT_2ADDR: |
| 2928 | is_two_addr = true; |
| 2929 | // Fallthrough |
| 2930 | case Instruction::XOR_INT: |
| 2931 | op = kOpXor; |
| 2932 | break; |
| 2933 | case Instruction::SHL_INT_2ADDR: |
| 2934 | is_two_addr = true; |
| 2935 | // Fallthrough |
| 2936 | case Instruction::SHL_INT: |
| 2937 | shift_op = true; |
| 2938 | op = kOpLsl; |
| 2939 | break; |
| 2940 | case Instruction::SHR_INT_2ADDR: |
| 2941 | is_two_addr = true; |
| 2942 | // Fallthrough |
| 2943 | case Instruction::SHR_INT: |
| 2944 | shift_op = true; |
| 2945 | op = kOpAsr; |
| 2946 | break; |
| 2947 | case Instruction::USHR_INT_2ADDR: |
| 2948 | is_two_addr = true; |
| 2949 | // Fallthrough |
| 2950 | case Instruction::USHR_INT: |
| 2951 | shift_op = true; |
| 2952 | op = kOpLsr; |
| 2953 | break; |
| 2954 | default: |
| 2955 | LOG(FATAL) << "Invalid word arith op: " << opcode; |
| 2956 | } |
| 2957 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2958 | // Can we convert to a two address instruction? |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2959 | if (!is_two_addr && |
| 2960 | (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 2961 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low))) { |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 2962 | is_two_addr = true; |
| 2963 | } |
| 2964 | |
| 2965 | if (!GenerateTwoOperandInstructions()) { |
| 2966 | is_two_addr = false; |
| 2967 | } |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2968 | |
| 2969 | // Get the div/rem stuff out of the way. |
| 2970 | if (is_div_rem) { |
| 2971 | rl_result = GenDivRem(rl_dest, rl_lhs, rl_rhs, op == kOpDiv, true); |
| 2972 | StoreValue(rl_dest, rl_result); |
| 2973 | return; |
| 2974 | } |
| 2975 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2976 | // If we generate any memory access below, it will reference a dalvik reg. |
| 2977 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 2978 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2979 | if (unary) { |
| 2980 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2981 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2982 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2983 | OpRegReg(op, rl_result.reg, rl_lhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2984 | } else { |
| 2985 | if (shift_op) { |
| 2986 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2987 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2988 | LoadValueDirectFixed(rl_rhs, t_reg); |
| 2989 | if (is_two_addr) { |
| 2990 | // Can we do this directly into memory? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 2991 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2992 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 2993 | if (rl_result.location != kLocPhysReg) { |
| 2994 | // Okay, we can do this into memory |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 2995 | OpMemReg(op, rl_result, t_reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2996 | FreeTemp(t_reg); |
| 2997 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 2998 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 2999 | // Can do this directly into the result register |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3000 | OpRegReg(op, rl_result.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3001 | FreeTemp(t_reg); |
| 3002 | StoreFinalValue(rl_dest, rl_result); |
| 3003 | return; |
| 3004 | } |
| 3005 | } |
| 3006 | // Three address form, or we can't do directly. |
| 3007 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3008 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3009 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, t_reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3010 | FreeTemp(t_reg); |
| 3011 | } else { |
| 3012 | // Multiply is 3 operand only (sort of). |
| 3013 | if (is_two_addr && op != kOpMul) { |
| 3014 | // Can we do this directly into memory? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3015 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3016 | if (rl_result.location == kLocPhysReg) { |
Serguei Katkov | 366f8ae | 2014-04-15 16:55:26 +0700 | [diff] [blame] | 3017 | // Ensure res is in a core reg |
| 3018 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3019 | // Can we do this from memory directly? |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3020 | rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3021 | if (rl_rhs.location != kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3022 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3023 | StoreFinalValue(rl_dest, rl_result); |
| 3024 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3025 | } else if (!rl_rhs.reg.IsFloat()) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3026 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3027 | StoreFinalValue(rl_dest, rl_result); |
| 3028 | return; |
| 3029 | } |
| 3030 | } |
| 3031 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
Serguei Katkov | d293fb4 | 2014-05-19 15:45:42 +0700 | [diff] [blame] | 3032 | // It might happen rl_rhs and rl_dest are the same VR |
| 3033 | // in this case rl_dest is in reg after LoadValue while |
| 3034 | // rl_result is not updated yet, so do this |
| 3035 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3036 | if (rl_result.location != kLocPhysReg) { |
| 3037 | // Okay, we can do this into memory. |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 3038 | OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3039 | return; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3040 | } else if (!rl_result.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3041 | // Can do this directly into the result register. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3042 | OpRegReg(op, rl_result.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3043 | StoreFinalValue(rl_dest, rl_result); |
| 3044 | return; |
| 3045 | } else { |
| 3046 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3047 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3048 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3049 | } |
| 3050 | } else { |
| 3051 | // Try to use reg/memory instructions. |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 3052 | rl_lhs = UpdateLocTyped(rl_lhs, kCoreReg); |
| 3053 | rl_rhs = UpdateLocTyped(rl_rhs, kCoreReg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3054 | // We can't optimize with FP registers. |
| 3055 | if (!IsOperationSafeWithoutTemps(rl_lhs, rl_rhs)) { |
| 3056 | // Something is difficult, so fall back to the standard case. |
| 3057 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3058 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3059 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3060 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3061 | } else { |
| 3062 | // We can optimize by moving to result and using memory operands. |
| 3063 | if (rl_rhs.location != kLocPhysReg) { |
| 3064 | // Force LHS into result. |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3065 | // We should be careful with order here |
| 3066 | // If rl_dest and rl_lhs points to the same VR we should load first |
| 3067 | // If the are different we should find a register first for dest |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3068 | if (mir_graph_->SRegToVReg(rl_dest.s_reg_low) == |
| 3069 | mir_graph_->SRegToVReg(rl_lhs.s_reg_low)) { |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3070 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3071 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 3072 | // No-op if these are the same. |
| 3073 | OpRegCopy(rl_result.reg, rl_lhs.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3074 | } else { |
| 3075 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3076 | LoadValueDirect(rl_lhs, rl_result.reg); |
Serguei Katkov | 66da136 | 2014-03-14 13:33:33 +0700 | [diff] [blame] | 3077 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3078 | OpRegMem(op, rl_result.reg, rl_rhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3079 | } else if (rl_lhs.location != kLocPhysReg) { |
| 3080 | // RHS is in a register; LHS is in memory. |
| 3081 | if (op != kOpSub) { |
| 3082 | // Force RHS into result and operate on memory. |
| 3083 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3084 | OpRegCopy(rl_result.reg, rl_rhs.reg); |
| 3085 | OpRegMem(op, rl_result.reg, rl_lhs); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3086 | } else { |
| 3087 | // Subtraction isn't commutative. |
| 3088 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3089 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3090 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3091 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3092 | } |
| 3093 | } else { |
| 3094 | // Both are in registers. |
| 3095 | rl_lhs = LoadValue(rl_lhs, kCoreReg); |
| 3096 | rl_rhs = LoadValue(rl_rhs, kCoreReg); |
| 3097 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 3098 | OpRegRegReg(op, rl_result.reg, rl_lhs.reg, rl_rhs.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3099 | } |
| 3100 | } |
| 3101 | } |
| 3102 | } |
| 3103 | } |
| 3104 | StoreValue(rl_dest, rl_result); |
| 3105 | } |
| 3106 | |
| 3107 | bool X86Mir2Lir::IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs) { |
| 3108 | // If we have non-core registers, then we can't do good things. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3109 | if (rl_lhs.location == kLocPhysReg && rl_lhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3110 | return false; |
| 3111 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 3112 | if (rl_rhs.location == kLocPhysReg && rl_rhs.reg.IsFloat()) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 3113 | return false; |
| 3114 | } |
| 3115 | |
| 3116 | // Everything will be fine :-). |
| 3117 | return true; |
| 3118 | } |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3119 | |
| 3120 | void X86Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3121 | if (!cu_->target64) { |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3122 | Mir2Lir::GenIntToLong(rl_dest, rl_src); |
| 3123 | return; |
| 3124 | } |
Serguei Katkov | e63d9d4 | 2014-06-25 00:25:35 +0700 | [diff] [blame] | 3125 | rl_src = UpdateLocTyped(rl_src, kCoreReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3126 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 3127 | if (rl_src.location == kLocPhysReg) { |
| 3128 | NewLIR2(kX86MovsxdRR, rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
| 3129 | } else { |
| 3130 | int displacement = SRegOffset(rl_src.s_reg_low); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3131 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3132 | LIR *m = NewLIR3(kX86MovsxdRM, rl_result.reg.GetReg(), rs_rX86_SP.GetReg(), |
| 3133 | displacement + LOWORD_OFFSET); |
| 3134 | AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, |
| 3135 | true /* is_load */, true /* is_64bit */); |
| 3136 | } |
| 3137 | StoreValueWide(rl_dest, rl_result); |
| 3138 | } |
| 3139 | |
| 3140 | void X86Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, |
| 3141 | RegLocation rl_src1, RegLocation rl_shift) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 3142 | if (!cu_->target64) { |
Yixin Shou | f40f890 | 2014-08-14 14:10:32 -0400 | [diff] [blame] | 3143 | // Long shift operations in 32-bit. Use shld or shrd to create a 32-bit register filled from |
| 3144 | // the other half, shift the other half, if the shift amount is less than 32 we're done, |
| 3145 | // otherwise move one register to the other and place zero or sign bits in the other. |
| 3146 | LIR* branch; |
| 3147 | FlushAllRegs(); |
| 3148 | LockCallTemps(); |
| 3149 | LoadValueDirectFixed(rl_shift, rs_rCX); |
| 3150 | RegStorage r_tmp = RegStorage::MakeRegPair(rs_rAX, rs_rDX); |
| 3151 | LoadValueDirectWideFixed(rl_src1, r_tmp); |
| 3152 | switch (opcode) { |
| 3153 | case Instruction::SHL_LONG: |
| 3154 | case Instruction::SHL_LONG_2ADDR: |
| 3155 | NewLIR3(kX86Shld32RRC, r_tmp.GetHighReg(), r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3156 | NewLIR2(kX86Sal32RC, r_tmp.GetLowReg(), rs_rCX.GetReg()); |
| 3157 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3158 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3159 | OpRegCopy(r_tmp.GetHigh(), r_tmp.GetLow()); |
| 3160 | LoadConstant(r_tmp.GetLow(), 0); |
| 3161 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3162 | break; |
| 3163 | case Instruction::SHR_LONG: |
| 3164 | case Instruction::SHR_LONG_2ADDR: |
| 3165 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3166 | NewLIR2(kX86Sar32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3167 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3168 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3169 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3170 | NewLIR2(kX86Sar32RI, r_tmp.GetHighReg(), 31); |
| 3171 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3172 | break; |
| 3173 | case Instruction::USHR_LONG: |
| 3174 | case Instruction::USHR_LONG_2ADDR: |
| 3175 | NewLIR3(kX86Shrd32RRC, r_tmp.GetLowReg(), r_tmp.GetHighReg(), |
| 3176 | rs_rCX.GetReg()); |
| 3177 | NewLIR2(kX86Shr32RC, r_tmp.GetHighReg(), rs_rCX.GetReg()); |
| 3178 | NewLIR2(kX86Test8RI, rs_rCX.GetReg(), 32); |
| 3179 | branch = NewLIR2(kX86Jcc8, 0, kX86CondZ); |
| 3180 | OpRegCopy(r_tmp.GetLow(), r_tmp.GetHigh()); |
| 3181 | LoadConstant(r_tmp.GetHigh(), 0); |
| 3182 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 3183 | break; |
| 3184 | default: |
| 3185 | LOG(FATAL) << "Unexpected case: " << opcode; |
| 3186 | return; |
| 3187 | } |
| 3188 | RegLocation rl_result = LocCReturnWide(); |
| 3189 | StoreValueWide(rl_dest, rl_result); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3190 | return; |
| 3191 | } |
| 3192 | |
| 3193 | bool is_two_addr = false; |
| 3194 | OpKind op = kOpBkpt; |
| 3195 | RegLocation rl_result; |
| 3196 | |
| 3197 | switch (opcode) { |
| 3198 | case Instruction::SHL_LONG_2ADDR: |
| 3199 | is_two_addr = true; |
| 3200 | // Fallthrough |
| 3201 | case Instruction::SHL_LONG: |
| 3202 | op = kOpLsl; |
| 3203 | break; |
| 3204 | case Instruction::SHR_LONG_2ADDR: |
| 3205 | is_two_addr = true; |
| 3206 | // Fallthrough |
| 3207 | case Instruction::SHR_LONG: |
| 3208 | op = kOpAsr; |
| 3209 | break; |
| 3210 | case Instruction::USHR_LONG_2ADDR: |
| 3211 | is_two_addr = true; |
| 3212 | // Fallthrough |
| 3213 | case Instruction::USHR_LONG: |
| 3214 | op = kOpLsr; |
| 3215 | break; |
| 3216 | default: |
| 3217 | op = kOpBkpt; |
| 3218 | } |
| 3219 | |
| 3220 | // X86 doesn't require masking and must use ECX. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 3221 | RegStorage t_reg = TargetReg(kCount, kNotWide); // rCX |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3222 | LoadValueDirectFixed(rl_shift, t_reg); |
| 3223 | if (is_two_addr) { |
| 3224 | // Can we do this directly into memory? |
| 3225 | rl_result = UpdateLocWideTyped(rl_dest, kCoreReg); |
| 3226 | if (rl_result.location != kLocPhysReg) { |
| 3227 | // Okay, we can do this into memory |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 3228 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a014776 | 2014-06-06 18:38:49 -0700 | [diff] [blame] | 3229 | OpMemReg(op, rl_result, t_reg.GetReg()); |
| 3230 | } else if (!rl_result.reg.IsFloat()) { |
| 3231 | // Can do this directly into the result register |
| 3232 | OpRegReg(op, rl_result.reg, t_reg); |
| 3233 | StoreFinalValueWide(rl_dest, rl_result); |
| 3234 | } |
| 3235 | } else { |
| 3236 | // Three address form, or we can't do directly. |
| 3237 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 3238 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 3239 | OpRegRegReg(op, rl_result.reg, rl_src1.reg, t_reg); |
| 3240 | StoreFinalValueWide(rl_dest, rl_result); |
| 3241 | } |
| 3242 | |
| 3243 | FreeTemp(t_reg); |
| 3244 | } |
| 3245 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 3246 | } // namespace art |