Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "arm64_lir.h" |
| 18 | #include "codegen_arm64.h" |
| 19 | #include "dex/quick/mir_to_lir-inl.h" |
| 20 | |
| 21 | namespace art { |
| 22 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 23 | /* This file contains codegen for the A64 ISA. */ |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 24 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 25 | static int32_t EncodeImmSingle(uint32_t bits) { |
| 26 | /* |
| 27 | * Valid values will have the form: |
| 28 | * |
| 29 | * aBbb.bbbc.defg.h000.0000.0000.0000.0000 |
| 30 | * |
| 31 | * where B = not(b). In other words, if b == 1, then B == 0 and viceversa. |
| 32 | */ |
| 33 | |
| 34 | // bits[19..0] are cleared. |
| 35 | if ((bits & 0x0007ffff) != 0) |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 36 | return -1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 37 | |
| 38 | // bits[29..25] are all set or all cleared. |
| 39 | uint32_t b_pattern = (bits >> 16) & 0x3e00; |
| 40 | if (b_pattern != 0 && b_pattern != 0x3e00) |
| 41 | return -1; |
| 42 | |
| 43 | // bit[30] and bit[29] are opposite. |
| 44 | if (((bits ^ (bits << 1)) & 0x40000000) == 0) |
| 45 | return -1; |
| 46 | |
| 47 | // bits: aBbb.bbbc.defg.h000.0000.0000.0000.0000 |
| 48 | // bit7: a000.0000 |
| 49 | uint32_t bit7 = ((bits >> 31) & 0x1) << 7; |
| 50 | // bit6: 0b00.0000 |
| 51 | uint32_t bit6 = ((bits >> 29) & 0x1) << 6; |
| 52 | // bit5_to_0: 00cd.efgh |
| 53 | uint32_t bit5_to_0 = (bits >> 19) & 0x3f; |
| 54 | return (bit7 | bit6 | bit5_to_0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 55 | } |
| 56 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 57 | static int32_t EncodeImmDouble(uint64_t bits) { |
| 58 | /* |
| 59 | * Valid values will have the form: |
| 60 | * |
| 61 | * aBbb.bbbb.bbcd.efgh.0000.0000.0000.0000 |
| 62 | * 0000.0000.0000.0000.0000.0000.0000.0000 |
| 63 | * |
| 64 | * where B = not(b). |
| 65 | */ |
| 66 | |
| 67 | // bits[47..0] are cleared. |
| 68 | if ((bits & UINT64_C(0xffffffffffff)) != 0) |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 69 | return -1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 70 | |
| 71 | // bits[61..54] are all set or all cleared. |
| 72 | uint32_t b_pattern = (bits >> 48) & 0x3fc0; |
| 73 | if (b_pattern != 0 && b_pattern != 0x3fc0) |
| 74 | return -1; |
| 75 | |
| 76 | // bit[62] and bit[61] are opposite. |
| 77 | if (((bits ^ (bits << 1)) & UINT64_C(0x4000000000000000)) == 0) |
| 78 | return -1; |
| 79 | |
| 80 | // bit7: a000.0000 |
| 81 | uint32_t bit7 = ((bits >> 63) & 0x1) << 7; |
| 82 | // bit6: 0b00.0000 |
| 83 | uint32_t bit6 = ((bits >> 61) & 0x1) << 6; |
| 84 | // bit5_to_0: 00cd.efgh |
| 85 | uint32_t bit5_to_0 = (bits >> 48) & 0x3f; |
| 86 | return (bit7 | bit6 | bit5_to_0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 87 | } |
| 88 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 89 | LIR* Arm64Mir2Lir::LoadFPConstantValue(int r_dest, int32_t value) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 90 | DCHECK(RegStorage::IsSingle(r_dest)); |
| 91 | if (value == 0) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 92 | return NewLIR2(kA64Fmov2sw, r_dest, rwzr); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 93 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 94 | int32_t encoded_imm = EncodeImmSingle((uint32_t)value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 95 | if (encoded_imm >= 0) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 96 | return NewLIR2(kA64Fmov2fI, r_dest, encoded_imm); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 97 | } |
| 98 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 99 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 100 | LIR* data_target = ScanLiteralPool(literal_list_, value, 0); |
| 101 | if (data_target == NULL) { |
| 102 | data_target = AddWordData(&literal_list_, value); |
| 103 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 104 | |
| 105 | LIR* load_pc_rel = RawLIR(current_dalvik_offset_, kA64Ldr2fp, |
| 106 | r_dest, 0, 0, 0, 0, data_target); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 107 | SetMemRefType(load_pc_rel, true, kLiteral); |
| 108 | AppendLIR(load_pc_rel); |
| 109 | return load_pc_rel; |
| 110 | } |
| 111 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 112 | LIR* Arm64Mir2Lir::LoadFPConstantValueWide(int r_dest, int64_t value) { |
| 113 | DCHECK(RegStorage::IsDouble(r_dest)); |
| 114 | if (value == 0) { |
| 115 | return NewLIR2(kA64Fmov2Sx, r_dest, rwzr); |
| 116 | } else { |
| 117 | int32_t encoded_imm = EncodeImmDouble(value); |
| 118 | if (encoded_imm >= 0) { |
| 119 | return NewLIR2(FWIDE(kA64Fmov2fI), r_dest, encoded_imm); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 120 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | // No short form - load from the literal pool. |
| 124 | int32_t val_lo = Low32Bits(value); |
| 125 | int32_t val_hi = High32Bits(value); |
| 126 | LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); |
| 127 | if (data_target == NULL) { |
| 128 | data_target = AddWideData(&literal_list_, val_lo, val_hi); |
| 129 | } |
| 130 | |
| 131 | DCHECK(RegStorage::IsFloat(r_dest)); |
| 132 | LIR* load_pc_rel = RawLIR(current_dalvik_offset_, FWIDE(kA64Ldr2fp), |
| 133 | r_dest, 0, 0, 0, 0, data_target); |
| 134 | SetMemRefType(load_pc_rel, true, kLiteral); |
| 135 | AppendLIR(load_pc_rel); |
| 136 | return load_pc_rel; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 137 | } |
| 138 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 139 | static int CountLeadingZeros(bool is_wide, uint64_t value) { |
| 140 | return (is_wide) ? __builtin_clzl(value) : __builtin_clz((uint32_t)value); |
| 141 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 142 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 143 | static int CountTrailingZeros(bool is_wide, uint64_t value) { |
| 144 | return (is_wide) ? __builtin_ctzl(value) : __builtin_ctz((uint32_t)value); |
| 145 | } |
| 146 | |
| 147 | static int CountSetBits(bool is_wide, uint64_t value) { |
| 148 | return ((is_wide) ? |
| 149 | __builtin_popcountl(value) : __builtin_popcount((uint32_t)value)); |
| 150 | } |
| 151 | |
| 152 | /** |
| 153 | * @brief Try encoding an immediate in the form required by logical instructions. |
| 154 | * |
| 155 | * @param is_wide Whether @p value is a 64-bit (as opposed to 32-bit) value. |
| 156 | * @param value An integer to be encoded. This is interpreted as 64-bit if @p is_wide is true and as |
| 157 | * 32-bit if @p is_wide is false. |
| 158 | * @return A non-negative integer containing the encoded immediate or -1 if the encoding failed. |
| 159 | * @note This is the inverse of Arm64Mir2Lir::DecodeLogicalImmediate(). |
| 160 | */ |
| 161 | int Arm64Mir2Lir::EncodeLogicalImmediate(bool is_wide, uint64_t value) { |
| 162 | unsigned n, imm_s, imm_r; |
| 163 | |
| 164 | // Logical immediates are encoded using parameters n, imm_s and imm_r using |
| 165 | // the following table: |
| 166 | // |
| 167 | // N imms immr size S R |
| 168 | // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) |
| 169 | // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) |
| 170 | // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) |
| 171 | // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) |
| 172 | // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) |
| 173 | // 0 11110s xxxxxr 2 UInt(s) UInt(r) |
| 174 | // (s bits must not be all set) |
| 175 | // |
| 176 | // A pattern is constructed of size bits, where the least significant S+1 |
| 177 | // bits are set. The pattern is rotated right by R, and repeated across a |
| 178 | // 32 or 64-bit value, depending on destination register width. |
| 179 | // |
| 180 | // To test if an arbitary immediate can be encoded using this scheme, an |
| 181 | // iterative algorithm is used. |
| 182 | // |
| 183 | |
| 184 | // 1. If the value has all set or all clear bits, it can't be encoded. |
| 185 | if (value == 0 || value == ~UINT64_C(0) || |
| 186 | (!is_wide && (uint32_t)value == ~UINT32_C(0))) { |
| 187 | return -1; |
| 188 | } |
| 189 | |
| 190 | unsigned lead_zero = CountLeadingZeros(is_wide, value); |
| 191 | unsigned lead_one = CountLeadingZeros(is_wide, ~value); |
| 192 | unsigned trail_zero = CountTrailingZeros(is_wide, value); |
| 193 | unsigned trail_one = CountTrailingZeros(is_wide, ~value); |
| 194 | unsigned set_bits = CountSetBits(is_wide, value); |
| 195 | |
| 196 | // The fixed bits in the immediate s field. |
| 197 | // If width == 64 (X reg), start at 0xFFFFFF80. |
| 198 | // If width == 32 (W reg), start at 0xFFFFFFC0, as the iteration for 64-bit |
| 199 | // widths won't be executed. |
| 200 | unsigned width = (is_wide) ? 64 : 32; |
| 201 | int imm_s_fixed = (is_wide) ? -128 : -64; |
| 202 | int imm_s_mask = 0x3f; |
| 203 | |
| 204 | for (;;) { |
| 205 | // 2. If the value is two bits wide, it can be encoded. |
| 206 | if (width == 2) { |
| 207 | n = 0; |
| 208 | imm_s = 0x3C; |
| 209 | imm_r = (value & 3) - 1; |
| 210 | break; |
| 211 | } |
| 212 | |
| 213 | n = (width == 64) ? 1 : 0; |
| 214 | imm_s = ((imm_s_fixed | (set_bits - 1)) & imm_s_mask); |
| 215 | if ((lead_zero + set_bits) == width) { |
| 216 | imm_r = 0; |
| 217 | } else { |
| 218 | imm_r = (lead_zero > 0) ? (width - trail_zero) : lead_one; |
| 219 | } |
| 220 | |
| 221 | // 3. If the sum of leading zeros, trailing zeros and set bits is |
| 222 | // equal to the bit width of the value, it can be encoded. |
| 223 | if (lead_zero + trail_zero + set_bits == width) { |
| 224 | break; |
| 225 | } |
| 226 | |
| 227 | // 4. If the sum of leading ones, trailing ones and unset bits in the |
| 228 | // value is equal to the bit width of the value, it can be encoded. |
| 229 | if (lead_one + trail_one + (width - set_bits) == width) { |
| 230 | break; |
| 231 | } |
| 232 | |
| 233 | // 5. If the most-significant half of the bitwise value is equal to |
| 234 | // the least-significant half, return to step 2 using the |
| 235 | // least-significant half of the value. |
| 236 | uint64_t mask = (UINT64_C(1) << (width >> 1)) - 1; |
| 237 | if ((value & mask) == ((value >> (width >> 1)) & mask)) { |
| 238 | width >>= 1; |
| 239 | set_bits >>= 1; |
| 240 | imm_s_fixed >>= 1; |
| 241 | continue; |
| 242 | } |
| 243 | |
| 244 | // 6. Otherwise, the value can't be encoded. |
| 245 | return -1; |
| 246 | } |
| 247 | |
| 248 | return (n << 12 | imm_r << 6 | imm_s); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 252 | return false; // (ModifiedImmediate(value) >= 0) || (ModifiedImmediate(~value) >= 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 253 | } |
| 254 | |
| 255 | bool Arm64Mir2Lir::InexpensiveConstantFloat(int32_t value) { |
| 256 | return EncodeImmSingle(value) >= 0; |
| 257 | } |
| 258 | |
| 259 | bool Arm64Mir2Lir::InexpensiveConstantLong(int64_t value) { |
| 260 | return InexpensiveConstantInt(High32Bits(value)) && InexpensiveConstantInt(Low32Bits(value)); |
| 261 | } |
| 262 | |
| 263 | bool Arm64Mir2Lir::InexpensiveConstantDouble(int64_t value) { |
| 264 | return EncodeImmDouble(value) >= 0; |
| 265 | } |
| 266 | |
| 267 | /* |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 268 | * Load a immediate using one single instruction when possible; otherwise |
| 269 | * use a pair of movz and movk instructions. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 270 | * |
| 271 | * No additional register clobbering operation performed. Use this version when |
| 272 | * 1) r_dest is freshly returned from AllocTemp or |
| 273 | * 2) The codegen is under fixed register usage |
| 274 | */ |
| 275 | LIR* Arm64Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { |
| 276 | LIR* res; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 277 | |
| 278 | if (r_dest.IsFloat()) { |
| 279 | return LoadFPConstantValue(r_dest.GetReg(), value); |
| 280 | } |
| 281 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 282 | // Loading SP/ZR with an immediate is not supported. |
| 283 | DCHECK_NE(r_dest.GetReg(), rwsp); |
| 284 | DCHECK_NE(r_dest.GetReg(), rwzr); |
| 285 | |
| 286 | // Compute how many movk, movz instructions are needed to load the value. |
| 287 | uint16_t high_bits = High16Bits(value); |
| 288 | uint16_t low_bits = Low16Bits(value); |
| 289 | |
| 290 | bool low_fast = ((uint16_t)(low_bits + 1) <= 1); |
| 291 | bool high_fast = ((uint16_t)(high_bits + 1) <= 1); |
| 292 | |
| 293 | if (LIKELY(low_fast || high_fast)) { |
| 294 | // 1 instruction is enough to load the immediate. |
| 295 | if (LIKELY(low_bits == high_bits)) { |
| 296 | // Value is either 0 or -1: we can just use wzr. |
| 297 | ArmOpcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; |
| 298 | res = NewLIR2(opcode, r_dest.GetReg(), rwzr); |
| 299 | } else { |
| 300 | uint16_t uniform_bits, useful_bits; |
| 301 | int shift; |
| 302 | |
| 303 | if (LIKELY(high_fast)) { |
| 304 | shift = 0; |
| 305 | uniform_bits = high_bits; |
| 306 | useful_bits = low_bits; |
| 307 | } else { |
| 308 | shift = 1; |
| 309 | uniform_bits = low_bits; |
| 310 | useful_bits = high_bits; |
| 311 | } |
| 312 | |
| 313 | if (UNLIKELY(uniform_bits != 0)) { |
| 314 | res = NewLIR3(kA64Movn3rdM, r_dest.GetReg(), ~useful_bits, shift); |
| 315 | } else { |
| 316 | res = NewLIR3(kA64Movz3rdM, r_dest.GetReg(), useful_bits, shift); |
| 317 | } |
| 318 | } |
| 319 | } else { |
| 320 | // movk, movz require 2 instructions. Try detecting logical immediates. |
| 321 | int log_imm = EncodeLogicalImmediate(/*is_wide=*/false, value); |
| 322 | if (log_imm >= 0) { |
| 323 | res = NewLIR3(kA64Orr3Rrl, r_dest.GetReg(), rwzr, log_imm); |
| 324 | } else { |
| 325 | // Use 2 instructions. |
| 326 | res = NewLIR3(kA64Movz3rdM, r_dest.GetReg(), low_bits, 0); |
| 327 | NewLIR3(kA64Movk3rdM, r_dest.GetReg(), high_bits, 1); |
| 328 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 329 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 330 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 331 | return res; |
| 332 | } |
| 333 | |
| 334 | LIR* Arm64Mir2Lir::OpUnconditionalBranch(LIR* target) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 335 | LIR* res = NewLIR1(kA64B1t, 0 /* offset to be patched during assembly */); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 336 | res->target = target; |
| 337 | return res; |
| 338 | } |
| 339 | |
| 340 | LIR* Arm64Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 341 | LIR* branch = NewLIR2(kA64B2ct, ArmConditionEncoding(cc), |
| 342 | 0 /* offset to be patched */); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 343 | branch->target = target; |
| 344 | return branch; |
| 345 | } |
| 346 | |
| 347 | LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 348 | ArmOpcode opcode = kA64Brk1d; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 349 | switch (op) { |
| 350 | case kOpBlx: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 351 | opcode = kA64Blr1x; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 352 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 353 | // TODO(Arm64): port kThumbBx. |
| 354 | // case kOpBx: |
| 355 | // opcode = kThumbBx; |
| 356 | // break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 357 | default: |
| 358 | LOG(FATAL) << "Bad opcode " << op; |
| 359 | } |
| 360 | return NewLIR1(opcode, r_dest_src.GetReg()); |
| 361 | } |
| 362 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 363 | LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) { |
| 364 | ArmOpcode wide = (r_dest_src1.Is64Bit()) ? WIDE(0) : UNWIDE(0); |
| 365 | CHECK_EQ(r_dest_src1.Is64Bit(), r_src2.Is64Bit()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 366 | ArmOpcode opcode = kA64Brk1d; |
| 367 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 368 | switch (op) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 369 | case kOpCmn: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 370 | opcode = kA64Cmn3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 371 | break; |
| 372 | case kOpCmp: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 373 | opcode = kA64Cmp3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 374 | break; |
| 375 | case kOpMov: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 376 | opcode = kA64Mov2rr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 377 | break; |
| 378 | case kOpMvn: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 379 | opcode = kA64Mvn2rr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 380 | break; |
| 381 | case kOpNeg: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 382 | opcode = kA64Neg3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 383 | break; |
| 384 | case kOpTst: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 385 | opcode = kA64Tst3rro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 386 | break; |
| 387 | case kOpRev: |
| 388 | DCHECK_EQ(shift, 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 389 | // Binary, but rm is encoded twice. |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 390 | return NewLIR3(kA64Rev2rr | wide, r_dest_src1.GetReg(), r_src2.GetReg(), r_src2.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 391 | break; |
| 392 | case kOpRevsh: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 393 | // Binary, but rm is encoded twice. |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 394 | return NewLIR3(kA64Rev162rr | wide, r_dest_src1.GetReg(), r_src2.GetReg(), r_src2.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 395 | break; |
| 396 | case kOp2Byte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 397 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
| 398 | // "sbfx r1, r2, #imm1, #imm2" is "sbfm r1, r2, #imm1, #(imm1 + imm2 - 1)". |
| 399 | // For now we use sbfm directly. |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 400 | return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 7); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 401 | case kOp2Short: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 402 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
| 403 | // For now we use sbfm rather than its alias, sbfx. |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 404 | return NewLIR4(kA64Sbfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 405 | case kOp2Char: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 406 | // "ubfx r1, r2, #imm1, #imm2" is "ubfm r1, r2, #imm1, #(imm1 + imm2 - 1)". |
| 407 | // For now we use ubfm directly. |
| 408 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 409 | return NewLIR4(kA64Ubfm4rrdd | wide, r_dest_src1.GetReg(), r_src2.GetReg(), 0, 15); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 410 | default: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 411 | return OpRegRegRegShift(op, r_dest_src1.GetReg(), r_dest_src1.GetReg(), r_src2.GetReg(), shift); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 412 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 413 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 414 | DCHECK(!IsPseudoLirOp(opcode)); |
| 415 | if (EncodingMap[opcode].flags & IS_BINARY_OP) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 416 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 417 | return NewLIR2(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 418 | } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 419 | ArmEncodingKind kind = EncodingMap[opcode].field_loc[2].kind; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 420 | if (kind == kFmtShift) { |
| 421 | return NewLIR3(opcode | wide, r_dest_src1.GetReg(), r_src2.GetReg(), shift); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 422 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 423 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 424 | |
| 425 | LOG(FATAL) << "Unexpected encoding operand count"; |
| 426 | return NULL; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 427 | } |
| 428 | |
| 429 | LIR* Arm64Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 430 | return OpRegRegShift(op, r_dest_src1, r_src2, ENCODE_NO_SHIFT); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | LIR* Arm64Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) { |
| 434 | UNIMPLEMENTED(FATAL); |
| 435 | return nullptr; |
| 436 | } |
| 437 | |
| 438 | LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { |
| 439 | UNIMPLEMENTED(FATAL); |
| 440 | return nullptr; |
| 441 | } |
| 442 | |
| 443 | LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 444 | LOG(FATAL) << "Unexpected use of OpCondRegReg for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 445 | return NULL; |
| 446 | } |
| 447 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 448 | LIR* Arm64Mir2Lir::OpRegRegRegShift(OpKind op, int r_dest, int r_src1, |
| 449 | int r_src2, int shift, bool is_wide) { |
| 450 | ArmOpcode opcode = kA64Brk1d; |
| 451 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 452 | switch (op) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 453 | case kOpAdd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 454 | opcode = kA64Add4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 455 | break; |
| 456 | case kOpSub: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 457 | opcode = kA64Sub4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 458 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 459 | // case kOpRsub: |
| 460 | // opcode = kA64RsubWWW; |
| 461 | // break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 462 | case kOpAdc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 463 | opcode = kA64Adc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 464 | break; |
| 465 | case kOpAnd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 466 | opcode = kA64And4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 467 | break; |
| 468 | case kOpXor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 469 | opcode = kA64Eor4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 470 | break; |
| 471 | case kOpMul: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 472 | opcode = kA64Mul3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 473 | break; |
| 474 | case kOpDiv: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 475 | opcode = kA64Sdiv3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 476 | break; |
| 477 | case kOpOr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 478 | opcode = kA64Orr4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 479 | break; |
| 480 | case kOpSbc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 481 | opcode = kA64Sbc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 482 | break; |
| 483 | case kOpLsl: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 484 | opcode = kA64Lsl3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 485 | break; |
| 486 | case kOpLsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 487 | opcode = kA64Lsr3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 488 | break; |
| 489 | case kOpAsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 490 | opcode = kA64Asr3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 491 | break; |
| 492 | case kOpRor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 493 | opcode = kA64Ror3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 494 | break; |
| 495 | default: |
| 496 | LOG(FATAL) << "Bad opcode: " << op; |
| 497 | break; |
| 498 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 499 | |
| 500 | // The instructions above belong to two kinds: |
| 501 | // - 4-operands instructions, where the last operand is a shift/extend immediate, |
| 502 | // - 3-operands instructions with no shift/extend. |
| 503 | ArmOpcode widened_opcode = (is_wide) ? WIDE(opcode) : opcode; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 504 | if (EncodingMap[opcode].flags & IS_QUAD_OP) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 505 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
| 506 | return NewLIR4(widened_opcode, r_dest, r_src1, r_src2, shift); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 507 | } else { |
| 508 | DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 509 | DCHECK_EQ(shift, ENCODE_NO_SHIFT); |
| 510 | return NewLIR3(widened_opcode, r_dest, r_src1, r_src2); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 511 | } |
| 512 | } |
| 513 | |
| 514 | LIR* Arm64Mir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 515 | return OpRegRegRegShift(op, r_dest.GetReg(), r_src1.GetReg(), r_src2.GetReg(), ENCODE_NO_SHIFT); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | LIR* Arm64Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { |
| 519 | LIR* res; |
| 520 | bool neg = (value < 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 521 | int64_t abs_value = (neg) ? -value : value; |
| 522 | ArmOpcode opcode = kA64Brk1d; |
| 523 | ArmOpcode alt_opcode = kA64Brk1d; |
| 524 | int32_t log_imm = -1; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 525 | bool is_wide = r_dest.Is64Bit(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 526 | ArmOpcode wide = (is_wide) ? WIDE(0) : UNWIDE(0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 527 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 528 | switch (op) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 529 | case kOpLsl: { |
| 530 | // "lsl w1, w2, #imm" is an alias of "ubfm w1, w2, #(-imm MOD 32), #(31-imm)" |
| 531 | // and "lsl x1, x2, #imm" of "ubfm x1, x2, #(-imm MOD 32), #(31-imm)". |
| 532 | // For now, we just use ubfm directly. |
| 533 | int max_value = (is_wide) ? 64 : 32; |
| 534 | return NewLIR4(kA64Ubfm4rrdd | wide, r_dest.GetReg(), r_src1.GetReg(), |
| 535 | (-value) & (max_value - 1), max_value - value); |
| 536 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 537 | case kOpLsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 538 | return NewLIR3(kA64Lsr3rrd | wide, r_dest.GetReg(), r_src1.GetReg(), value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 539 | case kOpAsr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 540 | return NewLIR3(kA64Asr3rrd | wide, r_dest.GetReg(), r_src1.GetReg(), value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 541 | case kOpRor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 542 | // "ror r1, r2, #imm" is an alias of "extr r1, r2, r2, #imm". |
| 543 | // For now, we just use extr directly. |
| 544 | return NewLIR4(kA64Extr4rrrd | wide, r_dest.GetReg(), r_src1.GetReg(), r_src1.GetReg(), |
| 545 | value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 546 | case kOpAdd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 547 | neg = !neg; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 548 | // Note: intentional fallthrough |
| 549 | case kOpSub: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 550 | // Add and sub below read/write sp rather than xzr. |
| 551 | if (abs_value < 0x1000) { |
| 552 | opcode = (neg) ? kA64Add4RRdT : kA64Sub4RRdT; |
| 553 | return NewLIR4(opcode | wide, r_dest.GetReg(), r_src1.GetReg(), abs_value, 0); |
| 554 | } else if ((abs_value & UINT64_C(0xfff)) == 0 && ((abs_value >> 12) < 0x1000)) { |
| 555 | opcode = (neg) ? kA64Add4RRdT : kA64Sub4RRdT; |
| 556 | return NewLIR4(opcode | wide, r_dest.GetReg(), r_src1.GetReg(), abs_value >> 12, 1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 557 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 558 | log_imm = -1; |
| 559 | alt_opcode = (neg) ? kA64Add4rrro : kA64Sub4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 560 | } |
| 561 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 562 | // case kOpRsub: |
| 563 | // opcode = kThumb2RsubRRI8M; |
| 564 | // alt_opcode = kThumb2RsubRRR; |
| 565 | // break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 566 | case kOpAdc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 567 | log_imm = -1; |
| 568 | alt_opcode = kA64Adc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 569 | break; |
| 570 | case kOpSbc: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 571 | log_imm = -1; |
| 572 | alt_opcode = kA64Sbc3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 573 | break; |
| 574 | case kOpOr: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 575 | log_imm = EncodeLogicalImmediate(is_wide, value); |
| 576 | opcode = kA64Orr3Rrl; |
| 577 | alt_opcode = kA64Orr4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 578 | break; |
| 579 | case kOpAnd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 580 | log_imm = EncodeLogicalImmediate(is_wide, value); |
| 581 | opcode = kA64And3Rrl; |
| 582 | alt_opcode = kA64And4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 583 | break; |
| 584 | case kOpXor: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 585 | log_imm = EncodeLogicalImmediate(is_wide, value); |
| 586 | opcode = kA64Eor3Rrl; |
| 587 | alt_opcode = kA64Eor4rrro; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 588 | break; |
| 589 | case kOpMul: |
| 590 | // TUNING: power of 2, shift & add |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 591 | log_imm = -1; |
| 592 | alt_opcode = kA64Mul3rrr; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 593 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 594 | default: |
| 595 | LOG(FATAL) << "Bad opcode: " << op; |
| 596 | } |
| 597 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 598 | if (log_imm >= 0) { |
| 599 | return NewLIR3(opcode | wide, r_dest.GetReg(), r_src1.GetReg(), log_imm); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 600 | } else { |
| 601 | RegStorage r_scratch = AllocTemp(); |
| 602 | LoadConstant(r_scratch, value); |
| 603 | if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) |
| 604 | res = NewLIR4(alt_opcode, r_dest.GetReg(), r_src1.GetReg(), r_scratch.GetReg(), 0); |
| 605 | else |
| 606 | res = NewLIR3(alt_opcode, r_dest.GetReg(), r_src1.GetReg(), r_scratch.GetReg()); |
| 607 | FreeTemp(r_scratch); |
| 608 | return res; |
| 609 | } |
| 610 | } |
| 611 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 612 | LIR* Arm64Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 613 | return OpRegImm64(op, r_dest_src1, static_cast<int64_t>(value), /*is_wide*/false); |
| 614 | } |
| 615 | |
| 616 | LIR* Arm64Mir2Lir::OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value, bool is_wide) { |
| 617 | ArmOpcode wide = (is_wide) ? WIDE(0) : UNWIDE(0); |
| 618 | ArmOpcode opcode = kA64Brk1d; |
| 619 | ArmOpcode neg_opcode = kA64Brk1d; |
| 620 | bool shift; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 621 | bool neg = (value < 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 622 | uint64_t abs_value = (neg) ? -value : value; |
| 623 | |
| 624 | if (LIKELY(abs_value < 0x1000)) { |
| 625 | // abs_value is a 12-bit immediate. |
| 626 | shift = false; |
| 627 | } else if ((abs_value & UINT64_C(0xfff)) == 0 && ((abs_value >> 12) < 0x1000)) { |
| 628 | // abs_value is a shifted 12-bit immediate. |
| 629 | shift = true; |
| 630 | abs_value >>= 12; |
| 631 | } else { |
| 632 | RegStorage r_tmp = AllocTemp(); |
| 633 | LIR* res = LoadConstant(r_tmp, value); |
| 634 | OpRegReg(op, r_dest_src1, r_tmp); |
| 635 | FreeTemp(r_tmp); |
| 636 | return res; |
| 637 | } |
| 638 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 639 | switch (op) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 640 | case kOpAdd: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 641 | neg_opcode = kA64Sub4RRdT; |
| 642 | opcode = kA64Add4RRdT; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 643 | break; |
| 644 | case kOpSub: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 645 | neg_opcode = kA64Add4RRdT; |
| 646 | opcode = kA64Sub4RRdT; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 647 | break; |
| 648 | case kOpCmp: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 649 | neg_opcode = kA64Cmn3RdT; |
| 650 | opcode = kA64Cmp3RdT; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 651 | break; |
| 652 | default: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 653 | LOG(FATAL) << "Bad op-kind in OpRegImm: " << op; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 654 | break; |
| 655 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 656 | |
| 657 | if (UNLIKELY(neg)) |
| 658 | opcode = neg_opcode; |
| 659 | |
| 660 | if (EncodingMap[opcode].flags & IS_QUAD_OP) |
| 661 | return NewLIR4(opcode | wide, r_dest_src1.GetReg(), r_dest_src1.GetReg(), abs_value, |
| 662 | (shift) ? 1 : 0); |
| 663 | else |
| 664 | return NewLIR3(opcode | wide, r_dest_src1.GetReg(), abs_value, (shift) ? 1 : 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | LIR* Arm64Mir2Lir::LoadConstantWide(RegStorage r_dest, int64_t value) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 668 | if (r_dest.IsFloat()) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 669 | return LoadFPConstantValueWide(r_dest.GetReg(), value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 670 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 671 | // TODO(Arm64): check whether we can load the immediate with a short form. |
| 672 | // e.g. via movz, movk or via logical immediate. |
| 673 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 674 | // No short form - load from the literal pool. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 675 | int32_t val_lo = Low32Bits(value); |
| 676 | int32_t val_hi = High32Bits(value); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 677 | LIR* data_target = ScanLiteralPoolWide(literal_list_, val_lo, val_hi); |
| 678 | if (data_target == NULL) { |
| 679 | data_target = AddWideData(&literal_list_, val_lo, val_hi); |
| 680 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 681 | |
| 682 | LIR* res = RawLIR(current_dalvik_offset_, WIDE(kA64Ldr2rp), |
| 683 | r_dest.GetReg(), 0, 0, 0, 0, data_target); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 684 | SetMemRefType(res, true, kLiteral); |
| 685 | AppendLIR(res); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 686 | return res; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 687 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 688 | } |
| 689 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 690 | int Arm64Mir2Lir::EncodeShift(int shift_type, int amount) { |
| 691 | return ((shift_type & 0x3) << 7) | (amount & 0x1f); |
| 692 | } |
| 693 | |
| 694 | int Arm64Mir2Lir::EncodeExtend(int extend_type, int amount) { |
| 695 | return (1 << 6) | ((extend_type & 0x7) << 3) | (amount & 0x7); |
| 696 | } |
| 697 | |
| 698 | bool Arm64Mir2Lir::IsExtendEncoding(int encoded_value) { |
| 699 | return ((1 << 6) & encoded_value) != 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 700 | } |
| 701 | |
| 702 | LIR* Arm64Mir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 703 | int scale, OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 704 | LIR* load; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 705 | ArmOpcode opcode = kA64Brk1d; |
| 706 | ArmOpcode wide = kA64NotWide; |
| 707 | |
| 708 | DCHECK(scale == 0 || scale == 1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 709 | |
| 710 | if (r_dest.IsFloat()) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 711 | bool is_double = r_dest.IsDouble(); |
| 712 | bool is_single = !is_double; |
| 713 | DCHECK_EQ(is_single, r_dest.IsSingle()); |
| 714 | |
| 715 | // If r_dest is a single, then size must be either k32 or kSingle. |
| 716 | // If r_dest is a double, then size must be either k64 or kDouble. |
| 717 | DCHECK(!is_single || size == k32 || size == kSingle); |
| 718 | DCHECK(!is_double || size == k64 || size == kDouble); |
| 719 | return NewLIR4((is_double) ? FWIDE(kA64Ldr4fXxG) : kA64Ldr4fXxG, |
| 720 | r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 721 | } |
| 722 | |
| 723 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 724 | case kDouble: |
| 725 | case kWord: |
| 726 | case k64: |
| 727 | wide = kA64Wide; |
| 728 | // Intentional fall-trough. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 729 | case kSingle: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 730 | case k32: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 731 | case kReference: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 732 | opcode = kA64Ldr4rXxG; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 733 | break; |
| 734 | case kUnsignedHalf: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 735 | opcode = kA64Ldrh4wXxd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 736 | break; |
| 737 | case kSignedHalf: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 738 | opcode = kA64Ldrsh4rXxd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 739 | break; |
| 740 | case kUnsignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 741 | opcode = kA64Ldrb3wXx; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 742 | break; |
| 743 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 744 | opcode = kA64Ldrsb3rXx; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 745 | break; |
| 746 | default: |
| 747 | LOG(FATAL) << "Bad size: " << size; |
| 748 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 749 | |
| 750 | if (UNLIKELY((EncodingMap[opcode].flags & IS_TERTIARY_OP) != 0)) { |
| 751 | // Tertiary ops (e.g. ldrb, ldrsb) do not support scale. |
| 752 | DCHECK_EQ(scale, 0); |
| 753 | load = NewLIR3(opcode | wide, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg()); |
| 754 | } else { |
| 755 | DCHECK(scale == 0 || scale == ((wide == kA64Wide) ? 3 : 2)); |
| 756 | load = NewLIR4(opcode | wide, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), |
| 757 | (scale != 0) ? 1 : 0); |
| 758 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 759 | |
| 760 | return load; |
| 761 | } |
| 762 | |
| 763 | LIR* Arm64Mir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 764 | int scale, OpSize size) { |
| 765 | LIR* store; |
| 766 | ArmOpcode opcode = kA64Brk1d; |
| 767 | ArmOpcode wide = kA64NotWide; |
| 768 | |
| 769 | DCHECK(scale == 0 || scale == 1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 770 | |
| 771 | if (r_src.IsFloat()) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 772 | bool is_double = r_src.IsDouble(); |
| 773 | bool is_single = !is_double; |
| 774 | DCHECK_EQ(is_single, r_src.IsSingle()); |
| 775 | |
| 776 | // If r_src is a single, then size must be either k32 or kSingle. |
| 777 | // If r_src is a double, then size must be either k64 or kDouble. |
| 778 | DCHECK(!is_single || size == k32 || size == kSingle); |
| 779 | DCHECK(!is_double || size == k64 || size == kDouble); |
| 780 | return NewLIR4((is_double) ? FWIDE(kA64Str4fXxG) : kA64Str4fXxG, |
| 781 | r_src.GetReg(), r_base.GetReg(), r_index.GetReg(), scale); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 782 | } |
| 783 | |
| 784 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 785 | case kDouble: // Intentional fall-trough. |
| 786 | case kWord: // Intentional fall-trough. |
| 787 | case k64: |
| 788 | opcode = kA64Str4rXxG; |
| 789 | wide = kA64Wide; |
| 790 | break; |
| 791 | case kSingle: // Intentional fall-trough. |
| 792 | case k32: // Intentional fall-trough. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 793 | case kReference: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 794 | opcode = kA64Str4rXxG; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 795 | break; |
| 796 | case kUnsignedHalf: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 797 | case kSignedHalf: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 798 | opcode = kA64Strh4wXxd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 799 | break; |
| 800 | case kUnsignedByte: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 801 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 802 | opcode = kA64Strb3wXx; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 803 | break; |
| 804 | default: |
| 805 | LOG(FATAL) << "Bad size: " << size; |
| 806 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 807 | |
| 808 | if (UNLIKELY((EncodingMap[opcode].flags & IS_TERTIARY_OP) != 0)) { |
| 809 | // Tertiary ops (e.g. strb) do not support scale. |
| 810 | DCHECK_EQ(scale, 0); |
| 811 | store = NewLIR3(opcode | wide, r_src.GetReg(), r_base.GetReg(), r_index.GetReg()); |
| 812 | } else { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 813 | store = NewLIR4(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg(), scale); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 814 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 815 | |
| 816 | return store; |
| 817 | } |
| 818 | |
| 819 | /* |
| 820 | * Load value from base + displacement. Optionally perform null check |
| 821 | * on base (which must have an associated s_reg and MIR). If not |
| 822 | * performing null check, incoming MIR can be null. |
| 823 | */ |
| 824 | LIR* Arm64Mir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 825 | OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 826 | LIR* load = NULL; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 827 | ArmOpcode opcode = kA64Brk1d; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 828 | ArmOpcode alt_opcode = kA64Brk1d; |
| 829 | int scale = 0; |
| 830 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 831 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 832 | case kDouble: // Intentional fall-through. |
| 833 | case kWord: // Intentional fall-through. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 834 | case k64: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 835 | scale = 3; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 836 | if (r_dest.IsFloat()) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 837 | DCHECK(r_dest.IsDouble()); |
| 838 | opcode = FWIDE(kA64Ldr3fXD); |
| 839 | alt_opcode = FWIDE(kA64Ldur3fXd); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 840 | } else { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 841 | opcode = FWIDE(kA64Ldr3rXD); |
| 842 | alt_opcode = FWIDE(kA64Ldur3rXd); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 843 | } |
| 844 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 845 | case kSingle: // Intentional fall-through. |
| 846 | case k32: // Intentional fall-trough. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 847 | case kReference: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 848 | scale = 2; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 849 | if (r_dest.IsFloat()) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 850 | DCHECK(r_dest.IsSingle()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 851 | opcode = kA64Ldr3fXD; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 852 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 853 | opcode = kA64Ldr3rXD; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 854 | } |
| 855 | break; |
| 856 | case kUnsignedHalf: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 857 | scale = 1; |
| 858 | opcode = kA64Ldrh3wXF; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 859 | break; |
| 860 | case kSignedHalf: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 861 | scale = 1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 862 | opcode = kA64Ldrsh3rXF; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 863 | break; |
| 864 | case kUnsignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 865 | opcode = kA64Ldrb3wXd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 866 | break; |
| 867 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 868 | opcode = kA64Ldrsb3rXd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 869 | break; |
| 870 | default: |
| 871 | LOG(FATAL) << "Bad size: " << size; |
| 872 | } |
| 873 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 874 | bool displacement_is_aligned = (displacement & ((1 << scale) - 1)) == 0; |
| 875 | int scaled_disp = displacement >> scale; |
| 876 | if (displacement_is_aligned && scaled_disp >= 0 && scaled_disp < 4096) { |
| 877 | // Can use scaled load. |
| 878 | load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), scaled_disp); |
| 879 | } else if (alt_opcode != kA64Brk1d && IS_SIGNED_IMM9(displacement)) { |
| 880 | // Can use unscaled load. |
| 881 | load = NewLIR3(alt_opcode, r_dest.GetReg(), r_base.GetReg(), displacement); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 882 | } else { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 883 | // Use long sequence. |
| 884 | RegStorage r_scratch = AllocTemp(); |
| 885 | LoadConstant(r_scratch, displacement); |
| 886 | load = LoadBaseIndexed(r_base, r_scratch, r_dest, 0, size); |
| 887 | FreeTemp(r_scratch); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 888 | } |
| 889 | |
| 890 | // TODO: in future may need to differentiate Dalvik accesses w/ spills |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 891 | if (r_base == rs_rA64_SP) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 892 | AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 893 | } |
| 894 | return load; |
| 895 | } |
| 896 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 897 | LIR* Arm64Mir2Lir::LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, |
| 898 | OpSize size) { |
| 899 | // LoadBaseDisp() will emit correct insn for atomic load on arm64 |
| 900 | // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). |
| 901 | return LoadBaseDisp(r_base, displacement, r_dest, size); |
| 902 | } |
| 903 | |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 904 | LIR* Arm64Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, |
| 905 | OpSize size) { |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 906 | return LoadBaseDispBody(r_base, displacement, r_dest, size); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 907 | } |
| 908 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 909 | |
| 910 | LIR* Arm64Mir2Lir::StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 911 | OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 912 | LIR* store = NULL; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 913 | ArmOpcode opcode = kA64Brk1d; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 914 | ArmOpcode alt_opcode = kA64Brk1d; |
| 915 | int scale = 0; |
| 916 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 917 | switch (size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 918 | case kDouble: // Intentional fall-through. |
| 919 | case kWord: // Intentional fall-through. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 920 | case k64: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 921 | scale = 3; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 922 | if (r_src.IsFloat()) { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 923 | DCHECK(r_src.IsDouble()); |
| 924 | opcode = FWIDE(kA64Str3fXD); |
| 925 | alt_opcode = FWIDE(kA64Stur3fXd); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 926 | } else { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 927 | opcode = FWIDE(kA64Str3rXD); |
| 928 | alt_opcode = FWIDE(kA64Stur3rXd); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 929 | } |
| 930 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 931 | case kSingle: // Intentional fall-through. |
| 932 | case k32: // Intentional fall-trough. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 933 | case kReference: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 934 | scale = 2; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 935 | if (r_src.IsFloat()) { |
| 936 | DCHECK(r_src.IsSingle()); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 937 | opcode = kA64Str3fXD; |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 938 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 939 | opcode = kA64Str3rXD; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 940 | } |
| 941 | break; |
| 942 | case kUnsignedHalf: |
| 943 | case kSignedHalf: |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 944 | scale = 1; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 945 | opcode = kA64Strh3wXF; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 946 | break; |
| 947 | case kUnsignedByte: |
| 948 | case kSignedByte: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 949 | opcode = kA64Strb3wXd; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 950 | break; |
| 951 | default: |
| 952 | LOG(FATAL) << "Bad size: " << size; |
| 953 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 954 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 955 | bool displacement_is_aligned = (displacement & ((1 << scale) - 1)) == 0; |
| 956 | int scaled_disp = displacement >> scale; |
| 957 | if (displacement_is_aligned && scaled_disp >= 0 && scaled_disp < 4096) { |
| 958 | // Can use scaled store. |
| 959 | store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), scaled_disp); |
| 960 | } else if (alt_opcode != kA64Brk1d && IS_SIGNED_IMM9(displacement)) { |
| 961 | // Can use unscaled store. |
| 962 | store = NewLIR3(alt_opcode, r_src.GetReg(), r_base.GetReg(), displacement); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 963 | } else { |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 964 | // Use long sequence. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 965 | RegStorage r_scratch = AllocTemp(); |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 966 | LoadConstant(r_scratch, displacement); |
| 967 | store = StoreBaseIndexed(r_base, r_scratch, r_src, 0, size); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 968 | FreeTemp(r_scratch); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 969 | } |
| 970 | |
Matteo Franchin | bc6d197 | 2014-05-13 12:33:28 +0100 | [diff] [blame^] | 971 | // TODO: In future, may need to differentiate Dalvik & spill accesses. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 972 | if (r_base == rs_rA64_SP) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 973 | AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 974 | } |
| 975 | return store; |
| 976 | } |
| 977 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 978 | LIR* Arm64Mir2Lir::StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src, |
| 979 | OpSize size) { |
| 980 | // StoreBaseDisp() will emit correct insn for atomic store on arm64 |
| 981 | // assuming r_dest is correctly prepared using RegClassForFieldLoadStore(). |
| 982 | return StoreBaseDisp(r_base, displacement, r_src, size); |
| 983 | } |
| 984 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 985 | LIR* Arm64Mir2Lir::StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 986 | OpSize size) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 987 | return StoreBaseDispBody(r_base, displacement, r_src, size); |
| 988 | } |
| 989 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 990 | LIR* Arm64Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 991 | LOG(FATAL) << "Unexpected use of OpFpRegCopy for Arm64"; |
| 992 | return NULL; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 993 | } |
| 994 | |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 995 | LIR* Arm64Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) { |
| 996 | UNIMPLEMENTED(FATAL) << "Should not be used."; |
| 997 | return nullptr; |
| 998 | } |
| 999 | |
| 1000 | LIR* Arm64Mir2Lir::OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1001 | LOG(FATAL) << "Unexpected use of OpThreadMem for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1002 | return NULL; |
| 1003 | } |
| 1004 | |
| 1005 | LIR* Arm64Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1006 | LOG(FATAL) << "Unexpected use of OpMem for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1007 | return NULL; |
| 1008 | } |
| 1009 | |
| 1010 | LIR* Arm64Mir2Lir::StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1011 | int displacement, RegStorage r_src, OpSize size) { |
| 1012 | LOG(FATAL) << "Unexpected use of StoreBaseIndexedDisp for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1013 | return NULL; |
| 1014 | } |
| 1015 | |
| 1016 | LIR* Arm64Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1017 | LOG(FATAL) << "Unexpected use of OpRegMem for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1018 | return NULL; |
| 1019 | } |
| 1020 | |
| 1021 | LIR* Arm64Mir2Lir::LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 1022 | int displacement, RegStorage r_dest, OpSize size) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 1023 | LOG(FATAL) << "Unexpected use of LoadBaseIndexedDisp for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1024 | return NULL; |
| 1025 | } |
| 1026 | |
| 1027 | } // namespace art |