blob: 604134d25293d9354e7248574ca0d8f8a36068b9 [file] [log] [blame]
Douglas Leung200f0402016-02-25 20:05:47 -08001%default {"preinstr":"", "result0":"a0", "result1":"a1", "chkzero":"0", "arg0":"a0", "arg1":"a1", "arg2":"a2", "arg3":"a3"}
2 /*
3 * Generic 64-bit binary operation. Provide an "instr" line that
4 * specifies an instruction that performs "result = a0-a1 op a2-a3".
5 * This could be a MIPS instruction or a function call. (If the result
Alexey Frunze84603bf2016-10-21 19:54:43 -07006 * comes back in a register pair other than a0-a1, you can override "result".)
Douglas Leung200f0402016-02-25 20:05:47 -08007 *
8 * If "chkzero" is set to 1, we perform a divide-by-zero check on
Alexey Frunze84603bf2016-10-21 19:54:43 -07009 * vCC (a2-a3). Useful for integer division and modulus.
Douglas Leung200f0402016-02-25 20:05:47 -080010 *
11 * for: add-long, sub-long, div-long, rem-long, and-long, or-long,
12 * xor-long
13 *
14 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both.
15 */
16 /* binop vAA, vBB, vCC */
17 FETCH(a0, 1) # a0 <- CCBB
18 GET_OPA(rOBJ) # rOBJ <- AA
19 and a2, a0, 255 # a2 <- BB
20 srl a3, a0, 8 # a3 <- CC
21 EAS2(a2, rFP, a2) # a2 <- &fp[BB]
22 EAS2(t1, rFP, a3) # a3 <- &fp[CC]
23 LOAD64($arg0, $arg1, a2) # a0/a1 <- vBB/vBB+1
24 LOAD64($arg2, $arg3, t1) # a2/a3 <- vCC/vCC+1
25 .if $chkzero
26 or t0, $arg2, $arg3 # second arg (a2-a3) is zero?
27 beqz t0, common_errDivideByZero
28 .endif
29 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
30
31 $preinstr # optional op
32 $instr # result <- op, a0-a3 changed
33 GET_INST_OPCODE(t0) # extract opcode from rINST
34 SET_VREG64_GOTO($result0, $result1, rOBJ, t0) # vAA/vAA+1 <- $result0/$result1