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gerrit-public.fairphone.software / platform / art / c0f3918c0ff37a34ec0ebe27a71537aef22f8f20 / . / runtime / interpreter / mterp / mips / op_cmpl_double.S
blob: 369e5b30fd6b4fcc10115d8eebd3e441112a7f8d [file] [log] [blame]
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]1%default { "gt_bias":"0" }
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]2 /*
3 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]4 * into the destination register based on the comparison results.
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]5 *
6 * For: cmpl-double, cmpg-double
7 */
8 /* op vAA, vBB, vCC */
9
10 FETCH(a0, 1) # a0 <- CCBB
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]11 and rOBJ, a0, 255 # rOBJ <- BB
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]12 srl t0, a0, 8 # t0 <- CC
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]13 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB]
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]14 EAS2(t0, rFP, t0) # t0 <- &fp[CC]
15 LOAD64_F(ft0, ft0f, rOBJ)
16 LOAD64_F(ft1, ft1f, t0)
17#ifdef MIPS32REVGE6
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]18 cmp.eq.d ft2, ft0, ft1
19 li rTEMP, 0
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]20 bc1nez ft2, 1f # done if vBB == vCC (ordered)
21 .if $gt_bias
22 cmp.lt.d ft2, ft0, ft1
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]23 li rTEMP, -1
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]24 bc1nez ft2, 1f # done if vBB < vCC (ordered)
25 li rTEMP, 1 # vBB > vCC or unordered
26 .else
27 cmp.lt.d ft2, ft1, ft0
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]28 li rTEMP, 1
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]29 bc1nez ft2, 1f # done if vBB > vCC (ordered)
30 li rTEMP, -1 # vBB < vCC or unordered
31 .endif
32#else
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]33 c.eq.d fcc0, ft0, ft1
34 li rTEMP, 0
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]35 bc1t fcc0, 1f # done if vBB == vCC (ordered)
36 .if $gt_bias
37 c.olt.d fcc0, ft0, ft1
38 li rTEMP, -1
39 bc1t fcc0, 1f # done if vBB < vCC (ordered)
40 li rTEMP, 1 # vBB > vCC or unordered
41 .else
42 c.olt.d fcc0, ft1, ft0
43 li rTEMP, 1
44 bc1t fcc0, 1f # done if vBB > vCC (ordered)
45 li rTEMP, -1 # vBB < vCC or unordered
46 .endif
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]47#endif
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]481:
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]49 GET_OPA(rOBJ)
50 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
51 GET_INST_OPCODE(t0) # extract opcode from rINST
52 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP