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gerrit-public.fairphone.software / platform / art / c0f3918c0ff37a34ec0ebe27a71537aef22f8f20 / . / runtime / interpreter / mterp / mips / op_cmpl_float.S
blob: 1dd55067e985b44c70976efe7611441983c61bfd [file] [log] [blame]
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]1%default { "gt_bias":"0" }
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]2 /*
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]3 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<)
4 * into the destination register based on the comparison results.
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]5 *
6 * for: cmpl-float, cmpg-float
7 */
8 /* op vAA, vBB, vCC */
9
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]10 FETCH(a0, 1) # a0 <- CCBB
11 and a2, a0, 255 # a2 <- BB
12 srl a3, a0, 8
13 GET_VREG_F(ft0, a2)
14 GET_VREG_F(ft1, a3)
15#ifdef MIPS32REVGE6
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]16 cmp.eq.s ft2, ft0, ft1
17 li rTEMP, 0
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]18 bc1nez ft2, 1f # done if vBB == vCC (ordered)
19 .if $gt_bias
20 cmp.lt.s ft2, ft0, ft1
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]21 li rTEMP, -1
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]22 bc1nez ft2, 1f # done if vBB < vCC (ordered)
23 li rTEMP, 1 # vBB > vCC or unordered
24 .else
25 cmp.lt.s ft2, ft1, ft0
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]26 li rTEMP, 1
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]27 bc1nez ft2, 1f # done if vBB > vCC (ordered)
28 li rTEMP, -1 # vBB < vCC or unordered
29 .endif
30#else
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]31 c.eq.s fcc0, ft0, ft1
32 li rTEMP, 0
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]33 bc1t fcc0, 1f # done if vBB == vCC (ordered)
34 .if $gt_bias
35 c.olt.s fcc0, ft0, ft1
36 li rTEMP, -1
37 bc1t fcc0, 1f # done if vBB < vCC (ordered)
38 li rTEMP, 1 # vBB > vCC or unordered
39 .else
40 c.olt.s fcc0, ft1, ft0
41 li rTEMP, 1
42 bc1t fcc0, 1f # done if vBB > vCC (ordered)
43 li rTEMP, -1 # vBB < vCC or unordered
44 .endif
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]45#endif
Alexey Frunze84603bf2016-10-21 19:54:43 -0700[diff] [blame]461:
Douglas Leung200f0402016-02-25 20:05:47 -0800[diff] [blame]47 GET_OPA(rOBJ)
48 FETCH_ADVANCE_INST(2) # advance rPC, load rINST
49 GET_INST_OPCODE(t0) # extract opcode from rINST
50 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP