| Douglas Leung | 200f040 | 2016-02-25 20:05:47 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Long integer shift. This is different from the generic 32/64-bit |
| 3 | * binary operations because vAA/vBB are 64-bit but vCC (the shift |
| 4 | * distance) is 32-bit. Also, Dalvik requires us to mask off the low |
| 5 | * 6 bits of the shift distance. |
| 6 | */ |
| 7 | /* shl-long vAA, vBB, vCC */ |
| 8 | FETCH(a0, 1) # a0 <- CCBB |
| 9 | GET_OPA(t2) # t2 <- AA |
| 10 | and a3, a0, 255 # a3 <- BB |
| 11 | srl a0, a0, 8 # a0 <- CC |
| 12 | EAS2(a3, rFP, a3) # a3 <- &fp[BB] |
| 13 | GET_VREG(a2, a0) # a2 <- vCC |
| 14 | LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 |
| 15 | |
| 16 | FETCH_ADVANCE_INST(2) # advance rPC, load rINST |
| 17 | GET_INST_OPCODE(t0) # extract opcode from rINST |
| 18 | |
| 19 | andi v1, a2, 0x20 # shift< shift & 0x20 |
| 20 | sll v0, a0, a2 # rlo<- alo << (shift&31) |
| 21 | bnez v1, .L${opcode}_finish |
| 22 | not v1, a2 # rhi<- 31-shift (shift is 5b) |
| 23 | srl a0, 1 |
| 24 | srl a0, v1 # alo<- alo >> (32-(shift&31)) |
| 25 | sll v1, a1, a2 # rhi<- ahi << (shift&31) |
| 26 | or v1, a0 # rhi<- rhi | alo |
| Alexey Frunze | 84603bf | 2016-10-21 19:54:43 -0700 | [diff] [blame] | 27 | SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 |
| Douglas Leung | 200f040 | 2016-02-25 20:05:47 -0800 | [diff] [blame] | 28 | %break |
| 29 | |
| 30 | .L${opcode}_finish: |
| 31 | SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi |