| Douglas Leung | 200f040 | 2016-02-25 20:05:47 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Long integer shift. This is different from the generic 32/64-bit |
| 3 | * binary operations because vAA/vBB are 64-bit but vCC (the shift |
| 4 | * distance) is 32-bit. Also, Dalvik requires us to mask off the low |
| 5 | * 6 bits of the shift distance. |
| 6 | */ |
| 7 | /* shr-long vAA, vBB, vCC */ |
| 8 | FETCH(a0, 1) # a0 <- CCBB |
| 9 | GET_OPA(t3) # t3 <- AA |
| 10 | and a3, a0, 255 # a3 <- BB |
| 11 | srl a0, a0, 8 # a0 <- CC |
| 12 | EAS2(a3, rFP, a3) # a3 <- &fp[BB] |
| 13 | GET_VREG(a2, a0) # a2 <- vCC |
| 14 | LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 |
| 15 | FETCH_ADVANCE_INST(2) # advance rPC, load rINST |
| 16 | GET_INST_OPCODE(t0) # extract opcode from rINST |
| 17 | |
| 18 | andi v0, a2, 0x20 # shift & 0x20 |
| 19 | sra v1, a1, a2 # rhi<- ahi >> (shift&31) |
| 20 | bnez v0, .L${opcode}_finish |
| 21 | srl v0, a0, a2 # rlo<- alo >> (shift&31) |
| 22 | not a0, a2 # alo<- 31-shift (shift is 5b) |
| 23 | sll a1, 1 |
| 24 | sll a1, a0 # ahi<- ahi << (32-(shift&31)) |
| 25 | or v0, a1 # rlo<- rlo | ahi |
| Alexey Frunze | 84603bf | 2016-10-21 19:54:43 -0700 | [diff] [blame] | 26 | SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 |
| Douglas Leung | 200f040 | 2016-02-25 20:05:47 -0800 | [diff] [blame] | 27 | %break |
| 28 | |
| 29 | .L${opcode}_finish: |
| 30 | sra a3, a1, 31 # a3<- sign(ah) |
| 31 | SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi |