Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "codegen_arm64.h" |
| 18 | |
| 19 | #include <inttypes.h> |
| 20 | |
| 21 | #include <string> |
| 22 | |
| 23 | #include "dex/compiler_internals.h" |
| 24 | #include "dex/quick/mir_to_lir-inl.h" |
| 25 | |
| 26 | namespace art { |
| 27 | |
| 28 | // TODO: rework this when c++11 support allows. |
| 29 | static const RegStorage core_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 30 | {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, |
| 31 | rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, |
| 32 | rs_x16, rs_x17, rs_x18, rs_x19, rs_x20, rs_x21, rs_x22, rs_x23, |
| 33 | rs_x24, rs_x25, rs_x26, rs_x27, rs_x28, rs_x29, rs_x30, rs_x31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 34 | static const RegStorage sp_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 35 | {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, |
| 36 | rs_f8, rs_f9, rs_f10, rs_f11, rs_f12, rs_f13, rs_f14, rs_f15, |
| 37 | rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, |
| 38 | rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 39 | static const RegStorage dp_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 40 | {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 41 | rs_d8, rs_d9, rs_d10, rs_d11, rs_d12, rs_d13, rs_d14, rs_d15, |
| 42 | rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, |
| 43 | rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 44 | static const RegStorage reserved_regs_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 45 | {rs_rA64_SUSPEND, rs_rA64_SELF, rs_rA64_SP, rs_rA64_LR}; |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 46 | // TUING: Are there too many temp registers and too less promote target? |
| 47 | // This definition need to be matched with runtime.cc, quick entry assembly and JNI compiler |
| 48 | // Note: we are not able to call to C function directly if it un-match C ABI. |
| 49 | // Currently, rs_rA64_SELF is not a callee save register which does not match C ABI. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 50 | static const RegStorage core_temps_arr[] = |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 51 | {rs_x0, rs_x1, rs_x2, rs_x3, rs_x4, rs_x5, rs_x6, rs_x7, |
| 52 | rs_x8, rs_x9, rs_x10, rs_x11, rs_x12, rs_x13, rs_x14, rs_x15, rs_x16, |
| 53 | rs_x17}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 54 | static const RegStorage sp_temps_arr[] = |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 55 | {rs_f0, rs_f1, rs_f2, rs_f3, rs_f4, rs_f5, rs_f6, rs_f7, |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 56 | rs_f16, rs_f17, rs_f18, rs_f19, rs_f20, rs_f21, rs_f22, rs_f23, |
| 57 | rs_f24, rs_f25, rs_f26, rs_f27, rs_f28, rs_f29, rs_f30, rs_f31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 58 | static const RegStorage dp_temps_arr[] = |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 59 | {rs_d0, rs_d1, rs_d2, rs_d3, rs_d4, rs_d5, rs_d6, rs_d7, |
| 60 | rs_d16, rs_d17, rs_d18, rs_d19, rs_d20, rs_d21, rs_d22, rs_d23, |
| 61 | rs_d24, rs_d25, rs_d26, rs_d27, rs_d28, rs_d29, rs_d30, rs_d31}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 62 | |
| 63 | static const std::vector<RegStorage> core_regs(core_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 64 | core_regs_arr + arraysize(core_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 65 | static const std::vector<RegStorage> sp_regs(sp_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 66 | sp_regs_arr + arraysize(sp_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 67 | static const std::vector<RegStorage> dp_regs(dp_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 68 | dp_regs_arr + arraysize(dp_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 69 | static const std::vector<RegStorage> reserved_regs(reserved_regs_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 70 | reserved_regs_arr + arraysize(reserved_regs_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 71 | static const std::vector<RegStorage> core_temps(core_temps_arr, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 72 | core_temps_arr + arraysize(core_temps_arr)); |
| 73 | static const std::vector<RegStorage> sp_temps(sp_temps_arr, sp_temps_arr + arraysize(sp_temps_arr)); |
| 74 | static const std::vector<RegStorage> dp_temps(dp_temps_arr, dp_temps_arr + arraysize(dp_temps_arr)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 75 | |
| 76 | RegLocation Arm64Mir2Lir::LocCReturn() { |
| 77 | return arm_loc_c_return; |
| 78 | } |
| 79 | |
| 80 | RegLocation Arm64Mir2Lir::LocCReturnWide() { |
| 81 | return arm_loc_c_return_wide; |
| 82 | } |
| 83 | |
| 84 | RegLocation Arm64Mir2Lir::LocCReturnFloat() { |
| 85 | return arm_loc_c_return_float; |
| 86 | } |
| 87 | |
| 88 | RegLocation Arm64Mir2Lir::LocCReturnDouble() { |
| 89 | return arm_loc_c_return_double; |
| 90 | } |
| 91 | |
| 92 | // Return a target-dependent special register. |
| 93 | RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 94 | // TODO(Arm64): this function doesn't work for hard-float ABI. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 95 | RegStorage res_reg = RegStorage::InvalidReg(); |
| 96 | switch (reg) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 97 | case kSelf: res_reg = rs_rA64_SELF; break; |
| 98 | case kSuspend: res_reg = rs_rA64_SUSPEND; break; |
| 99 | case kLr: res_reg = rs_rA64_LR; break; |
| 100 | case kPc: res_reg = RegStorage::InvalidReg(); break; |
| 101 | case kSp: res_reg = rs_rA64_SP; break; |
| 102 | case kArg0: res_reg = rs_x0; break; |
| 103 | case kArg1: res_reg = rs_x1; break; |
| 104 | case kArg2: res_reg = rs_x2; break; |
| 105 | case kArg3: res_reg = rs_x3; break; |
| 106 | case kFArg0: res_reg = rs_f0; break; |
| 107 | case kFArg1: res_reg = rs_f1; break; |
| 108 | case kFArg2: res_reg = rs_f2; break; |
| 109 | case kFArg3: res_reg = rs_f3; break; |
| 110 | case kRet0: res_reg = rs_x0; break; |
| 111 | case kRet1: res_reg = rs_x0; break; |
| 112 | case kInvokeTgt: res_reg = rs_rA64_LR; break; |
| 113 | case kHiddenArg: res_reg = rs_x12; break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 114 | case kHiddenFpArg: res_reg = RegStorage::InvalidReg(); break; |
| 115 | case kCount: res_reg = RegStorage::InvalidReg(); break; |
| 116 | } |
| 117 | return res_reg; |
| 118 | } |
| 119 | |
| 120 | RegStorage Arm64Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 121 | return RegStorage::InvalidReg(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | /* |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 125 | * Decode the register id. This routine makes assumptions on the encoding made by RegStorage. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 126 | */ |
| 127 | uint64_t Arm64Mir2Lir::GetRegMaskCommon(RegStorage reg) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 128 | // TODO(Arm64): this function depends too much on the internal RegStorage encoding. Refactor. |
| 129 | |
| 130 | int reg_raw = reg.GetRawBits(); |
| 131 | // Check if the shape mask is zero (i.e. invalid). |
| 132 | if (UNLIKELY(reg == rs_wzr || reg == rs_xzr)) { |
| 133 | // The zero register is not a true register. It is just an immediate zero. |
| 134 | return 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 135 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 136 | |
| 137 | return UINT64_C(1) << (reg_raw & RegStorage::kRegTypeMask); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | uint64_t Arm64Mir2Lir::GetPCUseDefEncoding() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 141 | LOG(FATAL) << "Unexpected call to GetPCUseDefEncoding for Arm64"; |
| 142 | return 0ULL; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 143 | } |
| 144 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 145 | // Arm64 specific setup. TODO: inline?: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 146 | void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 147 | DCHECK_EQ(cu_->instruction_set, kArm64); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 148 | DCHECK(!lir->flags.use_def_invalid); |
| 149 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 150 | // These flags are somewhat uncommon - bypass if we can. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 151 | if ((flags & (REG_DEF_SP | REG_USE_SP | REG_DEF_LR)) != 0) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 152 | if (flags & REG_DEF_SP) { |
| 153 | lir->u.m.def_mask |= ENCODE_ARM_REG_SP; |
| 154 | } |
| 155 | |
| 156 | if (flags & REG_USE_SP) { |
| 157 | lir->u.m.use_mask |= ENCODE_ARM_REG_SP; |
| 158 | } |
| 159 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 160 | if (flags & REG_DEF_LR) { |
| 161 | lir->u.m.def_mask |= ENCODE_ARM_REG_LR; |
| 162 | } |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { |
| 167 | ArmConditionCode res; |
| 168 | switch (ccode) { |
| 169 | case kCondEq: res = kArmCondEq; break; |
| 170 | case kCondNe: res = kArmCondNe; break; |
| 171 | case kCondCs: res = kArmCondCs; break; |
| 172 | case kCondCc: res = kArmCondCc; break; |
| 173 | case kCondUlt: res = kArmCondCc; break; |
| 174 | case kCondUge: res = kArmCondCs; break; |
| 175 | case kCondMi: res = kArmCondMi; break; |
| 176 | case kCondPl: res = kArmCondPl; break; |
| 177 | case kCondVs: res = kArmCondVs; break; |
| 178 | case kCondVc: res = kArmCondVc; break; |
| 179 | case kCondHi: res = kArmCondHi; break; |
| 180 | case kCondLs: res = kArmCondLs; break; |
| 181 | case kCondGe: res = kArmCondGe; break; |
| 182 | case kCondLt: res = kArmCondLt; break; |
| 183 | case kCondGt: res = kArmCondGt; break; |
| 184 | case kCondLe: res = kArmCondLe; break; |
| 185 | case kCondAl: res = kArmCondAl; break; |
| 186 | case kCondNv: res = kArmCondNv; break; |
| 187 | default: |
| 188 | LOG(FATAL) << "Bad condition code " << ccode; |
| 189 | res = static_cast<ArmConditionCode>(0); // Quiet gcc |
| 190 | } |
| 191 | return res; |
| 192 | } |
| 193 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 194 | static const char *shift_names[4] = { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 195 | "lsl", |
| 196 | "lsr", |
| 197 | "asr", |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 198 | "ror" |
| 199 | }; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 200 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 201 | static const char* extend_names[8] = { |
| 202 | "uxtb", |
| 203 | "uxth", |
| 204 | "uxtw", |
| 205 | "uxtx", |
| 206 | "sxtb", |
| 207 | "sxth", |
| 208 | "sxtw", |
| 209 | "sxtx", |
| 210 | }; |
| 211 | |
| 212 | /* Decode and print a register extension (e.g. ", uxtb #1") */ |
| 213 | static void DecodeRegExtendOrShift(int operand, char *buf, size_t buf_size) { |
| 214 | if ((operand & (1 << 6)) == 0) { |
| 215 | const char *shift_name = shift_names[(operand >> 7) & 0x3]; |
| 216 | int amount = operand & 0x3f; |
| 217 | snprintf(buf, buf_size, ", %s #%d", shift_name, amount); |
| 218 | } else { |
| 219 | const char *extend_name = extend_names[(operand >> 3) & 0x7]; |
| 220 | int amount = operand & 0x7; |
| 221 | if (amount == 0) { |
| 222 | snprintf(buf, buf_size, ", %s", extend_name); |
| 223 | } else { |
| 224 | snprintf(buf, buf_size, ", %s #%d", extend_name, amount); |
| 225 | } |
| 226 | } |
| 227 | } |
| 228 | |
| 229 | #define BIT_MASK(w) ((UINT64_C(1) << (w)) - UINT64_C(1)) |
| 230 | |
| 231 | static uint64_t RotateRight(uint64_t value, unsigned rotate, unsigned width) { |
| 232 | DCHECK_LE(width, 64U); |
| 233 | rotate &= 63; |
| 234 | value = value & BIT_MASK(width); |
| 235 | return ((value & BIT_MASK(rotate)) << (width - rotate)) | (value >> rotate); |
| 236 | } |
| 237 | |
| 238 | static uint64_t RepeatBitsAcrossReg(bool is_wide, uint64_t value, unsigned width) { |
| 239 | unsigned i; |
| 240 | unsigned reg_size = (is_wide) ? 64 : 32; |
| 241 | uint64_t result = value & BIT_MASK(width); |
| 242 | DCHECK_NE(width, reg_size); |
| 243 | for (i = width; i < reg_size; i *= 2) { |
| 244 | result |= (result << i); |
| 245 | } |
| 246 | DCHECK_EQ(i, reg_size); |
| 247 | return result; |
| 248 | } |
| 249 | |
| 250 | /** |
| 251 | * @brief Decode an immediate in the form required by logical instructions. |
| 252 | * |
| 253 | * @param is_wide Whether @p value encodes a 64-bit (as opposed to 32-bit) immediate. |
| 254 | * @param value The encoded logical immediates that is to be decoded. |
| 255 | * @return The decoded logical immediate. |
| 256 | * @note This is the inverse of Arm64Mir2Lir::EncodeLogicalImmediate(). |
| 257 | */ |
| 258 | uint64_t Arm64Mir2Lir::DecodeLogicalImmediate(bool is_wide, int value) { |
| 259 | unsigned n = (value >> 12) & 0x01; |
| 260 | unsigned imm_r = (value >> 6) & 0x3f; |
| 261 | unsigned imm_s = (value >> 0) & 0x3f; |
| 262 | |
| 263 | // An integer is constructed from the n, imm_s and imm_r bits according to |
| 264 | // the following table: |
| 265 | // |
| 266 | // N imms immr size S R |
| 267 | // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) |
| 268 | // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) |
| 269 | // 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr) |
| 270 | // 0 110sss xxxrrr 8 UInt(sss) UInt(rrr) |
| 271 | // 0 1110ss xxxxrr 4 UInt(ss) UInt(rr) |
| 272 | // 0 11110s xxxxxr 2 UInt(s) UInt(r) |
| 273 | // (s bits must not be all set) |
| 274 | // |
| 275 | // A pattern is constructed of size bits, where the least significant S+1 |
| 276 | // bits are set. The pattern is rotated right by R, and repeated across a |
| 277 | // 32 or 64-bit value, depending on destination register width. |
| 278 | |
| 279 | if (n == 1) { |
| 280 | DCHECK_NE(imm_s, 0x3fU); |
| 281 | uint64_t bits = BIT_MASK(imm_s + 1); |
| 282 | return RotateRight(bits, imm_r, 64); |
| 283 | } else { |
| 284 | DCHECK_NE((imm_s >> 1), 0x1fU); |
| 285 | for (unsigned width = 0x20; width >= 0x2; width >>= 1) { |
| 286 | if ((imm_s & width) == 0) { |
| 287 | unsigned mask = (unsigned)(width - 1); |
| 288 | DCHECK_NE((imm_s & mask), mask); |
| 289 | uint64_t bits = BIT_MASK((imm_s & mask) + 1); |
| 290 | return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 291 | } |
| 292 | } |
| 293 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 294 | return 0; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 295 | } |
| 296 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 297 | /** |
| 298 | * @brief Decode an 8-bit single point number encoded with EncodeImmSingle(). |
| 299 | */ |
| 300 | static float DecodeImmSingle(uint8_t small_float) { |
| 301 | int mantissa = (small_float & 0x0f) + 0x10; |
| 302 | int sign = ((small_float & 0x80) == 0) ? 1 : -1; |
| 303 | float signed_mantissa = static_cast<float>(sign*mantissa); |
| 304 | int exponent = (((small_float >> 4) & 0x7) + 4) & 0x7; |
| 305 | return signed_mantissa*static_cast<float>(1 << exponent)*0.0078125f; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 306 | } |
| 307 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 308 | static const char* cc_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
| 309 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"}; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 310 | /* |
| 311 | * Interpret a format string and build a string no longer than size |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 312 | * See format key in assemble_arm64.cc. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 313 | */ |
| 314 | std::string Arm64Mir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) { |
| 315 | std::string buf; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 316 | const char* fmt_end = &fmt[strlen(fmt)]; |
| 317 | char tbuf[256]; |
| 318 | const char* name; |
| 319 | char nc; |
| 320 | while (fmt < fmt_end) { |
| 321 | int operand; |
| 322 | if (*fmt == '!') { |
| 323 | fmt++; |
| 324 | DCHECK_LT(fmt, fmt_end); |
| 325 | nc = *fmt++; |
| 326 | if (nc == '!') { |
| 327 | strcpy(tbuf, "!"); |
| 328 | } else { |
| 329 | DCHECK_LT(fmt, fmt_end); |
| 330 | DCHECK_LT(static_cast<unsigned>(nc-'0'), 4U); |
| 331 | operand = lir->operands[nc-'0']; |
| 332 | switch (*fmt++) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 333 | case 'e': { |
| 334 | // Omit ", uxtw #0" in strings like "add w0, w1, w3, uxtw #0" and |
| 335 | // ", uxtx #0" in strings like "add x0, x1, x3, uxtx #0" |
| 336 | int omittable = ((IS_WIDE(lir->opcode)) ? EncodeExtend(kA64Uxtw, 0) : |
| 337 | EncodeExtend(kA64Uxtw, 0)); |
| 338 | if (LIKELY(operand == omittable)) { |
| 339 | strcpy(tbuf, ""); |
| 340 | } else { |
| 341 | DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); |
| 342 | } |
| 343 | } |
| 344 | break; |
| 345 | case 'o': |
| 346 | // Omit ", lsl #0" |
| 347 | if (LIKELY(operand == EncodeShift(kA64Lsl, 0))) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 348 | strcpy(tbuf, ""); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 349 | } else { |
| 350 | DecodeRegExtendOrShift(operand, tbuf, arraysize(tbuf)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 351 | } |
| 352 | break; |
| 353 | case 'B': |
| 354 | switch (operand) { |
| 355 | case kSY: |
| 356 | name = "sy"; |
| 357 | break; |
| 358 | case kST: |
| 359 | name = "st"; |
| 360 | break; |
| 361 | case kISH: |
| 362 | name = "ish"; |
| 363 | break; |
| 364 | case kISHST: |
| 365 | name = "ishst"; |
| 366 | break; |
| 367 | case kNSH: |
| 368 | name = "nsh"; |
| 369 | break; |
| 370 | case kNSHST: |
| 371 | name = "shst"; |
| 372 | break; |
| 373 | default: |
| 374 | name = "DecodeError2"; |
| 375 | break; |
| 376 | } |
| 377 | strcpy(tbuf, name); |
| 378 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 379 | case 's': |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 380 | snprintf(tbuf, arraysize(tbuf), "s%d", operand & ARM_FP_REG_MASK); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 381 | break; |
| 382 | case 'S': |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 383 | snprintf(tbuf, arraysize(tbuf), "d%d", operand & ARM_FP_REG_MASK); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 384 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 385 | case 'f': |
| 386 | snprintf(tbuf, arraysize(tbuf), "%c%d", (IS_FWIDE(lir->opcode)) ? 'd' : 's', |
| 387 | operand & ARM_FP_REG_MASK); |
| 388 | break; |
| 389 | case 'l': { |
| 390 | bool is_wide = IS_WIDE(lir->opcode); |
| 391 | uint64_t imm = DecodeLogicalImmediate(is_wide, operand); |
| 392 | snprintf(tbuf, arraysize(tbuf), "%" PRId64 " (%#" PRIx64 ")", imm, imm); |
| 393 | } |
| 394 | break; |
| 395 | case 'I': |
| 396 | snprintf(tbuf, arraysize(tbuf), "%f", DecodeImmSingle(operand)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 397 | break; |
| 398 | case 'M': |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 399 | if (LIKELY(operand == 0)) |
| 400 | strcpy(tbuf, ""); |
| 401 | else |
| 402 | snprintf(tbuf, arraysize(tbuf), ", lsl #%d", 16*operand); |
| 403 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 404 | case 'd': |
| 405 | snprintf(tbuf, arraysize(tbuf), "%d", operand); |
| 406 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 407 | case 'w': |
| 408 | if (LIKELY(operand != rwzr)) |
| 409 | snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); |
| 410 | else |
| 411 | strcpy(tbuf, "wzr"); |
| 412 | break; |
| 413 | case 'W': |
| 414 | if (LIKELY(operand != rwsp)) |
| 415 | snprintf(tbuf, arraysize(tbuf), "w%d", operand & RegStorage::kRegNumMask); |
| 416 | else |
| 417 | strcpy(tbuf, "wsp"); |
| 418 | break; |
| 419 | case 'x': |
| 420 | if (LIKELY(operand != rxzr)) |
| 421 | snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); |
| 422 | else |
| 423 | strcpy(tbuf, "xzr"); |
| 424 | break; |
| 425 | case 'X': |
| 426 | if (LIKELY(operand != rsp)) |
| 427 | snprintf(tbuf, arraysize(tbuf), "x%d", operand & RegStorage::kRegNumMask); |
| 428 | else |
| 429 | strcpy(tbuf, "sp"); |
| 430 | break; |
| 431 | case 'D': |
| 432 | snprintf(tbuf, arraysize(tbuf), "%d", operand*((IS_WIDE(lir->opcode)) ? 8 : 4)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 433 | break; |
| 434 | case 'E': |
| 435 | snprintf(tbuf, arraysize(tbuf), "%d", operand*4); |
| 436 | break; |
| 437 | case 'F': |
| 438 | snprintf(tbuf, arraysize(tbuf), "%d", operand*2); |
| 439 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 440 | case 'G': |
| 441 | if (LIKELY(operand == 0)) |
| 442 | strcpy(tbuf, ""); |
| 443 | else |
| 444 | strcpy(tbuf, (IS_WIDE(lir->opcode)) ? ", lsl #3" : ", lsl #2"); |
| 445 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 446 | case 'c': |
| 447 | strcpy(tbuf, cc_names[operand]); |
| 448 | break; |
| 449 | case 't': |
| 450 | snprintf(tbuf, arraysize(tbuf), "0x%08" PRIxPTR " (L%p)", |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 451 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + (operand << 2), |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 452 | lir->target); |
| 453 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 454 | case 'r': { |
| 455 | bool is_wide = IS_WIDE(lir->opcode); |
| 456 | if (LIKELY(operand != rwzr && operand != rxzr)) { |
| 457 | snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', |
| 458 | operand & RegStorage::kRegNumMask); |
| 459 | } else { |
| 460 | strcpy(tbuf, (is_wide) ? "xzr" : "wzr"); |
| 461 | } |
| 462 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 463 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 464 | case 'R': { |
| 465 | bool is_wide = IS_WIDE(lir->opcode); |
| 466 | if (LIKELY(operand != rwsp || operand != rsp)) { |
| 467 | snprintf(tbuf, arraysize(tbuf), "%c%d", (is_wide) ? 'x' : 'w', |
| 468 | operand & RegStorage::kRegNumMask); |
| 469 | } else { |
| 470 | strcpy(tbuf, (is_wide) ? "sp" : "wsp"); |
| 471 | } |
| 472 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 473 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 474 | case 'p': |
| 475 | snprintf(tbuf, arraysize(tbuf), ".+%d (addr %#" PRIxPTR ")", 4*operand, |
| 476 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4*operand); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 477 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 478 | case 'T': |
| 479 | if (LIKELY(operand == 0)) |
| 480 | strcpy(tbuf, ""); |
| 481 | else if (operand == 1) |
| 482 | strcpy(tbuf, ", lsl #12"); |
| 483 | else |
| 484 | strcpy(tbuf, ", DecodeError3"); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 485 | break; |
| 486 | default: |
| 487 | strcpy(tbuf, "DecodeError1"); |
| 488 | break; |
| 489 | } |
| 490 | buf += tbuf; |
| 491 | } |
| 492 | } else { |
| 493 | buf += *fmt++; |
| 494 | } |
| 495 | } |
| 496 | return buf; |
| 497 | } |
| 498 | |
| 499 | void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefix) { |
| 500 | char buf[256]; |
| 501 | buf[0] = 0; |
| 502 | |
| 503 | if (mask == ENCODE_ALL) { |
| 504 | strcpy(buf, "all"); |
| 505 | } else { |
| 506 | char num[8]; |
| 507 | int i; |
| 508 | |
| 509 | for (i = 0; i < kArmRegEnd; i++) { |
| 510 | if (mask & (1ULL << i)) { |
| 511 | snprintf(num, arraysize(num), "%d ", i); |
| 512 | strcat(buf, num); |
| 513 | } |
| 514 | } |
| 515 | |
| 516 | if (mask & ENCODE_CCODE) { |
| 517 | strcat(buf, "cc "); |
| 518 | } |
| 519 | if (mask & ENCODE_FP_STATUS) { |
| 520 | strcat(buf, "fpcc "); |
| 521 | } |
| 522 | |
| 523 | /* Memory bits */ |
| 524 | if (arm_lir && (mask & ENCODE_DALVIK_REG)) { |
| 525 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 526 | DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info), |
| 527 | DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : ""); |
| 528 | } |
| 529 | if (mask & ENCODE_LITERAL) { |
| 530 | strcat(buf, "lit "); |
| 531 | } |
| 532 | |
| 533 | if (mask & ENCODE_HEAP_REF) { |
| 534 | strcat(buf, "heap "); |
| 535 | } |
| 536 | if (mask & ENCODE_MUST_NOT_ALIAS) { |
| 537 | strcat(buf, "noalias "); |
| 538 | } |
| 539 | } |
| 540 | if (buf[0]) { |
| 541 | LOG(INFO) << prefix << ": " << buf; |
| 542 | } |
| 543 | } |
| 544 | |
| 545 | bool Arm64Mir2Lir::IsUnconditionalBranch(LIR* lir) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 546 | return (lir->opcode == kA64B1t); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 547 | } |
| 548 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 549 | bool Arm64Mir2Lir::SupportsVolatileLoadStore(OpSize size) { |
| 550 | return true; |
| 551 | } |
| 552 | |
| 553 | RegisterClass Arm64Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { |
| 554 | if (UNLIKELY(is_volatile)) { |
| 555 | // On arm64, fp register load/store is atomic only for single bytes. |
| 556 | if (size != kSignedByte && size != kUnsignedByte) { |
| 557 | return kCoreReg; |
| 558 | } |
| 559 | } |
| 560 | return RegClassBySize(size); |
| 561 | } |
| 562 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 563 | Arm64Mir2Lir::Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
| 564 | : Mir2Lir(cu, mir_graph, arena) { |
| 565 | // Sanity check - make sure encoding map lines up. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 566 | for (int i = 0; i < kA64Last; i++) { |
| 567 | if (UNWIDE(Arm64Mir2Lir::EncodingMap[i].opcode) != i) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 568 | LOG(FATAL) << "Encoding order for " << Arm64Mir2Lir::EncodingMap[i].name |
| 569 | << " is wrong: expecting " << i << ", seeing " |
| 570 | << static_cast<int>(Arm64Mir2Lir::EncodingMap[i].opcode); |
| 571 | } |
| 572 | } |
| 573 | } |
| 574 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 575 | Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 576 | ArenaAllocator* const arena) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 577 | return new Arm64Mir2Lir(cu, mir_graph, arena); |
| 578 | } |
| 579 | |
| 580 | // Alloc a pair of core registers, or a double. |
| 581 | RegStorage Arm64Mir2Lir::AllocTypedTempWide(bool fp_hint, int reg_class) { |
| 582 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) { |
| 583 | return AllocTempDouble(); |
| 584 | } else { |
| 585 | RegStorage low_reg = AllocTemp(); |
| 586 | RegStorage high_reg = AllocTemp(); |
| 587 | return RegStorage::MakeRegPair(low_reg, high_reg); |
| 588 | } |
| 589 | } |
| 590 | |
| 591 | RegStorage Arm64Mir2Lir::AllocTypedTemp(bool fp_hint, int reg_class) { |
| 592 | if (((reg_class == kAnyReg) && fp_hint) || (reg_class == kFPReg)) |
| 593 | return AllocTempSingle(); |
| 594 | return AllocTemp(); |
| 595 | } |
| 596 | |
| 597 | void Arm64Mir2Lir::CompilerInitializeRegAlloc() { |
| 598 | reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs, sp_regs, dp_regs, reserved_regs, |
| 599 | core_temps, sp_temps, dp_temps); |
| 600 | |
| 601 | // Target-specific adjustments. |
| 602 | |
| 603 | // Alias single precision floats to appropriate half of overlapping double. |
| 604 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); |
| 605 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 606 | int sp_reg_num = info->GetReg().GetRegNum(); |
| 607 | int dp_reg_num = sp_reg_num >> 1; |
| 608 | RegStorage dp_reg = RegStorage::Solo64(RegStorage::kFloatingPoint | dp_reg_num); |
| 609 | RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); |
| 610 | // Double precision register's master storage should refer to itself. |
| 611 | DCHECK_EQ(dp_reg_info, dp_reg_info->Master()); |
| 612 | // Redirect single precision's master storage to master. |
| 613 | info->SetMaster(dp_reg_info); |
| 614 | // Singles should show a single 32-bit mask bit, at first referring to the low half. |
| 615 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 616 | if (sp_reg_num & 1) { |
| 617 | // For odd singles, change to user the high word of the backing double. |
| 618 | info->SetStorageMask(0x2); |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | // TODO: re-enable this when we can safely save r4 over the suspension code path. |
| 623 | bool no_suspend = NO_SUSPEND; // || !Runtime::Current()->ExplicitSuspendChecks(); |
| 624 | if (no_suspend) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 625 | GetRegInfo(rs_rA64_SUSPEND)->MarkFree(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. |
| 629 | // TODO: adjust when we roll to hard float calling convention. |
| 630 | reg_pool_->next_core_reg_ = 2; |
| 631 | reg_pool_->next_sp_reg_ = 0; |
| 632 | reg_pool_->next_dp_reg_ = 0; |
| 633 | } |
| 634 | |
| 635 | void Arm64Mir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 636 | LOG(FATAL) << "Unexpected call to FreeRegLocTemps for Arm64"; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | /* |
| 640 | * TUNING: is true leaf? Can't just use METHOD_IS_LEAF to determine as some |
| 641 | * instructions might call out to C/assembly helper functions. Until |
| 642 | * machinery is in place, always spill lr. |
| 643 | */ |
| 644 | |
| 645 | void Arm64Mir2Lir::AdjustSpillMask() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 646 | core_spill_mask_ |= (1 << rs_rA64_LR.GetRegNum()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 647 | num_core_spills_++; |
| 648 | } |
| 649 | |
| 650 | /* |
| 651 | * Mark a callee-save fp register as promoted. Note that |
| 652 | * vpush/vpop uses contiguous register lists so we must |
| 653 | * include any holes in the mask. Associate holes with |
| 654 | * Dalvik register INVALID_VREG (0xFFFFU). |
| 655 | */ |
| 656 | void Arm64Mir2Lir::MarkPreservedSingle(int v_reg, RegStorage reg) { |
| 657 | DCHECK_GE(reg.GetRegNum(), ARM_FP_CALLEE_SAVE_BASE); |
| 658 | int adjusted_reg_num = reg.GetRegNum() - ARM_FP_CALLEE_SAVE_BASE; |
| 659 | // Ensure fp_vmap_table is large enough |
| 660 | int table_size = fp_vmap_table_.size(); |
| 661 | for (int i = table_size; i < (adjusted_reg_num + 1); i++) { |
| 662 | fp_vmap_table_.push_back(INVALID_VREG); |
| 663 | } |
| 664 | // Add the current mapping |
| 665 | fp_vmap_table_[adjusted_reg_num] = v_reg; |
| 666 | // Size of fp_vmap_table is high-water mark, use to set mask |
| 667 | num_fp_spills_ = fp_vmap_table_.size(); |
| 668 | fp_spill_mask_ = ((1 << num_fp_spills_) - 1) << ARM_FP_CALLEE_SAVE_BASE; |
| 669 | } |
| 670 | |
| 671 | void Arm64Mir2Lir::MarkPreservedDouble(int v_reg, RegStorage reg) { |
| 672 | // TEMP: perform as 2 singles. |
| 673 | int reg_num = reg.GetRegNum() << 1; |
| 674 | RegStorage lo = RegStorage::Solo32(RegStorage::kFloatingPoint | reg_num); |
| 675 | RegStorage hi = RegStorage::Solo32(RegStorage::kFloatingPoint | reg_num | 1); |
| 676 | MarkPreservedSingle(v_reg, lo); |
| 677 | MarkPreservedSingle(v_reg + 1, hi); |
| 678 | } |
| 679 | |
| 680 | /* Clobber all regs that might be used by an external C call */ |
| 681 | void Arm64Mir2Lir::ClobberCallerSave() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 682 | // TODO(Arm64): implement this. |
| 683 | UNIMPLEMENTED(WARNING); |
| 684 | |
| 685 | Clobber(rs_x0); |
| 686 | Clobber(rs_x1); |
| 687 | Clobber(rs_x2); |
| 688 | Clobber(rs_x3); |
| 689 | Clobber(rs_x12); |
| 690 | Clobber(rs_x30); |
| 691 | Clobber(rs_f0); |
| 692 | Clobber(rs_f1); |
| 693 | Clobber(rs_f2); |
| 694 | Clobber(rs_f3); |
| 695 | Clobber(rs_f4); |
| 696 | Clobber(rs_f5); |
| 697 | Clobber(rs_f6); |
| 698 | Clobber(rs_f7); |
| 699 | Clobber(rs_f8); |
| 700 | Clobber(rs_f9); |
| 701 | Clobber(rs_f10); |
| 702 | Clobber(rs_f11); |
| 703 | Clobber(rs_f12); |
| 704 | Clobber(rs_f13); |
| 705 | Clobber(rs_f14); |
| 706 | Clobber(rs_f15); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | RegLocation Arm64Mir2Lir::GetReturnWideAlt() { |
| 710 | RegLocation res = LocCReturnWide(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 711 | res.reg.SetReg(rx2); |
| 712 | res.reg.SetHighReg(rx3); |
| 713 | Clobber(rs_x2); |
| 714 | Clobber(rs_x3); |
| 715 | MarkInUse(rs_x2); |
| 716 | MarkInUse(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 717 | MarkWide(res.reg); |
| 718 | return res; |
| 719 | } |
| 720 | |
| 721 | RegLocation Arm64Mir2Lir::GetReturnAlt() { |
| 722 | RegLocation res = LocCReturn(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 723 | res.reg.SetReg(rx1); |
| 724 | Clobber(rs_x1); |
| 725 | MarkInUse(rs_x1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 726 | return res; |
| 727 | } |
| 728 | |
| 729 | /* To be used when explicitly managing register use */ |
| 730 | void Arm64Mir2Lir::LockCallTemps() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 731 | LockTemp(rs_x0); |
| 732 | LockTemp(rs_x1); |
| 733 | LockTemp(rs_x2); |
| 734 | LockTemp(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | /* To be used when explicitly managing register use */ |
| 738 | void Arm64Mir2Lir::FreeCallTemps() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 739 | FreeTemp(rs_x0); |
| 740 | FreeTemp(rs_x1); |
| 741 | FreeTemp(rs_x2); |
| 742 | FreeTemp(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 743 | } |
| 744 | |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 745 | RegStorage Arm64Mir2Lir::LoadHelper(ThreadOffset<4> offset) { |
| 746 | UNIMPLEMENTED(FATAL) << "Should not be called."; |
| 747 | return RegStorage::InvalidReg(); |
| 748 | } |
| 749 | |
| 750 | RegStorage Arm64Mir2Lir::LoadHelper(ThreadOffset<8> offset) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 751 | // TODO(Arm64): use LoadWordDisp instead. |
| 752 | // e.g. LoadWordDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR); |
| 753 | LoadBaseDisp(rs_rA64_SELF, offset.Int32Value(), rs_rA64_LR, k64); |
| 754 | return rs_rA64_LR; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 755 | } |
| 756 | |
| 757 | LIR* Arm64Mir2Lir::CheckSuspendUsingLoad() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 758 | RegStorage tmp = rs_x0; |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 759 | LoadWordDisp(rs_rA64_SELF, Thread::ThreadSuspendTriggerOffset<8>().Int32Value(), tmp); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 760 | LIR* load2 = LoadWordDisp(tmp, 0, tmp); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 761 | return load2; |
| 762 | } |
| 763 | |
| 764 | uint64_t Arm64Mir2Lir::GetTargetInstFlags(int opcode) { |
| 765 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 766 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].flags; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 767 | } |
| 768 | |
| 769 | const char* Arm64Mir2Lir::GetTargetInstName(int opcode) { |
| 770 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 771 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].name; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | const char* Arm64Mir2Lir::GetTargetInstFmt(int opcode) { |
| 775 | DCHECK(!IsPseudoLirOp(opcode)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 776 | return Arm64Mir2Lir::EncodingMap[UNWIDE(opcode)].fmt; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 777 | } |
| 778 | |
| 779 | /* |
| 780 | * Somewhat messy code here. We want to allocate a pair of contiguous |
| 781 | * physical single-precision floating point registers starting with |
| 782 | * an even numbered reg. It is possible that the paired s_reg (s_reg+1) |
| 783 | * has already been allocated - try to fit if possible. Fail to |
| 784 | * allocate if we can't meet the requirements for the pair of |
| 785 | * s_reg<=sX[even] & (s_reg+1)<= sX+1. |
| 786 | */ |
| 787 | // TODO: needs rewrite to support non-backed 64-bit float regs. |
| 788 | RegStorage Arm64Mir2Lir::AllocPreservedDouble(int s_reg) { |
| 789 | RegStorage res; |
| 790 | int v_reg = mir_graph_->SRegToVReg(s_reg); |
| 791 | int p_map_idx = SRegToPMap(s_reg); |
| 792 | if (promotion_map_[p_map_idx+1].fp_location == kLocPhysReg) { |
| 793 | // Upper reg is already allocated. Can we fit? |
| 794 | int high_reg = promotion_map_[p_map_idx+1].FpReg; |
| 795 | if ((high_reg & 1) == 0) { |
| 796 | // High reg is even - fail. |
| 797 | return res; // Invalid. |
| 798 | } |
| 799 | // Is the low reg of the pair free? |
| 800 | // FIXME: rework. |
| 801 | RegisterInfo* p = GetRegInfo(RegStorage::FloatSolo32(high_reg - 1)); |
| 802 | if (p->InUse() || p->IsTemp()) { |
| 803 | // Already allocated or not preserved - fail. |
| 804 | return res; // Invalid. |
| 805 | } |
| 806 | // OK - good to go. |
| 807 | res = RegStorage::FloatSolo64(p->GetReg().GetRegNum() >> 1); |
| 808 | p->MarkInUse(); |
| 809 | MarkPreservedSingle(v_reg, p->GetReg()); |
| 810 | } else { |
| 811 | /* |
| 812 | * TODO: until runtime support is in, make sure we avoid promoting the same vreg to |
| 813 | * different underlying physical registers. |
| 814 | */ |
| 815 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->dp_regs_); |
| 816 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 817 | if (!info->IsTemp() && !info->InUse()) { |
| 818 | res = info->GetReg(); |
| 819 | info->MarkInUse(); |
| 820 | MarkPreservedDouble(v_reg, info->GetReg()); |
| 821 | break; |
| 822 | } |
| 823 | } |
| 824 | } |
| 825 | if (res.Valid()) { |
| 826 | promotion_map_[p_map_idx].fp_location = kLocPhysReg; |
| 827 | promotion_map_[p_map_idx].FpReg = res.DoubleToLowSingle().GetReg(); |
| 828 | promotion_map_[p_map_idx+1].fp_location = kLocPhysReg; |
| 829 | promotion_map_[p_map_idx+1].FpReg = res.DoubleToHighSingle().GetReg(); |
| 830 | } |
| 831 | return res; |
| 832 | } |
| 833 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 834 | // TODO(Arm64): reuse info in QuickArgumentVisitor? |
| 835 | static RegStorage GetArgPhysicalReg(RegLocation* loc, int* num_gpr_used, int* num_fpr_used, |
| 836 | OpSize* op_size) { |
| 837 | if (loc->fp) { |
| 838 | int n = *num_fpr_used; |
| 839 | if (n < 8) { |
| 840 | *num_fpr_used = n + 1; |
| 841 | RegStorage::RegStorageKind reg_kind; |
| 842 | if (loc->wide) { |
| 843 | *op_size = kDouble; |
| 844 | reg_kind = RegStorage::k64BitSolo; |
| 845 | } else { |
| 846 | *op_size = kSingle; |
| 847 | reg_kind = RegStorage::k32BitSolo; |
| 848 | } |
| 849 | return RegStorage(RegStorage::kValid | reg_kind | RegStorage::kFloatingPoint | n); |
| 850 | } |
| 851 | } else { |
| 852 | int n = *num_gpr_used; |
| 853 | if (n < 7) { |
| 854 | *num_gpr_used = n + 1; |
| 855 | if (loc->wide) { |
| 856 | *op_size = k64; |
| 857 | return RegStorage::Solo64(n); |
| 858 | } else { |
| 859 | *op_size = k32; |
| 860 | return RegStorage::Solo32(n); |
| 861 | } |
| 862 | } |
| 863 | } |
| 864 | |
| 865 | return RegStorage::InvalidReg(); |
| 866 | } |
| 867 | |
| 868 | /* |
| 869 | * If there are any ins passed in registers that have not been promoted |
| 870 | * to a callee-save register, flush them to the frame. Perform initial |
| 871 | * assignment of promoted arguments. |
| 872 | * |
| 873 | * ArgLocs is an array of location records describing the incoming arguments |
| 874 | * with one location record per word of argument. |
| 875 | */ |
| 876 | void Arm64Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { |
| 877 | int num_gpr_used = 1; |
| 878 | int num_fpr_used = 0; |
| 879 | |
| 880 | /* |
| 881 | * Dummy up a RegLocation for the incoming Method* |
| 882 | * It will attempt to keep kArg0 live (or copy it to home location |
| 883 | * if promoted). |
| 884 | */ |
| 885 | RegLocation rl_src = rl_method; |
| 886 | rl_src.location = kLocPhysReg; |
| 887 | rl_src.reg = TargetReg(kArg0); |
| 888 | rl_src.home = false; |
| 889 | MarkLive(rl_src); |
| 890 | |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 891 | // rl_method might be 32-bit, but ArtMethod* on stack is 64-bit, so always flush it. |
| 892 | StoreWordDisp(TargetReg(kSp), 0, TargetReg(kArg0)); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 893 | |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 894 | // If Method* has been promoted, load it, |
| 895 | // otherwise, rl_method is the 32-bit value on [sp], and has already been loaded. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 896 | if (rl_method.location == kLocPhysReg) { |
Zheng Xu | c830430 | 2014-05-15 17:21:01 +0100 | [diff] [blame^] | 897 | StoreValue(rl_method, rl_src); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 898 | } |
| 899 | |
| 900 | if (cu_->num_ins == 0) { |
| 901 | return; |
| 902 | } |
| 903 | |
| 904 | int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; |
| 905 | for (int i = 0; i < cu_->num_ins; i++) { |
| 906 | PromotionMap* v_map = &promotion_map_[start_vreg + i]; |
| 907 | RegLocation* t_loc = &ArgLocs[i]; |
| 908 | OpSize op_size; |
| 909 | RegStorage reg = GetArgPhysicalReg(t_loc, &num_gpr_used, &num_fpr_used, &op_size); |
| 910 | |
| 911 | if (reg.Valid()) { |
| 912 | if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { |
| 913 | OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg); |
| 914 | } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { |
| 915 | OpRegCopy(RegStorage::Solo32(v_map->FpReg), reg); |
| 916 | } else { |
| 917 | StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), reg, op_size); |
| 918 | if (reg.Is64Bit()) { |
| 919 | if (SRegOffset(start_vreg + i) + 4 != SRegOffset(start_vreg + i + 1)) { |
| 920 | LOG(FATAL) << "64 bit value stored in non-consecutive 4 bytes slots"; |
| 921 | } |
| 922 | i += 1; |
| 923 | } |
| 924 | } |
| 925 | } else { |
| 926 | // If arriving in frame & promoted |
| 927 | if (v_map->core_location == kLocPhysReg) { |
| 928 | LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), |
| 929 | RegStorage::Solo32(v_map->core_reg)); |
| 930 | } |
| 931 | if (v_map->fp_location == kLocPhysReg) { |
| 932 | LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->FpReg)); |
| 933 | } |
| 934 | } |
| 935 | } |
| 936 | } |
| 937 | |
| 938 | int Arm64Mir2Lir::LoadArgRegs(CallInfo* info, int call_state, |
| 939 | NextCallInsn next_call_insn, |
| 940 | const MethodReference& target_method, |
| 941 | uint32_t vtable_idx, uintptr_t direct_code, |
| 942 | uintptr_t direct_method, InvokeType type, bool skip_this) { |
| 943 | int last_arg_reg = TargetReg(kArg3).GetReg(); |
| 944 | int next_reg = TargetReg(kArg1).GetReg(); |
| 945 | int next_arg = 0; |
| 946 | if (skip_this) { |
| 947 | next_reg++; |
| 948 | next_arg++; |
| 949 | } |
| 950 | for (; (next_reg <= last_arg_reg) && (next_arg < info->num_arg_words); next_reg++) { |
| 951 | RegLocation rl_arg = info->args[next_arg++]; |
| 952 | rl_arg = UpdateRawLoc(rl_arg); |
| 953 | if (rl_arg.wide && (next_reg <= TargetReg(kArg2).GetReg())) { |
| 954 | RegStorage r_tmp(RegStorage::k64BitPair, next_reg, next_reg + 1); |
| 955 | LoadValueDirectWideFixed(rl_arg, r_tmp); |
| 956 | next_reg++; |
| 957 | next_arg++; |
| 958 | } else { |
| 959 | if (rl_arg.wide) { |
| 960 | rl_arg = NarrowRegLoc(rl_arg); |
| 961 | rl_arg.is_const = false; |
| 962 | } |
| 963 | LoadValueDirectFixed(rl_arg, RegStorage::Solo32(next_reg)); |
| 964 | } |
| 965 | call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, |
| 966 | direct_code, direct_method, type); |
| 967 | } |
| 968 | return call_state; |
| 969 | } |
| 970 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 971 | } // namespace art |