Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the Thumb2 ISA. */ |
| 18 | |
| 19 | #include "arm_lir.h" |
| 20 | #include "codegen_arm.h" |
| 21 | #include "dex/quick/mir_to_lir-inl.h" |
| 22 | #include "mirror/array.h" |
| 23 | #include "oat/runtime/oat_support_entrypoints.h" |
| 24 | |
| 25 | namespace art { |
| 26 | |
| 27 | LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, int src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 28 | int src2, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | OpRegReg(kOpCmp, src1, src2); |
| 30 | return OpCondBranch(cond, target); |
| 31 | } |
| 32 | |
| 33 | /* |
| 34 | * Generate a Thumb2 IT instruction, which can nullify up to |
| 35 | * four subsequent instructions based on a condition and its |
| 36 | * inverse. The condition applies to the first instruction, which |
| 37 | * is executed if the condition is met. The string "guide" consists |
| 38 | * of 0 to 3 chars, and applies to the 2nd through 4th instruction. |
| 39 | * A "T" means the instruction is executed if the condition is |
| 40 | * met, and an "E" means the instruction is executed if the condition |
| 41 | * is not met. |
| 42 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 43 | LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 44 | int mask; |
| 45 | int mask3 = 0; |
| 46 | int mask2 = 0; |
| 47 | int mask1 = 0; |
| 48 | ArmConditionCode code = ArmConditionEncoding(ccode); |
| 49 | int cond_bit = code & 1; |
| 50 | int alt_bit = cond_bit ^ 1; |
| 51 | |
| 52 | //Note: case fallthroughs intentional |
| 53 | switch (strlen(guide)) { |
| 54 | case 3: |
| 55 | mask1 = (guide[2] == 'T') ? cond_bit : alt_bit; |
| 56 | case 2: |
| 57 | mask2 = (guide[1] == 'T') ? cond_bit : alt_bit; |
| 58 | case 1: |
| 59 | mask3 = (guide[0] == 'T') ? cond_bit : alt_bit; |
| 60 | break; |
| 61 | case 0: |
| 62 | break; |
| 63 | default: |
| 64 | LOG(FATAL) << "OAT: bad case in OpIT"; |
| 65 | } |
| 66 | mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | |
| 67 | (1 << (3 - strlen(guide))); |
| 68 | return NewLIR2(kThumb2It, code, mask); |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * 64-bit 3way compare function. |
| 73 | * mov rX, #-1 |
| 74 | * cmp op1hi, op2hi |
| 75 | * blt done |
| 76 | * bgt flip |
| 77 | * sub rX, op1lo, op2lo (treat as unsigned) |
| 78 | * beq done |
| 79 | * ite hi |
| 80 | * mov(hi) rX, #-1 |
| 81 | * mov(!hi) rX, #1 |
| 82 | * flip: |
| 83 | * neg rX |
| 84 | * done: |
| 85 | */ |
| 86 | void ArmMir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 87 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 88 | LIR* target1; |
| 89 | LIR* target2; |
| 90 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 91 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 92 | int t_reg = AllocTemp(); |
| 93 | LoadConstant(t_reg, -1); |
| 94 | OpRegReg(kOpCmp, rl_src1.high_reg, rl_src2.high_reg); |
| 95 | LIR* branch1 = OpCondBranch(kCondLt, NULL); |
| 96 | LIR* branch2 = OpCondBranch(kCondGt, NULL); |
| 97 | OpRegRegReg(kOpSub, t_reg, rl_src1.low_reg, rl_src2.low_reg); |
| 98 | LIR* branch3 = OpCondBranch(kCondEq, NULL); |
| 99 | |
| 100 | OpIT(kCondHi, "E"); |
| 101 | NewLIR2(kThumb2MovImmShift, t_reg, ModifiedImmediate(-1)); |
| 102 | LoadConstant(t_reg, 1); |
| 103 | GenBarrier(); |
| 104 | |
| 105 | target2 = NewLIR0(kPseudoTargetLabel); |
| 106 | OpRegReg(kOpNeg, t_reg, t_reg); |
| 107 | |
| 108 | target1 = NewLIR0(kPseudoTargetLabel); |
| 109 | |
| 110 | RegLocation rl_temp = LocCReturn(); // Just using as template, will change |
| 111 | rl_temp.low_reg = t_reg; |
| 112 | StoreValue(rl_dest, rl_temp); |
| 113 | FreeTemp(t_reg); |
| 114 | |
| 115 | branch1->target = target1; |
| 116 | branch2->target = target2; |
| 117 | branch3->target = branch1->target; |
| 118 | } |
| 119 | |
| 120 | void ArmMir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 121 | int64_t val, ConditionCode ccode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 122 | int32_t val_lo = Low32Bits(val); |
| 123 | int32_t val_hi = High32Bits(val); |
| 124 | DCHECK(ModifiedImmediate(val_lo) >= 0); |
| 125 | DCHECK(ModifiedImmediate(val_hi) >= 0); |
| 126 | LIR* taken = &block_label_list_[bb->taken->id]; |
| 127 | LIR* not_taken = &block_label_list_[bb->fall_through->id]; |
| 128 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 129 | int32_t low_reg = rl_src1.low_reg; |
| 130 | int32_t high_reg = rl_src1.high_reg; |
| 131 | |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame^] | 132 | switch (ccode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 133 | case kCondEq: |
| 134 | case kCondNe: |
| 135 | LIR* target; |
| 136 | ConditionCode condition; |
| 137 | if (ccode == kCondEq) { |
| 138 | target = not_taken; |
| 139 | condition = kCondEq; |
| 140 | } else { |
| 141 | target = taken; |
| 142 | condition = kCondNe; |
| 143 | } |
| 144 | if (val == 0) { |
| 145 | int t_reg = AllocTemp(); |
| 146 | NewLIR4(kThumb2OrrRRRs, t_reg, low_reg, high_reg, 0); |
| 147 | FreeTemp(t_reg); |
| 148 | OpCondBranch(condition, taken); |
| 149 | return; |
| 150 | } |
| 151 | OpCmpImmBranch(kCondNe, high_reg, val_hi, target); |
| 152 | break; |
| 153 | case kCondLt: |
| 154 | OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); |
| 155 | OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); |
| 156 | ccode = kCondCc; |
| 157 | break; |
| 158 | case kCondLe: |
| 159 | OpCmpImmBranch(kCondLt, high_reg, val_hi, taken); |
| 160 | OpCmpImmBranch(kCondGt, high_reg, val_hi, not_taken); |
| 161 | ccode = kCondLs; |
| 162 | break; |
| 163 | case kCondGt: |
| 164 | OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); |
| 165 | OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); |
| 166 | ccode = kCondHi; |
| 167 | break; |
| 168 | case kCondGe: |
| 169 | OpCmpImmBranch(kCondGt, high_reg, val_hi, taken); |
| 170 | OpCmpImmBranch(kCondLt, high_reg, val_hi, not_taken); |
| 171 | ccode = kCondCs; |
| 172 | break; |
| 173 | default: |
| 174 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 175 | } |
| 176 | OpCmpImmBranch(ccode, low_reg, val_lo, taken); |
| 177 | } |
| 178 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 179 | void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 180 | RegLocation rl_result; |
| 181 | RegLocation rl_src = mir_graph_->GetSrc(mir, 0); |
| 182 | // Temporary debugging code |
| 183 | int dest_sreg = mir->ssa_rep->defs[0]; |
| 184 | if ((dest_sreg < 0) || (dest_sreg >= mir_graph_->GetNumSSARegs())) { |
| 185 | LOG(INFO) << "Bad target sreg: " << dest_sreg << ", in " |
Brian Carlstrom | b1eba21 | 2013-07-17 18:07:19 -0700 | [diff] [blame] | 186 | << PrettyMethod(cu_->method_idx, *cu_->dex_file); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 187 | LOG(INFO) << "at dex offset 0x" << std::hex << mir->offset; |
| 188 | LOG(INFO) << "vreg = " << mir_graph_->SRegToVReg(dest_sreg); |
| 189 | LOG(INFO) << "num uses = " << mir->ssa_rep->num_uses; |
| 190 | if (mir->ssa_rep->num_uses == 1) { |
| 191 | LOG(INFO) << "CONST case, vals = " << mir->dalvikInsn.vB << ", " << mir->dalvikInsn.vC; |
| 192 | } else { |
| 193 | LOG(INFO) << "MOVE case, operands = " << mir->ssa_rep->uses[1] << ", " |
| 194 | << mir->ssa_rep->uses[2]; |
| 195 | } |
| 196 | CHECK(false) << "Invalid target sreg on Select."; |
| 197 | } |
| 198 | // End temporary debugging code |
| 199 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
| 200 | rl_src = LoadValue(rl_src, kCoreReg); |
| 201 | if (mir->ssa_rep->num_uses == 1) { |
| 202 | // CONST case |
| 203 | int true_val = mir->dalvikInsn.vB; |
| 204 | int false_val = mir->dalvikInsn.vC; |
| 205 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 206 | if ((true_val == 1) && (false_val == 0)) { |
| 207 | OpRegRegImm(kOpRsub, rl_result.low_reg, rl_src.low_reg, 1); |
| 208 | OpIT(kCondCc, ""); |
| 209 | LoadConstant(rl_result.low_reg, 0); |
| 210 | GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact |
| 211 | } else if (InexpensiveConstantInt(true_val) && InexpensiveConstantInt(false_val)) { |
| 212 | OpRegImm(kOpCmp, rl_src.low_reg, 0); |
| 213 | OpIT(kCondEq, "E"); |
| 214 | LoadConstant(rl_result.low_reg, true_val); |
| 215 | LoadConstant(rl_result.low_reg, false_val); |
| 216 | GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact |
| 217 | } else { |
| 218 | // Unlikely case - could be tuned. |
| 219 | int t_reg1 = AllocTemp(); |
| 220 | int t_reg2 = AllocTemp(); |
| 221 | LoadConstant(t_reg1, true_val); |
| 222 | LoadConstant(t_reg2, false_val); |
| 223 | OpRegImm(kOpCmp, rl_src.low_reg, 0); |
| 224 | OpIT(kCondEq, "E"); |
| 225 | OpRegCopy(rl_result.low_reg, t_reg1); |
| 226 | OpRegCopy(rl_result.low_reg, t_reg2); |
| 227 | GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact |
| 228 | } |
| 229 | } else { |
| 230 | // MOVE case |
| 231 | RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]]; |
| 232 | RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]]; |
| 233 | rl_true = LoadValue(rl_true, kCoreReg); |
| 234 | rl_false = LoadValue(rl_false, kCoreReg); |
| 235 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 236 | OpRegImm(kOpCmp, rl_src.low_reg, 0); |
| 237 | OpIT(kCondEq, "E"); |
| 238 | LIR* l1 = OpRegCopy(rl_result.low_reg, rl_true.low_reg); |
| 239 | l1->flags.is_nop = false; // Make sure this instruction isn't optimized away |
| 240 | LIR* l2 = OpRegCopy(rl_result.low_reg, rl_false.low_reg); |
| 241 | l2->flags.is_nop = false; // Make sure this instruction isn't optimized away |
| 242 | GenBarrier(); // Add a scheduling barrier to keep the IT shadow intact |
| 243 | } |
| 244 | StoreValue(rl_dest, rl_result); |
| 245 | } |
| 246 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 247 | void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 248 | RegLocation rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 249 | RegLocation rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
| 250 | // Normalize such that if either operand is constant, src2 will be constant. |
| 251 | ConditionCode ccode = static_cast<ConditionCode>(mir->dalvikInsn.arg[0]); |
| 252 | if (rl_src1.is_const) { |
| 253 | RegLocation rl_temp = rl_src1; |
| 254 | rl_src1 = rl_src2; |
| 255 | rl_src2 = rl_temp; |
| 256 | ccode = FlipComparisonOrder(ccode); |
| 257 | } |
| 258 | if (rl_src2.is_const) { |
| 259 | RegLocation rl_temp = UpdateLocWide(rl_src2); |
| 260 | // Do special compare/branch against simple const operand if not already in registers. |
| 261 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 262 | if ((rl_temp.location != kLocPhysReg) && |
| 263 | ((ModifiedImmediate(Low32Bits(val)) >= 0) && (ModifiedImmediate(High32Bits(val)) >= 0))) { |
| 264 | GenFusedLongCmpImmBranch(bb, rl_src1, val, ccode); |
| 265 | return; |
| 266 | } |
| 267 | } |
| 268 | LIR* taken = &block_label_list_[bb->taken->id]; |
| 269 | LIR* not_taken = &block_label_list_[bb->fall_through->id]; |
| 270 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 271 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 272 | OpRegReg(kOpCmp, rl_src1.high_reg, rl_src2.high_reg); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame^] | 273 | switch (ccode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 274 | case kCondEq: |
| 275 | OpCondBranch(kCondNe, not_taken); |
| 276 | break; |
| 277 | case kCondNe: |
| 278 | OpCondBranch(kCondNe, taken); |
| 279 | break; |
| 280 | case kCondLt: |
| 281 | OpCondBranch(kCondLt, taken); |
| 282 | OpCondBranch(kCondGt, not_taken); |
| 283 | ccode = kCondCc; |
| 284 | break; |
| 285 | case kCondLe: |
| 286 | OpCondBranch(kCondLt, taken); |
| 287 | OpCondBranch(kCondGt, not_taken); |
| 288 | ccode = kCondLs; |
| 289 | break; |
| 290 | case kCondGt: |
| 291 | OpCondBranch(kCondGt, taken); |
| 292 | OpCondBranch(kCondLt, not_taken); |
| 293 | ccode = kCondHi; |
| 294 | break; |
| 295 | case kCondGe: |
| 296 | OpCondBranch(kCondGt, taken); |
| 297 | OpCondBranch(kCondLt, not_taken); |
| 298 | ccode = kCondCs; |
| 299 | break; |
| 300 | default: |
| 301 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 302 | } |
| 303 | OpRegReg(kOpCmp, rl_src1.low_reg, rl_src2.low_reg); |
| 304 | OpCondBranch(ccode, taken); |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * Generate a register comparison to an immediate and branch. Caller |
| 309 | * is responsible for setting branch target field. |
| 310 | */ |
| 311 | LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, int reg, int check_value, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 312 | LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 313 | LIR* branch; |
| 314 | int mod_imm; |
| 315 | ArmConditionCode arm_cond = ArmConditionEncoding(cond); |
| 316 | if ((ARM_LOWREG(reg)) && (check_value == 0) && |
| 317 | ((arm_cond == kArmCondEq) || (arm_cond == kArmCondNe))) { |
| 318 | branch = NewLIR2((arm_cond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz, |
| 319 | reg, 0); |
| 320 | } else { |
| 321 | mod_imm = ModifiedImmediate(check_value); |
| 322 | if (ARM_LOWREG(reg) && ((check_value & 0xff) == check_value)) { |
| 323 | NewLIR2(kThumbCmpRI8, reg, check_value); |
| 324 | } else if (mod_imm >= 0) { |
| 325 | NewLIR2(kThumb2CmpRI12, reg, mod_imm); |
| 326 | } else { |
| 327 | int t_reg = AllocTemp(); |
| 328 | LoadConstant(t_reg, check_value); |
| 329 | OpRegReg(kOpCmp, reg, t_reg); |
| 330 | } |
| 331 | branch = NewLIR2(kThumbBCond, 0, arm_cond); |
| 332 | } |
| 333 | branch->target = target; |
| 334 | return branch; |
| 335 | } |
| 336 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 337 | LIR* ArmMir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 338 | LIR* res; |
| 339 | int opcode; |
| 340 | if (ARM_FPREG(r_dest) || ARM_FPREG(r_src)) |
| 341 | return OpFpRegCopy(r_dest, r_src); |
| 342 | if (ARM_LOWREG(r_dest) && ARM_LOWREG(r_src)) |
| 343 | opcode = kThumbMovRR; |
| 344 | else if (!ARM_LOWREG(r_dest) && !ARM_LOWREG(r_src)) |
| 345 | opcode = kThumbMovRR_H2H; |
| 346 | else if (ARM_LOWREG(r_dest)) |
| 347 | opcode = kThumbMovRR_H2L; |
| 348 | else |
| 349 | opcode = kThumbMovRR_L2H; |
| 350 | res = RawLIR(current_dalvik_offset_, opcode, r_dest, r_src); |
| 351 | if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { |
| 352 | res->flags.is_nop = true; |
| 353 | } |
| 354 | return res; |
| 355 | } |
| 356 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 357 | LIR* ArmMir2Lir::OpRegCopy(int r_dest, int r_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 358 | LIR* res = OpRegCopyNoInsert(r_dest, r_src); |
| 359 | AppendLIR(res); |
| 360 | return res; |
| 361 | } |
| 362 | |
| 363 | void ArmMir2Lir::OpRegCopyWide(int dest_lo, int dest_hi, int src_lo, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 364 | int src_hi) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 365 | bool dest_fp = ARM_FPREG(dest_lo) && ARM_FPREG(dest_hi); |
| 366 | bool src_fp = ARM_FPREG(src_lo) && ARM_FPREG(src_hi); |
| 367 | DCHECK_EQ(ARM_FPREG(src_lo), ARM_FPREG(src_hi)); |
| 368 | DCHECK_EQ(ARM_FPREG(dest_lo), ARM_FPREG(dest_hi)); |
| 369 | if (dest_fp) { |
| 370 | if (src_fp) { |
| 371 | OpRegCopy(S2d(dest_lo, dest_hi), S2d(src_lo, src_hi)); |
| 372 | } else { |
| 373 | NewLIR3(kThumb2Fmdrr, S2d(dest_lo, dest_hi), src_lo, src_hi); |
| 374 | } |
| 375 | } else { |
| 376 | if (src_fp) { |
| 377 | NewLIR3(kThumb2Fmrrd, dest_lo, dest_hi, S2d(src_lo, src_hi)); |
| 378 | } else { |
| 379 | // Handle overlap |
| 380 | if (src_hi == dest_lo) { |
| 381 | OpRegCopy(dest_hi, src_hi); |
| 382 | OpRegCopy(dest_lo, src_lo); |
| 383 | } else { |
| 384 | OpRegCopy(dest_lo, src_lo); |
| 385 | OpRegCopy(dest_hi, src_hi); |
| 386 | } |
| 387 | } |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | // Table of magic divisors |
| 392 | struct MagicTable { |
| 393 | uint32_t magic; |
| 394 | uint32_t shift; |
| 395 | DividePattern pattern; |
| 396 | }; |
| 397 | |
| 398 | static const MagicTable magic_table[] = { |
| 399 | {0, 0, DivideNone}, // 0 |
| 400 | {0, 0, DivideNone}, // 1 |
| 401 | {0, 0, DivideNone}, // 2 |
| 402 | {0x55555556, 0, Divide3}, // 3 |
| 403 | {0, 0, DivideNone}, // 4 |
| 404 | {0x66666667, 1, Divide5}, // 5 |
| 405 | {0x2AAAAAAB, 0, Divide3}, // 6 |
| 406 | {0x92492493, 2, Divide7}, // 7 |
| 407 | {0, 0, DivideNone}, // 8 |
| 408 | {0x38E38E39, 1, Divide5}, // 9 |
| 409 | {0x66666667, 2, Divide5}, // 10 |
| 410 | {0x2E8BA2E9, 1, Divide5}, // 11 |
| 411 | {0x2AAAAAAB, 1, Divide5}, // 12 |
| 412 | {0x4EC4EC4F, 2, Divide5}, // 13 |
| 413 | {0x92492493, 3, Divide7}, // 14 |
| 414 | {0x88888889, 3, Divide7}, // 15 |
| 415 | }; |
| 416 | |
| 417 | // Integer division by constant via reciprocal multiply (Hacker's Delight, 10-4) |
| 418 | bool ArmMir2Lir::SmallLiteralDivide(Instruction::Code dalvik_opcode, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 419 | RegLocation rl_src, RegLocation rl_dest, int lit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 420 | if ((lit < 0) || (lit >= static_cast<int>(sizeof(magic_table)/sizeof(magic_table[0])))) { |
| 421 | return false; |
| 422 | } |
| 423 | DividePattern pattern = magic_table[lit].pattern; |
| 424 | if (pattern == DivideNone) { |
| 425 | return false; |
| 426 | } |
| 427 | // Tuning: add rem patterns |
| 428 | if (dalvik_opcode != Instruction::DIV_INT_LIT8) { |
| 429 | return false; |
| 430 | } |
| 431 | |
| 432 | int r_magic = AllocTemp(); |
| 433 | LoadConstant(r_magic, magic_table[lit].magic); |
| 434 | rl_src = LoadValue(rl_src, kCoreReg); |
| 435 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 436 | int r_hi = AllocTemp(); |
| 437 | int r_lo = AllocTemp(); |
| 438 | NewLIR4(kThumb2Smull, r_lo, r_hi, r_magic, rl_src.low_reg); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame^] | 439 | switch (pattern) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 440 | case Divide3: |
| 441 | OpRegRegRegShift(kOpSub, rl_result.low_reg, r_hi, |
| 442 | rl_src.low_reg, EncodeShift(kArmAsr, 31)); |
| 443 | break; |
| 444 | case Divide5: |
| 445 | OpRegRegImm(kOpAsr, r_lo, rl_src.low_reg, 31); |
| 446 | OpRegRegRegShift(kOpRsub, rl_result.low_reg, r_lo, r_hi, |
| 447 | EncodeShift(kArmAsr, magic_table[lit].shift)); |
| 448 | break; |
| 449 | case Divide7: |
| 450 | OpRegReg(kOpAdd, r_hi, rl_src.low_reg); |
| 451 | OpRegRegImm(kOpAsr, r_lo, rl_src.low_reg, 31); |
| 452 | OpRegRegRegShift(kOpRsub, rl_result.low_reg, r_lo, r_hi, |
| 453 | EncodeShift(kArmAsr, magic_table[lit].shift)); |
| 454 | break; |
| 455 | default: |
| 456 | LOG(FATAL) << "Unexpected pattern: " << pattern; |
| 457 | } |
| 458 | StoreValue(rl_dest, rl_result); |
| 459 | return true; |
| 460 | } |
| 461 | |
| 462 | LIR* ArmMir2Lir::GenRegMemCheck(ConditionCode c_code, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 463 | int reg1, int base, int offset, ThrowKind kind) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 464 | LOG(FATAL) << "Unexpected use of GenRegMemCheck for Arm"; |
| 465 | return NULL; |
| 466 | } |
| 467 | |
| 468 | RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 469 | bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 470 | LOG(FATAL) << "Unexpected use of GenDivRemLit for Arm"; |
| 471 | return rl_dest; |
| 472 | } |
| 473 | |
| 474 | RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 475 | bool is_div) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 476 | LOG(FATAL) << "Unexpected use of GenDivRem for Arm"; |
| 477 | return rl_dest; |
| 478 | } |
| 479 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 480 | bool ArmMir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 481 | DCHECK_EQ(cu_->instruction_set, kThumb2); |
| 482 | RegLocation rl_src1 = info->args[0]; |
| 483 | RegLocation rl_src2 = info->args[1]; |
| 484 | rl_src1 = LoadValue(rl_src1, kCoreReg); |
| 485 | rl_src2 = LoadValue(rl_src2, kCoreReg); |
| 486 | RegLocation rl_dest = InlineTarget(info); |
| 487 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 488 | OpRegReg(kOpCmp, rl_src1.low_reg, rl_src2.low_reg); |
| 489 | OpIT((is_min) ? kCondGt : kCondLt, "E"); |
| 490 | OpRegReg(kOpMov, rl_result.low_reg, rl_src2.low_reg); |
| 491 | OpRegReg(kOpMov, rl_result.low_reg, rl_src1.low_reg); |
| 492 | GenBarrier(); |
| 493 | StoreValue(rl_dest, rl_result); |
| 494 | return true; |
| 495 | } |
| 496 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 497 | void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 498 | LOG(FATAL) << "Unexpected use of OpLea for Arm"; |
| 499 | } |
| 500 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 501 | void ArmMir2Lir::OpTlsCmp(int offset, int val) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 502 | LOG(FATAL) << "Unexpected use of OpTlsCmp for Arm"; |
| 503 | } |
| 504 | |
| 505 | bool ArmMir2Lir::GenInlinedCas32(CallInfo* info, bool need_write_barrier) { |
| 506 | DCHECK_EQ(cu_->instruction_set, kThumb2); |
| 507 | // Unused - RegLocation rl_src_unsafe = info->args[0]; |
| 508 | RegLocation rl_src_obj= info->args[1]; // Object - known non-null |
| 509 | RegLocation rl_src_offset= info->args[2]; // long low |
| 510 | rl_src_offset.wide = 0; // ignore high half in info->args[3] |
| 511 | RegLocation rl_src_expected= info->args[4]; // int or Object |
| 512 | RegLocation rl_src_new_value= info->args[5]; // int or Object |
| 513 | RegLocation rl_dest = InlineTarget(info); // boolean place for result |
| 514 | |
| 515 | |
| 516 | // Release store semantics, get the barrier out of the way. TODO: revisit |
| 517 | GenMemBarrier(kStoreLoad); |
| 518 | |
| 519 | RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg); |
| 520 | RegLocation rl_new_value = LoadValue(rl_src_new_value, kCoreReg); |
| 521 | |
| 522 | if (need_write_barrier && !mir_graph_->IsConstantNullRef(rl_new_value)) { |
| 523 | // Mark card for object assuming new value is stored. |
| 524 | MarkGCCard(rl_new_value.low_reg, rl_object.low_reg); |
| 525 | } |
| 526 | |
| 527 | RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); |
| 528 | |
| 529 | int r_ptr = AllocTemp(); |
| 530 | OpRegRegReg(kOpAdd, r_ptr, rl_object.low_reg, rl_offset.low_reg); |
| 531 | |
| 532 | // Free now unneeded rl_object and rl_offset to give more temps. |
| 533 | ClobberSReg(rl_object.s_reg_low); |
| 534 | FreeTemp(rl_object.low_reg); |
| 535 | ClobberSReg(rl_offset.s_reg_low); |
| 536 | FreeTemp(rl_offset.low_reg); |
| 537 | |
| 538 | int r_old_value = AllocTemp(); |
| 539 | NewLIR3(kThumb2Ldrex, r_old_value, r_ptr, 0); // r_old_value := [r_ptr] |
| 540 | |
| 541 | RegLocation rl_expected = LoadValue(rl_src_expected, kCoreReg); |
| 542 | |
| 543 | // if (r_old_value == rExpected) { |
| 544 | // [r_ptr] <- r_new_value && r_result := success ? 0 : 1 |
| 545 | // r_result ^= 1 |
| 546 | // } else { |
| 547 | // r_result := 0 |
| 548 | // } |
| 549 | OpRegReg(kOpCmp, r_old_value, rl_expected.low_reg); |
| 550 | FreeTemp(r_old_value); // Now unneeded. |
| 551 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 552 | OpIT(kCondEq, "TE"); |
| 553 | NewLIR4(kThumb2Strex, rl_result.low_reg, rl_new_value.low_reg, r_ptr, 0); |
| 554 | FreeTemp(r_ptr); // Now unneeded. |
| 555 | OpRegImm(kOpXor, rl_result.low_reg, 1); |
| 556 | OpRegReg(kOpXor, rl_result.low_reg, rl_result.low_reg); |
| 557 | |
| 558 | StoreValue(rl_dest, rl_result); |
| 559 | |
| 560 | return true; |
| 561 | } |
| 562 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 563 | LIR* ArmMir2Lir::OpPcRelLoad(int reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 564 | return RawLIR(current_dalvik_offset_, kThumb2LdrPcRel12, reg, 0, 0, 0, 0, target); |
| 565 | } |
| 566 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 567 | LIR* ArmMir2Lir::OpVldm(int rBase, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 568 | return NewLIR3(kThumb2Vldms, rBase, fr0, count); |
| 569 | } |
| 570 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 571 | LIR* ArmMir2Lir::OpVstm(int rBase, int count) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 572 | return NewLIR3(kThumb2Vstms, rBase, fr0, count); |
| 573 | } |
| 574 | |
| 575 | void ArmMir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src, |
| 576 | RegLocation rl_result, int lit, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 577 | int first_bit, int second_bit) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 578 | OpRegRegRegShift(kOpAdd, rl_result.low_reg, rl_src.low_reg, rl_src.low_reg, |
| 579 | EncodeShift(kArmLsl, second_bit - first_bit)); |
| 580 | if (first_bit != 0) { |
| 581 | OpRegRegImm(kOpLsl, rl_result.low_reg, rl_result.low_reg, first_bit); |
| 582 | } |
| 583 | } |
| 584 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 585 | void ArmMir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 586 | int t_reg = AllocTemp(); |
| 587 | NewLIR4(kThumb2OrrRRRs, t_reg, reg_lo, reg_hi, 0); |
| 588 | FreeTemp(t_reg); |
| 589 | GenCheck(kCondEq, kThrowDivZero); |
| 590 | } |
| 591 | |
| 592 | // Test suspend flag, return target of taken suspend branch |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 593 | LIR* ArmMir2Lir::OpTestSuspend(LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 594 | NewLIR2(kThumbSubRI8, rARM_SUSPEND, 1); |
| 595 | return OpCondBranch((target == NULL) ? kCondEq : kCondNe, target); |
| 596 | } |
| 597 | |
| 598 | // Decrement register and branch on condition |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 599 | LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 600 | // Combine sub & test using sub setflags encoding here |
| 601 | NewLIR3(kThumb2SubsRRI12, reg, reg, 1); |
| 602 | return OpCondBranch(c_code, target); |
| 603 | } |
| 604 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 605 | void ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 606 | #if ANDROID_SMP != 0 |
| 607 | int dmb_flavor; |
| 608 | // TODO: revisit Arm barrier kinds |
| 609 | switch (barrier_kind) { |
| 610 | case kLoadStore: dmb_flavor = kSY; break; |
| 611 | case kLoadLoad: dmb_flavor = kSY; break; |
| 612 | case kStoreStore: dmb_flavor = kST; break; |
| 613 | case kStoreLoad: dmb_flavor = kSY; break; |
| 614 | default: |
| 615 | LOG(FATAL) << "Unexpected MemBarrierKind: " << barrier_kind; |
| 616 | dmb_flavor = kSY; // quiet gcc. |
| 617 | break; |
| 618 | } |
| 619 | LIR* dmb = NewLIR1(kThumb2Dmb, dmb_flavor); |
| 620 | dmb->def_mask = ENCODE_ALL; |
| 621 | #endif |
| 622 | } |
| 623 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 624 | void ArmMir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 625 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 626 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 627 | int z_reg = AllocTemp(); |
| 628 | LoadConstantNoClobber(z_reg, 0); |
| 629 | // Check for destructive overlap |
| 630 | if (rl_result.low_reg == rl_src.high_reg) { |
| 631 | int t_reg = AllocTemp(); |
| 632 | OpRegRegReg(kOpSub, rl_result.low_reg, z_reg, rl_src.low_reg); |
| 633 | OpRegRegReg(kOpSbc, rl_result.high_reg, z_reg, t_reg); |
| 634 | FreeTemp(t_reg); |
| 635 | } else { |
| 636 | OpRegRegReg(kOpSub, rl_result.low_reg, z_reg, rl_src.low_reg); |
| 637 | OpRegRegReg(kOpSbc, rl_result.high_reg, z_reg, rl_src.high_reg); |
| 638 | } |
| 639 | FreeTemp(z_reg); |
| 640 | StoreValueWide(rl_dest, rl_result); |
| 641 | } |
| 642 | |
| 643 | |
| 644 | /* |
| 645 | * Check to see if a result pair has a misaligned overlap with an operand pair. This |
| 646 | * is not usual for dx to generate, but it is legal (for now). In a future rev of |
| 647 | * dex, we'll want to make this case illegal. |
| 648 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 649 | bool ArmMir2Lir::BadOverlap(RegLocation rl_src, RegLocation rl_dest) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 650 | DCHECK(rl_src.wide); |
| 651 | DCHECK(rl_dest.wide); |
| 652 | return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) == 1); |
| 653 | } |
| 654 | |
| 655 | void ArmMir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 656 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 657 | /* |
| 658 | * To pull off inline multiply, we have a worst-case requirement of 8 temporary |
| 659 | * registers. Normally for Arm, we get 5. We can get to 6 by including |
| 660 | * lr in the temp set. The only problematic case is all operands and result are |
| 661 | * distinct, and none have been promoted. In that case, we can succeed by aggressively |
| 662 | * freeing operand temp registers after they are no longer needed. All other cases |
| 663 | * can proceed normally. We'll just punt on the case of the result having a misaligned |
| 664 | * overlap with either operand and send that case to a runtime handler. |
| 665 | */ |
| 666 | RegLocation rl_result; |
| 667 | if (BadOverlap(rl_src1, rl_dest) || (BadOverlap(rl_src2, rl_dest))) { |
| 668 | int func_offset = ENTRYPOINT_OFFSET(pLmul); |
| 669 | FlushAllRegs(); |
| 670 | CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); |
| 671 | rl_result = GetReturnWide(false); |
| 672 | StoreValueWide(rl_dest, rl_result); |
| 673 | return; |
| 674 | } |
| 675 | // Temporarily add LR to the temp pool, and assign it to tmp1 |
| 676 | MarkTemp(rARM_LR); |
| 677 | FreeTemp(rARM_LR); |
| 678 | int tmp1 = rARM_LR; |
| 679 | LockTemp(rARM_LR); |
| 680 | |
| 681 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 682 | rl_src2 = LoadValueWide(rl_src2, kCoreReg); |
| 683 | |
| 684 | bool special_case = true; |
| 685 | // If operands are the same, or any pair has been promoted we're not the special case. |
| 686 | if ((rl_src1.s_reg_low == rl_src2.s_reg_low) || |
| 687 | (!IsTemp(rl_src1.low_reg) && !IsTemp(rl_src1.high_reg)) || |
| 688 | (!IsTemp(rl_src2.low_reg) && !IsTemp(rl_src2.high_reg))) { |
| 689 | special_case = false; |
| 690 | } |
| 691 | // Tuning: if rl_dest has been promoted and is *not* either operand, could use directly. |
| 692 | int res_lo = AllocTemp(); |
| 693 | int res_hi; |
| 694 | if (rl_src1.low_reg == rl_src2.low_reg) { |
| 695 | res_hi = AllocTemp(); |
| 696 | NewLIR3(kThumb2MulRRR, tmp1, rl_src1.low_reg, rl_src1.high_reg); |
| 697 | NewLIR4(kThumb2Umull, res_lo, res_hi, rl_src1.low_reg, rl_src1.low_reg); |
| 698 | OpRegRegRegShift(kOpAdd, res_hi, res_hi, tmp1, EncodeShift(kArmLsl, 1)); |
| 699 | } else { |
| 700 | // In the special case, all temps are now allocated |
| 701 | NewLIR3(kThumb2MulRRR, tmp1, rl_src2.low_reg, rl_src1.high_reg); |
| 702 | if (special_case) { |
| 703 | DCHECK_NE(rl_src1.low_reg, rl_src2.low_reg); |
| 704 | DCHECK_NE(rl_src1.high_reg, rl_src2.high_reg); |
| 705 | FreeTemp(rl_src1.high_reg); |
| 706 | } |
| 707 | res_hi = AllocTemp(); |
| 708 | |
| 709 | NewLIR4(kThumb2Umull, res_lo, res_hi, rl_src2.low_reg, rl_src1.low_reg); |
| 710 | NewLIR4(kThumb2Mla, tmp1, rl_src1.low_reg, rl_src2.high_reg, tmp1); |
| 711 | NewLIR4(kThumb2AddRRR, res_hi, tmp1, res_hi, 0); |
| 712 | if (special_case) { |
| 713 | FreeTemp(rl_src1.low_reg); |
| 714 | Clobber(rl_src1.low_reg); |
| 715 | Clobber(rl_src1.high_reg); |
| 716 | } |
| 717 | } |
| 718 | FreeTemp(tmp1); |
| 719 | rl_result = GetReturnWide(false); // Just using as a template. |
| 720 | rl_result.low_reg = res_lo; |
| 721 | rl_result.high_reg = res_hi; |
| 722 | StoreValueWide(rl_dest, rl_result); |
| 723 | // Now, restore lr to its non-temp status. |
| 724 | Clobber(rARM_LR); |
| 725 | UnmarkTemp(rARM_LR); |
| 726 | } |
| 727 | |
| 728 | void ArmMir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 729 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 730 | LOG(FATAL) << "Unexpected use of GenAddLong for Arm"; |
| 731 | } |
| 732 | |
| 733 | void ArmMir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 734 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 735 | LOG(FATAL) << "Unexpected use of GenSubLong for Arm"; |
| 736 | } |
| 737 | |
| 738 | void ArmMir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 739 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 740 | LOG(FATAL) << "Unexpected use of GenAndLong for Arm"; |
| 741 | } |
| 742 | |
| 743 | void ArmMir2Lir::GenOrLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 744 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 745 | LOG(FATAL) << "Unexpected use of GenOrLong for Arm"; |
| 746 | } |
| 747 | |
| 748 | void ArmMir2Lir::GenXorLong(RegLocation rl_dest, RegLocation rl_src1, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 749 | RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 750 | LOG(FATAL) << "Unexpected use of genXoLong for Arm"; |
| 751 | } |
| 752 | |
| 753 | /* |
| 754 | * Generate array load |
| 755 | */ |
| 756 | void ArmMir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 757 | RegLocation rl_index, RegLocation rl_dest, int scale) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 758 | RegisterClass reg_class = oat_reg_class_by_size(size); |
| 759 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 760 | int data_offset; |
| 761 | RegLocation rl_result; |
| 762 | bool constant_index = rl_index.is_const; |
| 763 | rl_array = LoadValue(rl_array, kCoreReg); |
| 764 | if (!constant_index) { |
| 765 | rl_index = LoadValue(rl_index, kCoreReg); |
| 766 | } |
| 767 | |
| 768 | if (rl_dest.wide) { |
| 769 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 770 | } else { |
| 771 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 772 | } |
| 773 | |
| 774 | // If index is constant, just fold it into the data offset |
| 775 | if (constant_index) { |
| 776 | data_offset += mir_graph_->ConstantValue(rl_index) << scale; |
| 777 | } |
| 778 | |
| 779 | /* null object? */ |
| 780 | GenNullCheck(rl_array.s_reg_low, rl_array.low_reg, opt_flags); |
| 781 | |
| 782 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
| 783 | int reg_len = INVALID_REG; |
| 784 | if (needs_range_check) { |
| 785 | reg_len = AllocTemp(); |
| 786 | /* Get len */ |
| 787 | LoadWordDisp(rl_array.low_reg, len_offset, reg_len); |
| 788 | } |
| 789 | if (rl_dest.wide || rl_dest.fp || constant_index) { |
| 790 | int reg_ptr; |
| 791 | if (constant_index) { |
| 792 | reg_ptr = rl_array.low_reg; // NOTE: must not alter reg_ptr in constant case. |
| 793 | } else { |
| 794 | // No special indexed operation, lea + load w/ displacement |
| 795 | reg_ptr = AllocTemp(); |
| 796 | OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.low_reg, rl_index.low_reg, |
| 797 | EncodeShift(kArmLsl, scale)); |
| 798 | FreeTemp(rl_index.low_reg); |
| 799 | } |
| 800 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 801 | |
| 802 | if (needs_range_check) { |
| 803 | if (constant_index) { |
| 804 | GenImmedCheck(kCondLs, reg_len, mir_graph_->ConstantValue(rl_index), kThrowConstantArrayBounds); |
| 805 | } else { |
| 806 | GenRegRegCheck(kCondLs, reg_len, rl_index.low_reg, kThrowArrayBounds); |
| 807 | } |
| 808 | FreeTemp(reg_len); |
| 809 | } |
| 810 | if (rl_dest.wide) { |
| 811 | LoadBaseDispWide(reg_ptr, data_offset, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); |
| 812 | if (!constant_index) { |
| 813 | FreeTemp(reg_ptr); |
| 814 | } |
| 815 | StoreValueWide(rl_dest, rl_result); |
| 816 | } else { |
| 817 | LoadBaseDisp(reg_ptr, data_offset, rl_result.low_reg, size, INVALID_SREG); |
| 818 | if (!constant_index) { |
| 819 | FreeTemp(reg_ptr); |
| 820 | } |
| 821 | StoreValue(rl_dest, rl_result); |
| 822 | } |
| 823 | } else { |
| 824 | // Offset base, then use indexed load |
| 825 | int reg_ptr = AllocTemp(); |
| 826 | OpRegRegImm(kOpAdd, reg_ptr, rl_array.low_reg, data_offset); |
| 827 | FreeTemp(rl_array.low_reg); |
| 828 | rl_result = EvalLoc(rl_dest, reg_class, true); |
| 829 | |
| 830 | if (needs_range_check) { |
| 831 | // TODO: change kCondCS to a more meaningful name, is the sense of |
| 832 | // carry-set/clear flipped? |
| 833 | GenRegRegCheck(kCondCs, rl_index.low_reg, reg_len, kThrowArrayBounds); |
| 834 | FreeTemp(reg_len); |
| 835 | } |
| 836 | LoadBaseIndexed(reg_ptr, rl_index.low_reg, rl_result.low_reg, scale, size); |
| 837 | FreeTemp(reg_ptr); |
| 838 | StoreValue(rl_dest, rl_result); |
| 839 | } |
| 840 | } |
| 841 | |
| 842 | /* |
| 843 | * Generate array store |
| 844 | * |
| 845 | */ |
| 846 | void ArmMir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 847 | RegLocation rl_index, RegLocation rl_src, int scale) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 848 | RegisterClass reg_class = oat_reg_class_by_size(size); |
| 849 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 850 | int data_offset; |
| 851 | bool constant_index = rl_index.is_const; |
| 852 | |
| 853 | if (rl_src.wide) { |
| 854 | data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Int32Value(); |
| 855 | } else { |
| 856 | data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Int32Value(); |
| 857 | } |
| 858 | |
| 859 | // If index is constant, just fold it into the data offset. |
| 860 | if (constant_index) { |
| 861 | data_offset += mir_graph_->ConstantValue(rl_index) << scale; |
| 862 | } |
| 863 | |
| 864 | rl_array = LoadValue(rl_array, kCoreReg); |
| 865 | if (!constant_index) { |
| 866 | rl_index = LoadValue(rl_index, kCoreReg); |
| 867 | } |
| 868 | |
| 869 | int reg_ptr; |
| 870 | if (constant_index) { |
| 871 | reg_ptr = rl_array.low_reg; |
| 872 | } else if (IsTemp(rl_array.low_reg)) { |
| 873 | Clobber(rl_array.low_reg); |
| 874 | reg_ptr = rl_array.low_reg; |
| 875 | } else { |
| 876 | reg_ptr = AllocTemp(); |
| 877 | } |
| 878 | |
| 879 | /* null object? */ |
| 880 | GenNullCheck(rl_array.s_reg_low, rl_array.low_reg, opt_flags); |
| 881 | |
| 882 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
| 883 | int reg_len = INVALID_REG; |
| 884 | if (needs_range_check) { |
| 885 | reg_len = AllocTemp(); |
| 886 | //NOTE: max live temps(4) here. |
| 887 | /* Get len */ |
| 888 | LoadWordDisp(rl_array.low_reg, len_offset, reg_len); |
| 889 | } |
| 890 | /* at this point, reg_ptr points to array, 2 live temps */ |
| 891 | if (rl_src.wide || rl_src.fp || constant_index) { |
| 892 | if (rl_src.wide) { |
| 893 | rl_src = LoadValueWide(rl_src, reg_class); |
| 894 | } else { |
| 895 | rl_src = LoadValue(rl_src, reg_class); |
| 896 | } |
| 897 | if (!constant_index) { |
| 898 | OpRegRegRegShift(kOpAdd, reg_ptr, rl_array.low_reg, rl_index.low_reg, |
| 899 | EncodeShift(kArmLsl, scale)); |
| 900 | } |
| 901 | if (needs_range_check) { |
| 902 | if (constant_index) { |
| 903 | GenImmedCheck(kCondLs, reg_len, mir_graph_->ConstantValue(rl_index), kThrowConstantArrayBounds); |
| 904 | } else { |
| 905 | GenRegRegCheck(kCondLs, reg_len, rl_index.low_reg, kThrowArrayBounds); |
| 906 | } |
| 907 | FreeTemp(reg_len); |
| 908 | } |
| 909 | |
| 910 | if (rl_src.wide) { |
| 911 | StoreBaseDispWide(reg_ptr, data_offset, rl_src.low_reg, rl_src.high_reg); |
| 912 | } else { |
| 913 | StoreBaseDisp(reg_ptr, data_offset, rl_src.low_reg, size); |
| 914 | } |
| 915 | } else { |
| 916 | /* reg_ptr -> array data */ |
| 917 | OpRegRegImm(kOpAdd, reg_ptr, rl_array.low_reg, data_offset); |
| 918 | rl_src = LoadValue(rl_src, reg_class); |
| 919 | if (needs_range_check) { |
| 920 | GenRegRegCheck(kCondCs, rl_index.low_reg, reg_len, kThrowArrayBounds); |
| 921 | FreeTemp(reg_len); |
| 922 | } |
| 923 | StoreBaseIndexed(reg_ptr, rl_index.low_reg, rl_src.low_reg, |
| 924 | scale, size); |
| 925 | } |
| 926 | if (!constant_index) { |
| 927 | FreeTemp(reg_ptr); |
| 928 | } |
| 929 | } |
| 930 | |
| 931 | /* |
| 932 | * Generate array store |
| 933 | * |
| 934 | */ |
| 935 | void ArmMir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 936 | RegLocation rl_index, RegLocation rl_src, int scale) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 937 | int len_offset = mirror::Array::LengthOffset().Int32Value(); |
| 938 | int data_offset = mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value(); |
| 939 | |
| 940 | FlushAllRegs(); // Use explicit registers |
| 941 | LockCallTemps(); |
| 942 | |
| 943 | int r_value = TargetReg(kArg0); // Register holding value |
| 944 | int r_array_class = TargetReg(kArg1); // Register holding array's Class |
| 945 | int r_array = TargetReg(kArg2); // Register holding array |
| 946 | int r_index = TargetReg(kArg3); // Register holding index into array |
| 947 | |
| 948 | LoadValueDirectFixed(rl_array, r_array); // Grab array |
| 949 | LoadValueDirectFixed(rl_src, r_value); // Grab value |
| 950 | LoadValueDirectFixed(rl_index, r_index); // Grab index |
| 951 | |
| 952 | GenNullCheck(rl_array.s_reg_low, r_array, opt_flags); // NPE? |
| 953 | |
| 954 | // Store of null? |
| 955 | LIR* null_value_check = OpCmpImmBranch(kCondEq, r_value, 0, NULL); |
| 956 | |
| 957 | // Get the array's class. |
| 958 | LoadWordDisp(r_array, mirror::Object::ClassOffset().Int32Value(), r_array_class); |
| 959 | CallRuntimeHelperRegReg(ENTRYPOINT_OFFSET(pCanPutArrayElementFromCode), r_value, |
| 960 | r_array_class, true); |
| 961 | // Redo LoadValues in case they didn't survive the call. |
| 962 | LoadValueDirectFixed(rl_array, r_array); // Reload array |
| 963 | LoadValueDirectFixed(rl_index, r_index); // Reload index |
| 964 | LoadValueDirectFixed(rl_src, r_value); // Reload value |
| 965 | r_array_class = INVALID_REG; |
| 966 | |
| 967 | // Branch here if value to be stored == null |
| 968 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 969 | null_value_check->target = target; |
| 970 | |
| 971 | bool needs_range_check = (!(opt_flags & MIR_IGNORE_RANGE_CHECK)); |
| 972 | int reg_len = INVALID_REG; |
| 973 | if (needs_range_check) { |
| 974 | reg_len = TargetReg(kArg1); |
| 975 | LoadWordDisp(r_array, len_offset, reg_len); // Get len |
| 976 | } |
| 977 | /* r_ptr -> array data */ |
| 978 | int r_ptr = AllocTemp(); |
| 979 | OpRegRegImm(kOpAdd, r_ptr, r_array, data_offset); |
| 980 | if (needs_range_check) { |
| 981 | GenRegRegCheck(kCondCs, r_index, reg_len, kThrowArrayBounds); |
| 982 | } |
| 983 | StoreBaseIndexed(r_ptr, r_index, r_value, scale, kWord); |
| 984 | FreeTemp(r_ptr); |
| 985 | FreeTemp(r_index); |
| 986 | if (!mir_graph_->IsConstantNullRef(rl_src)) { |
| 987 | MarkGCCard(r_value, r_array); |
| 988 | } |
| 989 | } |
| 990 | |
| 991 | void ArmMir2Lir::GenShiftImmOpLong(Instruction::Code opcode, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 992 | RegLocation rl_dest, RegLocation rl_src, RegLocation rl_shift) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 993 | rl_src = LoadValueWide(rl_src, kCoreReg); |
| 994 | // Per spec, we only care about low 6 bits of shift amount. |
| 995 | int shift_amount = mir_graph_->ConstantValue(rl_shift) & 0x3f; |
| 996 | if (shift_amount == 0) { |
| 997 | StoreValueWide(rl_dest, rl_src); |
| 998 | return; |
| 999 | } |
| 1000 | if (BadOverlap(rl_src, rl_dest)) { |
| 1001 | GenShiftOpLong(opcode, rl_dest, rl_src, rl_shift); |
| 1002 | return; |
| 1003 | } |
| 1004 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame^] | 1005 | switch (opcode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1006 | case Instruction::SHL_LONG: |
| 1007 | case Instruction::SHL_LONG_2ADDR: |
| 1008 | if (shift_amount == 1) { |
| 1009 | OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, rl_src.low_reg); |
| 1010 | OpRegRegReg(kOpAdc, rl_result.high_reg, rl_src.high_reg, rl_src.high_reg); |
| 1011 | } else if (shift_amount == 32) { |
| 1012 | OpRegCopy(rl_result.high_reg, rl_src.low_reg); |
| 1013 | LoadConstant(rl_result.low_reg, 0); |
| 1014 | } else if (shift_amount > 31) { |
| 1015 | OpRegRegImm(kOpLsl, rl_result.high_reg, rl_src.low_reg, shift_amount - 32); |
| 1016 | LoadConstant(rl_result.low_reg, 0); |
| 1017 | } else { |
| 1018 | OpRegRegImm(kOpLsl, rl_result.high_reg, rl_src.high_reg, shift_amount); |
| 1019 | OpRegRegRegShift(kOpOr, rl_result.high_reg, rl_result.high_reg, rl_src.low_reg, |
| 1020 | EncodeShift(kArmLsr, 32 - shift_amount)); |
| 1021 | OpRegRegImm(kOpLsl, rl_result.low_reg, rl_src.low_reg, shift_amount); |
| 1022 | } |
| 1023 | break; |
| 1024 | case Instruction::SHR_LONG: |
| 1025 | case Instruction::SHR_LONG_2ADDR: |
| 1026 | if (shift_amount == 32) { |
| 1027 | OpRegCopy(rl_result.low_reg, rl_src.high_reg); |
| 1028 | OpRegRegImm(kOpAsr, rl_result.high_reg, rl_src.high_reg, 31); |
| 1029 | } else if (shift_amount > 31) { |
| 1030 | OpRegRegImm(kOpAsr, rl_result.low_reg, rl_src.high_reg, shift_amount - 32); |
| 1031 | OpRegRegImm(kOpAsr, rl_result.high_reg, rl_src.high_reg, 31); |
| 1032 | } else { |
| 1033 | int t_reg = AllocTemp(); |
| 1034 | OpRegRegImm(kOpLsr, t_reg, rl_src.low_reg, shift_amount); |
| 1035 | OpRegRegRegShift(kOpOr, rl_result.low_reg, t_reg, rl_src.high_reg, |
| 1036 | EncodeShift(kArmLsl, 32 - shift_amount)); |
| 1037 | FreeTemp(t_reg); |
| 1038 | OpRegRegImm(kOpAsr, rl_result.high_reg, rl_src.high_reg, shift_amount); |
| 1039 | } |
| 1040 | break; |
| 1041 | case Instruction::USHR_LONG: |
| 1042 | case Instruction::USHR_LONG_2ADDR: |
| 1043 | if (shift_amount == 32) { |
| 1044 | OpRegCopy(rl_result.low_reg, rl_src.high_reg); |
| 1045 | LoadConstant(rl_result.high_reg, 0); |
| 1046 | } else if (shift_amount > 31) { |
| 1047 | OpRegRegImm(kOpLsr, rl_result.low_reg, rl_src.high_reg, shift_amount - 32); |
| 1048 | LoadConstant(rl_result.high_reg, 0); |
| 1049 | } else { |
| 1050 | int t_reg = AllocTemp(); |
| 1051 | OpRegRegImm(kOpLsr, t_reg, rl_src.low_reg, shift_amount); |
| 1052 | OpRegRegRegShift(kOpOr, rl_result.low_reg, t_reg, rl_src.high_reg, |
| 1053 | EncodeShift(kArmLsl, 32 - shift_amount)); |
| 1054 | FreeTemp(t_reg); |
| 1055 | OpRegRegImm(kOpLsr, rl_result.high_reg, rl_src.high_reg, shift_amount); |
| 1056 | } |
| 1057 | break; |
| 1058 | default: |
| 1059 | LOG(FATAL) << "Unexpected case"; |
| 1060 | } |
| 1061 | StoreValueWide(rl_dest, rl_result); |
| 1062 | } |
| 1063 | |
| 1064 | void ArmMir2Lir::GenArithImmOpLong(Instruction::Code opcode, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 1065 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1066 | if ((opcode == Instruction::SUB_LONG_2ADDR) || (opcode == Instruction::SUB_LONG)) { |
| 1067 | if (!rl_src2.is_const) { |
| 1068 | // Don't bother with special handling for subtract from immediate. |
| 1069 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1070 | return; |
| 1071 | } |
| 1072 | } else { |
| 1073 | // Normalize |
| 1074 | if (!rl_src2.is_const) { |
| 1075 | DCHECK(rl_src1.is_const); |
| 1076 | RegLocation rl_temp = rl_src1; |
| 1077 | rl_src1 = rl_src2; |
| 1078 | rl_src2 = rl_temp; |
| 1079 | } |
| 1080 | } |
| 1081 | if (BadOverlap(rl_src1, rl_dest)) { |
| 1082 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1083 | return; |
| 1084 | } |
| 1085 | DCHECK(rl_src2.is_const); |
| 1086 | int64_t val = mir_graph_->ConstantValueWide(rl_src2); |
| 1087 | uint32_t val_lo = Low32Bits(val); |
| 1088 | uint32_t val_hi = High32Bits(val); |
| 1089 | int32_t mod_imm_lo = ModifiedImmediate(val_lo); |
| 1090 | int32_t mod_imm_hi = ModifiedImmediate(val_hi); |
| 1091 | |
| 1092 | // Only a subset of add/sub immediate instructions set carry - so bail if we don't fit |
Brian Carlstrom | df62950 | 2013-07-17 22:39:56 -0700 | [diff] [blame^] | 1093 | switch (opcode) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1094 | case Instruction::ADD_LONG: |
| 1095 | case Instruction::ADD_LONG_2ADDR: |
| 1096 | case Instruction::SUB_LONG: |
| 1097 | case Instruction::SUB_LONG_2ADDR: |
| 1098 | if ((mod_imm_lo < 0) || (mod_imm_hi < 0)) { |
| 1099 | GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2); |
| 1100 | return; |
| 1101 | } |
| 1102 | break; |
| 1103 | default: |
| 1104 | break; |
| 1105 | } |
| 1106 | rl_src1 = LoadValueWide(rl_src1, kCoreReg); |
| 1107 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 1108 | // NOTE: once we've done the EvalLoc on dest, we can no longer bail. |
| 1109 | switch (opcode) { |
| 1110 | case Instruction::ADD_LONG: |
| 1111 | case Instruction::ADD_LONG_2ADDR: |
| 1112 | NewLIR3(kThumb2AddRRI8, rl_result.low_reg, rl_src1.low_reg, mod_imm_lo); |
| 1113 | NewLIR3(kThumb2AdcRRI8, rl_result.high_reg, rl_src1.high_reg, mod_imm_hi); |
| 1114 | break; |
| 1115 | case Instruction::OR_LONG: |
| 1116 | case Instruction::OR_LONG_2ADDR: |
| 1117 | if ((val_lo != 0) || (rl_result.low_reg != rl_src1.low_reg)) { |
| 1118 | OpRegRegImm(kOpOr, rl_result.low_reg, rl_src1.low_reg, val_lo); |
| 1119 | } |
| 1120 | if ((val_hi != 0) || (rl_result.high_reg != rl_src1.high_reg)) { |
| 1121 | OpRegRegImm(kOpOr, rl_result.high_reg, rl_src1.high_reg, val_hi); |
| 1122 | } |
| 1123 | break; |
| 1124 | case Instruction::XOR_LONG: |
| 1125 | case Instruction::XOR_LONG_2ADDR: |
| 1126 | OpRegRegImm(kOpXor, rl_result.low_reg, rl_src1.low_reg, val_lo); |
| 1127 | OpRegRegImm(kOpXor, rl_result.high_reg, rl_src1.high_reg, val_hi); |
| 1128 | break; |
| 1129 | case Instruction::AND_LONG: |
| 1130 | case Instruction::AND_LONG_2ADDR: |
| 1131 | if ((val_lo != 0xffffffff) || (rl_result.low_reg != rl_src1.low_reg)) { |
| 1132 | OpRegRegImm(kOpAnd, rl_result.low_reg, rl_src1.low_reg, val_lo); |
| 1133 | } |
| 1134 | if ((val_hi != 0xffffffff) || (rl_result.high_reg != rl_src1.high_reg)) { |
| 1135 | OpRegRegImm(kOpAnd, rl_result.high_reg, rl_src1.high_reg, val_hi); |
| 1136 | } |
| 1137 | break; |
| 1138 | case Instruction::SUB_LONG_2ADDR: |
| 1139 | case Instruction::SUB_LONG: |
| 1140 | NewLIR3(kThumb2SubRRI8, rl_result.low_reg, rl_src1.low_reg, mod_imm_lo); |
| 1141 | NewLIR3(kThumb2SbcRRI8, rl_result.high_reg, rl_src1.high_reg, mod_imm_hi); |
| 1142 | break; |
| 1143 | default: |
| 1144 | LOG(FATAL) << "Unexpected opcode " << opcode; |
| 1145 | } |
| 1146 | StoreValueWide(rl_dest, rl_result); |
| 1147 | } |
| 1148 | |
| 1149 | } // namespace art |