Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the X86 ISA */ |
| 18 | |
| 19 | #include "codegen_x86.h" |
| 20 | #include "dex/quick/mir_to_lir-inl.h" |
| 21 | #include "x86_lir.h" |
| 22 | |
| 23 | namespace art { |
| 24 | |
| 25 | void X86Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 26 | SpecialCaseHandler special_case) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 27 | // TODO |
| 28 | } |
| 29 | |
| 30 | /* |
| 31 | * The sparse table in the literal pool is an array of <key,displacement> |
| 32 | * pairs. |
| 33 | */ |
| 34 | void X86Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 35 | RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 36 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 37 | if (cu_->verbose) { |
| 38 | DumpSparseSwitchTable(table); |
| 39 | } |
| 40 | int entries = table[1]; |
| 41 | const int* keys = reinterpret_cast<const int*>(&table[2]); |
| 42 | const int* targets = &keys[entries]; |
| 43 | rl_src = LoadValue(rl_src, kCoreReg); |
| 44 | for (int i = 0; i < entries; i++) { |
| 45 | int key = keys[i]; |
| 46 | BasicBlock* case_block = |
| 47 | mir_graph_->FindBlock(current_dalvik_offset_ + targets[i]); |
| 48 | OpCmpImmBranch(kCondEq, rl_src.low_reg, key, |
| 49 | &block_label_list_[case_block->id]); |
| 50 | } |
| 51 | } |
| 52 | |
| 53 | /* |
| 54 | * Code pattern will look something like: |
| 55 | * |
| 56 | * mov r_val, .. |
| 57 | * call 0 |
| 58 | * pop r_start_of_method |
| 59 | * sub r_start_of_method, .. |
| 60 | * mov r_key_reg, r_val |
| 61 | * sub r_key_reg, low_key |
| 62 | * cmp r_key_reg, size-1 ; bound check |
| 63 | * ja done |
| 64 | * mov r_disp, [r_start_of_method + r_key_reg * 4 + table_offset] |
| 65 | * add r_start_of_method, r_disp |
| 66 | * jmp r_start_of_method |
| 67 | * done: |
| 68 | */ |
| 69 | void X86Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset, |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 70 | RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 71 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 72 | if (cu_->verbose) { |
| 73 | DumpPackedSwitchTable(table); |
| 74 | } |
| 75 | // Add the table to the list - we'll process it later |
| 76 | SwitchTable *tab_rec = |
| 77 | static_cast<SwitchTable *>(arena_->NewMem(sizeof(SwitchTable), true, |
| 78 | ArenaAllocator::kAllocData)); |
| 79 | tab_rec->table = table; |
| 80 | tab_rec->vaddr = current_dalvik_offset_; |
| 81 | int size = table[1]; |
| 82 | tab_rec->targets = static_cast<LIR**>(arena_->NewMem(size * sizeof(LIR*), true, |
| 83 | ArenaAllocator::kAllocLIR)); |
| 84 | switch_tables_.Insert(tab_rec); |
| 85 | |
| 86 | // Get the switch value |
| 87 | rl_src = LoadValue(rl_src, kCoreReg); |
| 88 | int start_of_method_reg = AllocTemp(); |
| 89 | // Materialize a pointer to the switch table |
| 90 | //NewLIR0(kX86Bkpt); |
| 91 | NewLIR1(kX86StartOfMethod, start_of_method_reg); |
| 92 | int low_key = s4FromSwitchData(&table[2]); |
| 93 | int keyReg; |
| 94 | // Remove the bias, if necessary |
| 95 | if (low_key == 0) { |
| 96 | keyReg = rl_src.low_reg; |
| 97 | } else { |
| 98 | keyReg = AllocTemp(); |
| 99 | OpRegRegImm(kOpSub, keyReg, rl_src.low_reg, low_key); |
| 100 | } |
| 101 | // Bounds check - if < 0 or >= size continue following switch |
| 102 | OpRegImm(kOpCmp, keyReg, size-1); |
| 103 | LIR* branch_over = OpCondBranch(kCondHi, NULL); |
| 104 | |
| 105 | // Load the displacement from the switch table |
| 106 | int disp_reg = AllocTemp(); |
| 107 | NewLIR5(kX86PcRelLoadRA, disp_reg, start_of_method_reg, keyReg, 2, |
| 108 | reinterpret_cast<uintptr_t>(tab_rec)); |
| 109 | // Add displacement to start of method |
| 110 | OpRegReg(kOpAdd, start_of_method_reg, disp_reg); |
| 111 | // ..and go! |
| 112 | LIR* switch_branch = NewLIR1(kX86JmpR, start_of_method_reg); |
| 113 | tab_rec->anchor = switch_branch; |
| 114 | |
| 115 | /* branch_over target here */ |
| 116 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 117 | branch_over->target = target; |
| 118 | } |
| 119 | |
| 120 | /* |
| 121 | * Array data table format: |
| 122 | * ushort ident = 0x0300 magic value |
| 123 | * ushort width width of each element in the table |
| 124 | * uint size number of elements in the table |
| 125 | * ubyte data[size*width] table of data values (may contain a single-byte |
| 126 | * padding at the end) |
| 127 | * |
| 128 | * Total size is 4+(width * size + 1)/2 16-bit code units. |
| 129 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 130 | void X86Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 131 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 132 | // Add the table to the list - we'll process it later |
| 133 | FillArrayData *tab_rec = |
| 134 | static_cast<FillArrayData*>(arena_->NewMem(sizeof(FillArrayData), true, |
| 135 | ArenaAllocator::kAllocData)); |
| 136 | tab_rec->table = table; |
| 137 | tab_rec->vaddr = current_dalvik_offset_; |
| 138 | uint16_t width = tab_rec->table[1]; |
| 139 | uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); |
| 140 | tab_rec->size = (size * width) + 8; |
| 141 | |
| 142 | fill_array_data_.Insert(tab_rec); |
| 143 | |
| 144 | // Making a call - use explicit registers |
| 145 | FlushAllRegs(); /* Everything to home location */ |
| 146 | LoadValueDirectFixed(rl_src, rX86_ARG0); |
| 147 | // Materialize a pointer to the fill data image |
| 148 | NewLIR1(kX86StartOfMethod, rX86_ARG2); |
| 149 | NewLIR2(kX86PcRelAdr, rX86_ARG1, reinterpret_cast<uintptr_t>(tab_rec)); |
| 150 | NewLIR2(kX86Add32RR, rX86_ARG1, rX86_ARG2); |
| 151 | CallRuntimeHelperRegReg(ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rX86_ARG0, |
| 152 | rX86_ARG1, true); |
| 153 | } |
| 154 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 155 | void X86Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 156 | FlushAllRegs(); |
| 157 | LoadValueDirectFixed(rl_src, rCX); // Get obj |
| 158 | LockCallTemps(); // Prepare for explicit register usage |
| 159 | GenNullCheck(rl_src.s_reg_low, rCX, opt_flags); |
| 160 | // If lock is unheld, try to grab it quickly with compare and exchange |
| 161 | // TODO: copy and clear hash state? |
| 162 | NewLIR2(kX86Mov32RT, rDX, Thread::ThinLockIdOffset().Int32Value()); |
| 163 | NewLIR2(kX86Sal32RI, rDX, LW_LOCK_OWNER_SHIFT); |
| 164 | NewLIR2(kX86Xor32RR, rAX, rAX); |
| 165 | NewLIR3(kX86LockCmpxchgMR, rCX, mirror::Object::MonitorOffset().Int32Value(), rDX); |
| 166 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); |
| 167 | // If lock is held, go the expensive route - artLockObjectFromCode(self, obj); |
| 168 | CallRuntimeHelperReg(ENTRYPOINT_OFFSET(pLockObjectFromCode), rCX, true); |
| 169 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 170 | } |
| 171 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 172 | void X86Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 173 | FlushAllRegs(); |
| 174 | LoadValueDirectFixed(rl_src, rAX); // Get obj |
| 175 | LockCallTemps(); // Prepare for explicit register usage |
| 176 | GenNullCheck(rl_src.s_reg_low, rAX, opt_flags); |
| 177 | // If lock is held by the current thread, clear it to quickly release it |
| 178 | // TODO: clear hash state? |
| 179 | NewLIR2(kX86Mov32RT, rDX, Thread::ThinLockIdOffset().Int32Value()); |
| 180 | NewLIR2(kX86Sal32RI, rDX, LW_LOCK_OWNER_SHIFT); |
| 181 | NewLIR3(kX86Mov32RM, rCX, rAX, mirror::Object::MonitorOffset().Int32Value()); |
| 182 | OpRegReg(kOpSub, rCX, rDX); |
| 183 | LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); |
| 184 | NewLIR3(kX86Mov32MR, rAX, mirror::Object::MonitorOffset().Int32Value(), rCX); |
| 185 | LIR* branch2 = NewLIR1(kX86Jmp8, 0); |
| 186 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 187 | // Otherwise, go the expensive route - UnlockObjectFromCode(obj); |
| 188 | CallRuntimeHelperReg(ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rAX, true); |
| 189 | branch2->target = NewLIR0(kPseudoTargetLabel); |
| 190 | } |
| 191 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 192 | void X86Mir2Lir::GenMoveException(RegLocation rl_dest) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 193 | int ex_offset = Thread::ExceptionOffset().Int32Value(); |
| 194 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 195 | NewLIR2(kX86Mov32RT, rl_result.low_reg, ex_offset); |
| 196 | NewLIR2(kX86Mov32TI, ex_offset, 0); |
| 197 | StoreValue(rl_dest, rl_result); |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * Mark garbage collection card. Skip if the value we're storing is null. |
| 202 | */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 203 | void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 204 | int reg_card_base = AllocTemp(); |
| 205 | int reg_card_no = AllocTemp(); |
| 206 | LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); |
| 207 | NewLIR2(kX86Mov32RT, reg_card_base, Thread::CardTableOffset().Int32Value()); |
| 208 | OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); |
| 209 | StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, |
| 210 | kUnsignedByte); |
| 211 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 212 | branch_over->target = target; |
| 213 | FreeTemp(reg_card_base); |
| 214 | FreeTemp(reg_card_no); |
| 215 | } |
| 216 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 217 | void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 218 | /* |
| 219 | * On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live. Let the register |
| 220 | * allocation mechanism know so it doesn't try to use any of them when |
| 221 | * expanding the frame or flushing. This leaves the utility |
| 222 | * code with no spare temps. |
| 223 | */ |
| 224 | LockTemp(rX86_ARG0); |
| 225 | LockTemp(rX86_ARG1); |
| 226 | LockTemp(rX86_ARG2); |
| 227 | |
| 228 | /* Build frame, return address already on stack */ |
| 229 | OpRegImm(kOpSub, rX86_SP, frame_size_ - 4); |
| 230 | |
| 231 | /* |
| 232 | * We can safely skip the stack overflow check if we're |
| 233 | * a leaf *and* our frame size < fudge factor. |
| 234 | */ |
| 235 | bool skip_overflow_check = (mir_graph_->MethodIsLeaf() && |
| 236 | (static_cast<size_t>(frame_size_) < |
| 237 | Thread::kStackOverflowReservedBytes)); |
| 238 | NewLIR0(kPseudoMethodEntry); |
| 239 | /* Spill core callee saves */ |
| 240 | SpillCoreRegs(); |
| 241 | /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */ |
| 242 | DCHECK_EQ(num_fp_spills_, 0); |
| 243 | if (!skip_overflow_check) { |
| 244 | // cmp rX86_SP, fs:[stack_end_]; jcc throw_launchpad |
| 245 | LIR* tgt = RawLIR(0, kPseudoThrowTarget, kThrowStackOverflow, 0, 0, 0, 0); |
| 246 | OpRegThreadMem(kOpCmp, rX86_SP, Thread::StackEndOffset().Int32Value()); |
| 247 | OpCondBranch(kCondUlt, tgt); |
| 248 | // Remember branch target - will process later |
| 249 | throw_launchpads_.Insert(tgt); |
| 250 | } |
| 251 | |
| 252 | FlushIns(ArgLocs, rl_method); |
| 253 | |
| 254 | FreeTemp(rX86_ARG0); |
| 255 | FreeTemp(rX86_ARG1); |
| 256 | FreeTemp(rX86_ARG2); |
| 257 | } |
| 258 | |
| 259 | void X86Mir2Lir::GenExitSequence() { |
| 260 | /* |
| 261 | * In the exit path, rX86_RET0/rX86_RET1 are live - make sure they aren't |
| 262 | * allocated by the register utilities as temps. |
| 263 | */ |
| 264 | LockTemp(rX86_RET0); |
| 265 | LockTemp(rX86_RET1); |
| 266 | |
| 267 | NewLIR0(kPseudoMethodExit); |
| 268 | UnSpillCoreRegs(); |
| 269 | /* Remove frame except for return address */ |
| 270 | OpRegImm(kOpAdd, rX86_SP, frame_size_ - 4); |
| 271 | NewLIR0(kX86Ret); |
| 272 | } |
| 273 | |
| 274 | } // namespace art |