Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "dex/compiler_ir.h" |
| 18 | #include "dex/compiler_internals.h" |
| 19 | #include "dex/quick/mir_to_lir-inl.h" |
| 20 | #include "invoke_type.h" |
| 21 | |
| 22 | namespace art { |
| 23 | |
| 24 | /* This file contains target-independent codegen and support. */ |
| 25 | |
| 26 | /* |
| 27 | * Load an immediate value into a fixed or temp register. Target |
| 28 | * register is clobbered, and marked in_use. |
| 29 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 30 | LIR* Mir2Lir::LoadConstant(RegStorage r_dest, int value) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 31 | if (IsTemp(r_dest)) { |
| 32 | Clobber(r_dest); |
| 33 | MarkInUse(r_dest); |
| 34 | } |
| 35 | return LoadConstantNoClobber(r_dest, value); |
| 36 | } |
| 37 | |
| 38 | /* |
| 39 | * Temporary workaround for Issue 7250540. If we're loading a constant zero into a |
| 40 | * promoted floating point register, also copy a zero into the int/ref identity of |
| 41 | * that sreg. |
| 42 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 43 | void Mir2Lir::Workaround7250540(RegLocation rl_dest, RegStorage zero_reg) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 44 | if (rl_dest.fp) { |
| 45 | int pmap_index = SRegToPMap(rl_dest.s_reg_low); |
| 46 | if (promotion_map_[pmap_index].fp_location == kLocPhysReg) { |
| 47 | // Now, determine if this vreg is ever used as a reference. If not, we're done. |
| 48 | bool used_as_reference = false; |
| 49 | int base_vreg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); |
| 50 | for (int i = 0; !used_as_reference && (i < mir_graph_->GetNumSSARegs()); i++) { |
| 51 | if (mir_graph_->SRegToVReg(mir_graph_->reg_location_[i].s_reg_low) == base_vreg) { |
| 52 | used_as_reference |= mir_graph_->reg_location_[i].ref; |
| 53 | } |
| 54 | } |
| 55 | if (!used_as_reference) { |
| 56 | return; |
| 57 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 58 | RegStorage temp_reg = zero_reg; |
| 59 | if (!temp_reg.Valid()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 60 | temp_reg = AllocTemp(); |
| 61 | LoadConstant(temp_reg, 0); |
| 62 | } |
| 63 | if (promotion_map_[pmap_index].core_location == kLocPhysReg) { |
| 64 | // Promoted - just copy in a zero |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 65 | OpRegCopy(RegStorage::Solo32(promotion_map_[pmap_index].core_reg), temp_reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 66 | } else { |
| 67 | // Lives in the frame, need to store. |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 68 | StoreBaseDisp(TargetReg(kSp), SRegOffset(rl_dest.s_reg_low), temp_reg, k32); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 69 | } |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 70 | if (!zero_reg.Valid()) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 71 | FreeTemp(temp_reg); |
| 72 | } |
| 73 | } |
| 74 | } |
| 75 | } |
| 76 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 77 | /* |
| 78 | * Load a Dalvik register into a physical register. Take care when |
| 79 | * using this routine, as it doesn't perform any bookkeeping regarding |
| 80 | * register liveness. That is the responsibility of the caller. |
| 81 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 82 | void Mir2Lir::LoadValueDirect(RegLocation rl_src, RegStorage r_dest) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 83 | rl_src = UpdateLoc(rl_src); |
| 84 | if (rl_src.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 85 | OpRegCopy(r_dest, rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 86 | } else if (IsInexpensiveConstant(rl_src)) { |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 87 | // On 64-bit targets, will sign extend. Make sure constant reference is always NULL. |
| 88 | DCHECK(!rl_src.ref || (mir_graph_->ConstantValue(rl_src) == 0)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 89 | LoadConstantNoClobber(r_dest, mir_graph_->ConstantValue(rl_src)); |
| 90 | } else { |
| 91 | DCHECK((rl_src.location == kLocDalvikFrame) || |
| 92 | (rl_src.location == kLocCompilerTemp)); |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 93 | if (rl_src.ref) { |
| 94 | LoadRefDisp(TargetReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest); |
| 95 | } else { |
| 96 | Load32Disp(TargetReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest); |
| 97 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 98 | } |
| 99 | } |
| 100 | |
| 101 | /* |
| 102 | * Similar to LoadValueDirect, but clobbers and allocates the target |
| 103 | * register. Should be used when loading to a fixed register (for example, |
| 104 | * loading arguments to an out of line call. |
| 105 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 106 | void Mir2Lir::LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 107 | Clobber(r_dest); |
| 108 | MarkInUse(r_dest); |
| 109 | LoadValueDirect(rl_src, r_dest); |
| 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Load a Dalvik register pair into a physical register[s]. Take care when |
| 114 | * using this routine, as it doesn't perform any bookkeeping regarding |
| 115 | * register liveness. That is the responsibility of the caller. |
| 116 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 117 | void Mir2Lir::LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 118 | rl_src = UpdateLocWide(rl_src); |
| 119 | if (rl_src.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 120 | OpRegCopyWide(r_dest, rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 121 | } else if (IsInexpensiveConstant(rl_src)) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 122 | LoadConstantWide(r_dest, mir_graph_->ConstantValueWide(rl_src)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 123 | } else { |
| 124 | DCHECK((rl_src.location == kLocDalvikFrame) || |
| 125 | (rl_src.location == kLocCompilerTemp)); |
Vladimir Marko | 3bf7c60 | 2014-05-07 14:55:43 +0100 | [diff] [blame] | 126 | LoadBaseDisp(TargetReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 127 | } |
| 128 | } |
| 129 | |
| 130 | /* |
| 131 | * Similar to LoadValueDirect, but clobbers and allocates the target |
| 132 | * registers. Should be used when loading to a fixed registers (for example, |
| 133 | * loading arguments to an out of line call. |
| 134 | */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 135 | void Mir2Lir::LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest) { |
| 136 | Clobber(r_dest); |
| 137 | MarkInUse(r_dest); |
| 138 | LoadValueDirectWide(rl_src, r_dest); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 141 | RegLocation Mir2Lir::LoadValue(RegLocation rl_src, RegisterClass op_kind) { |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 142 | DCHECK(!rl_src.ref || op_kind == kRefReg); |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 143 | rl_src = UpdateLoc(rl_src); |
| 144 | if (rl_src.location == kLocPhysReg) { |
| 145 | if (!RegClassMatches(op_kind, rl_src.reg)) { |
| 146 | // Wrong register class, realloc, copy and transfer ownership. |
| 147 | RegStorage new_reg = AllocTypedTemp(rl_src.fp, op_kind); |
| 148 | OpRegCopy(new_reg, rl_src.reg); |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 149 | // Clobber the old reg. |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 150 | Clobber(rl_src.reg); |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 151 | // ...and mark the new one live. |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 152 | rl_src.reg = new_reg; |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 153 | MarkLive(rl_src); |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 154 | } |
| 155 | return rl_src; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 156 | } |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 157 | |
| 158 | DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); |
| 159 | rl_src.reg = AllocTypedTemp(rl_src.fp, op_kind); |
| 160 | LoadValueDirect(rl_src, rl_src.reg); |
| 161 | rl_src.location = kLocPhysReg; |
| 162 | MarkLive(rl_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 163 | return rl_src; |
| 164 | } |
| 165 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 166 | RegLocation Mir2Lir::LoadValue(RegLocation rl_src) { |
| 167 | return LoadValue(rl_src, LocToRegClass(rl_src)); |
| 168 | } |
| 169 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 170 | void Mir2Lir::StoreValue(RegLocation rl_dest, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 171 | /* |
| 172 | * Sanity checking - should never try to store to the same |
| 173 | * ssa name during the compilation of a single instruction |
| 174 | * without an intervening ClobberSReg(). |
| 175 | */ |
| 176 | if (kIsDebugBuild) { |
| 177 | DCHECK((live_sreg_ == INVALID_SREG) || |
| 178 | (rl_dest.s_reg_low != live_sreg_)); |
| 179 | live_sreg_ = rl_dest.s_reg_low; |
| 180 | } |
| 181 | LIR* def_start; |
| 182 | LIR* def_end; |
| 183 | DCHECK(!rl_dest.wide); |
| 184 | DCHECK(!rl_src.wide); |
| 185 | rl_src = UpdateLoc(rl_src); |
| 186 | rl_dest = UpdateLoc(rl_dest); |
| 187 | if (rl_src.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 188 | if (IsLive(rl_src.reg) || |
| 189 | IsPromoted(rl_src.reg) || |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 190 | (rl_dest.location == kLocPhysReg)) { |
| 191 | // Src is live/promoted or Dest has assigned reg. |
| 192 | rl_dest = EvalLoc(rl_dest, kAnyReg, false); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 193 | OpRegCopy(rl_dest.reg, rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 194 | } else { |
| 195 | // Just re-assign the registers. Dest gets Src's regs |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 196 | rl_dest.reg = rl_src.reg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 197 | Clobber(rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 198 | } |
| 199 | } else { |
| 200 | // Load Src either into promoted Dest or temps allocated for Dest |
| 201 | rl_dest = EvalLoc(rl_dest, kAnyReg, false); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 202 | LoadValueDirect(rl_src, rl_dest.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 203 | } |
| 204 | |
| 205 | // Dest is now live and dirty (until/if we flush it to home location) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 206 | MarkLive(rl_dest); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 207 | MarkDirty(rl_dest); |
| 208 | |
| 209 | |
| 210 | ResetDefLoc(rl_dest); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 211 | if (IsDirty(rl_dest.reg) && LiveOut(rl_dest.s_reg_low)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 212 | def_start = last_lir_insn_; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 213 | Store32Disp(TargetReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 214 | MarkClean(rl_dest); |
| 215 | def_end = last_lir_insn_; |
| 216 | if (!rl_dest.ref) { |
| 217 | // Exclude references from store elimination |
| 218 | MarkDef(rl_dest, def_start, def_end); |
| 219 | } |
| 220 | } |
| 221 | } |
| 222 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 223 | RegLocation Mir2Lir::LoadValueWide(RegLocation rl_src, RegisterClass op_kind) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 224 | DCHECK(rl_src.wide); |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 225 | rl_src = UpdateLocWide(rl_src); |
| 226 | if (rl_src.location == kLocPhysReg) { |
| 227 | if (!RegClassMatches(op_kind, rl_src.reg)) { |
| 228 | // Wrong register class, realloc, copy and transfer ownership. |
| 229 | RegStorage new_regs = AllocTypedTempWide(rl_src.fp, op_kind); |
| 230 | OpRegCopyWide(new_regs, rl_src.reg); |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 231 | // Clobber the old regs. |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 232 | Clobber(rl_src.reg); |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 233 | // ...and mark the new ones live. |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 234 | rl_src.reg = new_regs; |
buzbee | 082833c | 2014-05-17 23:16:26 -0700 | [diff] [blame] | 235 | MarkLive(rl_src); |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 236 | } |
| 237 | return rl_src; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 238 | } |
Vladimir Marko | 0dc242d | 2014-05-12 16:22:14 +0100 | [diff] [blame] | 239 | |
| 240 | DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); |
| 241 | DCHECK_NE(GetSRegHi(rl_src.s_reg_low), INVALID_SREG); |
| 242 | rl_src.reg = AllocTypedTempWide(rl_src.fp, op_kind); |
| 243 | LoadValueDirectWide(rl_src, rl_src.reg); |
| 244 | rl_src.location = kLocPhysReg; |
| 245 | MarkLive(rl_src); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 246 | return rl_src; |
| 247 | } |
| 248 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 249 | void Mir2Lir::StoreValueWide(RegLocation rl_dest, RegLocation rl_src) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 250 | /* |
| 251 | * Sanity checking - should never try to store to the same |
| 252 | * ssa name during the compilation of a single instruction |
| 253 | * without an intervening ClobberSReg(). |
| 254 | */ |
| 255 | if (kIsDebugBuild) { |
| 256 | DCHECK((live_sreg_ == INVALID_SREG) || |
| 257 | (rl_dest.s_reg_low != live_sreg_)); |
| 258 | live_sreg_ = rl_dest.s_reg_low; |
| 259 | } |
| 260 | LIR* def_start; |
| 261 | LIR* def_end; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 262 | DCHECK(rl_dest.wide); |
| 263 | DCHECK(rl_src.wide); |
Alexei Zavjalov | c17ebe8 | 2014-02-26 10:38:23 +0700 | [diff] [blame] | 264 | rl_src = UpdateLocWide(rl_src); |
| 265 | rl_dest = UpdateLocWide(rl_dest); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 266 | if (rl_src.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 267 | if (IsLive(rl_src.reg) || |
| 268 | IsPromoted(rl_src.reg) || |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 269 | (rl_dest.location == kLocPhysReg)) { |
buzbee | 30adc73 | 2014-05-09 15:10:18 -0700 | [diff] [blame] | 270 | /* |
| 271 | * If src reg[s] are tied to the original Dalvik vreg via liveness or promotion, we |
| 272 | * can't repurpose them. Similarly, if the dest reg[s] are tied to Dalvik vregs via |
| 273 | * promotion, we can't just re-assign. In these cases, we have to copy. |
| 274 | */ |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 275 | rl_dest = EvalLoc(rl_dest, kAnyReg, false); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 276 | OpRegCopyWide(rl_dest.reg, rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 277 | } else { |
| 278 | // Just re-assign the registers. Dest gets Src's regs |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 279 | rl_dest.reg = rl_src.reg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 280 | Clobber(rl_src.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 281 | } |
| 282 | } else { |
| 283 | // Load Src either into promoted Dest or temps allocated for Dest |
| 284 | rl_dest = EvalLoc(rl_dest, kAnyReg, false); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 285 | LoadValueDirectWide(rl_src, rl_dest.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 286 | } |
| 287 | |
| 288 | // Dest is now live and dirty (until/if we flush it to home location) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 289 | MarkLive(rl_dest); |
| 290 | MarkWide(rl_dest.reg); |
| 291 | MarkDirty(rl_dest); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 292 | |
| 293 | ResetDefLocWide(rl_dest); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 294 | if (IsDirty(rl_dest.reg) && (LiveOut(rl_dest.s_reg_low) || |
| 295 | LiveOut(GetSRegHi(rl_dest.s_reg_low)))) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 296 | def_start = last_lir_insn_; |
| 297 | DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1), |
| 298 | mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low))); |
Vladimir Marko | 455759b | 2014-05-06 20:49:36 +0100 | [diff] [blame] | 299 | StoreBaseDisp(TargetReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 300 | MarkClean(rl_dest); |
| 301 | def_end = last_lir_insn_; |
| 302 | MarkDefWide(rl_dest, def_start, def_end); |
| 303 | } |
| 304 | } |
| 305 | |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 306 | void Mir2Lir::StoreFinalValue(RegLocation rl_dest, RegLocation rl_src) { |
| 307 | DCHECK_EQ(rl_src.location, kLocPhysReg); |
| 308 | |
| 309 | if (rl_dest.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 310 | OpRegCopy(rl_dest.reg, rl_src.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 311 | } else { |
| 312 | // Just re-assign the register. Dest gets Src's reg. |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 313 | rl_dest.location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 314 | rl_dest.reg = rl_src.reg; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 315 | Clobber(rl_src.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 316 | } |
| 317 | |
| 318 | // Dest is now live and dirty (until/if we flush it to home location) |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 319 | MarkLive(rl_dest); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 320 | MarkDirty(rl_dest); |
| 321 | |
| 322 | |
| 323 | ResetDefLoc(rl_dest); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 324 | if (IsDirty(rl_dest.reg) && LiveOut(rl_dest.s_reg_low)) { |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 325 | LIR *def_start = last_lir_insn_; |
buzbee | 695d13a | 2014-04-19 13:32:20 -0700 | [diff] [blame] | 326 | Store32Disp(TargetReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg); |
Mark Mendell | feb2b4e | 2014-01-28 12:59:49 -0800 | [diff] [blame] | 327 | MarkClean(rl_dest); |
| 328 | LIR *def_end = last_lir_insn_; |
| 329 | if (!rl_dest.ref) { |
| 330 | // Exclude references from store elimination |
| 331 | MarkDef(rl_dest, def_start, def_end); |
| 332 | } |
| 333 | } |
| 334 | } |
| 335 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 336 | void Mir2Lir::StoreFinalValueWide(RegLocation rl_dest, RegLocation rl_src) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 337 | DCHECK(rl_dest.wide); |
| 338 | DCHECK(rl_src.wide); |
| 339 | DCHECK_EQ(rl_src.location, kLocPhysReg); |
| 340 | |
| 341 | if (rl_dest.location == kLocPhysReg) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 342 | OpRegCopyWide(rl_dest.reg, rl_src.reg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 343 | } else { |
| 344 | // Just re-assign the registers. Dest gets Src's regs. |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 345 | rl_dest.location = kLocPhysReg; |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 346 | rl_dest.reg = rl_src.reg; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 347 | Clobber(rl_src.reg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 348 | } |
| 349 | |
| 350 | // Dest is now live and dirty (until/if we flush it to home location). |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 351 | MarkLive(rl_dest); |
| 352 | MarkWide(rl_dest.reg); |
| 353 | MarkDirty(rl_dest); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 354 | |
| 355 | ResetDefLocWide(rl_dest); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 356 | if (IsDirty(rl_dest.reg) && (LiveOut(rl_dest.s_reg_low) || |
| 357 | LiveOut(GetSRegHi(rl_dest.s_reg_low)))) { |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 358 | LIR *def_start = last_lir_insn_; |
| 359 | DCHECK_EQ((mir_graph_->SRegToVReg(rl_dest.s_reg_low)+1), |
| 360 | mir_graph_->SRegToVReg(GetSRegHi(rl_dest.s_reg_low))); |
Vladimir Marko | 455759b | 2014-05-06 20:49:36 +0100 | [diff] [blame] | 361 | StoreBaseDisp(TargetReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 362 | MarkClean(rl_dest); |
| 363 | LIR *def_end = last_lir_insn_; |
| 364 | MarkDefWide(rl_dest, def_start, def_end); |
| 365 | } |
| 366 | } |
| 367 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 368 | /* Utilities to load the current Method* */ |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 369 | void Mir2Lir::LoadCurrMethodDirect(RegStorage r_tgt) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 370 | LoadValueDirectFixed(mir_graph_->GetMethodLoc(), r_tgt); |
| 371 | } |
| 372 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 373 | RegLocation Mir2Lir::LoadCurrMethod() { |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 374 | return LoadValue(mir_graph_->GetMethodLoc(), kRefReg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 375 | } |
| 376 | |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 377 | RegLocation Mir2Lir::ForceTemp(RegLocation loc) { |
| 378 | DCHECK(!loc.wide); |
| 379 | DCHECK(loc.location == kLocPhysReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 380 | DCHECK(!loc.reg.IsFloat()); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 381 | if (IsTemp(loc.reg)) { |
| 382 | Clobber(loc.reg); |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 383 | } else { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 384 | RegStorage temp_low = AllocTemp(); |
| 385 | OpRegCopy(temp_low, loc.reg); |
| 386 | loc.reg = temp_low; |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 387 | } |
| 388 | |
| 389 | // Ensure that this doesn't represent the original SR any more. |
| 390 | loc.s_reg_low = INVALID_SREG; |
| 391 | return loc; |
| 392 | } |
| 393 | |
| 394 | RegLocation Mir2Lir::ForceTempWide(RegLocation loc) { |
| 395 | DCHECK(loc.wide); |
| 396 | DCHECK(loc.location == kLocPhysReg); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 397 | DCHECK(!loc.reg.IsFloat()); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 398 | |
| 399 | if (!loc.reg.IsPair()) { |
| 400 | if (IsTemp(loc.reg)) { |
| 401 | Clobber(loc.reg); |
| 402 | } else { |
| 403 | RegStorage temp = AllocTempWide(); |
| 404 | OpRegCopy(temp, loc.reg); |
| 405 | loc.reg = temp; |
| 406 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 407 | } else { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame^] | 408 | if (IsTemp(loc.reg.GetLow())) { |
| 409 | Clobber(loc.reg.GetLow()); |
| 410 | } else { |
| 411 | RegStorage temp_low = AllocTemp(); |
| 412 | OpRegCopy(temp_low, loc.reg.GetLow()); |
| 413 | loc.reg.SetLowReg(temp_low.GetReg()); |
| 414 | } |
| 415 | if (IsTemp(loc.reg.GetHigh())) { |
| 416 | Clobber(loc.reg.GetHigh()); |
| 417 | } else { |
| 418 | RegStorage temp_high = AllocTemp(); |
| 419 | OpRegCopy(temp_high, loc.reg.GetHigh()); |
| 420 | loc.reg.SetHighReg(temp_high.GetReg()); |
| 421 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 422 | } |
| 423 | |
| 424 | // Ensure that this doesn't represent the original SR any more. |
| 425 | loc.s_reg_low = INVALID_SREG; |
| 426 | return loc; |
| 427 | } |
| 428 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 429 | } // namespace art |