Elliott Hughes | 2faa5f1 | 2012-01-30 14:42:07 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 16 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_ |
| 18 | #define ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 19 | |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 20 | #include <vector> |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 21 | |
| 22 | #include "base/arena_containers.h" |
Vladimir Marko | 80afd02 | 2015-05-19 18:08:00 +0100 | [diff] [blame] | 23 | #include "base/bit_utils.h" |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 24 | #include "base/enums.h" |
Elliott Hughes | 7616005 | 2012-12-12 16:31:20 -0800 | [diff] [blame] | 25 | #include "base/macros.h" |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 26 | #include "constants_x86.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 27 | #include "globals.h" |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 28 | #include "managed_register_x86.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 29 | #include "offsets.h" |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 30 | #include "utils/array_ref.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 31 | #include "utils/assembler.h" |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 32 | |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 33 | namespace art { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 34 | namespace x86 { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 35 | |
Ian Rogers | cf7f191 | 2014-10-22 22:06:39 -0700 | [diff] [blame] | 36 | class Immediate : public ValueObject { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 37 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 38 | explicit Immediate(int32_t value_in) : value_(value_in) {} |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 39 | |
| 40 | int32_t value() const { return value_; } |
| 41 | |
Andreas Gampe | ab1eb0d | 2015-02-13 19:23:55 -0800 | [diff] [blame] | 42 | bool is_int8() const { return IsInt<8>(value_); } |
| 43 | bool is_uint8() const { return IsUint<8>(value_); } |
| 44 | bool is_int16() const { return IsInt<16>(value_); } |
| 45 | bool is_uint16() const { return IsUint<16>(value_); } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 46 | |
| 47 | private: |
| 48 | const int32_t value_; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | |
Ian Rogers | cf7f191 | 2014-10-22 22:06:39 -0700 | [diff] [blame] | 52 | class Operand : public ValueObject { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 53 | public: |
| 54 | uint8_t mod() const { |
| 55 | return (encoding_at(0) >> 6) & 3; |
| 56 | } |
| 57 | |
| 58 | Register rm() const { |
| 59 | return static_cast<Register>(encoding_at(0) & 7); |
| 60 | } |
| 61 | |
| 62 | ScaleFactor scale() const { |
| 63 | return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3); |
| 64 | } |
| 65 | |
| 66 | Register index() const { |
| 67 | return static_cast<Register>((encoding_at(1) >> 3) & 7); |
| 68 | } |
| 69 | |
| 70 | Register base() const { |
| 71 | return static_cast<Register>(encoding_at(1) & 7); |
| 72 | } |
| 73 | |
| 74 | int8_t disp8() const { |
| 75 | CHECK_GE(length_, 2); |
| 76 | return static_cast<int8_t>(encoding_[length_ - 1]); |
| 77 | } |
| 78 | |
| 79 | int32_t disp32() const { |
| 80 | CHECK_GE(length_, 5); |
| 81 | int32_t value; |
| 82 | memcpy(&value, &encoding_[length_ - 4], sizeof(value)); |
| 83 | return value; |
| 84 | } |
| 85 | |
| 86 | bool IsRegister(Register reg) const { |
| 87 | return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only. |
| 88 | && ((encoding_[0] & 0x07) == reg); // Register codes match. |
| 89 | } |
| 90 | |
| 91 | protected: |
| 92 | // Operand can be sub classed (e.g: Address). |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 93 | Operand() : length_(0), fixup_(nullptr) { } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 94 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 95 | void SetModRM(int mod_in, Register rm_in) { |
| 96 | CHECK_EQ(mod_in & ~3, 0); |
| 97 | encoding_[0] = (mod_in << 6) | rm_in; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 98 | length_ = 1; |
| 99 | } |
| 100 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 101 | void SetSIB(ScaleFactor scale_in, Register index_in, Register base_in) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 102 | CHECK_EQ(length_, 1); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 103 | CHECK_EQ(scale_in & ~3, 0); |
| 104 | encoding_[1] = (scale_in << 6) | (index_in << 3) | base_in; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 105 | length_ = 2; |
| 106 | } |
| 107 | |
| 108 | void SetDisp8(int8_t disp) { |
| 109 | CHECK(length_ == 1 || length_ == 2); |
| 110 | encoding_[length_++] = static_cast<uint8_t>(disp); |
| 111 | } |
| 112 | |
| 113 | void SetDisp32(int32_t disp) { |
| 114 | CHECK(length_ == 1 || length_ == 2); |
| 115 | int disp_size = sizeof(disp); |
| 116 | memmove(&encoding_[length_], &disp, disp_size); |
| 117 | length_ += disp_size; |
| 118 | } |
| 119 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 120 | AssemblerFixup* GetFixup() const { |
| 121 | return fixup_; |
| 122 | } |
| 123 | |
| 124 | void SetFixup(AssemblerFixup* fixup) { |
| 125 | fixup_ = fixup; |
| 126 | } |
| 127 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 128 | private: |
Ian Rogers | 1373595 | 2014-10-08 12:43:28 -0700 | [diff] [blame] | 129 | uint8_t length_; |
| 130 | uint8_t encoding_[6]; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 131 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 132 | // A fixup can be associated with the operand, in order to be applied after the |
| 133 | // code has been generated. This is used for constant area fixups. |
| 134 | AssemblerFixup* fixup_; |
| 135 | |
| 136 | explicit Operand(Register reg) : fixup_(nullptr) { SetModRM(3, reg); } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 137 | |
| 138 | // Get the operand encoding byte at the given index. |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 139 | uint8_t encoding_at(int index_in) const { |
| 140 | CHECK_GE(index_in, 0); |
| 141 | CHECK_LT(index_in, length_); |
| 142 | return encoding_[index_in]; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 143 | } |
| 144 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 145 | friend class X86Assembler; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | |
| 149 | class Address : public Operand { |
| 150 | public: |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 151 | Address(Register base_in, int32_t disp) { |
| 152 | Init(base_in, disp); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 153 | } |
| 154 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 155 | Address(Register base_in, int32_t disp, AssemblerFixup *fixup) { |
| 156 | Init(base_in, disp); |
| 157 | SetFixup(fixup); |
| 158 | } |
| 159 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 160 | Address(Register base_in, Offset disp) { |
| 161 | Init(base_in, disp.Int32Value()); |
Ian Rogers | a04d397 | 2011-08-17 11:33:44 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 164 | Address(Register base_in, FrameOffset disp) { |
| 165 | CHECK_EQ(base_in, ESP); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 166 | Init(ESP, disp.Int32Value()); |
| 167 | } |
| 168 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 169 | Address(Register base_in, MemberOffset disp) { |
| 170 | Init(base_in, disp.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 171 | } |
| 172 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 173 | Address(Register index_in, ScaleFactor scale_in, int32_t disp) { |
| 174 | CHECK_NE(index_in, ESP); // Illegal addressing mode. |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 175 | SetModRM(0, ESP); |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 176 | SetSIB(scale_in, index_in, EBP); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 177 | SetDisp32(disp); |
| 178 | } |
| 179 | |
Andreas Gampe | 277ccbd | 2014-11-03 21:36:10 -0800 | [diff] [blame] | 180 | Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) { |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 181 | Init(base_in, index_in, scale_in, disp); |
| 182 | } |
| 183 | |
| 184 | Address(Register base_in, |
| 185 | Register index_in, |
| 186 | ScaleFactor scale_in, |
| 187 | int32_t disp, AssemblerFixup *fixup) { |
| 188 | Init(base_in, index_in, scale_in, disp); |
| 189 | SetFixup(fixup); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 190 | } |
| 191 | |
Ian Rogers | 1373595 | 2014-10-08 12:43:28 -0700 | [diff] [blame] | 192 | static Address Absolute(uintptr_t addr) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 193 | Address result; |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 194 | result.SetModRM(0, EBP); |
| 195 | result.SetDisp32(addr); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 196 | return result; |
| 197 | } |
| 198 | |
Andreas Gampe | 542451c | 2016-07-26 09:02:02 -0700 | [diff] [blame] | 199 | static Address Absolute(ThreadOffset32 addr) { |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 200 | return Absolute(addr.Int32Value()); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 201 | } |
| 202 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 203 | private: |
| 204 | Address() {} |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 205 | |
| 206 | void Init(Register base_in, int32_t disp) { |
| 207 | if (disp == 0 && base_in != EBP) { |
| 208 | SetModRM(0, base_in); |
| 209 | if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in); |
| 210 | } else if (disp >= -128 && disp <= 127) { |
| 211 | SetModRM(1, base_in); |
| 212 | if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in); |
| 213 | SetDisp8(disp); |
| 214 | } else { |
| 215 | SetModRM(2, base_in); |
| 216 | if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in); |
| 217 | SetDisp32(disp); |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | void Init(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) { |
| 222 | CHECK_NE(index_in, ESP); // Illegal addressing mode. |
| 223 | if (disp == 0 && base_in != EBP) { |
| 224 | SetModRM(0, ESP); |
| 225 | SetSIB(scale_in, index_in, base_in); |
| 226 | } else if (disp >= -128 && disp <= 127) { |
| 227 | SetModRM(1, ESP); |
| 228 | SetSIB(scale_in, index_in, base_in); |
| 229 | SetDisp8(disp); |
| 230 | } else { |
| 231 | SetModRM(2, ESP); |
| 232 | SetSIB(scale_in, index_in, base_in); |
| 233 | SetDisp32(disp); |
| 234 | } |
| 235 | } |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 236 | }; |
| 237 | |
| 238 | |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 239 | // This is equivalent to the Label class, used in a slightly different context. We |
| 240 | // inherit the functionality of the Label class, but prevent unintended |
| 241 | // derived-to-base conversions by making the base class private. |
| 242 | class NearLabel : private Label { |
| 243 | public: |
| 244 | NearLabel() : Label() {} |
| 245 | |
| 246 | // Expose the Label routines that we need. |
| 247 | using Label::Position; |
| 248 | using Label::LinkPosition; |
| 249 | using Label::IsBound; |
| 250 | using Label::IsUnused; |
| 251 | using Label::IsLinked; |
| 252 | |
| 253 | private: |
| 254 | using Label::BindTo; |
| 255 | using Label::LinkTo; |
| 256 | |
| 257 | friend class x86::X86Assembler; |
| 258 | |
| 259 | DISALLOW_COPY_AND_ASSIGN(NearLabel); |
| 260 | }; |
| 261 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 262 | /** |
| 263 | * Class to handle constant area values. |
| 264 | */ |
| 265 | class ConstantArea { |
| 266 | public: |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 267 | explicit ConstantArea(ArenaAllocator* arena) : buffer_(arena->Adapter(kArenaAllocAssembler)) {} |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 268 | |
| 269 | // Add a double to the constant area, returning the offset into |
| 270 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 271 | size_t AddDouble(double v); |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 272 | |
| 273 | // Add a float to the constant area, returning the offset into |
| 274 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 275 | size_t AddFloat(float v); |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 276 | |
| 277 | // Add an int32_t to the constant area, returning the offset into |
| 278 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 279 | size_t AddInt32(int32_t v); |
| 280 | |
| 281 | // Add an int32_t to the end of the constant area, returning the offset into |
| 282 | // the constant area where the literal resides. |
| 283 | size_t AppendInt32(int32_t v); |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 284 | |
| 285 | // Add an int64_t to the constant area, returning the offset into |
| 286 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 287 | size_t AddInt64(int64_t v); |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 288 | |
| 289 | bool IsEmpty() const { |
| 290 | return buffer_.size() == 0; |
| 291 | } |
| 292 | |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 293 | size_t GetSize() const { |
| 294 | return buffer_.size() * elem_size_; |
| 295 | } |
| 296 | |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 297 | ArrayRef<const int32_t> GetBuffer() const { |
| 298 | return ArrayRef<const int32_t>(buffer_); |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 299 | } |
| 300 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 301 | private: |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 302 | static constexpr size_t elem_size_ = sizeof(int32_t); |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 303 | ArenaVector<int32_t> buffer_; |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 304 | }; |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 305 | |
Andreas Gampe | 9954e3b | 2016-08-05 20:34:39 -0700 | [diff] [blame] | 306 | class X86Assembler FINAL : public Assembler { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 307 | public: |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 308 | explicit X86Assembler(ArenaAllocator* arena) : Assembler(arena), constant_area_(arena) {} |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 309 | virtual ~X86Assembler() {} |
buzbee | c143c55 | 2011-08-20 17:38:58 -0700 | [diff] [blame] | 310 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 311 | /* |
| 312 | * Emit Machine Instructions. |
| 313 | */ |
| 314 | void call(Register reg); |
| 315 | void call(const Address& address); |
| 316 | void call(Label* label); |
Nicolas Geoffray | 8ccc3f5 | 2014-03-19 10:34:11 +0000 | [diff] [blame] | 317 | void call(const ExternalLabel& label); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 318 | |
| 319 | void pushl(Register reg); |
| 320 | void pushl(const Address& address); |
| 321 | void pushl(const Immediate& imm); |
| 322 | |
| 323 | void popl(Register reg); |
| 324 | void popl(const Address& address); |
| 325 | |
| 326 | void movl(Register dst, const Immediate& src); |
| 327 | void movl(Register dst, Register src); |
| 328 | |
| 329 | void movl(Register dst, const Address& src); |
| 330 | void movl(const Address& dst, Register src); |
| 331 | void movl(const Address& dst, const Immediate& imm); |
Ian Rogers | bdb0391 | 2011-09-14 00:55:44 -0700 | [diff] [blame] | 332 | void movl(const Address& dst, Label* lbl); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 333 | |
Mark Mendell | 7a08fb5 | 2015-07-15 14:09:35 -0400 | [diff] [blame] | 334 | void movntl(const Address& dst, Register src); |
| 335 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 336 | void bswapl(Register dst); |
Aart Bik | c39dac1 | 2016-01-21 08:59:48 -0800 | [diff] [blame] | 337 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 338 | void bsfl(Register dst, Register src); |
| 339 | void bsfl(Register dst, const Address& src); |
Mark Mendell | 8ae3ffb | 2015-08-12 21:16:41 -0400 | [diff] [blame] | 340 | void bsrl(Register dst, Register src); |
| 341 | void bsrl(Register dst, const Address& src); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 342 | |
Aart Bik | c39dac1 | 2016-01-21 08:59:48 -0800 | [diff] [blame] | 343 | void popcntl(Register dst, Register src); |
| 344 | void popcntl(Register dst, const Address& src); |
| 345 | |
Mark Mendell | bcee092 | 2015-09-15 21:45:01 -0400 | [diff] [blame] | 346 | void rorl(Register reg, const Immediate& imm); |
| 347 | void rorl(Register operand, Register shifter); |
| 348 | void roll(Register reg, const Immediate& imm); |
| 349 | void roll(Register operand, Register shifter); |
| 350 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 351 | void movzxb(Register dst, ByteRegister src); |
| 352 | void movzxb(Register dst, const Address& src); |
| 353 | void movsxb(Register dst, ByteRegister src); |
| 354 | void movsxb(Register dst, const Address& src); |
| 355 | void movb(Register dst, const Address& src); |
| 356 | void movb(const Address& dst, ByteRegister src); |
| 357 | void movb(const Address& dst, const Immediate& imm); |
| 358 | |
| 359 | void movzxw(Register dst, Register src); |
| 360 | void movzxw(Register dst, const Address& src); |
| 361 | void movsxw(Register dst, Register src); |
| 362 | void movsxw(Register dst, const Address& src); |
| 363 | void movw(Register dst, const Address& src); |
| 364 | void movw(const Address& dst, Register src); |
Nicolas Geoffray | 26a25ef | 2014-09-30 13:54:09 +0100 | [diff] [blame] | 365 | void movw(const Address& dst, const Immediate& imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 366 | |
| 367 | void leal(Register dst, const Address& src); |
| 368 | |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 369 | void cmovl(Condition condition, Register dst, Register src); |
Mark Mendell | abdac47 | 2016-02-12 13:49:03 -0500 | [diff] [blame] | 370 | void cmovl(Condition condition, Register dst, const Address& src); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 371 | |
Nicolas Geoffray | 5b4b898 | 2014-12-18 17:45:56 +0000 | [diff] [blame] | 372 | void setb(Condition condition, Register dst); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 373 | |
Nicolas Geoffray | 7fb49da | 2014-10-06 09:12:41 +0100 | [diff] [blame] | 374 | void movaps(XmmRegister dst, XmmRegister src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 375 | void movss(XmmRegister dst, const Address& src); |
| 376 | void movss(const Address& dst, XmmRegister src); |
| 377 | void movss(XmmRegister dst, XmmRegister src); |
| 378 | |
| 379 | void movd(XmmRegister dst, Register src); |
| 380 | void movd(Register dst, XmmRegister src); |
| 381 | |
| 382 | void addss(XmmRegister dst, XmmRegister src); |
| 383 | void addss(XmmRegister dst, const Address& src); |
| 384 | void subss(XmmRegister dst, XmmRegister src); |
| 385 | void subss(XmmRegister dst, const Address& src); |
| 386 | void mulss(XmmRegister dst, XmmRegister src); |
| 387 | void mulss(XmmRegister dst, const Address& src); |
| 388 | void divss(XmmRegister dst, XmmRegister src); |
| 389 | void divss(XmmRegister dst, const Address& src); |
| 390 | |
| 391 | void movsd(XmmRegister dst, const Address& src); |
| 392 | void movsd(const Address& dst, XmmRegister src); |
| 393 | void movsd(XmmRegister dst, XmmRegister src); |
| 394 | |
Calin Juravle | 52c4896 | 2014-12-16 17:02:57 +0000 | [diff] [blame] | 395 | void psrlq(XmmRegister reg, const Immediate& shift_count); |
| 396 | void punpckldq(XmmRegister dst, XmmRegister src); |
| 397 | |
Nicolas Geoffray | 234d69d | 2015-03-09 10:28:50 +0000 | [diff] [blame] | 398 | void movhpd(XmmRegister dst, const Address& src); |
| 399 | void movhpd(const Address& dst, XmmRegister src); |
| 400 | |
| 401 | void psrldq(XmmRegister reg, const Immediate& shift_count); |
| 402 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 403 | void addsd(XmmRegister dst, XmmRegister src); |
| 404 | void addsd(XmmRegister dst, const Address& src); |
| 405 | void subsd(XmmRegister dst, XmmRegister src); |
| 406 | void subsd(XmmRegister dst, const Address& src); |
| 407 | void mulsd(XmmRegister dst, XmmRegister src); |
| 408 | void mulsd(XmmRegister dst, const Address& src); |
| 409 | void divsd(XmmRegister dst, XmmRegister src); |
| 410 | void divsd(XmmRegister dst, const Address& src); |
| 411 | |
| 412 | void cvtsi2ss(XmmRegister dst, Register src); |
| 413 | void cvtsi2sd(XmmRegister dst, Register src); |
| 414 | |
| 415 | void cvtss2si(Register dst, XmmRegister src); |
| 416 | void cvtss2sd(XmmRegister dst, XmmRegister src); |
| 417 | |
| 418 | void cvtsd2si(Register dst, XmmRegister src); |
| 419 | void cvtsd2ss(XmmRegister dst, XmmRegister src); |
| 420 | |
| 421 | void cvttss2si(Register dst, XmmRegister src); |
| 422 | void cvttsd2si(Register dst, XmmRegister src); |
| 423 | |
| 424 | void cvtdq2pd(XmmRegister dst, XmmRegister src); |
| 425 | |
| 426 | void comiss(XmmRegister a, XmmRegister b); |
Aart Bik | 18ba121 | 2016-08-01 14:11:20 -0700 | [diff] [blame] | 427 | void comiss(XmmRegister a, const Address& b); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 428 | void comisd(XmmRegister a, XmmRegister b); |
Aart Bik | 18ba121 | 2016-08-01 14:11:20 -0700 | [diff] [blame] | 429 | void comisd(XmmRegister a, const Address& b); |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 430 | void ucomiss(XmmRegister a, XmmRegister b); |
Mark Mendell | 9f51f26 | 2015-10-30 09:21:37 -0400 | [diff] [blame] | 431 | void ucomiss(XmmRegister a, const Address& b); |
Calin Juravle | ddb7df2 | 2014-11-25 20:56:51 +0000 | [diff] [blame] | 432 | void ucomisd(XmmRegister a, XmmRegister b); |
Mark Mendell | 9f51f26 | 2015-10-30 09:21:37 -0400 | [diff] [blame] | 433 | void ucomisd(XmmRegister a, const Address& b); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 434 | |
Mark Mendell | fb8d279 | 2015-03-31 22:16:59 -0400 | [diff] [blame] | 435 | void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm); |
| 436 | void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm); |
| 437 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 438 | void sqrtsd(XmmRegister dst, XmmRegister src); |
| 439 | void sqrtss(XmmRegister dst, XmmRegister src); |
| 440 | |
| 441 | void xorpd(XmmRegister dst, const Address& src); |
| 442 | void xorpd(XmmRegister dst, XmmRegister src); |
| 443 | void xorps(XmmRegister dst, const Address& src); |
| 444 | void xorps(XmmRegister dst, XmmRegister src); |
| 445 | |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 446 | void andpd(XmmRegister dst, XmmRegister src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 447 | void andpd(XmmRegister dst, const Address& src); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 448 | void andps(XmmRegister dst, XmmRegister src); |
| 449 | void andps(XmmRegister dst, const Address& src); |
| 450 | |
| 451 | void orpd(XmmRegister dst, XmmRegister src); |
| 452 | void orps(XmmRegister dst, XmmRegister src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 453 | |
| 454 | void flds(const Address& src); |
| 455 | void fstps(const Address& dst); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 456 | void fsts(const Address& dst); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 457 | |
| 458 | void fldl(const Address& src); |
| 459 | void fstpl(const Address& dst); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 460 | void fstl(const Address& dst); |
| 461 | |
| 462 | void fstsw(); |
| 463 | |
| 464 | void fucompp(); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 465 | |
| 466 | void fnstcw(const Address& dst); |
| 467 | void fldcw(const Address& src); |
| 468 | |
| 469 | void fistpl(const Address& dst); |
| 470 | void fistps(const Address& dst); |
| 471 | void fildl(const Address& src); |
Roland Levillain | 0a18601 | 2015-04-13 17:00:20 +0100 | [diff] [blame] | 472 | void filds(const Address& src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 473 | |
| 474 | void fincstp(); |
| 475 | void ffree(const Immediate& index); |
| 476 | |
| 477 | void fsin(); |
| 478 | void fcos(); |
| 479 | void fptan(); |
Mark Mendell | 24f2dfa | 2015-01-14 19:51:45 -0500 | [diff] [blame] | 480 | void fprem(); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 481 | |
| 482 | void xchgl(Register dst, Register src); |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 483 | void xchgl(Register reg, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 484 | |
Serguei Katkov | 3b62593 | 2016-05-06 10:24:17 +0600 | [diff] [blame] | 485 | void cmpb(const Address& address, const Immediate& imm); |
Nicolas Geoffray | 3c04974 | 2014-09-24 18:10:46 +0100 | [diff] [blame] | 486 | void cmpw(const Address& address, const Immediate& imm); |
| 487 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 488 | void cmpl(Register reg, const Immediate& imm); |
| 489 | void cmpl(Register reg0, Register reg1); |
| 490 | void cmpl(Register reg, const Address& address); |
| 491 | |
| 492 | void cmpl(const Address& address, Register reg); |
| 493 | void cmpl(const Address& address, const Immediate& imm); |
| 494 | |
| 495 | void testl(Register reg1, Register reg2); |
| 496 | void testl(Register reg, const Immediate& imm); |
Nicolas Geoffray | f12feb8 | 2014-07-17 18:32:41 +0100 | [diff] [blame] | 497 | void testl(Register reg1, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 498 | |
Vladimir Marko | 953437b | 2016-08-24 08:30:46 +0000 | [diff] [blame] | 499 | void testb(const Address& dst, const Immediate& imm); |
| 500 | void testl(const Address& dst, const Immediate& imm); |
| 501 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 502 | void andl(Register dst, const Immediate& imm); |
| 503 | void andl(Register dst, Register src); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 504 | void andl(Register dst, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 505 | |
| 506 | void orl(Register dst, const Immediate& imm); |
| 507 | void orl(Register dst, Register src); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 508 | void orl(Register dst, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 509 | |
| 510 | void xorl(Register dst, Register src); |
Nicolas Geoffray | b55f835 | 2014-04-07 15:26:35 +0100 | [diff] [blame] | 511 | void xorl(Register dst, const Immediate& imm); |
Nicolas Geoffray | 9574c4b | 2014-11-12 13:19:37 +0000 | [diff] [blame] | 512 | void xorl(Register dst, const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 513 | |
| 514 | void addl(Register dst, Register src); |
| 515 | void addl(Register reg, const Immediate& imm); |
| 516 | void addl(Register reg, const Address& address); |
| 517 | |
| 518 | void addl(const Address& address, Register reg); |
| 519 | void addl(const Address& address, const Immediate& imm); |
| 520 | |
| 521 | void adcl(Register dst, Register src); |
| 522 | void adcl(Register reg, const Immediate& imm); |
| 523 | void adcl(Register dst, const Address& address); |
| 524 | |
| 525 | void subl(Register dst, Register src); |
| 526 | void subl(Register reg, const Immediate& imm); |
| 527 | void subl(Register reg, const Address& address); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 528 | void subl(const Address& address, Register src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 529 | |
| 530 | void cdq(); |
| 531 | |
| 532 | void idivl(Register reg); |
| 533 | |
| 534 | void imull(Register dst, Register src); |
| 535 | void imull(Register reg, const Immediate& imm); |
Mark Mendell | 4a2aa4a | 2015-07-27 16:13:10 -0400 | [diff] [blame] | 536 | void imull(Register dst, Register src, const Immediate& imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 537 | void imull(Register reg, const Address& address); |
| 538 | |
| 539 | void imull(Register reg); |
| 540 | void imull(const Address& address); |
| 541 | |
| 542 | void mull(Register reg); |
| 543 | void mull(const Address& address); |
| 544 | |
| 545 | void sbbl(Register dst, Register src); |
| 546 | void sbbl(Register reg, const Immediate& imm); |
| 547 | void sbbl(Register reg, const Address& address); |
Mark Mendell | 09ed1a3 | 2015-03-25 08:30:06 -0400 | [diff] [blame] | 548 | void sbbl(const Address& address, Register src); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 549 | |
| 550 | void incl(Register reg); |
| 551 | void incl(const Address& address); |
| 552 | |
| 553 | void decl(Register reg); |
| 554 | void decl(const Address& address); |
| 555 | |
| 556 | void shll(Register reg, const Immediate& imm); |
| 557 | void shll(Register operand, Register shifter); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 558 | void shll(const Address& address, const Immediate& imm); |
| 559 | void shll(const Address& address, Register shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 560 | void shrl(Register reg, const Immediate& imm); |
| 561 | void shrl(Register operand, Register shifter); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 562 | void shrl(const Address& address, const Immediate& imm); |
| 563 | void shrl(const Address& address, Register shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 564 | void sarl(Register reg, const Immediate& imm); |
| 565 | void sarl(Register operand, Register shifter); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 566 | void sarl(const Address& address, const Immediate& imm); |
| 567 | void sarl(const Address& address, Register shifter); |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 568 | void shld(Register dst, Register src, Register shifter); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 569 | void shld(Register dst, Register src, const Immediate& imm); |
Calin Juravle | 9aec02f | 2014-11-18 23:06:35 +0000 | [diff] [blame] | 570 | void shrd(Register dst, Register src, Register shifter); |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 571 | void shrd(Register dst, Register src, const Immediate& imm); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 572 | |
| 573 | void negl(Register reg); |
| 574 | void notl(Register reg); |
| 575 | |
| 576 | void enter(const Immediate& imm); |
| 577 | void leave(); |
| 578 | |
| 579 | void ret(); |
| 580 | void ret(const Immediate& imm); |
| 581 | |
| 582 | void nop(); |
| 583 | void int3(); |
| 584 | void hlt(); |
| 585 | |
| 586 | void j(Condition condition, Label* label); |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 587 | void j(Condition condition, NearLabel* label); |
| 588 | void jecxz(NearLabel* label); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 589 | |
| 590 | void jmp(Register reg); |
Ian Rogers | 7caad77 | 2012-03-30 01:07:54 -0700 | [diff] [blame] | 591 | void jmp(const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 592 | void jmp(Label* label); |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 593 | void jmp(NearLabel* label); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 594 | |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 595 | void repne_scasb(); |
Andreas Gampe | 21030dd | 2015-05-07 14:46:15 -0700 | [diff] [blame] | 596 | void repne_scasw(); |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 597 | void repe_cmpsb(); |
agicsaki | 71311f8 | 2015-07-27 11:34:13 -0700 | [diff] [blame] | 598 | void repe_cmpsw(); |
agicsaki | 970abfb | 2015-07-31 10:31:14 -0700 | [diff] [blame] | 599 | void repe_cmpsl(); |
jessicahandojo | b03d640 | 2016-09-07 12:16:53 -0700 | [diff] [blame] | 600 | void rep_movsb(); |
Mark Mendell | b9c4bbe | 2015-07-01 14:26:52 -0400 | [diff] [blame] | 601 | void rep_movsw(); |
Andreas Gampe | 21030dd | 2015-05-07 14:46:15 -0700 | [diff] [blame] | 602 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 603 | X86Assembler* lock(); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 604 | void cmpxchgl(const Address& address, Register reg); |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 605 | void cmpxchg8b(const Address& address); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 606 | |
Elliott Hughes | 79ab9e3 | 2012-03-12 15:41:35 -0700 | [diff] [blame] | 607 | void mfence(); |
| 608 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 609 | X86Assembler* fs(); |
Ian Rogers | befbd57 | 2014-03-06 01:13:39 -0800 | [diff] [blame] | 610 | X86Assembler* gs(); |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 611 | |
| 612 | // |
| 613 | // Macros for High-level operations. |
| 614 | // |
| 615 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 616 | void AddImmediate(Register reg, const Immediate& imm); |
| 617 | |
Roland Levillain | 647b9ed | 2014-11-27 12:06:00 +0000 | [diff] [blame] | 618 | void LoadLongConstant(XmmRegister dst, int64_t value); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 619 | void LoadDoubleConstant(XmmRegister dst, double value); |
| 620 | |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 621 | void LockCmpxchgl(const Address& address, Register reg) { |
Ian Rogers | 0d666d8 | 2011-08-14 16:03:46 -0700 | [diff] [blame] | 622 | lock()->cmpxchgl(address, reg); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 623 | } |
| 624 | |
Mark Mendell | 58d25fd | 2015-04-03 14:52:31 -0400 | [diff] [blame] | 625 | void LockCmpxchg8b(const Address& address) { |
| 626 | lock()->cmpxchg8b(address); |
| 627 | } |
| 628 | |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 629 | // |
| 630 | // Misc. functionality |
| 631 | // |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 632 | int PreferredLoopAlignment() { return 16; } |
| 633 | void Align(int alignment, int offset); |
Andreas Gampe | 85b62f2 | 2015-09-09 13:15:38 -0700 | [diff] [blame] | 634 | void Bind(Label* label) OVERRIDE; |
| 635 | void Jump(Label* label) OVERRIDE { |
| 636 | jmp(label); |
| 637 | } |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 638 | void Bind(NearLabel* label); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 639 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 640 | // |
Roland Levillain | 4d02711 | 2015-07-01 15:41:14 +0100 | [diff] [blame] | 641 | // Heap poisoning. |
| 642 | // |
| 643 | |
| 644 | // Poison a heap reference contained in `reg`. |
| 645 | void PoisonHeapReference(Register reg) { negl(reg); } |
| 646 | // Unpoison a heap reference contained in `reg`. |
| 647 | void UnpoisonHeapReference(Register reg) { negl(reg); } |
Roland Levillain | 0b671c0 | 2016-08-19 12:02:34 +0100 | [diff] [blame] | 648 | // Poison a heap reference contained in `reg` if heap poisoning is enabled. |
| 649 | void MaybePoisonHeapReference(Register reg) { |
| 650 | if (kPoisonHeapReferences) { |
| 651 | PoisonHeapReference(reg); |
| 652 | } |
| 653 | } |
Roland Levillain | 4d02711 | 2015-07-01 15:41:14 +0100 | [diff] [blame] | 654 | // Unpoison a heap reference contained in `reg` if heap poisoning is enabled. |
| 655 | void MaybeUnpoisonHeapReference(Register reg) { |
| 656 | if (kPoisonHeapReferences) { |
| 657 | UnpoisonHeapReference(reg); |
| 658 | } |
| 659 | } |
| 660 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 661 | // Add a double to the constant area, returning the offset into |
| 662 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 663 | size_t AddDouble(double v) { return constant_area_.AddDouble(v); } |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 664 | |
| 665 | // Add a float to the constant area, returning the offset into |
| 666 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 667 | size_t AddFloat(float v) { return constant_area_.AddFloat(v); } |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 668 | |
| 669 | // Add an int32_t to the constant area, returning the offset into |
| 670 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 671 | size_t AddInt32(int32_t v) { |
| 672 | return constant_area_.AddInt32(v); |
| 673 | } |
| 674 | |
| 675 | // Add an int32_t to the end of the constant area, returning the offset into |
| 676 | // the constant area where the literal resides. |
| 677 | size_t AppendInt32(int32_t v) { |
| 678 | return constant_area_.AppendInt32(v); |
| 679 | } |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 680 | |
| 681 | // Add an int64_t to the constant area, returning the offset into |
| 682 | // the constant area where the literal resides. |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 683 | size_t AddInt64(int64_t v) { return constant_area_.AddInt64(v); } |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 684 | |
| 685 | // Add the contents of the constant area to the assembler buffer. |
| 686 | void AddConstantArea(); |
| 687 | |
| 688 | // Is the constant area empty? Return true if there are no literals in the constant area. |
| 689 | bool IsConstantAreaEmpty() const { return constant_area_.IsEmpty(); } |
Mark Mendell | 805b3b5 | 2015-09-18 14:10:29 -0400 | [diff] [blame] | 690 | |
| 691 | // Return the current size of the constant area. |
| 692 | size_t ConstantAreaSize() const { return constant_area_.GetSize(); } |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 693 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 694 | private: |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 695 | inline void EmitUint8(uint8_t value); |
| 696 | inline void EmitInt32(int32_t value); |
| 697 | inline void EmitRegisterOperand(int rm, int reg); |
| 698 | inline void EmitXmmRegisterOperand(int rm, XmmRegister reg); |
| 699 | inline void EmitFixup(AssemblerFixup* fixup); |
| 700 | inline void EmitOperandSizeOverride(); |
| 701 | |
| 702 | void EmitOperand(int rm, const Operand& operand); |
| 703 | void EmitImmediate(const Immediate& imm); |
| 704 | void EmitComplex(int rm, const Operand& operand, const Immediate& immediate); |
| 705 | void EmitLabel(Label* label, int instruction_size); |
| 706 | void EmitLabelLink(Label* label); |
Mark Mendell | 73f455e | 2015-08-21 09:30:05 -0400 | [diff] [blame] | 707 | void EmitLabelLink(NearLabel* label); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 708 | |
Mark P Mendell | 7394569 | 2015-04-29 14:56:17 +0000 | [diff] [blame] | 709 | void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm); |
| 710 | void EmitGenericShift(int rm, const Operand& operand, Register shifter); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 711 | |
Mark Mendell | 0616ae0 | 2015-04-17 12:49:27 -0400 | [diff] [blame] | 712 | ConstantArea constant_area_; |
| 713 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 714 | DISALLOW_COPY_AND_ASSIGN(X86Assembler); |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 715 | }; |
| 716 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 717 | inline void X86Assembler::EmitUint8(uint8_t value) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 718 | buffer_.Emit<uint8_t>(value); |
| 719 | } |
| 720 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 721 | inline void X86Assembler::EmitInt32(int32_t value) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 722 | buffer_.Emit<int32_t>(value); |
| 723 | } |
| 724 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 725 | inline void X86Assembler::EmitRegisterOperand(int rm, int reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 726 | CHECK_GE(rm, 0); |
| 727 | CHECK_LT(rm, 8); |
| 728 | buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg); |
| 729 | } |
| 730 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 731 | inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 732 | EmitRegisterOperand(rm, static_cast<Register>(reg)); |
| 733 | } |
| 734 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 735 | inline void X86Assembler::EmitFixup(AssemblerFixup* fixup) { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 736 | buffer_.EmitFixup(fixup); |
| 737 | } |
| 738 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 739 | inline void X86Assembler::EmitOperandSizeOverride() { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 740 | EmitUint8(0x66); |
| 741 | } |
| 742 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 743 | } // namespace x86 |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 744 | } // namespace art |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 745 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 746 | #endif // ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_ |