Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "arm64_lir.h" |
| 18 | #include "codegen_arm64.h" |
| 19 | #include "dex/quick/mir_to_lir-inl.h" |
| 20 | |
| 21 | namespace art { |
| 22 | |
| 23 | void Arm64Mir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 24 | RegLocation rl_src1, RegLocation rl_src2) { |
| 25 | int op = kA64Brk1d; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 26 | RegLocation rl_result; |
| 27 | |
| 28 | /* |
| 29 | * Don't attempt to optimize register usage since these opcodes call out to |
| 30 | * the handlers. |
| 31 | */ |
| 32 | switch (opcode) { |
| 33 | case Instruction::ADD_FLOAT_2ADDR: |
| 34 | case Instruction::ADD_FLOAT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 35 | op = kA64Fadd3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 36 | break; |
| 37 | case Instruction::SUB_FLOAT_2ADDR: |
| 38 | case Instruction::SUB_FLOAT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 39 | op = kA64Fsub3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 40 | break; |
| 41 | case Instruction::DIV_FLOAT_2ADDR: |
| 42 | case Instruction::DIV_FLOAT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 43 | op = kA64Fdiv3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 44 | break; |
| 45 | case Instruction::MUL_FLOAT_2ADDR: |
| 46 | case Instruction::MUL_FLOAT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 47 | op = kA64Fmul3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 48 | break; |
| 49 | case Instruction::REM_FLOAT_2ADDR: |
| 50 | case Instruction::REM_FLOAT: |
| 51 | FlushAllRegs(); // Send everything to home location |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 52 | CallRuntimeHelperRegLocationRegLocation(A64_QUICK_ENTRYPOINT_OFFSET(pFmodf), rl_src1, rl_src2, |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 53 | false); |
| 54 | rl_result = GetReturn(true); |
| 55 | StoreValue(rl_dest, rl_result); |
| 56 | return; |
| 57 | case Instruction::NEG_FLOAT: |
| 58 | GenNegFloat(rl_dest, rl_src1); |
| 59 | return; |
| 60 | default: |
| 61 | LOG(FATAL) << "Unexpected opcode: " << opcode; |
| 62 | } |
| 63 | rl_src1 = LoadValue(rl_src1, kFPReg); |
| 64 | rl_src2 = LoadValue(rl_src2, kFPReg); |
| 65 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
| 66 | NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
| 67 | StoreValue(rl_dest, rl_result); |
| 68 | } |
| 69 | |
| 70 | void Arm64Mir2Lir::GenArithOpDouble(Instruction::Code opcode, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 71 | RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { |
| 72 | int op = kA64Brk1d; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 73 | RegLocation rl_result; |
| 74 | |
| 75 | switch (opcode) { |
| 76 | case Instruction::ADD_DOUBLE_2ADDR: |
| 77 | case Instruction::ADD_DOUBLE: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 78 | op = kA64Fadd3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 79 | break; |
| 80 | case Instruction::SUB_DOUBLE_2ADDR: |
| 81 | case Instruction::SUB_DOUBLE: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 82 | op = kA64Fsub3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 83 | break; |
| 84 | case Instruction::DIV_DOUBLE_2ADDR: |
| 85 | case Instruction::DIV_DOUBLE: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 86 | op = kA64Fdiv3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 87 | break; |
| 88 | case Instruction::MUL_DOUBLE_2ADDR: |
| 89 | case Instruction::MUL_DOUBLE: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 90 | op = kA64Fmul3fff; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 91 | break; |
| 92 | case Instruction::REM_DOUBLE_2ADDR: |
| 93 | case Instruction::REM_DOUBLE: |
| 94 | FlushAllRegs(); // Send everything to home location |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 95 | CallRuntimeHelperRegLocationRegLocation(A64_QUICK_ENTRYPOINT_OFFSET(pFmod), rl_src1, rl_src2, |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 96 | false); |
| 97 | rl_result = GetReturnWide(true); |
| 98 | StoreValueWide(rl_dest, rl_result); |
| 99 | return; |
| 100 | case Instruction::NEG_DOUBLE: |
| 101 | GenNegDouble(rl_dest, rl_src1); |
| 102 | return; |
| 103 | default: |
| 104 | LOG(FATAL) << "Unexpected opcode: " << opcode; |
| 105 | } |
| 106 | |
| 107 | rl_src1 = LoadValueWide(rl_src1, kFPReg); |
| 108 | DCHECK(rl_src1.wide); |
| 109 | rl_src2 = LoadValueWide(rl_src2, kFPReg); |
| 110 | DCHECK(rl_src2.wide); |
| 111 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
| 112 | DCHECK(rl_dest.wide); |
| 113 | DCHECK(rl_result.wide); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 114 | NewLIR3(FWIDE(op), rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 115 | StoreValueWide(rl_dest, rl_result); |
| 116 | } |
| 117 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 118 | void Arm64Mir2Lir::GenConversion(Instruction::Code opcode, |
| 119 | RegLocation rl_dest, RegLocation rl_src) { |
| 120 | int op = kA64Brk1d; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 121 | RegLocation rl_result; |
| 122 | |
| 123 | switch (opcode) { |
| 124 | case Instruction::INT_TO_FLOAT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 125 | op = kA64Scvtf2fw; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 126 | break; |
| 127 | case Instruction::FLOAT_TO_INT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 128 | op = kA64Fcvtzs2wf; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 129 | break; |
| 130 | case Instruction::DOUBLE_TO_FLOAT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 131 | op = kA64Fcvt2sS; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 132 | break; |
| 133 | case Instruction::FLOAT_TO_DOUBLE: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 134 | op = kA64Fcvt2Ss; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 135 | break; |
| 136 | case Instruction::INT_TO_DOUBLE: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 137 | op = FWIDE(kA64Scvtf2fw); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 138 | break; |
| 139 | case Instruction::DOUBLE_TO_INT: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 140 | op = FWIDE(kA64Fcvtzs2wf); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 141 | break; |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 142 | case Instruction::LONG_TO_DOUBLE: |
| 143 | op = FWIDE(kA64Scvtf2fx); |
| 144 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 145 | case Instruction::FLOAT_TO_LONG: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 146 | op = kA64Fcvtzs2xf; |
| 147 | break; |
| 148 | case Instruction::LONG_TO_FLOAT: |
| 149 | op = kA64Scvtf2fx; |
| 150 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 151 | case Instruction::DOUBLE_TO_LONG: |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 152 | op = FWIDE(kA64Fcvtzs2xf); |
| 153 | break; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 154 | default: |
| 155 | LOG(FATAL) << "Unexpected opcode: " << opcode; |
| 156 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 157 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 158 | if (rl_src.wide) { |
| 159 | rl_src = LoadValueWide(rl_src, kFPReg); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 160 | } else { |
| 161 | rl_src = LoadValue(rl_src, kFPReg); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 162 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 163 | |
| 164 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
| 165 | NewLIR2(op, rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
| 166 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 167 | if (rl_dest.wide) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 168 | StoreValueWide(rl_dest, rl_result); |
| 169 | } else { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 170 | StoreValue(rl_dest, rl_result); |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | void Arm64Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, |
| 175 | bool is_double) { |
| 176 | LIR* target = &block_label_list_[bb->taken]; |
| 177 | RegLocation rl_src1; |
| 178 | RegLocation rl_src2; |
| 179 | if (is_double) { |
| 180 | rl_src1 = mir_graph_->GetSrcWide(mir, 0); |
| 181 | rl_src2 = mir_graph_->GetSrcWide(mir, 2); |
| 182 | rl_src1 = LoadValueWide(rl_src1, kFPReg); |
| 183 | rl_src2 = LoadValueWide(rl_src2, kFPReg); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 184 | NewLIR2(FWIDE(kA64Fcmp2ff), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 185 | } else { |
| 186 | rl_src1 = mir_graph_->GetSrc(mir, 0); |
| 187 | rl_src2 = mir_graph_->GetSrc(mir, 1); |
| 188 | rl_src1 = LoadValue(rl_src1, kFPReg); |
| 189 | rl_src2 = LoadValue(rl_src2, kFPReg); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 190 | NewLIR2(kA64Fcmp2ff, rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 191 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 192 | ConditionCode ccode = mir->meta.ccode; |
| 193 | switch (ccode) { |
| 194 | case kCondEq: |
| 195 | case kCondNe: |
| 196 | break; |
| 197 | case kCondLt: |
| 198 | if (gt_bias) { |
| 199 | ccode = kCondMi; |
| 200 | } |
| 201 | break; |
| 202 | case kCondLe: |
| 203 | if (gt_bias) { |
| 204 | ccode = kCondLs; |
| 205 | } |
| 206 | break; |
| 207 | case kCondGt: |
| 208 | if (gt_bias) { |
| 209 | ccode = kCondHi; |
| 210 | } |
| 211 | break; |
| 212 | case kCondGe: |
| 213 | if (gt_bias) { |
| 214 | ccode = kCondUge; |
| 215 | } |
| 216 | break; |
| 217 | default: |
| 218 | LOG(FATAL) << "Unexpected ccode: " << ccode; |
| 219 | } |
| 220 | OpCondBranch(ccode, target); |
| 221 | } |
| 222 | |
| 223 | |
| 224 | void Arm64Mir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 225 | RegLocation rl_src1, RegLocation rl_src2) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 226 | bool is_double = false; |
| 227 | int default_result = -1; |
| 228 | RegLocation rl_result; |
| 229 | |
| 230 | switch (opcode) { |
| 231 | case Instruction::CMPL_FLOAT: |
| 232 | is_double = false; |
| 233 | default_result = -1; |
| 234 | break; |
| 235 | case Instruction::CMPG_FLOAT: |
| 236 | is_double = false; |
| 237 | default_result = 1; |
| 238 | break; |
| 239 | case Instruction::CMPL_DOUBLE: |
| 240 | is_double = true; |
| 241 | default_result = -1; |
| 242 | break; |
| 243 | case Instruction::CMPG_DOUBLE: |
| 244 | is_double = true; |
| 245 | default_result = 1; |
| 246 | break; |
| 247 | default: |
| 248 | LOG(FATAL) << "Unexpected opcode: " << opcode; |
| 249 | } |
| 250 | if (is_double) { |
| 251 | rl_src1 = LoadValueWide(rl_src1, kFPReg); |
| 252 | rl_src2 = LoadValueWide(rl_src2, kFPReg); |
| 253 | // In case result vreg is also a src vreg, break association to avoid useless copy by EvalLoc() |
| 254 | ClobberSReg(rl_dest.s_reg_low); |
| 255 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 256 | LoadConstant(rl_result.reg, default_result); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 257 | NewLIR2(FWIDE(kA64Fcmp2ff), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 258 | } else { |
| 259 | rl_src1 = LoadValue(rl_src1, kFPReg); |
| 260 | rl_src2 = LoadValue(rl_src2, kFPReg); |
| 261 | // In case result vreg is also a srcvreg, break association to avoid useless copy by EvalLoc() |
| 262 | ClobberSReg(rl_dest.s_reg_low); |
| 263 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 264 | LoadConstant(rl_result.reg, default_result); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 265 | NewLIR2(kA64Fcmp2ff, rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 266 | } |
| 267 | DCHECK(!rl_result.reg.IsFloat()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 268 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 269 | // TODO(Arm64): should we rather do this? |
| 270 | // csinc wD, wzr, wzr, eq |
| 271 | // csneg wD, wD, wD, le |
| 272 | // (which requires 2 instructions rather than 3) |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 273 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 274 | // Rd = if cond then Rd else -Rd. |
| 275 | NewLIR4(kA64Csneg4rrrc, rl_result.reg.GetReg(), rl_result.reg.GetReg(), |
| 276 | rl_result.reg.GetReg(), (default_result == 1) ? kArmCondPl : kArmCondLe); |
| 277 | NewLIR4(kA64Csel4rrrc, rl_result.reg.GetReg(), rwzr, rl_result.reg.GetReg(), |
| 278 | kArmCondEq); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 279 | StoreValue(rl_dest, rl_result); |
| 280 | } |
| 281 | |
| 282 | void Arm64Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) { |
| 283 | RegLocation rl_result; |
| 284 | rl_src = LoadValue(rl_src, kFPReg); |
| 285 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 286 | NewLIR2(kA64Fneg2ff, rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 287 | StoreValue(rl_dest, rl_result); |
| 288 | } |
| 289 | |
| 290 | void Arm64Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) { |
| 291 | RegLocation rl_result; |
| 292 | rl_src = LoadValueWide(rl_src, kFPReg); |
| 293 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 294 | NewLIR2(FWIDE(kA64Fneg2ff), rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 295 | StoreValueWide(rl_dest, rl_result); |
| 296 | } |
| 297 | |
| 298 | bool Arm64Mir2Lir::GenInlinedSqrt(CallInfo* info) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 299 | // TODO(Arm64): implement this. |
| 300 | UNIMPLEMENTED(FATAL) << "GenInlinedSqrt not implemented for Arm64"; |
| 301 | |
| 302 | DCHECK_EQ(cu_->instruction_set, kArm64); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 303 | LIR *branch; |
| 304 | RegLocation rl_src = info->args[0]; |
| 305 | RegLocation rl_dest = InlineTargetWide(info); // double place for result |
| 306 | rl_src = LoadValueWide(rl_src, kFPReg); |
| 307 | RegLocation rl_result = EvalLoc(rl_dest, kFPReg, true); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 308 | NewLIR2(FWIDE(kA64Fsqrt2ff), rl_result.reg.GetReg(), rl_src.reg.GetReg()); |
| 309 | NewLIR2(FWIDE(kA64Fcmp2ff), rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
| 310 | branch = NewLIR2(kA64B2ct, kArmCondEq, 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 311 | ClobberCallerSave(); |
| 312 | LockCallTemps(); // Using fixed registers |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame^] | 313 | RegStorage r_tgt = LoadHelper(A64_QUICK_ENTRYPOINT_OFFSET(pSqrt)); |
| 314 | // NewLIR3(kThumb2Fmrrd, r0, r1, rl_src.reg.GetReg()); |
| 315 | NewLIR1(kA64Blr1x, r_tgt.GetReg()); |
| 316 | // NewLIR3(kThumb2Fmdrr, rl_result.reg.GetReg(), r0, r1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 317 | branch->target = NewLIR0(kPseudoTargetLabel); |
| 318 | StoreValueWide(rl_dest, rl_result); |
| 319 | return true; |
| 320 | } |
| 321 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 322 | } // namespace art |