Elliott Hughes | 2faa5f1 | 2012-01-30 14:42:07 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 16 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 17 | #ifndef ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_H_ |
| 18 | #define ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_H_ |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 19 | |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 20 | #include <type_traits> |
Elliott Hughes | 07ed66b | 2012-12-12 18:34:25 -0800 | [diff] [blame] | 21 | #include <vector> |
| 22 | |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 23 | #include "base/arena_allocator.h" |
| 24 | #include "base/arena_containers.h" |
Vladimir Marko | 80afd02 | 2015-05-19 18:08:00 +0100 | [diff] [blame] | 25 | #include "base/bit_utils.h" |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 26 | #include "base/enums.h" |
Elliott Hughes | 07ed66b | 2012-12-12 18:34:25 -0800 | [diff] [blame] | 27 | #include "base/logging.h" |
Vladimir Marko | 88b2b80 | 2015-12-04 14:19:04 +0000 | [diff] [blame] | 28 | #include "base/stl_util.h" |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 29 | #include "base/value_object.h" |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 30 | #include "constants_arm.h" |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 31 | #include "utils/arm/managed_register_arm.h" |
| 32 | #include "utils/assembler.h" |
Andreas Gampe | 3b165bc | 2016-08-01 22:07:04 -0700 | [diff] [blame] | 33 | #include "utils/jni_macro_assembler.h" |
Brian Carlstrom | 578bbdc | 2011-07-21 14:07:47 -0700 | [diff] [blame] | 34 | #include "offsets.h" |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 35 | |
Carl Shapiro | 6b6b5f0 | 2011-06-21 15:05:09 -0700 | [diff] [blame] | 36 | namespace art { |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 37 | namespace arm { |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 38 | |
Nicolas Geoffray | 3bcc8ea | 2014-11-28 15:00:02 +0000 | [diff] [blame] | 39 | class Arm32Assembler; |
| 40 | class Thumb2Assembler; |
| 41 | |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 42 | // Assembler literal is a value embedded in code, retrieved using a PC-relative load. |
| 43 | class Literal { |
Nicolas Geoffray | d56376c | 2015-05-21 12:32:34 +0000 | [diff] [blame] | 44 | public: |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 45 | static constexpr size_t kMaxSize = 8; |
| 46 | |
| 47 | Literal(uint32_t size, const uint8_t* data) |
| 48 | : label_(), size_(size) { |
| 49 | DCHECK_LE(size, Literal::kMaxSize); |
| 50 | memcpy(data_, data, size); |
| 51 | } |
| 52 | |
| 53 | template <typename T> |
| 54 | T GetValue() const { |
| 55 | DCHECK_EQ(size_, sizeof(T)); |
| 56 | T value; |
| 57 | memcpy(&value, data_, sizeof(T)); |
| 58 | return value; |
| 59 | } |
| 60 | |
| 61 | uint32_t GetSize() const { |
| 62 | return size_; |
| 63 | } |
| 64 | |
| 65 | const uint8_t* GetData() const { |
| 66 | return data_; |
| 67 | } |
| 68 | |
| 69 | Label* GetLabel() { |
| 70 | return &label_; |
| 71 | } |
| 72 | |
| 73 | const Label* GetLabel() const { |
| 74 | return &label_; |
| 75 | } |
Nicolas Geoffray | d56376c | 2015-05-21 12:32:34 +0000 | [diff] [blame] | 76 | |
| 77 | private: |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 78 | Label label_; |
| 79 | const uint32_t size_; |
| 80 | uint8_t data_[kMaxSize]; |
| 81 | |
| 82 | DISALLOW_COPY_AND_ASSIGN(Literal); |
Nicolas Geoffray | d56376c | 2015-05-21 12:32:34 +0000 | [diff] [blame] | 83 | }; |
| 84 | |
Andreas Gampe | 7cffc3b | 2015-10-19 21:31:53 -0700 | [diff] [blame] | 85 | // Jump table: table of labels emitted after the literals. Similar to literals. |
| 86 | class JumpTable { |
| 87 | public: |
| 88 | explicit JumpTable(std::vector<Label*>&& labels) |
| 89 | : label_(), anchor_label_(), labels_(std::move(labels)) { |
| 90 | } |
| 91 | |
| 92 | uint32_t GetSize() const { |
| 93 | return static_cast<uint32_t>(labels_.size()) * sizeof(uint32_t); |
| 94 | } |
| 95 | |
| 96 | const std::vector<Label*>& GetData() const { |
| 97 | return labels_; |
| 98 | } |
| 99 | |
| 100 | Label* GetLabel() { |
| 101 | return &label_; |
| 102 | } |
| 103 | |
| 104 | const Label* GetLabel() const { |
| 105 | return &label_; |
| 106 | } |
| 107 | |
| 108 | Label* GetAnchorLabel() { |
| 109 | return &anchor_label_; |
| 110 | } |
| 111 | |
| 112 | const Label* GetAnchorLabel() const { |
| 113 | return &anchor_label_; |
| 114 | } |
| 115 | |
| 116 | private: |
| 117 | Label label_; |
| 118 | Label anchor_label_; |
| 119 | std::vector<Label*> labels_; |
| 120 | |
| 121 | DISALLOW_COPY_AND_ASSIGN(JumpTable); |
| 122 | }; |
| 123 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 124 | class ShifterOperand { |
| 125 | public: |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 126 | ShifterOperand() : type_(kUnknown), rm_(kNoRegister), rs_(kNoRegister), |
| 127 | is_rotate_(false), is_shift_(false), shift_(kNoShift), rotate_(0), immed_(0) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 128 | } |
| 129 | |
Nicolas Geoffray | 96f89a2 | 2014-07-11 10:57:49 +0100 | [diff] [blame] | 130 | explicit ShifterOperand(uint32_t immed); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 131 | |
| 132 | // Data-processing operands - Register |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 133 | explicit ShifterOperand(Register rm) : type_(kRegister), rm_(rm), rs_(kNoRegister), |
| 134 | is_rotate_(false), is_shift_(false), shift_(kNoShift), rotate_(0), immed_(0) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 135 | } |
| 136 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 137 | ShifterOperand(uint32_t rotate, uint32_t immed8) : type_(kImmediate), rm_(kNoRegister), |
| 138 | rs_(kNoRegister), |
| 139 | is_rotate_(true), is_shift_(false), shift_(kNoShift), rotate_(rotate), immed_(immed8) { |
| 140 | } |
| 141 | |
| 142 | ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), |
| 143 | rs_(kNoRegister), |
| 144 | is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(shift_imm) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | // Data-processing operands - Logical shift/rotate by register |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 148 | ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), |
| 149 | rs_(rs), |
| 150 | is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(0) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 151 | } |
| 152 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 153 | bool is_valid() const { return (type_ == kImmediate) || (type_ == kRegister); } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 154 | |
| 155 | uint32_t type() const { |
| 156 | CHECK(is_valid()); |
| 157 | return type_; |
| 158 | } |
| 159 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 160 | uint32_t encodingArm() const; |
Dave Allison | 45fdb93 | 2014-06-25 12:37:10 -0700 | [diff] [blame] | 161 | uint32_t encodingThumb() const; |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 162 | |
| 163 | bool IsEmpty() const { |
| 164 | return type_ == kUnknown; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 165 | } |
| 166 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 167 | bool IsImmediate() const { |
| 168 | return type_ == kImmediate; |
| 169 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 170 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 171 | bool IsRegister() const { |
| 172 | return type_ == kRegister; |
| 173 | } |
| 174 | |
| 175 | bool IsShift() const { |
| 176 | return is_shift_; |
| 177 | } |
| 178 | |
| 179 | uint32_t GetImmediate() const { |
| 180 | return immed_; |
| 181 | } |
| 182 | |
| 183 | Shift GetShift() const { |
| 184 | return shift_; |
| 185 | } |
| 186 | |
| 187 | Register GetRegister() const { |
| 188 | return rm_; |
| 189 | } |
| 190 | |
Guillaume "Vermeille" Sanchez | ab4a2f5 | 2015-03-11 14:00:30 +0000 | [diff] [blame] | 191 | Register GetSecondRegister() const { |
| 192 | return rs_; |
| 193 | } |
| 194 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 195 | enum Type { |
| 196 | kUnknown = -1, |
| 197 | kRegister, |
| 198 | kImmediate |
| 199 | }; |
| 200 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 201 | private: |
| 202 | Type type_; |
| 203 | Register rm_; |
| 204 | Register rs_; |
| 205 | bool is_rotate_; |
| 206 | bool is_shift_; |
| 207 | Shift shift_; |
| 208 | uint32_t rotate_; |
| 209 | uint32_t immed_; |
| 210 | |
Nicolas Geoffray | 3bcc8ea | 2014-11-28 15:00:02 +0000 | [diff] [blame] | 211 | friend class Arm32Assembler; |
| 212 | friend class Thumb2Assembler; |
| 213 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 214 | #ifdef SOURCE_ASSEMBLER_SUPPORT |
| 215 | friend class BinaryAssembler; |
| 216 | #endif |
| 217 | }; |
| 218 | |
| 219 | |
| 220 | enum LoadOperandType { |
| 221 | kLoadSignedByte, |
| 222 | kLoadUnsignedByte, |
| 223 | kLoadSignedHalfword, |
| 224 | kLoadUnsignedHalfword, |
| 225 | kLoadWord, |
| 226 | kLoadWordPair, |
| 227 | kLoadSWord, |
| 228 | kLoadDWord |
| 229 | }; |
| 230 | |
| 231 | |
| 232 | enum StoreOperandType { |
| 233 | kStoreByte, |
| 234 | kStoreHalfword, |
| 235 | kStoreWord, |
| 236 | kStoreWordPair, |
| 237 | kStoreSWord, |
| 238 | kStoreDWord |
| 239 | }; |
| 240 | |
| 241 | |
| 242 | // Load/store multiple addressing mode. |
| 243 | enum BlockAddressMode { |
| 244 | // bit encoding P U W |
| 245 | DA = (0|0|0) << 21, // decrement after |
| 246 | IA = (0|4|0) << 21, // increment after |
| 247 | DB = (8|0|0) << 21, // decrement before |
| 248 | IB = (8|4|0) << 21, // increment before |
| 249 | DA_W = (0|0|1) << 21, // decrement after with writeback to base |
| 250 | IA_W = (0|4|1) << 21, // increment after with writeback to base |
| 251 | DB_W = (8|0|1) << 21, // decrement before with writeback to base |
| 252 | IB_W = (8|4|1) << 21 // increment before with writeback to base |
| 253 | }; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 254 | inline std::ostream& operator<<(std::ostream& os, const BlockAddressMode& rhs) { |
| 255 | os << static_cast<int>(rhs); |
| 256 | return os; |
| 257 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 258 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 259 | class Address : public ValueObject { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 260 | public: |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 261 | // Memory operand addressing mode (in ARM encoding form. For others we need |
| 262 | // to adjust) |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 263 | enum Mode { |
| 264 | // bit encoding P U W |
| 265 | Offset = (8|4|0) << 21, // offset (w/o writeback to base) |
| 266 | PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback |
| 267 | PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback |
| 268 | NegOffset = (8|0|0) << 21, // negative offset (w/o writeback to base) |
| 269 | NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback |
| 270 | NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback |
| 271 | }; |
| 272 | |
Dave Allison | 45fdb93 | 2014-06-25 12:37:10 -0700 | [diff] [blame] | 273 | Address(Register rn, int32_t offset = 0, Mode am = Offset) : rn_(rn), rm_(R0), |
| 274 | offset_(offset), |
| 275 | am_(am), is_immed_offset_(true), shift_(LSL) { |
| 276 | } |
| 277 | |
| 278 | Address(Register rn, Register rm, Mode am = Offset) : rn_(rn), rm_(rm), offset_(0), |
| 279 | am_(am), is_immed_offset_(false), shift_(LSL) { |
| 280 | CHECK_NE(rm, PC); |
| 281 | } |
| 282 | |
| 283 | Address(Register rn, Register rm, Shift shift, uint32_t count, Mode am = Offset) : |
| 284 | rn_(rn), rm_(rm), offset_(count), |
| 285 | am_(am), is_immed_offset_(false), shift_(shift) { |
| 286 | CHECK_NE(rm, PC); |
| 287 | } |
| 288 | |
| 289 | // LDR(literal) - pc relative load. |
| 290 | explicit Address(int32_t offset) : |
| 291 | rn_(PC), rm_(R0), offset_(offset), |
| 292 | am_(Offset), is_immed_offset_(false), shift_(LSL) { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 293 | } |
| 294 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 295 | static bool CanHoldLoadOffsetArm(LoadOperandType type, int offset); |
| 296 | static bool CanHoldStoreOffsetArm(StoreOperandType type, int offset); |
| 297 | |
| 298 | static bool CanHoldLoadOffsetThumb(LoadOperandType type, int offset); |
| 299 | static bool CanHoldStoreOffsetThumb(StoreOperandType type, int offset); |
| 300 | |
| 301 | uint32_t encodingArm() const; |
Dave Allison | 45fdb93 | 2014-06-25 12:37:10 -0700 | [diff] [blame] | 302 | uint32_t encodingThumb(bool is_32bit) const; |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 303 | |
| 304 | uint32_t encoding3() const; |
| 305 | uint32_t vencoding() const; |
| 306 | |
| 307 | uint32_t encodingThumbLdrdStrd() const; |
| 308 | |
| 309 | Register GetRegister() const { |
| 310 | return rn_; |
| 311 | } |
| 312 | |
Dave Allison | 45fdb93 | 2014-06-25 12:37:10 -0700 | [diff] [blame] | 313 | Register GetRegisterOffset() const { |
| 314 | return rm_; |
| 315 | } |
| 316 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 317 | int32_t GetOffset() const { |
| 318 | return offset_; |
| 319 | } |
| 320 | |
| 321 | Mode GetMode() const { |
| 322 | return am_; |
| 323 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 324 | |
Dave Allison | 45fdb93 | 2014-06-25 12:37:10 -0700 | [diff] [blame] | 325 | bool IsImmediate() const { |
| 326 | return is_immed_offset_; |
| 327 | } |
| 328 | |
| 329 | Shift GetShift() const { |
| 330 | return shift_; |
| 331 | } |
| 332 | |
| 333 | int32_t GetShiftCount() const { |
| 334 | CHECK(!is_immed_offset_); |
| 335 | return offset_; |
| 336 | } |
| 337 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 338 | private: |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 339 | const Register rn_; |
| 340 | const Register rm_; |
| 341 | const int32_t offset_; // Used as shift amount for register offset. |
| 342 | const Mode am_; |
| 343 | const bool is_immed_offset_; |
| 344 | const Shift shift_; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 345 | }; |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 346 | inline std::ostream& operator<<(std::ostream& os, const Address::Mode& rhs) { |
| 347 | os << static_cast<int>(rhs); |
| 348 | return os; |
| 349 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 350 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 351 | // Instruction encoding bits. |
| 352 | enum { |
| 353 | H = 1 << 5, // halfword (or byte) |
| 354 | L = 1 << 20, // load (or store) |
| 355 | S = 1 << 20, // set condition code (or leave unchanged) |
| 356 | W = 1 << 21, // writeback base register (or leave unchanged) |
| 357 | A = 1 << 21, // accumulate in multiply instruction (or not) |
| 358 | B = 1 << 22, // unsigned byte (or word) |
| 359 | N = 1 << 22, // long (or short) |
| 360 | U = 1 << 23, // positive (or negative) offset/index |
| 361 | P = 1 << 24, // offset/pre-indexed addressing (or post-indexed addressing) |
| 362 | I = 1 << 25, // immediate shifter operand (or not) |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 363 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 364 | B0 = 1, |
| 365 | B1 = 1 << 1, |
| 366 | B2 = 1 << 2, |
| 367 | B3 = 1 << 3, |
| 368 | B4 = 1 << 4, |
| 369 | B5 = 1 << 5, |
| 370 | B6 = 1 << 6, |
| 371 | B7 = 1 << 7, |
| 372 | B8 = 1 << 8, |
| 373 | B9 = 1 << 9, |
| 374 | B10 = 1 << 10, |
| 375 | B11 = 1 << 11, |
| 376 | B12 = 1 << 12, |
| 377 | B13 = 1 << 13, |
| 378 | B14 = 1 << 14, |
| 379 | B15 = 1 << 15, |
| 380 | B16 = 1 << 16, |
| 381 | B17 = 1 << 17, |
| 382 | B18 = 1 << 18, |
| 383 | B19 = 1 << 19, |
| 384 | B20 = 1 << 20, |
| 385 | B21 = 1 << 21, |
| 386 | B22 = 1 << 22, |
| 387 | B23 = 1 << 23, |
| 388 | B24 = 1 << 24, |
| 389 | B25 = 1 << 25, |
| 390 | B26 = 1 << 26, |
| 391 | B27 = 1 << 27, |
| 392 | B28 = 1 << 28, |
| 393 | B29 = 1 << 29, |
| 394 | B30 = 1 << 30, |
| 395 | B31 = 1 << 31, |
| 396 | |
| 397 | // Instruction bit masks. |
| 398 | RdMask = 15 << 12, // in str instruction |
| 399 | CondMask = 15 << 28, |
| 400 | CoprocessorMask = 15 << 8, |
| 401 | OpCodeMask = 15 << 21, // in data-processing instructions |
| 402 | Imm24Mask = (1 << 24) - 1, |
| 403 | Off12Mask = (1 << 12) - 1, |
| 404 | |
| 405 | // ldrex/strex register field encodings. |
| 406 | kLdExRnShift = 16, |
| 407 | kLdExRtShift = 12, |
| 408 | kStrExRnShift = 16, |
| 409 | kStrExRdShift = 12, |
| 410 | kStrExRtShift = 0, |
| 411 | }; |
| 412 | |
| 413 | // IfThen state for IT instructions. |
| 414 | enum ItState { |
| 415 | kItOmitted, |
| 416 | kItThen, |
| 417 | kItT = kItThen, |
| 418 | kItElse, |
| 419 | kItE = kItElse |
| 420 | }; |
| 421 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 422 | // Set condition codes request. |
| 423 | enum SetCc { |
| 424 | kCcDontCare, // Allows prioritizing 16-bit instructions on Thumb2 whether they set CCs or not. |
| 425 | kCcSet, |
| 426 | kCcKeep, |
| 427 | }; |
| 428 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 429 | constexpr uint32_t kNoItCondition = 3; |
| 430 | constexpr uint32_t kInvalidModifiedImmediate = -1; |
| 431 | |
| 432 | extern const char* kRegisterNames[]; |
| 433 | extern const char* kConditionNames[]; |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 434 | |
| 435 | // This is an abstract ARM assembler. Subclasses provide assemblers for the individual |
| 436 | // instruction sets (ARM32, Thumb2, etc.) |
| 437 | // |
Andreas Gampe | 60b1e1d | 2016-08-08 17:32:34 -0700 | [diff] [blame] | 438 | class ArmAssembler : public Assembler { |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 439 | public: |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 440 | virtual ~ArmAssembler() {} |
buzbee | c143c55 | 2011-08-20 17:38:58 -0700 | [diff] [blame] | 441 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 442 | // Is this assembler for the thumb instruction set? |
| 443 | virtual bool IsThumb() const = 0; |
| 444 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 445 | // Data-processing instructions. |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 446 | virtual void and_(Register rd, Register rn, const ShifterOperand& so, |
| 447 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 448 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 449 | virtual void ands(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 450 | and_(rd, rn, so, cond, kCcSet); |
| 451 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 452 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 453 | virtual void eor(Register rd, Register rn, const ShifterOperand& so, |
| 454 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 455 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 456 | virtual void eors(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 457 | eor(rd, rn, so, cond, kCcSet); |
| 458 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 459 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 460 | virtual void sub(Register rd, Register rn, const ShifterOperand& so, |
| 461 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 462 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 463 | virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 464 | sub(rd, rn, so, cond, kCcSet); |
| 465 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 466 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 467 | virtual void rsb(Register rd, Register rn, const ShifterOperand& so, |
| 468 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 469 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 470 | virtual void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 471 | rsb(rd, rn, so, cond, kCcSet); |
| 472 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 473 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 474 | virtual void add(Register rd, Register rn, const ShifterOperand& so, |
| 475 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 476 | |
| 477 | virtual void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 478 | add(rd, rn, so, cond, kCcSet); |
| 479 | } |
| 480 | |
| 481 | virtual void adc(Register rd, Register rn, const ShifterOperand& so, |
| 482 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 483 | |
| 484 | virtual void adcs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 485 | adc(rd, rn, so, cond, kCcSet); |
| 486 | } |
| 487 | |
| 488 | virtual void sbc(Register rd, Register rn, const ShifterOperand& so, |
| 489 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 490 | |
| 491 | virtual void sbcs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 492 | sbc(rd, rn, so, cond, kCcSet); |
| 493 | } |
| 494 | |
| 495 | virtual void rsc(Register rd, Register rn, const ShifterOperand& so, |
| 496 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 497 | |
| 498 | virtual void rscs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 499 | rsc(rd, rn, so, cond, kCcSet); |
| 500 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 501 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 502 | virtual void tst(Register rn, const ShifterOperand& so, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 503 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 504 | virtual void teq(Register rn, const ShifterOperand& so, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 505 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 506 | virtual void cmp(Register rn, const ShifterOperand& so, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 507 | |
Vladimir Marko | ac6ac10 | 2015-12-17 12:14:00 +0000 | [diff] [blame] | 508 | // Note: CMN updates flags based on addition of its operands. Do not confuse |
| 509 | // the "N" suffix with bitwise inversion performed by MVN. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 510 | virtual void cmn(Register rn, const ShifterOperand& so, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 511 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 512 | virtual void orr(Register rd, Register rn, const ShifterOperand& so, |
| 513 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 514 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 515 | virtual void orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 516 | orr(rd, rn, so, cond, kCcSet); |
| 517 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 518 | |
Vladimir Marko | d2b4ca2 | 2015-09-14 15:13:26 +0100 | [diff] [blame] | 519 | virtual void orn(Register rd, Register rn, const ShifterOperand& so, |
| 520 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 521 | |
| 522 | virtual void orns(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 523 | orn(rd, rn, so, cond, kCcSet); |
| 524 | } |
| 525 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 526 | virtual void mov(Register rd, const ShifterOperand& so, |
| 527 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 528 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 529 | virtual void movs(Register rd, const ShifterOperand& so, Condition cond = AL) { |
| 530 | mov(rd, so, cond, kCcSet); |
| 531 | } |
| 532 | |
| 533 | virtual void bic(Register rd, Register rn, const ShifterOperand& so, |
| 534 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 535 | |
| 536 | virtual void bics(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { |
| 537 | bic(rd, rn, so, cond, kCcSet); |
| 538 | } |
| 539 | |
| 540 | virtual void mvn(Register rd, const ShifterOperand& so, |
| 541 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 542 | |
| 543 | virtual void mvns(Register rd, const ShifterOperand& so, Condition cond = AL) { |
| 544 | mvn(rd, so, cond, kCcSet); |
| 545 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 546 | |
| 547 | // Miscellaneous data-processing instructions. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 548 | virtual void clz(Register rd, Register rm, Condition cond = AL) = 0; |
| 549 | virtual void movw(Register rd, uint16_t imm16, Condition cond = AL) = 0; |
| 550 | virtual void movt(Register rd, uint16_t imm16, Condition cond = AL) = 0; |
Scott Wakeling | 9ee23f4 | 2015-07-23 10:44:35 +0100 | [diff] [blame] | 551 | virtual void rbit(Register rd, Register rm, Condition cond = AL) = 0; |
Artem Serov | c257da7 | 2016-02-02 13:49:43 +0000 | [diff] [blame] | 552 | virtual void rev(Register rd, Register rm, Condition cond = AL) = 0; |
| 553 | virtual void rev16(Register rd, Register rm, Condition cond = AL) = 0; |
| 554 | virtual void revsh(Register rd, Register rm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 555 | |
| 556 | // Multiply instructions. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 557 | virtual void mul(Register rd, Register rn, Register rm, Condition cond = AL) = 0; |
| 558 | virtual void mla(Register rd, Register rn, Register rm, Register ra, |
| 559 | Condition cond = AL) = 0; |
| 560 | virtual void mls(Register rd, Register rn, Register rm, Register ra, |
| 561 | Condition cond = AL) = 0; |
Zheng Xu | c666710 | 2015-05-15 16:08:45 +0800 | [diff] [blame] | 562 | virtual void smull(Register rd_lo, Register rd_hi, Register rn, Register rm, |
| 563 | Condition cond = AL) = 0; |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 564 | virtual void umull(Register rd_lo, Register rd_hi, Register rn, Register rm, |
| 565 | Condition cond = AL) = 0; |
| 566 | |
| 567 | virtual void sdiv(Register rd, Register rn, Register rm, Condition cond = AL) = 0; |
| 568 | virtual void udiv(Register rd, Register rn, Register rm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 569 | |
Roland Levillain | 981e454 | 2014-11-14 11:47:14 +0000 | [diff] [blame] | 570 | // Bit field extract instructions. |
Roland Levillain | 51d3fc4 | 2014-11-13 14:11:42 +0000 | [diff] [blame] | 571 | virtual void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, |
| 572 | Condition cond = AL) = 0; |
Roland Levillain | 981e454 | 2014-11-14 11:47:14 +0000 | [diff] [blame] | 573 | virtual void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, |
| 574 | Condition cond = AL) = 0; |
Roland Levillain | 51d3fc4 | 2014-11-13 14:11:42 +0000 | [diff] [blame] | 575 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 576 | // Load/store instructions. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 577 | virtual void ldr(Register rd, const Address& ad, Condition cond = AL) = 0; |
| 578 | virtual void str(Register rd, const Address& ad, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 579 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 580 | virtual void ldrb(Register rd, const Address& ad, Condition cond = AL) = 0; |
| 581 | virtual void strb(Register rd, const Address& ad, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 582 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 583 | virtual void ldrh(Register rd, const Address& ad, Condition cond = AL) = 0; |
| 584 | virtual void strh(Register rd, const Address& ad, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 585 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 586 | virtual void ldrsb(Register rd, const Address& ad, Condition cond = AL) = 0; |
| 587 | virtual void ldrsh(Register rd, const Address& ad, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 588 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 589 | virtual void ldrd(Register rd, const Address& ad, Condition cond = AL) = 0; |
| 590 | virtual void strd(Register rd, const Address& ad, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 591 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 592 | virtual void ldm(BlockAddressMode am, Register base, |
| 593 | RegList regs, Condition cond = AL) = 0; |
| 594 | virtual void stm(BlockAddressMode am, Register base, |
| 595 | RegList regs, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 596 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 597 | virtual void ldrex(Register rd, Register rn, Condition cond = AL) = 0; |
| 598 | virtual void strex(Register rd, Register rt, Register rn, Condition cond = AL) = 0; |
Calin Juravle | 52c4896 | 2014-12-16 17:02:57 +0000 | [diff] [blame] | 599 | virtual void ldrexd(Register rt, Register rt2, Register rn, Condition cond = AL) = 0; |
| 600 | virtual void strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 601 | |
| 602 | // Miscellaneous instructions. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 603 | virtual void clrex(Condition cond = AL) = 0; |
| 604 | virtual void nop(Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 605 | |
| 606 | // Note that gdb sets breakpoints using the undefined instruction 0xe7f001f0. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 607 | virtual void bkpt(uint16_t imm16) = 0; |
| 608 | virtual void svc(uint32_t imm24) = 0; |
| 609 | |
Ian Rogers | 6a3c1fc | 2014-10-31 00:33:20 -0700 | [diff] [blame] | 610 | virtual void it(Condition firstcond ATTRIBUTE_UNUSED, |
| 611 | ItState i1 ATTRIBUTE_UNUSED = kItOmitted, |
| 612 | ItState i2 ATTRIBUTE_UNUSED = kItOmitted, |
| 613 | ItState i3 ATTRIBUTE_UNUSED = kItOmitted) { |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 614 | // Ignored if not supported. |
| 615 | } |
| 616 | |
| 617 | virtual void cbz(Register rn, Label* target) = 0; |
| 618 | virtual void cbnz(Register rn, Label* target) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 619 | |
| 620 | // Floating point instructions (VFPv3-D16 and VFPv3-D32 profiles). |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 621 | virtual void vmovsr(SRegister sn, Register rt, Condition cond = AL) = 0; |
| 622 | virtual void vmovrs(Register rt, SRegister sn, Condition cond = AL) = 0; |
| 623 | virtual void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) = 0; |
| 624 | virtual void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) = 0; |
| 625 | virtual void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) = 0; |
| 626 | virtual void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) = 0; |
| 627 | virtual void vmovs(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 628 | virtual void vmovd(DRegister dd, DRegister dm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 629 | |
| 630 | // Returns false if the immediate cannot be encoded. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 631 | virtual bool vmovs(SRegister sd, float s_imm, Condition cond = AL) = 0; |
| 632 | virtual bool vmovd(DRegister dd, double d_imm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 633 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 634 | virtual void vldrs(SRegister sd, const Address& ad, Condition cond = AL) = 0; |
| 635 | virtual void vstrs(SRegister sd, const Address& ad, Condition cond = AL) = 0; |
| 636 | virtual void vldrd(DRegister dd, const Address& ad, Condition cond = AL) = 0; |
| 637 | virtual void vstrd(DRegister dd, const Address& ad, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 638 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 639 | virtual void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) = 0; |
| 640 | virtual void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0; |
| 641 | virtual void vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) = 0; |
| 642 | virtual void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0; |
| 643 | virtual void vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) = 0; |
| 644 | virtual void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0; |
| 645 | virtual void vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) = 0; |
| 646 | virtual void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0; |
| 647 | virtual void vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) = 0; |
| 648 | virtual void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0; |
| 649 | virtual void vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) = 0; |
| 650 | virtual void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 651 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 652 | virtual void vabss(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 653 | virtual void vabsd(DRegister dd, DRegister dm, Condition cond = AL) = 0; |
| 654 | virtual void vnegs(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 655 | virtual void vnegd(DRegister dd, DRegister dm, Condition cond = AL) = 0; |
| 656 | virtual void vsqrts(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 657 | virtual void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 658 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 659 | virtual void vcvtsd(SRegister sd, DRegister dm, Condition cond = AL) = 0; |
| 660 | virtual void vcvtds(DRegister dd, SRegister sm, Condition cond = AL) = 0; |
| 661 | virtual void vcvtis(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 662 | virtual void vcvtid(SRegister sd, DRegister dm, Condition cond = AL) = 0; |
| 663 | virtual void vcvtsi(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 664 | virtual void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL) = 0; |
| 665 | virtual void vcvtus(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 666 | virtual void vcvtud(SRegister sd, DRegister dm, Condition cond = AL) = 0; |
| 667 | virtual void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 668 | virtual void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 669 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 670 | virtual void vcmps(SRegister sd, SRegister sm, Condition cond = AL) = 0; |
| 671 | virtual void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) = 0; |
| 672 | virtual void vcmpsz(SRegister sd, Condition cond = AL) = 0; |
| 673 | virtual void vcmpdz(DRegister dd, Condition cond = AL) = 0; |
| 674 | virtual void vmstat(Condition cond = AL) = 0; // VMRS APSR_nzcv, FPSCR |
| 675 | |
xueliang.zhong | e652c12 | 2016-06-13 14:42:27 +0100 | [diff] [blame] | 676 | virtual void vcntd(DRegister dd, DRegister dm) = 0; |
| 677 | virtual void vpaddld(DRegister dd, DRegister dm, int32_t size, bool is_unsigned) = 0; |
| 678 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 679 | virtual void vpushs(SRegister reg, int nregs, Condition cond = AL) = 0; |
| 680 | virtual void vpushd(DRegister reg, int nregs, Condition cond = AL) = 0; |
| 681 | virtual void vpops(SRegister reg, int nregs, Condition cond = AL) = 0; |
| 682 | virtual void vpopd(DRegister reg, int nregs, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 683 | |
| 684 | // Branch instructions. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 685 | virtual void b(Label* label, Condition cond = AL) = 0; |
| 686 | virtual void bl(Label* label, Condition cond = AL) = 0; |
| 687 | virtual void blx(Register rm, Condition cond = AL) = 0; |
| 688 | virtual void bx(Register rm, Condition cond = AL) = 0; |
| 689 | |
Nicolas Geoffray | 19a19cf | 2014-10-22 16:07:05 +0100 | [diff] [blame] | 690 | // Memory barriers. |
| 691 | virtual void dmb(DmbOptions flavor) = 0; |
| 692 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 693 | void Pad(uint32_t bytes); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 694 | |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 695 | // Adjust label position. |
| 696 | void AdjustLabelPosition(Label* label) { |
| 697 | DCHECK(label->IsBound()); |
| 698 | uint32_t old_position = static_cast<uint32_t>(label->Position()); |
| 699 | uint32_t new_position = GetAdjustedPosition(old_position); |
| 700 | label->Reinitialize(); |
| 701 | DCHECK_GE(static_cast<int>(new_position), 0); |
| 702 | label->BindTo(static_cast<int>(new_position)); |
| 703 | } |
| 704 | |
| 705 | // Get the final position of a label after local fixup based on the old position |
| 706 | // recorded before FinalizeCode(). |
| 707 | virtual uint32_t GetAdjustedPosition(uint32_t old_position) = 0; |
| 708 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 709 | // Macros. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 710 | // Most of these are pure virtual as they need to be implemented per instruction set. |
| 711 | |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 712 | // Create a new literal with a given value. |
Vladimir Marko | 88b2b80 | 2015-12-04 14:19:04 +0000 | [diff] [blame] | 713 | // NOTE: Force the template parameter to be explicitly specified. |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 714 | template <typename T> |
Vladimir Marko | 88b2b80 | 2015-12-04 14:19:04 +0000 | [diff] [blame] | 715 | Literal* NewLiteral(typename Identity<T>::type value) { |
Vladimir Marko | cf93a5c | 2015-06-16 11:33:24 +0000 | [diff] [blame] | 716 | static_assert(std::is_integral<T>::value, "T must be an integral type."); |
| 717 | return NewLiteral(sizeof(value), reinterpret_cast<const uint8_t*>(&value)); |
| 718 | } |
| 719 | |
| 720 | // Create a new literal with the given data. |
| 721 | virtual Literal* NewLiteral(size_t size, const uint8_t* data) = 0; |
| 722 | |
| 723 | // Load literal. |
| 724 | virtual void LoadLiteral(Register rt, Literal* literal) = 0; |
| 725 | virtual void LoadLiteral(Register rt, Register rt2, Literal* literal) = 0; |
| 726 | virtual void LoadLiteral(SRegister sd, Literal* literal) = 0; |
| 727 | virtual void LoadLiteral(DRegister dd, Literal* literal) = 0; |
| 728 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 729 | // Add signed constant value to rd. May clobber IP. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 730 | virtual void AddConstant(Register rd, Register rn, int32_t value, |
Vladimir Marko | 449b109 | 2015-09-08 12:16:45 +0100 | [diff] [blame] | 731 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 732 | void AddConstantSetFlags(Register rd, Register rn, int32_t value, Condition cond = AL) { |
| 733 | AddConstant(rd, rn, value, cond, kCcSet); |
| 734 | } |
| 735 | void AddConstant(Register rd, int32_t value, Condition cond = AL, SetCc set_cc = kCcDontCare) { |
| 736 | AddConstant(rd, rd, value, cond, set_cc); |
| 737 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 738 | |
Andreas Gampe | 7cffc3b | 2015-10-19 21:31:53 -0700 | [diff] [blame] | 739 | virtual void CmpConstant(Register rn, int32_t value, Condition cond = AL) = 0; |
| 740 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 741 | // Load and Store. May clobber IP. |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 742 | virtual void LoadImmediate(Register rd, int32_t value, Condition cond = AL) = 0; |
Nicolas Geoffray | 840e546 | 2015-01-07 16:01:24 +0000 | [diff] [blame] | 743 | void LoadSImmediate(SRegister sd, float value, Condition cond = AL) { |
| 744 | if (!vmovs(sd, value, cond)) { |
Nicolas Geoffray | ffe8a57 | 2015-02-11 01:10:39 +0000 | [diff] [blame] | 745 | int32_t int_value = bit_cast<int32_t, float>(value); |
| 746 | if (int_value == bit_cast<int32_t, float>(0.0f)) { |
| 747 | // 0.0 is quite common, so we special case it by loading |
| 748 | // 2.0 in `sd` and then substracting it. |
| 749 | bool success = vmovs(sd, 2.0, cond); |
| 750 | CHECK(success); |
| 751 | vsubs(sd, sd, sd, cond); |
| 752 | } else { |
| 753 | LoadImmediate(IP, int_value, cond); |
| 754 | vmovsr(sd, IP, cond); |
| 755 | } |
Nicolas Geoffray | 840e546 | 2015-01-07 16:01:24 +0000 | [diff] [blame] | 756 | } |
| 757 | } |
| 758 | |
Vladimir Marko | ebdbf4b | 2016-07-07 15:37:02 +0100 | [diff] [blame] | 759 | virtual void LoadDImmediate(DRegister dd, double value, Condition cond = AL) = 0; |
Nicolas Geoffray | f7a0c4e | 2015-02-10 17:08:47 +0000 | [diff] [blame] | 760 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 761 | virtual void MarkExceptionHandler(Label* label) = 0; |
| 762 | virtual void LoadFromOffset(LoadOperandType type, |
| 763 | Register reg, |
| 764 | Register base, |
| 765 | int32_t offset, |
| 766 | Condition cond = AL) = 0; |
| 767 | virtual void StoreToOffset(StoreOperandType type, |
| 768 | Register reg, |
| 769 | Register base, |
| 770 | int32_t offset, |
| 771 | Condition cond = AL) = 0; |
| 772 | virtual void LoadSFromOffset(SRegister reg, |
| 773 | Register base, |
| 774 | int32_t offset, |
| 775 | Condition cond = AL) = 0; |
| 776 | virtual void StoreSToOffset(SRegister reg, |
| 777 | Register base, |
| 778 | int32_t offset, |
| 779 | Condition cond = AL) = 0; |
| 780 | virtual void LoadDFromOffset(DRegister reg, |
| 781 | Register base, |
| 782 | int32_t offset, |
| 783 | Condition cond = AL) = 0; |
| 784 | virtual void StoreDToOffset(DRegister reg, |
| 785 | Register base, |
| 786 | int32_t offset, |
| 787 | Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 788 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 789 | virtual void Push(Register rd, Condition cond = AL) = 0; |
| 790 | virtual void Pop(Register rd, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 791 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 792 | virtual void PushList(RegList regs, Condition cond = AL) = 0; |
| 793 | virtual void PopList(RegList regs, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 794 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 795 | virtual void Mov(Register rd, Register rm, Condition cond = AL) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 796 | |
| 797 | // Convenience shift instructions. Use mov instruction with shifter operand |
| 798 | // for variants setting the status flags or using a register shift count. |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 799 | virtual void Lsl(Register rd, Register rm, uint32_t shift_imm, |
| 800 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
Dave Allison | 45fdb93 | 2014-06-25 12:37:10 -0700 | [diff] [blame] | 801 | |
Vladimir Marko | 73cf0fb | 2015-07-30 15:07:22 +0100 | [diff] [blame] | 802 | void Lsls(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) { |
| 803 | Lsl(rd, rm, shift_imm, cond, kCcSet); |
| 804 | } |
| 805 | |
| 806 | virtual void Lsr(Register rd, Register rm, uint32_t shift_imm, |
| 807 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 808 | |
| 809 | void Lsrs(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) { |
| 810 | Lsr(rd, rm, shift_imm, cond, kCcSet); |
| 811 | } |
| 812 | |
| 813 | virtual void Asr(Register rd, Register rm, uint32_t shift_imm, |
| 814 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 815 | |
| 816 | void Asrs(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) { |
| 817 | Asr(rd, rm, shift_imm, cond, kCcSet); |
| 818 | } |
| 819 | |
| 820 | virtual void Ror(Register rd, Register rm, uint32_t shift_imm, |
| 821 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 822 | |
| 823 | void Rors(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL) { |
| 824 | Ror(rd, rm, shift_imm, cond, kCcSet); |
| 825 | } |
| 826 | |
| 827 | virtual void Rrx(Register rd, Register rm, |
| 828 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 829 | |
| 830 | void Rrxs(Register rd, Register rm, Condition cond = AL) { |
| 831 | Rrx(rd, rm, cond, kCcSet); |
| 832 | } |
| 833 | |
| 834 | virtual void Lsl(Register rd, Register rm, Register rn, |
| 835 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 836 | |
| 837 | void Lsls(Register rd, Register rm, Register rn, Condition cond = AL) { |
| 838 | Lsl(rd, rm, rn, cond, kCcSet); |
| 839 | } |
| 840 | |
| 841 | virtual void Lsr(Register rd, Register rm, Register rn, |
| 842 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 843 | |
| 844 | void Lsrs(Register rd, Register rm, Register rn, Condition cond = AL) { |
| 845 | Lsr(rd, rm, rn, cond, kCcSet); |
| 846 | } |
| 847 | |
| 848 | virtual void Asr(Register rd, Register rm, Register rn, |
| 849 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 850 | |
| 851 | void Asrs(Register rd, Register rm, Register rn, Condition cond = AL) { |
| 852 | Asr(rd, rm, rn, cond, kCcSet); |
| 853 | } |
| 854 | |
| 855 | virtual void Ror(Register rd, Register rm, Register rn, |
| 856 | Condition cond = AL, SetCc set_cc = kCcDontCare) = 0; |
| 857 | |
| 858 | void Rors(Register rd, Register rm, Register rn, Condition cond = AL) { |
| 859 | Ror(rd, rm, rn, cond, kCcSet); |
| 860 | } |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 861 | |
Nicolas Geoffray | 3bcc8ea | 2014-11-28 15:00:02 +0000 | [diff] [blame] | 862 | // Returns whether the `immediate` can fit in a `ShifterOperand`. If yes, |
| 863 | // `shifter_op` contains the operand. |
| 864 | virtual bool ShifterOperandCanHold(Register rd, |
| 865 | Register rn, |
| 866 | Opcode opcode, |
| 867 | uint32_t immediate, |
Vladimir Marko | f5c09c3 | 2015-12-17 12:08:08 +0000 | [diff] [blame] | 868 | SetCc set_cc, |
Nicolas Geoffray | 3bcc8ea | 2014-11-28 15:00:02 +0000 | [diff] [blame] | 869 | ShifterOperand* shifter_op) = 0; |
Vladimir Marko | f5c09c3 | 2015-12-17 12:08:08 +0000 | [diff] [blame] | 870 | bool ShifterOperandCanHold(Register rd, |
| 871 | Register rn, |
| 872 | Opcode opcode, |
| 873 | uint32_t immediate, |
| 874 | ShifterOperand* shifter_op) { |
| 875 | return ShifterOperandCanHold(rd, rn, opcode, immediate, kCcDontCare, shifter_op); |
| 876 | } |
Nicolas Geoffray | 3bcc8ea | 2014-11-28 15:00:02 +0000 | [diff] [blame] | 877 | |
Nicolas Geoffray | 0ccb383 | 2015-10-14 11:44:23 +0100 | [diff] [blame] | 878 | virtual bool ShifterOperandCanAlwaysHold(uint32_t immediate) = 0; |
Nicolas Geoffray | 5bd05a5 | 2015-10-13 09:48:30 +0100 | [diff] [blame] | 879 | |
Ian Rogers | 1373595 | 2014-10-08 12:43:28 -0700 | [diff] [blame] | 880 | static bool IsInstructionForExceptionHandling(uintptr_t pc); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 881 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 882 | virtual void CompareAndBranchIfZero(Register r, Label* label) = 0; |
| 883 | virtual void CompareAndBranchIfNonZero(Register r, Label* label) = 0; |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 884 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 885 | static uint32_t ModifiedImmediate(uint32_t value); |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 886 | |
Dave Allison | 45fdb93 | 2014-06-25 12:37:10 -0700 | [diff] [blame] | 887 | static bool IsLowRegister(Register r) { |
| 888 | return r < R8; |
| 889 | } |
| 890 | |
| 891 | static bool IsHighRegister(Register r) { |
| 892 | return r >= R8; |
| 893 | } |
| 894 | |
Roland Levillain | 4d02711 | 2015-07-01 15:41:14 +0100 | [diff] [blame] | 895 | // |
| 896 | // Heap poisoning. |
| 897 | // |
| 898 | |
| 899 | // Poison a heap reference contained in `reg`. |
| 900 | void PoisonHeapReference(Register reg) { |
| 901 | // reg = -reg. |
| 902 | rsb(reg, reg, ShifterOperand(0)); |
| 903 | } |
| 904 | // Unpoison a heap reference contained in `reg`. |
| 905 | void UnpoisonHeapReference(Register reg) { |
| 906 | // reg = -reg. |
| 907 | rsb(reg, reg, ShifterOperand(0)); |
| 908 | } |
| 909 | // Unpoison a heap reference contained in `reg` if heap poisoning is enabled. |
| 910 | void MaybeUnpoisonHeapReference(Register reg) { |
| 911 | if (kPoisonHeapReferences) { |
| 912 | UnpoisonHeapReference(reg); |
| 913 | } |
| 914 | } |
| 915 | |
Andreas Gampe | 85b62f2 | 2015-09-09 13:15:38 -0700 | [diff] [blame] | 916 | void Jump(Label* label) OVERRIDE { |
| 917 | b(label); |
| 918 | } |
| 919 | |
Andreas Gampe | 7cffc3b | 2015-10-19 21:31:53 -0700 | [diff] [blame] | 920 | // Jump table support. This is split into three functions: |
| 921 | // |
| 922 | // * CreateJumpTable creates the internal metadata to track the jump targets, and emits code to |
| 923 | // load the base address of the jump table. |
| 924 | // |
| 925 | // * EmitJumpTableDispatch emits the code to actually jump, assuming that the right table value |
| 926 | // has been loaded into a register already. |
| 927 | // |
| 928 | // * FinalizeTables emits the jump table into the literal pool. This can only be called after the |
| 929 | // labels for the jump targets have been finalized. |
| 930 | |
| 931 | // Create a jump table for the given labels that will be emitted when finalizing. Create a load |
| 932 | // sequence (or placeholder) that stores the base address into the given register. When the table |
| 933 | // is emitted, offsets will be relative to the location EmitJumpTableDispatch was called on (the |
| 934 | // anchor). |
| 935 | virtual JumpTable* CreateJumpTable(std::vector<Label*>&& labels, Register base_reg) = 0; |
| 936 | |
| 937 | // Emit the jump-table jump, assuming that the right value was loaded into displacement_reg. |
| 938 | virtual void EmitJumpTableDispatch(JumpTable* jump_table, Register displacement_reg) = 0; |
| 939 | |
| 940 | // Bind a Label that needs to be updated by the assembler in FinalizeCode() if its position |
| 941 | // changes due to branch/literal fixup. |
| 942 | void BindTrackedLabel(Label* label) { |
| 943 | Bind(label); |
| 944 | tracked_labels_.push_back(label); |
| 945 | } |
| 946 | |
Dave Allison | 65fcc2c | 2014-04-28 13:45:27 -0700 | [diff] [blame] | 947 | protected: |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 948 | explicit ArmAssembler(ArenaAllocator* arena) |
| 949 | : Assembler(arena), tracked_labels_(arena->Adapter(kArenaAllocAssembler)) {} |
| 950 | |
Carl Shapiro | a2e18e1 | 2011-06-21 18:57:55 -0700 | [diff] [blame] | 951 | // Returns whether or not the given register is used for passing parameters. |
| 952 | static int RegisterCompare(const Register* reg1, const Register* reg2) { |
| 953 | return *reg1 - *reg2; |
| 954 | } |
Andreas Gampe | 7cffc3b | 2015-10-19 21:31:53 -0700 | [diff] [blame] | 955 | |
| 956 | void FinalizeTrackedLabels(); |
| 957 | |
| 958 | // Tracked labels. Use a vector, as we need to sort before adjusting. |
Vladimir Marko | 93205e3 | 2016-04-13 11:59:46 +0100 | [diff] [blame] | 959 | ArenaVector<Label*> tracked_labels_; |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 960 | }; |
| 961 | |
Ian Rogers | 2c8f653 | 2011-09-02 17:16:34 -0700 | [diff] [blame] | 962 | } // namespace arm |
Ian Rogers | b033c75 | 2011-07-20 12:22:35 -0700 | [diff] [blame] | 963 | } // namespace art |
Carl Shapiro | a5d5cfd | 2011-06-21 12:46:59 -0700 | [diff] [blame] | 964 | |
Ian Rogers | 166db04 | 2013-07-26 12:05:57 -0700 | [diff] [blame] | 965 | #endif // ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_H_ |