Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | /* This file contains codegen for the Thumb2 ISA. */ |
| 18 | |
| 19 | #include "arm64_lir.h" |
| 20 | #include "codegen_arm64.h" |
| 21 | #include "dex/quick/mir_to_lir-inl.h" |
| 22 | #include "entrypoints/quick/quick_entrypoints.h" |
| 23 | |
| 24 | namespace art { |
| 25 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 26 | bool Arm64Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, |
| 27 | const InlineMethod& special) { |
| 28 | return Mir2Lir::GenSpecialCase(bb, mir, special); |
| 29 | } |
| 30 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 31 | /* |
| 32 | * The sparse table in the literal pool is an array of <key,displacement> |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 33 | * pairs. For each set, we'll load them as a pair using ldp. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 34 | * The test loop will look something like: |
| 35 | * |
| 36 | * adr r_base, <table> |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 37 | * ldr r_val, [rA64_SP, v_reg_off] |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 38 | * mov r_idx, #table_size |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 39 | * loop: |
| 40 | * cbz r_idx, quit |
| 41 | * ldp r_key, r_disp, [r_base], #8 |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 42 | * sub r_idx, #1 |
| 43 | * cmp r_val, r_key |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 44 | * b.ne loop |
| 45 | * adr r_base, #0 ; This is the instruction from which we compute displacements |
| 46 | * add r_base, r_disp |
| 47 | * br r_base |
| 48 | * quit: |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 49 | */ |
| 50 | void Arm64Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset, |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 51 | RegLocation rl_src) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 52 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 53 | if (cu_->verbose) { |
| 54 | DumpSparseSwitchTable(table); |
| 55 | } |
| 56 | // Add the table to the list - we'll process it later |
| 57 | SwitchTable *tab_rec = |
| 58 | static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), kArenaAllocData)); |
| 59 | tab_rec->table = table; |
| 60 | tab_rec->vaddr = current_dalvik_offset_; |
| 61 | uint32_t size = table[1]; |
| 62 | tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), kArenaAllocLIR)); |
| 63 | switch_tables_.Insert(tab_rec); |
| 64 | |
| 65 | // Get the switch value |
| 66 | rl_src = LoadValue(rl_src, kCoreReg); |
| 67 | RegStorage r_base = AllocTemp(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 68 | // Allocate key and disp temps. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 69 | RegStorage r_key = AllocTemp(); |
| 70 | RegStorage r_disp = AllocTemp(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 71 | // Materialize a pointer to the switch table |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 72 | NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, WrapPointer(tab_rec)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 73 | // Set up r_idx |
| 74 | RegStorage r_idx = AllocTemp(); |
| 75 | LoadConstant(r_idx, size); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 76 | |
| 77 | // Entry of loop. |
| 78 | LIR* loop_entry = NewLIR0(kPseudoTargetLabel); |
| 79 | LIR* branch_out = NewLIR2(kA64Cbz2rt, r_idx.GetReg(), 0); |
| 80 | |
| 81 | // Load next key/disp. |
| 82 | NewLIR4(kA64LdpPost4rrXD, r_key.GetReg(), r_disp.GetReg(), r_base.GetReg(), 2); |
| 83 | OpRegRegImm(kOpSub, r_idx, r_idx, 1); |
| 84 | |
| 85 | // Go to next case, if key does not match. |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 86 | OpRegReg(kOpCmp, r_key, rl_src.reg); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 87 | OpCondBranch(kCondNe, loop_entry); |
| 88 | |
| 89 | // Key does match: branch to case label. |
| 90 | LIR* switch_label = NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, -1); |
| 91 | tab_rec->anchor = switch_label; |
| 92 | |
| 93 | // Add displacement to base branch address and go! |
| 94 | OpRegRegRegShift(kOpAdd, r_base.GetReg(), r_base.GetReg(), r_disp.GetReg(), |
| 95 | ENCODE_NO_SHIFT, true); |
| 96 | NewLIR1(kA64Br1x, r_base.GetReg()); |
| 97 | |
| 98 | // Loop exit label. |
| 99 | LIR* loop_exit = NewLIR0(kPseudoTargetLabel); |
| 100 | branch_out->target = loop_exit; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | |
| 104 | void Arm64Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset, |
| 105 | RegLocation rl_src) { |
| 106 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 107 | if (cu_->verbose) { |
| 108 | DumpPackedSwitchTable(table); |
| 109 | } |
| 110 | // Add the table to the list - we'll process it later |
| 111 | SwitchTable *tab_rec = |
| 112 | static_cast<SwitchTable*>(arena_->Alloc(sizeof(SwitchTable), kArenaAllocData)); |
| 113 | tab_rec->table = table; |
| 114 | tab_rec->vaddr = current_dalvik_offset_; |
| 115 | uint32_t size = table[1]; |
| 116 | tab_rec->targets = |
| 117 | static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), kArenaAllocLIR)); |
| 118 | switch_tables_.Insert(tab_rec); |
| 119 | |
| 120 | // Get the switch value |
| 121 | rl_src = LoadValue(rl_src, kCoreReg); |
| 122 | RegStorage table_base = AllocTemp(); |
| 123 | // Materialize a pointer to the switch table |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 124 | NewLIR3(kA64Adr2xd, table_base.GetReg(), 0, WrapPointer(tab_rec)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 125 | int low_key = s4FromSwitchData(&table[2]); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 126 | RegStorage key_reg; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 127 | // Remove the bias, if necessary |
| 128 | if (low_key == 0) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 129 | key_reg = rl_src.reg; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 130 | } else { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 131 | key_reg = AllocTemp(); |
| 132 | OpRegRegImm(kOpSub, key_reg, rl_src.reg, low_key); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 133 | } |
| 134 | // Bounds check - if < 0 or >= size continue following switch |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 135 | OpRegImm(kOpCmp, key_reg, size - 1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 136 | LIR* branch_over = OpCondBranch(kCondHi, NULL); |
| 137 | |
| 138 | // Load the displacement from the switch table |
| 139 | RegStorage disp_reg = AllocTemp(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 140 | LoadBaseIndexed(table_base, key_reg, disp_reg, 2, k32); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 141 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 142 | // Get base branch address. |
| 143 | RegStorage branch_reg = AllocTemp(); |
| 144 | LIR* switch_label = NewLIR3(kA64Adr2xd, branch_reg.GetReg(), 0, -1); |
| 145 | tab_rec->anchor = switch_label; |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 146 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 147 | // Add displacement to base branch address and go! |
| 148 | OpRegRegRegShift(kOpAdd, branch_reg.GetReg(), branch_reg.GetReg(), disp_reg.GetReg(), |
| 149 | ENCODE_NO_SHIFT, true); |
| 150 | NewLIR1(kA64Br1x, branch_reg.GetReg()); |
| 151 | |
| 152 | // branch_over target here |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 153 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 154 | branch_over->target = target; |
| 155 | } |
| 156 | |
| 157 | /* |
| 158 | * Array data table format: |
| 159 | * ushort ident = 0x0300 magic value |
| 160 | * ushort width width of each element in the table |
| 161 | * uint size number of elements in the table |
| 162 | * ubyte data[size*width] table of data values (may contain a single-byte |
| 163 | * padding at the end) |
| 164 | * |
| 165 | * Total size is 4+(width * size + 1)/2 16-bit code units. |
| 166 | */ |
| 167 | void Arm64Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) { |
| 168 | const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; |
| 169 | // Add the table to the list - we'll process it later |
| 170 | FillArrayData *tab_rec = |
| 171 | static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), kArenaAllocData)); |
| 172 | tab_rec->table = table; |
| 173 | tab_rec->vaddr = current_dalvik_offset_; |
| 174 | uint16_t width = tab_rec->table[1]; |
| 175 | uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); |
| 176 | tab_rec->size = (size * width) + 8; |
| 177 | |
| 178 | fill_array_data_.Insert(tab_rec); |
| 179 | |
| 180 | // Making a call - use explicit registers |
| 181 | FlushAllRegs(); /* Everything to home location */ |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 182 | LoadValueDirectFixed(rl_src, rs_x0); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 183 | LoadWordDisp(rs_rA64_SELF, QUICK_ENTRYPOINT_OFFSET(8, pHandleFillArrayData).Int32Value(), |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 184 | rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 185 | // Materialize a pointer to the fill data image |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 186 | NewLIR3(kA64Adr2xd, rx1, 0, WrapPointer(tab_rec)); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 187 | ClobberCallerSave(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 188 | LIR* call_inst = OpReg(kOpBlx, rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 189 | MarkSafepointPC(call_inst); |
| 190 | } |
| 191 | |
| 192 | /* |
| 193 | * Handle unlocked -> thin locked transition inline or else call out to quick entrypoint. For more |
| 194 | * details see monitor.cc. |
| 195 | */ |
| 196 | void Arm64Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { |
| 197 | FlushAllRegs(); |
| 198 | // FIXME: need separate LoadValues for object references. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 199 | LoadValueDirectFixed(rl_src, rs_x0); // Get obj |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 200 | LockCallTemps(); // Prepare for explicit register usage |
| 201 | constexpr bool kArchVariantHasGoodBranchPredictor = false; // TODO: true if cortex-A15. |
| 202 | if (kArchVariantHasGoodBranchPredictor) { |
| 203 | LIR* null_check_branch = nullptr; |
| 204 | if ((opt_flags & MIR_IGNORE_NULL_CHECK) && !(cu_->disable_opt & (1 << kNullCheckElimination))) { |
| 205 | null_check_branch = nullptr; // No null check. |
| 206 | } else { |
| 207 | // If the null-check fails its handled by the slow-path to reduce exception related meta-data. |
| 208 | if (Runtime::Current()->ExplicitNullChecks()) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 209 | null_check_branch = OpCmpImmBranch(kCondEq, rs_x0, 0, NULL); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 210 | } |
| 211 | } |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 212 | Load32Disp(rs_rA64_SELF, Thread::ThinLockIdOffset<8>().Int32Value(), rs_x2); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 213 | NewLIR3(kA64Ldxr2rX, rx1, rx0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 214 | MarkPossibleNullPointerException(opt_flags); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 215 | LIR* not_unlocked_branch = OpCmpImmBranch(kCondNe, rs_x1, 0, NULL); |
| 216 | NewLIR4(kA64Stxr3wrX, rx1, rx2, rx0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 217 | LIR* lock_success_branch = OpCmpImmBranch(kCondEq, rs_x1, 0, NULL); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 218 | |
| 219 | |
| 220 | LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); |
| 221 | not_unlocked_branch->target = slow_path_target; |
| 222 | if (null_check_branch != nullptr) { |
| 223 | null_check_branch->target = slow_path_target; |
| 224 | } |
| 225 | // TODO: move to a slow path. |
| 226 | // Go expensive route - artLockObjectFromCode(obj); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 227 | LoadWordDisp(rs_rA64_SELF, QUICK_ENTRYPOINT_OFFSET(8, pLockObject).Int32Value(), rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 228 | ClobberCallerSave(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 229 | LIR* call_inst = OpReg(kOpBlx, rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 230 | MarkSafepointPC(call_inst); |
| 231 | |
| 232 | LIR* success_target = NewLIR0(kPseudoTargetLabel); |
| 233 | lock_success_branch->target = success_target; |
| 234 | GenMemBarrier(kLoadLoad); |
| 235 | } else { |
| 236 | // Explicit null-check as slow-path is entered using an IT. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 237 | GenNullCheck(rs_x0, opt_flags); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 238 | Load32Disp(rs_rA64_SELF, Thread::ThinLockIdOffset<8>().Int32Value(), rs_x2); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 239 | MarkPossibleNullPointerException(opt_flags); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 240 | NewLIR3(kA64Ldxr2rX, rx1, rx0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 241 | OpRegImm(kOpCmp, rs_x1, 0); |
| 242 | OpIT(kCondEq, ""); |
| 243 | NewLIR4(kA64Stxr3wrX/*eq*/, rx1, rx2, rx0, mirror::Object::MonitorOffset().Int32Value() >> 2); |
| 244 | OpRegImm(kOpCmp, rs_x1, 0); |
| 245 | OpIT(kCondNe, "T"); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 246 | // Go expensive route - artLockObjectFromCode(self, obj); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 247 | LoadWordDisp/*ne*/(rs_rA64_SELF, QUICK_ENTRYPOINT_OFFSET(8, pLockObject).Int32Value(), |
| 248 | rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 249 | ClobberCallerSave(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 250 | LIR* call_inst = OpReg(kOpBlx/*ne*/, rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 251 | MarkSafepointPC(call_inst); |
| 252 | GenMemBarrier(kLoadLoad); |
| 253 | } |
| 254 | } |
| 255 | |
| 256 | /* |
| 257 | * Handle thin locked -> unlocked transition inline or else call out to quick entrypoint. For more |
| 258 | * details see monitor.cc. Note the code below doesn't use ldrex/strex as the code holds the lock |
| 259 | * and can only give away ownership if its suspended. |
| 260 | */ |
| 261 | void Arm64Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { |
| 262 | FlushAllRegs(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 263 | LoadValueDirectFixed(rl_src, rs_x0); // Get obj |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 264 | LockCallTemps(); // Prepare for explicit register usage |
| 265 | LIR* null_check_branch = nullptr; |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 266 | Load32Disp(rs_rA64_SELF, Thread::ThinLockIdOffset<8>().Int32Value(), rs_x2); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 267 | constexpr bool kArchVariantHasGoodBranchPredictor = false; // TODO: true if cortex-A15. |
| 268 | if (kArchVariantHasGoodBranchPredictor) { |
| 269 | if ((opt_flags & MIR_IGNORE_NULL_CHECK) && !(cu_->disable_opt & (1 << kNullCheckElimination))) { |
| 270 | null_check_branch = nullptr; // No null check. |
| 271 | } else { |
| 272 | // If the null-check fails its handled by the slow-path to reduce exception related meta-data. |
| 273 | if (Runtime::Current()->ExplicitNullChecks()) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 274 | null_check_branch = OpCmpImmBranch(kCondEq, rs_x0, 0, NULL); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 275 | } |
| 276 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 277 | Load32Disp(rs_x0, mirror::Object::MonitorOffset().Int32Value(), rs_x1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 278 | MarkPossibleNullPointerException(opt_flags); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 279 | LoadConstantNoClobber(rs_x3, 0); |
| 280 | LIR* slow_unlock_branch = OpCmpBranch(kCondNe, rs_x1, rs_x2, NULL); |
| 281 | Store32Disp(rs_x0, mirror::Object::MonitorOffset().Int32Value(), rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 282 | LIR* unlock_success_branch = OpUnconditionalBranch(NULL); |
| 283 | |
| 284 | LIR* slow_path_target = NewLIR0(kPseudoTargetLabel); |
| 285 | slow_unlock_branch->target = slow_path_target; |
| 286 | if (null_check_branch != nullptr) { |
| 287 | null_check_branch->target = slow_path_target; |
| 288 | } |
| 289 | // TODO: move to a slow path. |
| 290 | // Go expensive route - artUnlockObjectFromCode(obj); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 291 | LoadWordDisp(rs_rA64_SELF, QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject).Int32Value(), rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 292 | ClobberCallerSave(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 293 | LIR* call_inst = OpReg(kOpBlx, rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 294 | MarkSafepointPC(call_inst); |
| 295 | |
| 296 | LIR* success_target = NewLIR0(kPseudoTargetLabel); |
| 297 | unlock_success_branch->target = success_target; |
| 298 | GenMemBarrier(kStoreLoad); |
| 299 | } else { |
| 300 | // Explicit null-check as slow-path is entered using an IT. |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 301 | GenNullCheck(rs_x0, opt_flags); |
| 302 | Load32Disp(rs_x0, mirror::Object::MonitorOffset().Int32Value(), rs_x1); // Get lock |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 303 | MarkPossibleNullPointerException(opt_flags); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 304 | Load32Disp(rs_rA64_SELF, Thread::ThinLockIdOffset<8>().Int32Value(), rs_x2); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 305 | LoadConstantNoClobber(rs_x3, 0); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 306 | // Is lock unheld on lock or held by us (==thread_id) on unlock? |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 307 | OpRegReg(kOpCmp, rs_x1, rs_x2); |
| 308 | OpIT(kCondEq, "EE"); |
| 309 | Store32Disp/*eq*/(rs_x0, mirror::Object::MonitorOffset().Int32Value(), rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 310 | // Go expensive route - UnlockObjectFromCode(obj); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 311 | LoadWordDisp/*ne*/(rs_rA64_SELF, QUICK_ENTRYPOINT_OFFSET(8, pUnlockObject).Int32Value(), |
| 312 | rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 313 | ClobberCallerSave(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 314 | LIR* call_inst = OpReg(kOpBlx/*ne*/, rs_rA64_LR); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 315 | MarkSafepointPC(call_inst); |
| 316 | GenMemBarrier(kStoreLoad); |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | void Arm64Mir2Lir::GenMoveException(RegLocation rl_dest) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 321 | int ex_offset = Thread::ExceptionOffset<8>().Int32Value(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 322 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 323 | RegStorage reset_reg = AllocTemp(); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 324 | Load32Disp(rs_rA64_SELF, ex_offset, rl_result.reg); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 325 | LoadConstant(reset_reg, 0); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 326 | Store32Disp(rs_rA64_SELF, ex_offset, reset_reg); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 327 | FreeTemp(reset_reg); |
| 328 | StoreValue(rl_dest, rl_result); |
| 329 | } |
| 330 | |
| 331 | /* |
| 332 | * Mark garbage collection card. Skip if the value we're storing is null. |
| 333 | */ |
| 334 | void Arm64Mir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { |
| 335 | RegStorage reg_card_base = AllocTemp(); |
| 336 | RegStorage reg_card_no = AllocTemp(); |
| 337 | LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 338 | LoadWordDisp(rs_rA64_SELF, Thread::CardTableOffset<8>().Int32Value(), reg_card_base); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 339 | OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); |
| 340 | StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte); |
| 341 | LIR* target = NewLIR0(kPseudoTargetLabel); |
| 342 | branch_over->target = target; |
| 343 | FreeTemp(reg_card_base); |
| 344 | FreeTemp(reg_card_no); |
| 345 | } |
| 346 | |
| 347 | void Arm64Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 348 | /* |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 349 | * On entry, x0, x1, x2 & x3 are live. Let the register allocation |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 350 | * mechanism know so it doesn't try to use any of them when |
| 351 | * expanding the frame or flushing. This leaves the utility |
| 352 | * code with a single temp: r12. This should be enough. |
| 353 | */ |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 354 | LockTemp(rs_x0); |
| 355 | LockTemp(rs_x1); |
| 356 | LockTemp(rs_x2); |
| 357 | LockTemp(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 358 | |
| 359 | /* |
| 360 | * We can safely skip the stack overflow check if we're |
| 361 | * a leaf *and* our frame size < fudge factor. |
| 362 | */ |
| 363 | bool skip_overflow_check = (mir_graph_->MethodIsLeaf() && |
| 364 | (static_cast<size_t>(frame_size_) < |
| 365 | Thread::kStackOverflowReservedBytes)); |
| 366 | NewLIR0(kPseudoMethodEntry); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 367 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 368 | if (!skip_overflow_check) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 369 | LoadWordDisp(rs_rA64_SELF, Thread::StackEndOffset<8>().Int32Value(), rs_x12); |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 370 | OpRegImm64(kOpSub, rs_rA64_SP, frame_size_, /*is_wide*/true); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 371 | if (Runtime::Current()->ExplicitStackOverflowChecks()) { |
| 372 | /* Load stack limit */ |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 373 | // TODO(Arm64): fix the line below: |
| 374 | // GenRegRegCheck(kCondUlt, rA64_SP, r12, kThrowStackOverflow); |
| 375 | } else { |
| 376 | // Implicit stack overflow check. |
| 377 | // Generate a load from [sp, #-framesize]. If this is in the stack |
| 378 | // redzone we will get a segmentation fault. |
| 379 | // TODO(Arm64): does the following really work or do we need a reg != rA64_ZR? |
| 380 | Load32Disp(rs_rA64_SP, 0, rs_wzr); |
| 381 | MarkPossibleStackOverflowException(); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 382 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 383 | } else if (frame_size_ > 0) { |
| 384 | OpRegImm64(kOpSub, rs_rA64_SP, frame_size_, /*is_wide*/true); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 385 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 386 | |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 387 | /* Spill core callee saves */ |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 388 | if (core_spill_mask_) { |
| 389 | SpillCoreRegs(rs_rA64_SP, frame_size_, core_spill_mask_); |
| 390 | } |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 391 | /* Need to spill any FP regs? */ |
| 392 | if (num_fp_spills_) { |
| 393 | /* |
| 394 | * NOTE: fp spills are a little different from core spills in that |
| 395 | * they are pushed as a contiguous block. When promoting from |
| 396 | * the fp set, we must allocate all singles from s16..highest-promoted |
| 397 | */ |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 398 | // TODO(Arm64): SpillFPRegs(rA64_SP, frame_size_, core_spill_mask_); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 399 | } |
| 400 | |
| 401 | FlushIns(ArgLocs, rl_method); |
| 402 | |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 403 | FreeTemp(rs_x0); |
| 404 | FreeTemp(rs_x1); |
| 405 | FreeTemp(rs_x2); |
| 406 | FreeTemp(rs_x3); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 407 | } |
| 408 | |
| 409 | void Arm64Mir2Lir::GenExitSequence() { |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 410 | /* |
| 411 | * In the exit path, r0/r1 are live - make sure they aren't |
| 412 | * allocated by the register utilities as temps. |
| 413 | */ |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 414 | LockTemp(rs_x0); |
| 415 | LockTemp(rs_x1); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 416 | |
| 417 | NewLIR0(kPseudoMethodExit); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 418 | /* Need to restore any FP callee saves? */ |
| 419 | if (num_fp_spills_) { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 420 | // TODO(Arm64): UnspillFPRegs(num_fp_spills_); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 421 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 422 | if (core_spill_mask_) { |
| 423 | UnSpillCoreRegs(rs_rA64_SP, frame_size_, core_spill_mask_); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 424 | } |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 425 | |
| 426 | OpRegImm64(kOpAdd, rs_rA64_SP, frame_size_, /*is_wide*/true); |
| 427 | NewLIR0(kA64Ret); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | void Arm64Mir2Lir::GenSpecialExitSequence() { |
Matteo Franchin | e45fb9e | 2014-05-06 10:10:30 +0100 | [diff] [blame] | 431 | NewLIR0(kA64Ret); |
Matteo Franchin | 43ec873 | 2014-03-31 15:00:14 +0100 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | } // namespace art |