src/f32-gemminc/4x8-aarch64-neonfma-cortex-a53.S - platform/external/XNNPACK - Gitiles

 // Auto-generated file. Do not edit!
 //   Template: src/f32-gemm/4x8-aarch64-neonfma-cortex-a53.S.in
 //   Generator: tools/xngen
 //
 // Copyright 2019 Google LLC
 //
 // This source code is licensed under the BSD-style license found in the
 // LICENSE file in the root directory of this source tree.

 #include <xnnpack/assembly.h>

 # void xnn_f32_gemminc_ukernel_4x8__aarch64_neonfma_cortex_a53(
 #     size_t mr,                x0
 #     size_t nc,                x1
 #     size_t kc,                x2 / x0
 #     const uint8_t*restrict a, x3
 #     size_t a_stride,          x4
 #     const void*restrict w,    x5
 #     uint8_t*restrict c,       x6
 #     size_t cm_stride,         x7
 #     size_t cn_stride,         [sp] -> x14
 #     const float*restrict acc,  [sp + 8] -> x15
 #     const union xnn_f32_output_params params[restrict static 1])  [sp + 16] -> x8

 # d8-d15 need to be preserved if used.
 # x19-30 need to be preserved if used.

 # A pointers
 #  x3 a0
 #  x9 a1
 # x10 a2
 #  x4 a3

 # C pointers
 #  x6 c0
 # x16 c1
 # x17 c2
 #  x7 c3

 # Vector register usage
 # A0  v0
 # A1  v0[1]
 # A2  v1
 # A3  v1[1]
 # B   v16 v17 v18 v19
 # C   v20 v21
 # C   v22 v23
 # C   v24 v25
 # C   v26 v27
 # Clamp v6 v7
 # unused A   v2 v3 v4 v5 v8 v9 v10 v11
 # unused B   v12 v13 v14 v15
 # unused C   v28 c29 v30 v31

 BEGIN_FUNCTION xnn_f32_gemminc_ukernel_4x8__aarch64_neonfma_cortex_a53

         # Load acc, params pointer
         LDP x15, x8, [sp, 8]

         # Clamp A and C pointers
         ADD x9, x3, x4           // a1 = a0 + a_stride
         ADD x16, x6, x7          // c1 = c0 + cm_stride
         CMP x0, 2                // if mr < 2
         CSEL x9, x3, x9, LO      //   a1 = a0
         CSEL x16, x6, x16, LO    //   c1 = c0

         ADD x10, x9, x4          // a2 = a1 + a_stride
         ADD x17, x16, x7         // c2 = c1 + cm_stride
                                  // if mr <= 2
         CSEL x10, x9, x10, LS    //   a2 = a1
         CSEL x17, x16, x17, LS   //   c2 = c1

         ADD x4, x10, x4          // a3 = a2 + a_stride
         ADD x7, x17, x7          // c3 = c2 + cm_stride
         CMP x0, 4                // if mr < 4
         CSEL x4, x10, x4, LO     //   a3 = a2
         CSEL x7, x17, x7, LO     //   c3 = c2

         # Load clamping_params values
         LD2R {v6.4s, v7.4s}, [x8]

         # Load cn_stride
         LDR x14, [sp]

 0:
         # Load initial accumulators
         LDP q20, q21, [x15], 32
         LDP q22, q23, [x15], 32
         LDP q24, q25, [x15], 32
         LDP q26, q27, [x15], 32
         PRFM PLDL1KEEP, [x5, 0]  // Prefetch B
         PRFM PLDL1KEEP, [x5, 64]
         PRFM PLDL1KEEP, [x5, 128]
         PRFM PLDL1KEEP,  [x3]    // Prefetch A
         PRFM PLDL1KEEP,  [x9]
         PRFM PLDL1KEEP, [x10]
         PRFM PLDL1KEEP,  [x4]

         # Is there at least 2 floats (8 bytes) for main loop?
         SUBS x0, x2, 8  // k = kc - 8
         B.LO 2f

         # Main loop - 2 floats of A (8 bytes)
         # 16 FMA + 4 LD64 A + 2 LDP B
 1:
         LDR   d0,  [x3], 8
         LDP  q16,  q17, [x5], 32
         LD1   {v0.d}[1], [x9], 8
         LDR   d1, [x10], 8
         LD1   {v1.d}[1], [x4], 8

         FMLA v20.4s, v16.4s,  v0.s[0]
         FMLA v22.4s, v16.4s,  v0.s[2]
         FMLA v24.4s, v16.4s,  v1.s[0]
         FMLA v26.4s, v16.4s,  v1.s[2]
         LDP  q18,  q19, [x5], 32
         FMLA v21.4s, v17.4s,  v0.s[0]
         FMLA v23.4s, v17.4s,  v0.s[2]
         FMLA v25.4s, v17.4s,  v1.s[0]
         FMLA v27.4s, v17.4s,  v1.s[2]

         FMLA v20.4s, v18.4s,  v0.s[1]
         FMLA v22.4s, v18.4s,  v0.s[3]
         FMLA v24.4s, v18.4s,  v1.s[1]
         FMLA v26.4s, v18.4s,  v1.s[3]
         FMLA v21.4s, v19.4s,  v0.s[1]
         FMLA v23.4s, v19.4s,  v0.s[3]
         SUBS x0, x0, 8
         FMLA v25.4s, v19.4s,  v1.s[1]
         FMLA v27.4s, v19.4s,  v1.s[3]
         B.HS 1b

 2:
         # Is there a remainder?- 1 floats of A (4 bytes)
         TBNZ x0, 2, 4f
 3:
         # Clamp
         FMIN v20.4s, v20.4s, v6.4s
         FMIN v21.4s, v21.4s, v6.4s
         FMIN v22.4s, v22.4s, v6.4s
         FMIN v23.4s, v23.4s, v6.4s
         FMIN v24.4s, v24.4s, v6.4s
         FMIN v25.4s, v25.4s, v6.4s
         FMIN v26.4s, v26.4s, v6.4s
         FMIN v27.4s, v27.4s, v6.4s
         FMAX v20.4s, v20.4s, v7.4s
         FMAX v21.4s, v21.4s, v7.4s
         FMAX v22.4s, v22.4s, v7.4s
         FMAX v23.4s, v23.4s, v7.4s
         FMAX v24.4s, v24.4s, v7.4s
         FMAX v25.4s, v25.4s, v7.4s
         FMAX v26.4s, v26.4s, v7.4s
         FMAX v27.4s, v27.4s, v7.4s

         # Store full 4 x 8
         CMP x1, 8
         B.LO 5f

         STP q26, q27, [x7]
         ADD x7, x7, x14
         SUB  x3,  x3, x2 // a0 -= kc
         STP q24, q25, [x17]
         ADD x17, x17, x14
         SUB  x9,  x9, x2 // a1 -= kc
         STP q22, q23, [x16]
         ADD x16, x16, x14
         SUB x10, x10, x2 // a2 -= kc
         STP q20, q21,  [x6]
         ADD  x6,  x6, x14
         SUB x4, x4, x2 // a3 -= kc

         SUBS x1, x1, 8
         B.HI 0b

         RET

 4:
         # Remainder- 1 floats of A (4 bytes)
         LDR   s0,  [x3], 4
         LDP  q16,  q17, [x5], 32
         LD1   {v0.s}[2], [x9], 4
         LDR   s1, [x10], 4
         LD1   {v1.s}[2], [x4], 4

         FMLA v20.4s, v16.4s,  v0.s[0]
         FMLA v22.4s, v16.4s,  v0.s[2]
         FMLA v24.4s, v16.4s,  v1.s[0]
         FMLA v26.4s, v16.4s,  v1.s[2]
         FMLA v21.4s, v17.4s,  v0.s[0]
         FMLA v23.4s, v17.4s,  v0.s[2]
         FMLA v25.4s, v17.4s,  v1.s[0]
         FMLA v27.4s, v17.4s,  v1.s[2]
         B 3b

         # Store odd width
 5:
         TBZ x1, 2, 6f
         STR q26, [x7], 16
         MOV v26.16b, v27.16b
         STR q24, [x17], 16
         MOV v24.16b, v25.16b
         STR q22, [x16], 16
         MOV v22.16b, v23.16b
         STR q20,  [x6], 16
         MOV v20.16b, v21.16b

 6:
         TBZ x1, 1, 7f
         STR d26,  [x7], 8
         DUP d26, v26.d[1]
         STR d24, [x17], 8
         DUP d24, v24.d[1]
         STR d22, [x16], 8
         DUP d22, v22.d[1]
         STR d20,  [x6], 8
         DUP d20, v20.d[1]

 7:
         TBZ x1, 0, 8f
         STR s26,  [x7]
         STR s24, [x17]
         STR s22, [x16]
         STR s20,  [x6]
 8:
         RET

 END_FUNCTION xnn_f32_gemminc_ukernel_4x8__aarch64_neonfma_cortex_a53

 #ifdef __ELF__
 .section ".note.GNU-stack","",%progbits
 #endif
	// Auto-generated file. Do not edit!
	// Template: src/f32-gemm/4x8-aarch64-neonfma-cortex-a53.S.in
	// Generator: tools/xngen
	//
	// Copyright 2019 Google LLC
	//
	// This source code is licensed under the BSD-style license found in the
	// LICENSE file in the root directory of this source tree.

	#include <xnnpack/assembly.h>

	# void xnn_f32_gemminc_ukernel_4x8__aarch64_neonfma_cortex_a53(
	# size_t mr, x0
	# size_t nc, x1
	# size_t kc, x2 / x0
	# const uint8_t*restrict a, x3
	# size_t a_stride, x4
	# const void*restrict w, x5
	# uint8_t*restrict c, x6
	# size_t cm_stride, x7
	# size_t cn_stride, [sp] -> x14
	# const float*restrict acc, [sp + 8] -> x15
	# const union xnn_f32_output_params params[restrict static 1]) [sp + 16] -> x8

	# d8-d15 need to be preserved if used.
	# x19-30 need to be preserved if used.

	# A pointers
	# x3 a0
	# x9 a1
	# x10 a2
	# x4 a3

	# C pointers
	# x6 c0
	# x16 c1
	# x17 c2
	# x7 c3

	# Vector register usage
	# A0 v0
	# A1 v0[1]
	# A2 v1
	# A3 v1[1]
	# B v16 v17 v18 v19
	# C v20 v21
	# C v22 v23
	# C v24 v25
	# C v26 v27
	# Clamp v6 v7
	# unused A v2 v3 v4 v5 v8 v9 v10 v11
	# unused B v12 v13 v14 v15
	# unused C v28 c29 v30 v31

	BEGIN_FUNCTION xnn_f32_gemminc_ukernel_4x8__aarch64_neonfma_cortex_a53

	# Load acc, params pointer
	LDP x15, x8, [sp, 8]

	# Clamp A and C pointers
	ADD x9, x3, x4 // a1 = a0 + a_stride
	ADD x16, x6, x7 // c1 = c0 + cm_stride
	CMP x0, 2 // if mr < 2
	CSEL x9, x3, x9, LO // a1 = a0
	CSEL x16, x6, x16, LO // c1 = c0

	ADD x10, x9, x4 // a2 = a1 + a_stride
	ADD x17, x16, x7 // c2 = c1 + cm_stride
	// if mr <= 2
	CSEL x10, x9, x10, LS // a2 = a1
	CSEL x17, x16, x17, LS // c2 = c1

	ADD x4, x10, x4 // a3 = a2 + a_stride
	ADD x7, x17, x7 // c3 = c2 + cm_stride
	CMP x0, 4 // if mr < 4
	CSEL x4, x10, x4, LO // a3 = a2
	CSEL x7, x17, x7, LO // c3 = c2

	# Load clamping_params values
	LD2R {v6.4s, v7.4s}, [x8]

	# Load cn_stride
	LDR x14, [sp]

	0:
	# Load initial accumulators
	LDP q20, q21, [x15], 32
	LDP q22, q23, [x15], 32
	LDP q24, q25, [x15], 32
	LDP q26, q27, [x15], 32
	PRFM PLDL1KEEP, [x5, 0] // Prefetch B
	PRFM PLDL1KEEP, [x5, 64]
	PRFM PLDL1KEEP, [x5, 128]
	PRFM PLDL1KEEP, [x3] // Prefetch A
	PRFM PLDL1KEEP, [x9]
	PRFM PLDL1KEEP, [x10]
	PRFM PLDL1KEEP, [x4]

	# Is there at least 2 floats (8 bytes) for main loop?
	SUBS x0, x2, 8 // k = kc - 8
	B.LO 2f

	# Main loop - 2 floats of A (8 bytes)
	# 16 FMA + 4 LD64 A + 2 LDP B
	1:
	LDR d0, [x3], 8
	LDP q16, q17, [x5], 32
	LD1 {v0.d}[1], [x9], 8
	LDR d1, [x10], 8
	LD1 {v1.d}[1], [x4], 8

	FMLA v20.4s, v16.4s, v0.s[0]
	FMLA v22.4s, v16.4s, v0.s[2]
	FMLA v24.4s, v16.4s, v1.s[0]
	FMLA v26.4s, v16.4s, v1.s[2]
	LDP q18, q19, [x5], 32
	FMLA v21.4s, v17.4s, v0.s[0]
	FMLA v23.4s, v17.4s, v0.s[2]
	FMLA v25.4s, v17.4s, v1.s[0]
	FMLA v27.4s, v17.4s, v1.s[2]

	FMLA v20.4s, v18.4s, v0.s[1]
	FMLA v22.4s, v18.4s, v0.s[3]
	FMLA v24.4s, v18.4s, v1.s[1]
	FMLA v26.4s, v18.4s, v1.s[3]
	FMLA v21.4s, v19.4s, v0.s[1]
	FMLA v23.4s, v19.4s, v0.s[3]
	SUBS x0, x0, 8
	FMLA v25.4s, v19.4s, v1.s[1]
	FMLA v27.4s, v19.4s, v1.s[3]
	B.HS 1b

	2:
	# Is there a remainder?- 1 floats of A (4 bytes)
	TBNZ x0, 2, 4f
	3:
	# Clamp
	FMIN v20.4s, v20.4s, v6.4s
	FMIN v21.4s, v21.4s, v6.4s
	FMIN v22.4s, v22.4s, v6.4s
	FMIN v23.4s, v23.4s, v6.4s
	FMIN v24.4s, v24.4s, v6.4s
	FMIN v25.4s, v25.4s, v6.4s
	FMIN v26.4s, v26.4s, v6.4s
	FMIN v27.4s, v27.4s, v6.4s
	FMAX v20.4s, v20.4s, v7.4s
	FMAX v21.4s, v21.4s, v7.4s
	FMAX v22.4s, v22.4s, v7.4s
	FMAX v23.4s, v23.4s, v7.4s
	FMAX v24.4s, v24.4s, v7.4s
	FMAX v25.4s, v25.4s, v7.4s
	FMAX v26.4s, v26.4s, v7.4s
	FMAX v27.4s, v27.4s, v7.4s

	# Store full 4 x 8
	CMP x1, 8
	B.LO 5f

	STP q26, q27, [x7]
	ADD x7, x7, x14
	SUB x3, x3, x2 // a0 -= kc
	STP q24, q25, [x17]
	ADD x17, x17, x14
	SUB x9, x9, x2 // a1 -= kc
	STP q22, q23, [x16]
	ADD x16, x16, x14
	SUB x10, x10, x2 // a2 -= kc
	STP q20, q21, [x6]
	ADD x6, x6, x14
	SUB x4, x4, x2 // a3 -= kc

	SUBS x1, x1, 8
	B.HI 0b

	RET

	4:
	# Remainder- 1 floats of A (4 bytes)
	LDR s0, [x3], 4
	LDP q16, q17, [x5], 32
	LD1 {v0.s}[2], [x9], 4
	LDR s1, [x10], 4
	LD1 {v1.s}[2], [x4], 4

	FMLA v20.4s, v16.4s, v0.s[0]
	FMLA v22.4s, v16.4s, v0.s[2]
	FMLA v24.4s, v16.4s, v1.s[0]
	FMLA v26.4s, v16.4s, v1.s[2]
	FMLA v21.4s, v17.4s, v0.s[0]
	FMLA v23.4s, v17.4s, v0.s[2]
	FMLA v25.4s, v17.4s, v1.s[0]
	FMLA v27.4s, v17.4s, v1.s[2]
	B 3b

	# Store odd width
	5:
	TBZ x1, 2, 6f
	STR q26, [x7], 16
	MOV v26.16b, v27.16b
	STR q24, [x17], 16
	MOV v24.16b, v25.16b
	STR q22, [x16], 16
	MOV v22.16b, v23.16b
	STR q20, [x6], 16
	MOV v20.16b, v21.16b

	6:
	TBZ x1, 1, 7f
	STR d26, [x7], 8
	DUP d26, v26.d[1]
	STR d24, [x17], 8
	DUP d24, v24.d[1]
	STR d22, [x16], 8
	DUP d22, v22.d[1]
	STR d20, [x6], 8
	DUP d20, v20.d[1]

	7:
	TBZ x1, 0, 8f
	STR s26, [x7]
	STR s24, [x17]
	STR s22, [x16]
	STR s20, [x6]
	8:
	RET

	END_FUNCTION xnn_f32_gemminc_ukernel_4x8__aarch64_neonfma_cortex_a53

	#ifdef __ELF__
	.section ".note.GNU-stack","",%progbits
	#endif