| // Copyright 2020 Google LLC |
| // |
| // This source code is licensed under the BSD-style license found in the |
| // LICENSE file in the root directory of this source tree. |
| |
| $assert ELEMENTS_TILE % 4 == 0 |
| $assert ELEMENTS_TILE >= 4 |
| $SIMD_TILE = ELEMENTS_TILE // 4 |
| $ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
| $VMULADDQ_F32 = "vfmaq_f32" if FMA else "vmlaq_f32" |
| #include <assert.h> |
| |
| #include <arm_neon.h> |
| |
| #include <xnnpack/common.h> |
| #include <xnnpack/raddstoreexpminusmax.h> |
| |
| |
| $PARAMS_STRUCT = "neonfma_rr1_p5" if FMA else "neon_rr2_p5" |
| void xnn_f32_raddstoreexpminusmax_ukernel__${"neonfma" if FMA else "neon"}_rr${1 if FMA else 2}_p5_x${ELEMENTS_TILE}${"" if ACCUMULATORS == 1 else "_acc%d" % ACCUMULATORS}( |
| size_t elements, |
| const float* input, |
| const float* max, |
| float* output, |
| float* sum, |
| const union xnn_f32_expminus_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS |
| { |
| assert(elements % sizeof(float) == 0); |
| |
| const float32x4_t vi_max = vld1q_dup_f32(max); |
| const float32x4_t vlog2e = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.log2e); |
| const float32x4_t vmagic_bias = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.magic_bias); |
| $if FMA: |
| const float32x4_t vminus_ln2 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.minus_ln2); |
| $else: |
| const float32x4_t vminus_ln2_hi = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.minus_ln2_hi); |
| const float32x4_t vminus_ln2_lo = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.minus_ln2_lo); |
| const float32x4_t vc5 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c5); |
| const float32x4_t vc4 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c4); |
| const float32x4_t vc3 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c3); |
| const float32x4_t vc2 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c2); |
| const float32x4_t vc1 = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.c1); |
| const float32x4_t vdenorm_cutoff = vld1q_dup_f32(¶ms->${PARAMS_STRUCT}.denorm_cutoff); |
| |
| $if ELEMENTS_TILE > 4: |
| $for K in range(ACCUMULATORS): |
| float32x4_t vacc${K} = vmovq_n_f32(0.0f); |
| for (; elements >= ${ELEMENTS_TILE} * sizeof(float); elements -= ${ELEMENTS_TILE} * sizeof(float)) { |
| $for N in range(0, ELEMENTS_TILE, 4): |
| const float32x4_t vi${ABC[N:N+4]} = vld1q_f32(input); input += 4; |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| const float32x4_t vx${ABC[N:N+4]} = vsubq_f32(vi${ABC[N:N+4]}, vi_max); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| float32x4_t vn${ABC[N:N+4]} = ${VMULADDQ_F32}(vmagic_bias, vx${ABC[N:N+4]}, vlog2e); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| const float32x4_t vs${ABC[N:N+4]} = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), 23)); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vn${ABC[N:N+4]} = vsubq_f32(vn${ABC[N:N+4]}, vmagic_bias); |
| |
| $if FMA: |
| $for N in range(0, ELEMENTS_TILE, 4): |
| float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vx${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2); |
| $else: |
| $for N in range(0, ELEMENTS_TILE, 4): |
| float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vx${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_hi); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_lo); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| float32x4_t vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc4, vc5, vt${ABC[N:N+4]}); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc3, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc2, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc1, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vt${ABC[N:N+4]} = vmulq_f32(vt${ABC[N:N+4]}, vs${ABC[N:N+4]}); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| float32x4_t vf${ABC[N:N+4]} = ${VMULADDQ_F32}(vs${ABC[N:N+4]}, vp${ABC[N:N+4]}, vt${ABC[N:N+4]}); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vf${ABC[N:N+4]} = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf${ABC[N:N+4]}), vcltq_f32(vx${ABC[N:N+4]}, vdenorm_cutoff))); |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vst1q_f32(output, vf${ABC[N:N+4]}); output += 4; |
| |
| $for N in range(0, ELEMENTS_TILE, 4): |
| vacc${N % ACCUMULATORS} = vaddq_f32(vacc${N % ACCUMULATORS}, vf${ABC[N:N+4]}); |
| } |
| $if ACCUMULATORS > 1: |
| $ACC_SLICE = 1 |
| $while ACC_SLICE < ACCUMULATORS: |
| $for A in range(0, ACCUMULATORS, ACC_SLICE * 2): |
| $if A + ACC_SLICE < ACCUMULATORS: |
| vacc${A} = vaddq_f32(vacc${A}, vacc${A + ACC_SLICE}); |
| $ACC_SLICE *= 2 |
| |
| float32x4_t vacc = vacc0; |
| $else: |
| float32x4_t vacc = vmovq_n_f32(0.0f); |
| for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) { |
| const float32x4_t vi = vld1q_f32(input); input += 4; |
| |
| const float32x4_t vx = vsubq_f32(vi, vi_max); |
| |
| float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vx, vlog2e); |
| |
| const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23)); |
| |
| vn = vsubq_f32(vn, vmagic_bias); |
| |
| $if FMA: |
| float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2); |
| $else: |
| float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2_hi); |
| vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo); |
| |
| float32x4_t vp = ${VMULADDQ_F32}(vc4, vc5, vt); |
| vp = ${VMULADDQ_F32}(vc3, vp, vt); |
| vp = ${VMULADDQ_F32}(vc2, vp, vt); |
| vp = ${VMULADDQ_F32}(vc1, vp, vt); |
| |
| vt = vmulq_f32(vt, vs); |
| float32x4_t vf = ${VMULADDQ_F32}(vs, vp, vt); |
| |
| vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff))); |
| |
| vst1q_f32(output, vf); output += 4; |
| |
| vacc = vaddq_f32(vacc, vf); |
| } |
| #if XNN_ARCH_ARM64 |
| float vacc_lo = vaddvq_f32(vacc); |
| #else |
| float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc)); |
| #endif |
| if (elements != 0) { |
| assert(elements >= 1 * sizeof(float)); |
| assert(elements <= 3 * sizeof(float)); |
| const float32x4_t vi = vld1q_f32(input); input += 4; |
| |
| const float32x4_t vx = vsubq_f32(vi, vi_max); |
| |
| float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vx, vlog2e); |
| |
| const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23)); |
| |
| vn = vsubq_f32(vn, vmagic_bias); |
| |
| $if FMA: |
| float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2); |
| $else: |
| float32x4_t vt = ${VMULADDQ_F32}(vx, vn, vminus_ln2_hi); |
| vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo); |
| |
| float32x4_t vp = ${VMULADDQ_F32}(vc4, vc5, vt); |
| vp = ${VMULADDQ_F32}(vc3, vp, vt); |
| vp = ${VMULADDQ_F32}(vc2, vp, vt); |
| vp = ${VMULADDQ_F32}(vc1, vp, vt); |
| |
| vt = vmulq_f32(vt, vs); |
| float32x4_t vf = ${VMULADDQ_F32}(vs, vp, vt); |
| |
| vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff))); |
| |
| float32x2_t vf_lo = vget_low_f32(vf); |
| if (elements & (2 * sizeof(float))) { |
| vst1_f32(output, vf_lo); output += 2; |
| |
| #if XNN_ARCH_ARM64 |
| vacc_lo += vaddv_f32(vf_lo); |
| #else |
| vacc_lo = vadd_f32(vacc_lo, vf_lo); |
| #endif |
| |
| vf_lo = vget_high_f32(vf); |
| } |
| if (elements & (1 * sizeof(float))) { |
| vst1_lane_f32(output, vf_lo, 0); |
| |
| #if XNN_ARCH_ARM64 |
| vacc_lo += vget_lane_f32(vf_lo, 0); |
| #else |
| vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32))); |
| #endif |
| } |
| } |
| #if XNN_ARCH_ARM64 |
| *sum = vacc_lo; |
| #else |
| vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0); |
| #endif |
| } |