src/f32-velu/neon-lut16-p3.c.in - platform/external/XNNPACK - Gitiles

 // Copyright 2020 Google LLC
 //
 // This source code is licensed under the BSD-style license found in the
 // LICENSE file in the root directory of this source tree.

 $assert BATCH_TILE % 4 == 0
 $assert BATCH_TILE >= 4
 $ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 $VMULADDQ_F32 = "vfmaq_f32" if FMA else "vmlaq_f32"
 #include <assert.h>

 #include <arm_neon.h>

 #include <xnnpack/vunary.h>
 #include <xnnpack/common.h>


 extern XNN_INTERNAL const int32_t xnn_table_exp2minus_k_over_16[16];

 $PARAMS_STRUCT = "neonfma_rr1_lut16_p3" if FMA else "neon_rr2_lut16_p3"
 void xnn_f32_velu_ukernel__${"neonfma" if FMA else "neon"}_rr${1 if FMA else 2}_lut16_p3_x${BATCH_TILE}(
     size_t n,
     const float* x,
     float* y,
     const union xnn_f32_elu_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
 {
   assert(n != 0);
   assert(n % sizeof(float) == 0);
   assert(x != NULL);
   assert(y != NULL);

   const float32x4_t vprescale = vld1q_dup_f32(&params->${PARAMS_STRUCT}.prescale);
   const float32x4_t valpha = vld1q_dup_f32(&params->${PARAMS_STRUCT}.alpha);
   const float32x4_t vbeta = vld1q_dup_f32(&params->${PARAMS_STRUCT}.beta);
   const float32x4_t vsat_cutoff = vld1q_dup_f32(&params->${PARAMS_STRUCT}.sat_cutoff);
   const float32x4_t vmagic_bias = vld1q_dup_f32(&params->${PARAMS_STRUCT}.magic_bias);
   const float32x4_t vlog2e = vld1q_dup_f32(&params->${PARAMS_STRUCT}.log2e);
   const int32x4_t vindex_mask = vmovq_n_s32(0xF);
   $if FMA:
     const float32x4_t vminus_ln2 = vld1q_dup_f32(&params->neonfma_rr1_lut16_p3.minus_ln2);
   $else:
     const float32x4_t vminus_ln2_hi = vld1q_dup_f32(&params->neon_rr2_lut16_p3.minus_ln2_hi);
     const float32x4_t vminus_ln2_lo = vld1q_dup_f32(&params->neon_rr2_lut16_p3.minus_ln2_lo);
   const float32x4_t vc3 = vld1q_dup_f32(&params->${PARAMS_STRUCT}.c3);
   const float32x4_t vc2 = vld1q_dup_f32(&params->${PARAMS_STRUCT}.c2);
   const float32x4_t vone = vmovq_n_f32(1.0f);

   $if BATCH_TILE > 4:
     for (; n >= ${BATCH_TILE} * sizeof(float); n -= ${BATCH_TILE} * sizeof(float)) {
       $for N in range(0, BATCH_TILE, 4):
         float32x4_t vx${ABC[N:N+4]} = vld1q_f32(x); x += 4;

       $for N in range(0, BATCH_TILE, 4):
         const float32x4_t vz${ABC[N:N+4]} = vmaxq_f32(vmulq_f32(vx${ABC[N:N+4]}, vprescale), vsat_cutoff);

       $for N in range(0, BATCH_TILE, 4):
         float32x4_t vn${ABC[N:N+4]} = ${VMULADDQ_F32}(vmagic_bias, vz${ABC[N:N+4]}, vlog2e);

       $for N in range(0, BATCH_TILE, 4):
         const uint64x2_t vidx${ABC[N:N+4]} = vreinterpretq_u64_s32(vshlq_n_s32(vandq_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), vindex_mask), 2));
         const int32x4_t ven${ABC[N:N+4]} = vshlq_n_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), 19);

       $for N in range(0, BATCH_TILE, 4):
         const uint64_t vidx${ABC[N:N+2]} = vgetq_lane_u64(vidx${ABC[N:N+4]}, 0);
         const uint64_t vidx${ABC[N+2:N+4]} = vgetq_lane_u64(vidx${ABC[N:N+4]}, 1);
         int32x2_t vl${ABC[N:N+2]} = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx${ABC[N:N+2]}));
         int32x2_t vl${ABC[N+2:N+4]} = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx${ABC[N+2:N+4]}));
         vl${ABC[N:N+2]} = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx${ABC[N:N+2]} >> 32)), vl${ABC[N:N+2]}, 1);
         vl${ABC[N+2:N+4]} = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx${ABC[N+2:N+4]} >> 32)), vl${ABC[N+2:N+4]}, 1);
         const int32x4_t vl${ABC[N:N+4]} = vcombine_s32(vl${ABC[N:N+2]}, vl${ABC[N+2:N+4]});

       $for N in range(0, BATCH_TILE, 4):
         vn${ABC[N:N+4]} = vsubq_f32(vn${ABC[N:N+4]}, vmagic_bias);
         float32x4_t vs${ABC[N:N+4]} = vreinterpretq_f32_s32(vaddq_s32(vl${ABC[N:N+4]}, ven${ABC[N:N+4]}));

       $if FMA:
         $for N in range(0, BATCH_TILE, 4):
           float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2);
       $else:
         $for N in range(0, BATCH_TILE, 4):
           float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_hi);

         $for N in range(0, BATCH_TILE, 4):
           vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_lo);

       $for N in range(0, BATCH_TILE, 4):
         float32x4_t vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc2, vc3, vt${ABC[N:N+4]});

       $for N in range(0, BATCH_TILE, 4):
         vp${ABC[N:N+4]} = vmulq_f32(vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

       $for N in range(0, BATCH_TILE, 4):
         vt${ABC[N:N+4]} = vmulq_f32(vt${ABC[N:N+4]}, vs${ABC[N:N+4]});
         vs${ABC[N:N+4]} = vsubq_f32(vs${ABC[N:N+4]}, vone);

       $for N in range(0, BATCH_TILE, 4):
         vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

       $for N in range(0, BATCH_TILE, 4):
         const float32x4_t ve${ABC[N:N+4]} = vmulq_f32(vaddq_f32(vp${ABC[N:N+4]}, vs${ABC[N:N+4]}), valpha);

       $for N in range(0, BATCH_TILE, 4):
         const uint32x4_t vm${ABC[N:N+4]} = vcltq_f32(vx${ABC[N:N+4]}, vmovq_n_f32(0.0f));
         vx${ABC[N:N+4]} = vmulq_f32(vx${ABC[N:N+4]}, vbeta);

       $for N in range(0, BATCH_TILE, 4):
         const float32x4_t vy${ABC[N:N+4]} = vbslq_f32(vm${ABC[N:N+4]}, ve${ABC[N:N+4]}, vx${ABC[N:N+4]});

       $for N in range(0, BATCH_TILE, 4):
         vst1q_f32(y, vy${ABC[N:N+4]}); y += 4;
     }
   for (; n >= 4 * sizeof(float); n -= 4 * sizeof(float)) {
     float32x4_t vx = vld1q_f32(x); x += 4;

     const float32x4_t vz = vmaxq_f32(vmulq_f32(vx, vprescale), vsat_cutoff);

     float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vlog2e);
     const uint64x2_t vidx = vreinterpretq_u64_s32(vshlq_n_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask), 2));
     const int32x4_t ven = vshlq_n_s32(vreinterpretq_s32_f32(vn), 19);

     const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0);
     const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1);
     int32x2_t vl_lo = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_lo));
     int32x2_t vl_hi = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_hi));
     vl_lo = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_lo >> 32)), vl_lo, 1);
     vl_hi = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_hi >> 32)), vl_hi, 1);

     vn = vsubq_f32(vn, vmagic_bias);
     const int32x4_t vl = vcombine_s32(vl_lo, vl_hi);

     $if FMA:
       float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2);
     $else:
       float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2_hi);
       vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo);
     float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vl, ven));

     float32x4_t vp = ${VMULADDQ_F32}(vc2, vc3, vt);
     vp = vmulq_f32(vp, vt);

     vt = vmulq_f32(vt, vs);
     vs = vsubq_f32(vs, vone);
     vp = ${VMULADDQ_F32}(vt, vp, vt);
     const float32x4_t ve = vmulq_f32(vaddq_f32(vp, vs), valpha);

     const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f));
     vx = vmulq_f32(vx, vbeta);
     const float32x4_t vy = vbslq_f32(vm, ve, vx);

     vst1q_f32(y, vy); y += 4;
   }
   if XNN_UNLIKELY(n != 0) {
     float32x4_t vx = vld1q_f32(x);

     const float32x4_t vz = vmaxq_f32(vmulq_f32(vx, vprescale), vsat_cutoff);

     float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vlog2e);
     const uint64x2_t vidx = vreinterpretq_u64_s32(vshlq_n_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask), 2));
     const int32x4_t ven = vshlq_n_s32(vreinterpretq_s32_f32(vn), 19);

     const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0);
     const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1);
     int32x2_t vl_lo = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_lo));
     int32x2_t vl_hi = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_hi));
     vl_lo = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_lo >> 32)), vl_lo, 1);
     vl_hi = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_hi >> 32)), vl_hi, 1);

     vn = vsubq_f32(vn, vmagic_bias);
     const int32x4_t vl = vcombine_s32(vl_lo, vl_hi);

     $if FMA:
       float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2);
     $else:
       float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2_hi);
       vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo);
     float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vl, ven));

     float32x4_t vp = ${VMULADDQ_F32}(vc2, vc3, vt);
     vp = vmulq_f32(vp, vt);

     vt = vmulq_f32(vt, vs);
     vs = vsubq_f32(vs, vone);
     vp = ${VMULADDQ_F32}(vt, vp, vt);
     const float32x4_t ve = vmulq_f32(vaddq_f32(vp, vs), valpha);

     const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f));
     vx = vmulq_f32(vx, vbeta);
     const float32x4_t vy = vbslq_f32(vm, ve, vx);

     float32x2_t vy_lo = vget_low_f32(vy);
     if (n & (2 * sizeof(float))) {
       vst1_f32(y, vy_lo); y += 2;
       vy_lo = vget_high_f32(vy);
     }
     if (n & (1 * sizeof(float))) {
       vst1_lane_f32(y, vy_lo, 0);
     }
   }
 }
	// Copyright 2020 Google LLC
	//
	// This source code is licensed under the BSD-style license found in the
	// LICENSE file in the root directory of this source tree.

	$assert BATCH_TILE % 4 == 0
	$assert BATCH_TILE >= 4
	$ABC = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"
	$VMULADDQ_F32 = "vfmaq_f32" if FMA else "vmlaq_f32"
	#include <assert.h>

	#include <arm_neon.h>

	#include <xnnpack/vunary.h>
	#include <xnnpack/common.h>


	extern XNN_INTERNAL const int32_t xnn_table_exp2minus_k_over_16[16];

	$PARAMS_STRUCT = "neonfma_rr1_lut16_p3" if FMA else "neon_rr2_lut16_p3"
	void xnn_f32_velu_ukernel__${"neonfma" if FMA else "neon"}_rr${1 if FMA else 2}_lut16_p3_x${BATCH_TILE}(
	size_t n,
	const float* x,
	float* y,
	const union xnn_f32_elu_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
	{
	assert(n != 0);
	assert(n % sizeof(float) == 0);
	assert(x != NULL);
	assert(y != NULL);

	const float32x4_t vprescale = vld1q_dup_f32(&params->${PARAMS_STRUCT}.prescale);
	const float32x4_t valpha = vld1q_dup_f32(&params->${PARAMS_STRUCT}.alpha);
	const float32x4_t vbeta = vld1q_dup_f32(&params->${PARAMS_STRUCT}.beta);
	const float32x4_t vsat_cutoff = vld1q_dup_f32(&params->${PARAMS_STRUCT}.sat_cutoff);
	const float32x4_t vmagic_bias = vld1q_dup_f32(&params->${PARAMS_STRUCT}.magic_bias);
	const float32x4_t vlog2e = vld1q_dup_f32(&params->${PARAMS_STRUCT}.log2e);
	const int32x4_t vindex_mask = vmovq_n_s32(0xF);
	$if FMA:
	const float32x4_t vminus_ln2 = vld1q_dup_f32(&params->neonfma_rr1_lut16_p3.minus_ln2);
	$else:
	const float32x4_t vminus_ln2_hi = vld1q_dup_f32(&params->neon_rr2_lut16_p3.minus_ln2_hi);
	const float32x4_t vminus_ln2_lo = vld1q_dup_f32(&params->neon_rr2_lut16_p3.minus_ln2_lo);
	const float32x4_t vc3 = vld1q_dup_f32(&params->${PARAMS_STRUCT}.c3);
	const float32x4_t vc2 = vld1q_dup_f32(&params->${PARAMS_STRUCT}.c2);
	const float32x4_t vone = vmovq_n_f32(1.0f);

	$if BATCH_TILE > 4:
	for (; n >= ${BATCH_TILE} * sizeof(float); n -= ${BATCH_TILE} * sizeof(float)) {
	$for N in range(0, BATCH_TILE, 4):
	float32x4_t vx${ABC[N:N+4]} = vld1q_f32(x); x += 4;

	$for N in range(0, BATCH_TILE, 4):
	const float32x4_t vz${ABC[N:N+4]} = vmaxq_f32(vmulq_f32(vx${ABC[N:N+4]}, vprescale), vsat_cutoff);

	$for N in range(0, BATCH_TILE, 4):
	float32x4_t vn${ABC[N:N+4]} = ${VMULADDQ_F32}(vmagic_bias, vz${ABC[N:N+4]}, vlog2e);

	$for N in range(0, BATCH_TILE, 4):
	const uint64x2_t vidx${ABC[N:N+4]} = vreinterpretq_u64_s32(vshlq_n_s32(vandq_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), vindex_mask), 2));
	const int32x4_t ven${ABC[N:N+4]} = vshlq_n_s32(vreinterpretq_s32_f32(vn${ABC[N:N+4]}), 19);

	$for N in range(0, BATCH_TILE, 4):
	const uint64_t vidx${ABC[N:N+2]} = vgetq_lane_u64(vidx${ABC[N:N+4]}, 0);
	const uint64_t vidx${ABC[N+2:N+4]} = vgetq_lane_u64(vidx${ABC[N:N+4]}, 1);
	int32x2_t vl${ABC[N:N+2]} = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx${ABC[N:N+2]}));
	int32x2_t vl${ABC[N+2:N+4]} = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx${ABC[N+2:N+4]}));
	vl${ABC[N:N+2]} = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx${ABC[N:N+2]} >> 32)), vl${ABC[N:N+2]}, 1);
	vl${ABC[N+2:N+4]} = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx${ABC[N+2:N+4]} >> 32)), vl${ABC[N+2:N+4]}, 1);
	const int32x4_t vl${ABC[N:N+4]} = vcombine_s32(vl${ABC[N:N+2]}, vl${ABC[N+2:N+4]});

	$for N in range(0, BATCH_TILE, 4):
	vn${ABC[N:N+4]} = vsubq_f32(vn${ABC[N:N+4]}, vmagic_bias);
	float32x4_t vs${ABC[N:N+4]} = vreinterpretq_f32_s32(vaddq_s32(vl${ABC[N:N+4]}, ven${ABC[N:N+4]}));

	$if FMA:
	$for N in range(0, BATCH_TILE, 4):
	float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2);
	$else:
	$for N in range(0, BATCH_TILE, 4):
	float32x4_t vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vz${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_hi);

	$for N in range(0, BATCH_TILE, 4):
	vt${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vn${ABC[N:N+4]}, vminus_ln2_lo);

	$for N in range(0, BATCH_TILE, 4):
	float32x4_t vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vc2, vc3, vt${ABC[N:N+4]});

	$for N in range(0, BATCH_TILE, 4):
	vp${ABC[N:N+4]} = vmulq_f32(vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

	$for N in range(0, BATCH_TILE, 4):
	vt${ABC[N:N+4]} = vmulq_f32(vt${ABC[N:N+4]}, vs${ABC[N:N+4]});
	vs${ABC[N:N+4]} = vsubq_f32(vs${ABC[N:N+4]}, vone);

	$for N in range(0, BATCH_TILE, 4):
	vp${ABC[N:N+4]} = ${VMULADDQ_F32}(vt${ABC[N:N+4]}, vp${ABC[N:N+4]}, vt${ABC[N:N+4]});

	$for N in range(0, BATCH_TILE, 4):
	const float32x4_t ve${ABC[N:N+4]} = vmulq_f32(vaddq_f32(vp${ABC[N:N+4]}, vs${ABC[N:N+4]}), valpha);

	$for N in range(0, BATCH_TILE, 4):
	const uint32x4_t vm${ABC[N:N+4]} = vcltq_f32(vx${ABC[N:N+4]}, vmovq_n_f32(0.0f));
	vx${ABC[N:N+4]} = vmulq_f32(vx${ABC[N:N+4]}, vbeta);

	$for N in range(0, BATCH_TILE, 4):
	const float32x4_t vy${ABC[N:N+4]} = vbslq_f32(vm${ABC[N:N+4]}, ve${ABC[N:N+4]}, vx${ABC[N:N+4]});

	$for N in range(0, BATCH_TILE, 4):
	vst1q_f32(y, vy${ABC[N:N+4]}); y += 4;
	}
	for (; n >= 4 * sizeof(float); n -= 4 * sizeof(float)) {
	float32x4_t vx = vld1q_f32(x); x += 4;

	const float32x4_t vz = vmaxq_f32(vmulq_f32(vx, vprescale), vsat_cutoff);

	float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vlog2e);
	const uint64x2_t vidx = vreinterpretq_u64_s32(vshlq_n_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask), 2));
	const int32x4_t ven = vshlq_n_s32(vreinterpretq_s32_f32(vn), 19);

	const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0);
	const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1);
	int32x2_t vl_lo = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_lo));
	int32x2_t vl_hi = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_hi));
	vl_lo = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_lo >> 32)), vl_lo, 1);
	vl_hi = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_hi >> 32)), vl_hi, 1);

	vn = vsubq_f32(vn, vmagic_bias);
	const int32x4_t vl = vcombine_s32(vl_lo, vl_hi);

	$if FMA:
	float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2);
	$else:
	float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2_hi);
	vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo);
	float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vl, ven));

	float32x4_t vp = ${VMULADDQ_F32}(vc2, vc3, vt);
	vp = vmulq_f32(vp, vt);

	vt = vmulq_f32(vt, vs);
	vs = vsubq_f32(vs, vone);
	vp = ${VMULADDQ_F32}(vt, vp, vt);
	const float32x4_t ve = vmulq_f32(vaddq_f32(vp, vs), valpha);

	const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f));
	vx = vmulq_f32(vx, vbeta);
	const float32x4_t vy = vbslq_f32(vm, ve, vx);

	vst1q_f32(y, vy); y += 4;
	}
	if XNN_UNLIKELY(n != 0) {
	float32x4_t vx = vld1q_f32(x);

	const float32x4_t vz = vmaxq_f32(vmulq_f32(vx, vprescale), vsat_cutoff);

	float32x4_t vn = ${VMULADDQ_F32}(vmagic_bias, vz, vlog2e);
	const uint64x2_t vidx = vreinterpretq_u64_s32(vshlq_n_s32(vandq_s32(vreinterpretq_s32_f32(vn), vindex_mask), 2));
	const int32x4_t ven = vshlq_n_s32(vreinterpretq_s32_f32(vn), 19);

	const uint64_t vidx_lo = vgetq_lane_u64(vidx, 0);
	const uint64_t vidx_hi = vgetq_lane_u64(vidx, 1);
	int32x2_t vl_lo = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_lo));
	int32x2_t vl_hi = vld1_dup_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) vidx_hi));
	vl_lo = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_lo >> 32)), vl_lo, 1);
	vl_hi = vld1_lane_s32((const int32_t*) ((uintptr_t) xnn_table_exp2minus_k_over_16 + (uint32_t) (vidx_hi >> 32)), vl_hi, 1);

	vn = vsubq_f32(vn, vmagic_bias);
	const int32x4_t vl = vcombine_s32(vl_lo, vl_hi);

	$if FMA:
	float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2);
	$else:
	float32x4_t vt = ${VMULADDQ_F32}(vz, vn, vminus_ln2_hi);
	vt = ${VMULADDQ_F32}(vt, vn, vminus_ln2_lo);
	float32x4_t vs = vreinterpretq_f32_s32(vaddq_s32(vl, ven));

	float32x4_t vp = ${VMULADDQ_F32}(vc2, vc3, vt);
	vp = vmulq_f32(vp, vt);

	vt = vmulq_f32(vt, vs);
	vs = vsubq_f32(vs, vone);
	vp = ${VMULADDQ_F32}(vt, vp, vt);
	const float32x4_t ve = vmulq_f32(vaddq_f32(vp, vs), valpha);

	const uint32x4_t vm = vcltq_f32(vx, vmovq_n_f32(0.0f));
	vx = vmulq_f32(vx, vbeta);
	const float32x4_t vy = vbslq_f32(vm, ve, vx);

	float32x2_t vy_lo = vget_low_f32(vy);
	if (n & (2 * sizeof(float))) {
	vst1_f32(y, vy_lo); y += 2;
	vy_lo = vget_high_f32(vy);
	}
	if (n & (1 * sizeof(float))) {
	vst1_lane_f32(y, vy_lo, 0);
	}
	}
	}