| // Auto-generated file. Do not edit! |
| // Template: src/f32-vsigmoid/avx2-rr1-p5.c.in |
| // Generator: tools/xngen |
| // |
| // Copyright 2019 Google LLC |
| // |
| // This source code is licensed under the BSD-style license found in the |
| // LICENSE file in the root directory of this source tree. |
| |
| #include <assert.h> |
| |
| #include <immintrin.h> |
| |
| #include <xnnpack/common.h> |
| #include <xnnpack/vunary.h> |
| |
| |
| void xnn_f32_vsigmoid_ukernel__avx2_rr1_p5_nr1fma_x56( |
| size_t n, |
| const float* x, |
| float* y, |
| const union xnn_f32_sigmoid_params params[restrict XNN_MIN_ELEMENTS(1)]) |
| { |
| assert(n % sizeof(float) == 0); |
| |
| const __m256 vsign_mask = _mm256_load_ps(params->avx2_rr1_p5.sign_mask); |
| const __m256 vmagic_bias = _mm256_load_ps(params->avx2_rr1_p5.magic_bias); |
| const __m256 vlog2e = _mm256_load_ps(params->avx2_rr1_p5.log2e); |
| const __m256 vminus_ln2 = _mm256_load_ps(params->avx2_rr1_p5.minus_ln2); |
| const __m256 vc5 = _mm256_load_ps(params->avx2_rr1_p5.c5); |
| const __m256 vc4 = _mm256_load_ps(params->avx2_rr1_p5.c4); |
| const __m256 vc3 = _mm256_load_ps(params->avx2_rr1_p5.c3); |
| const __m256 vc2 = _mm256_load_ps(params->avx2_rr1_p5.c2); |
| const __m256 vc1 = _mm256_load_ps(params->avx2_rr1_p5.c1); |
| const __m256 vone = _mm256_load_ps(params->avx2_rr1_p5.one); |
| const __m256 vdenorm_cutoff = _mm256_load_ps(params->avx2_rr1_p5.denorm_cutoff); |
| |
| for (; n >= 56 * sizeof(float); n -= 56 * sizeof(float)) { |
| const __m256 vx0 = _mm256_loadu_ps(x); |
| const __m256 vx1 = _mm256_loadu_ps(x + 8); |
| const __m256 vx2 = _mm256_loadu_ps(x + 16); |
| const __m256 vx3 = _mm256_loadu_ps(x + 24); |
| const __m256 vx4 = _mm256_loadu_ps(x + 32); |
| const __m256 vx5 = _mm256_loadu_ps(x + 40); |
| const __m256 vx6 = _mm256_loadu_ps(x + 48); |
| x += 56; |
| |
| const __m256 vz0 = _mm256_or_ps(vx0, vsign_mask); |
| const __m256 vz1 = _mm256_or_ps(vx1, vsign_mask); |
| const __m256 vz2 = _mm256_or_ps(vx2, vsign_mask); |
| const __m256 vz3 = _mm256_or_ps(vx3, vsign_mask); |
| const __m256 vz4 = _mm256_or_ps(vx4, vsign_mask); |
| const __m256 vz5 = _mm256_or_ps(vx5, vsign_mask); |
| const __m256 vz6 = _mm256_or_ps(vx6, vsign_mask); |
| |
| __m256 vn0 = _mm256_fmadd_ps(vz0, vlog2e, vmagic_bias); |
| __m256 vn1 = _mm256_fmadd_ps(vz1, vlog2e, vmagic_bias); |
| __m256 vn2 = _mm256_fmadd_ps(vz2, vlog2e, vmagic_bias); |
| __m256 vn3 = _mm256_fmadd_ps(vz3, vlog2e, vmagic_bias); |
| __m256 vn4 = _mm256_fmadd_ps(vz4, vlog2e, vmagic_bias); |
| __m256 vn5 = _mm256_fmadd_ps(vz5, vlog2e, vmagic_bias); |
| __m256 vn6 = _mm256_fmadd_ps(vz6, vlog2e, vmagic_bias); |
| |
| const __m256 vs0 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn0), 23)); |
| const __m256 vs1 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn1), 23)); |
| const __m256 vs2 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn2), 23)); |
| const __m256 vs3 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn3), 23)); |
| const __m256 vs4 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn4), 23)); |
| const __m256 vs5 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn5), 23)); |
| const __m256 vs6 = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn6), 23)); |
| |
| vn0 = _mm256_sub_ps(vn0, vmagic_bias); |
| vn1 = _mm256_sub_ps(vn1, vmagic_bias); |
| vn2 = _mm256_sub_ps(vn2, vmagic_bias); |
| vn3 = _mm256_sub_ps(vn3, vmagic_bias); |
| vn4 = _mm256_sub_ps(vn4, vmagic_bias); |
| vn5 = _mm256_sub_ps(vn5, vmagic_bias); |
| vn6 = _mm256_sub_ps(vn6, vmagic_bias); |
| |
| __m256 vt0 = _mm256_fmadd_ps(vn0, vminus_ln2, vz0); |
| __m256 vt1 = _mm256_fmadd_ps(vn1, vminus_ln2, vz1); |
| __m256 vt2 = _mm256_fmadd_ps(vn2, vminus_ln2, vz2); |
| __m256 vt3 = _mm256_fmadd_ps(vn3, vminus_ln2, vz3); |
| __m256 vt4 = _mm256_fmadd_ps(vn4, vminus_ln2, vz4); |
| __m256 vt5 = _mm256_fmadd_ps(vn5, vminus_ln2, vz5); |
| __m256 vt6 = _mm256_fmadd_ps(vn6, vminus_ln2, vz6); |
| |
| __m256 vp0 = _mm256_fmadd_ps(vc5, vt0, vc4); |
| __m256 vp1 = _mm256_fmadd_ps(vc5, vt1, vc4); |
| __m256 vp2 = _mm256_fmadd_ps(vc5, vt2, vc4); |
| __m256 vp3 = _mm256_fmadd_ps(vc5, vt3, vc4); |
| __m256 vp4 = _mm256_fmadd_ps(vc5, vt4, vc4); |
| __m256 vp5 = _mm256_fmadd_ps(vc5, vt5, vc4); |
| __m256 vp6 = _mm256_fmadd_ps(vc5, vt6, vc4); |
| |
| vp0 = _mm256_fmadd_ps(vp0, vt0, vc3); |
| vp1 = _mm256_fmadd_ps(vp1, vt1, vc3); |
| vp2 = _mm256_fmadd_ps(vp2, vt2, vc3); |
| vp3 = _mm256_fmadd_ps(vp3, vt3, vc3); |
| vp4 = _mm256_fmadd_ps(vp4, vt4, vc3); |
| vp5 = _mm256_fmadd_ps(vp5, vt5, vc3); |
| vp6 = _mm256_fmadd_ps(vp6, vt6, vc3); |
| |
| vp0 = _mm256_fmadd_ps(vp0, vt0, vc2); |
| vp1 = _mm256_fmadd_ps(vp1, vt1, vc2); |
| vp2 = _mm256_fmadd_ps(vp2, vt2, vc2); |
| vp3 = _mm256_fmadd_ps(vp3, vt3, vc2); |
| vp4 = _mm256_fmadd_ps(vp4, vt4, vc2); |
| vp5 = _mm256_fmadd_ps(vp5, vt5, vc2); |
| vp6 = _mm256_fmadd_ps(vp6, vt6, vc2); |
| |
| vp0 = _mm256_fmadd_ps(vp0, vt0, vc1); |
| vp1 = _mm256_fmadd_ps(vp1, vt1, vc1); |
| vp2 = _mm256_fmadd_ps(vp2, vt2, vc1); |
| vp3 = _mm256_fmadd_ps(vp3, vt3, vc1); |
| vp4 = _mm256_fmadd_ps(vp4, vt4, vc1); |
| vp5 = _mm256_fmadd_ps(vp5, vt5, vc1); |
| vp6 = _mm256_fmadd_ps(vp6, vt6, vc1); |
| |
| vt0 = _mm256_mul_ps(vt0, vs0); |
| vt1 = _mm256_mul_ps(vt1, vs1); |
| vt2 = _mm256_mul_ps(vt2, vs2); |
| vt3 = _mm256_mul_ps(vt3, vs3); |
| vt4 = _mm256_mul_ps(vt4, vs4); |
| vt5 = _mm256_mul_ps(vt5, vs5); |
| vt6 = _mm256_mul_ps(vt6, vs6); |
| |
| const __m256 ve0 = _mm256_fmadd_ps(vt0, vp0, vs0); |
| const __m256 ve1 = _mm256_fmadd_ps(vt1, vp1, vs1); |
| const __m256 ve2 = _mm256_fmadd_ps(vt2, vp2, vs2); |
| const __m256 ve3 = _mm256_fmadd_ps(vt3, vp3, vs3); |
| const __m256 ve4 = _mm256_fmadd_ps(vt4, vp4, vs4); |
| const __m256 ve5 = _mm256_fmadd_ps(vt5, vp5, vs5); |
| const __m256 ve6 = _mm256_fmadd_ps(vt6, vp6, vs6); |
| |
| const __m256 vd0 = _mm256_add_ps(ve0, vone); |
| const __m256 vd1 = _mm256_add_ps(ve1, vone); |
| const __m256 vd2 = _mm256_add_ps(ve2, vone); |
| const __m256 vd3 = _mm256_add_ps(ve3, vone); |
| const __m256 vd4 = _mm256_add_ps(ve4, vone); |
| const __m256 vd5 = _mm256_add_ps(ve5, vone); |
| const __m256 vd6 = _mm256_add_ps(ve6, vone); |
| |
| __m256 vr0 = _mm256_rcp_ps(vd0); |
| __m256 vr1 = _mm256_rcp_ps(vd1); |
| __m256 vr2 = _mm256_rcp_ps(vd2); |
| __m256 vr3 = _mm256_rcp_ps(vd3); |
| __m256 vr4 = _mm256_rcp_ps(vd4); |
| __m256 vr5 = _mm256_rcp_ps(vd5); |
| __m256 vr6 = _mm256_rcp_ps(vd6); |
| |
| vr0 = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr0, vd0, vone), vr0, vr0); |
| vr1 = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr1, vd1, vone), vr1, vr1); |
| vr2 = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr2, vd2, vone), vr2, vr2); |
| vr3 = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr3, vd3, vone), vr3, vr3); |
| vr4 = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr4, vd4, vone), vr4, vr4); |
| vr5 = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr5, vd5, vone), vr5, vr5); |
| vr6 = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr6, vd6, vone), vr6, vr6); |
| |
| |
| __m256 vf0 = _mm256_mul_ps(ve0, vr0); |
| __m256 vf1 = _mm256_mul_ps(ve1, vr1); |
| __m256 vf2 = _mm256_mul_ps(ve2, vr2); |
| __m256 vf3 = _mm256_mul_ps(ve3, vr3); |
| __m256 vf4 = _mm256_mul_ps(ve4, vr4); |
| __m256 vf5 = _mm256_mul_ps(ve5, vr5); |
| __m256 vf6 = _mm256_mul_ps(ve6, vr6); |
| |
| vf0 = _mm256_andnot_ps(_mm256_cmp_ps(vz0, vdenorm_cutoff, _CMP_LT_OS), vf0); |
| vf1 = _mm256_andnot_ps(_mm256_cmp_ps(vz1, vdenorm_cutoff, _CMP_LT_OS), vf1); |
| vf2 = _mm256_andnot_ps(_mm256_cmp_ps(vz2, vdenorm_cutoff, _CMP_LT_OS), vf2); |
| vf3 = _mm256_andnot_ps(_mm256_cmp_ps(vz3, vdenorm_cutoff, _CMP_LT_OS), vf3); |
| vf4 = _mm256_andnot_ps(_mm256_cmp_ps(vz4, vdenorm_cutoff, _CMP_LT_OS), vf4); |
| vf5 = _mm256_andnot_ps(_mm256_cmp_ps(vz5, vdenorm_cutoff, _CMP_LT_OS), vf5); |
| vf6 = _mm256_andnot_ps(_mm256_cmp_ps(vz6, vdenorm_cutoff, _CMP_LT_OS), vf6); |
| |
| vf0 = _mm256_blendv_ps(_mm256_sub_ps(vone, vf0), vf0, vx0); |
| vf1 = _mm256_blendv_ps(_mm256_sub_ps(vone, vf1), vf1, vx1); |
| vf2 = _mm256_blendv_ps(_mm256_sub_ps(vone, vf2), vf2, vx2); |
| vf3 = _mm256_blendv_ps(_mm256_sub_ps(vone, vf3), vf3, vx3); |
| vf4 = _mm256_blendv_ps(_mm256_sub_ps(vone, vf4), vf4, vx4); |
| vf5 = _mm256_blendv_ps(_mm256_sub_ps(vone, vf5), vf5, vx5); |
| vf6 = _mm256_blendv_ps(_mm256_sub_ps(vone, vf6), vf6, vx6); |
| |
| _mm256_storeu_ps(y, vf0); |
| _mm256_storeu_ps(y + 8, vf1); |
| _mm256_storeu_ps(y + 16, vf2); |
| _mm256_storeu_ps(y + 24, vf3); |
| _mm256_storeu_ps(y + 32, vf4); |
| _mm256_storeu_ps(y + 40, vf5); |
| _mm256_storeu_ps(y + 48, vf6); |
| y += 56; |
| } |
| for (; n >= 8 * sizeof(float); n -= 8 * sizeof(float)) { |
| const __m256 vx = _mm256_loadu_ps(x); |
| x += 8; |
| |
| const __m256 vz = _mm256_or_ps(vx, vsign_mask); |
| |
| __m256 vn = _mm256_fmadd_ps(vz, vlog2e, vmagic_bias); |
| const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23)); |
| vn = _mm256_sub_ps(vn, vmagic_bias); |
| |
| __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vz); |
| |
| __m256 vp = _mm256_fmadd_ps(vc5, vt, vc4); |
| vp = _mm256_fmadd_ps(vp, vt, vc3); |
| vp = _mm256_fmadd_ps(vp, vt, vc2); |
| vp = _mm256_fmadd_ps(vp, vt, vc1); |
| |
| vt = _mm256_mul_ps(vt, vs); |
| const __m256 ve = _mm256_fmadd_ps(vt, vp, vs); |
| |
| const __m256 vd = _mm256_add_ps(ve, vone); |
| __m256 vr = _mm256_rcp_ps(vd); |
| vr = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr, vd, vone), vr, vr); |
| __m256 vf = _mm256_mul_ps(ve, vr); |
| |
| vf = _mm256_andnot_ps(_mm256_cmp_ps(vz, vdenorm_cutoff, _CMP_LT_OS), vf); |
| vf = _mm256_blendv_ps(_mm256_sub_ps(vone, vf), vf, vx); |
| |
| _mm256_storeu_ps(y, vf); |
| y += 8; |
| } |
| if XNN_UNLIKELY(n != 0) { |
| assert(n >= 1 * sizeof(float)); |
| assert(n <= 7 * sizeof(float)); |
| const __m256i vmask = _mm256_loadu_si256((const __m256i*) ((uintptr_t) ¶ms->avx2_rr1_p5.mask_table[7] - n)); |
| |
| const __m256 vx = _mm256_maskload_ps(x, vmask); |
| |
| const __m256 vz = _mm256_or_ps(vx, vsign_mask); |
| |
| __m256 vn = _mm256_fmadd_ps(vz, vlog2e, vmagic_bias); |
| const __m256 vs = _mm256_castsi256_ps(_mm256_slli_epi32(_mm256_castps_si256(vn), 23)); |
| vn = _mm256_sub_ps(vn, vmagic_bias); |
| |
| __m256 vt = _mm256_fmadd_ps(vn, vminus_ln2, vz); |
| |
| __m256 vp = _mm256_fmadd_ps(vc5, vt, vc4); |
| vp = _mm256_fmadd_ps(vp, vt, vc3); |
| vp = _mm256_fmadd_ps(vp, vt, vc2); |
| vp = _mm256_fmadd_ps(vp, vt, vc1); |
| |
| vt = _mm256_mul_ps(vt, vs); |
| const __m256 ve = _mm256_fmadd_ps(vt, vp, vs); |
| |
| const __m256 vd = _mm256_add_ps(ve, vone); |
| __m256 vr = _mm256_rcp_ps(vd); |
| vr = _mm256_fmadd_ps(_mm256_fnmadd_ps(vr, vd, vone), vr, vr); |
| __m256 vf = _mm256_mul_ps(ve, vr); |
| |
| vf = _mm256_andnot_ps(_mm256_cmp_ps(vz, vdenorm_cutoff, _CMP_LT_OS), vf); |
| vf = _mm256_blendv_ps(_mm256_sub_ps(vone, vf), vf, vx); |
| |
| __m128 vf_lo = _mm256_castps256_ps128(vf); |
| if (n & (4 * sizeof(float))) { |
| _mm_storeu_ps(y, vf_lo); |
| vf_lo = _mm256_extractf128_ps(vf, 1); |
| y += 4; |
| } |
| if (n & (2 * sizeof(float))) { |
| _mm_storel_pi((__m64*) y, vf_lo); |
| vf_lo = _mm_movehl_ps(vf_lo, vf_lo); |
| y += 2; |
| } |
| if (n & (1 * sizeof(float))) { |
| _mm_store_ss(y, vf_lo); |
| } |
| } |
| } |