Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 1 | // Copyright 2019 Google LLC |
| 2 | // |
| 3 | // This source code is licensed under the BSD-style license found in the |
| 4 | // LICENSE file in the root directory of this source tree. |
| 5 | |
| 6 | #include <algorithm> |
| 7 | #include <cmath> |
| 8 | #include <functional> |
| 9 | #include <random> |
| 10 | #include <vector> |
| 11 | |
| 12 | #include <xnnpack.h> |
| 13 | |
| 14 | #include <benchmark/benchmark.h> |
| 15 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 16 | #include "bench/end2end.h" |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 17 | #include "bench/utils.h" |
| 18 | #include "models/models.h" |
| 19 | #include <xnnpack/dwconv.h> |
| 20 | #include <xnnpack/params.h> |
| 21 | |
| 22 | |
| 23 | static void DWConvEnd2EndBenchmark( |
| 24 | benchmark::State& state, |
Marat Dukhan | aefaef3 | 2020-04-09 07:09:34 -0700 | [diff] [blame] | 25 | models::ExecutionPlanFactory model_factory, |
Marat Dukhan | 163a7e6 | 2020-04-09 04:19:26 -0700 | [diff] [blame] | 26 | xnn_f32_dwconv_minmax_unipass_ukernel_function dwconv, |
Marat Dukhan | aefaef3 | 2020-04-09 07:09:34 -0700 | [diff] [blame] | 27 | uint8_t channel_tile, uint8_t primary_tile, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 28 | benchmark::utils::IsaCheckFunction isa_check = nullptr) |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 29 | { |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 30 | if (isa_check && !isa_check(state)) { |
| 31 | return; |
| 32 | } |
Marat Dukhan | 04f03be | 2019-11-19 12:36:47 -0800 | [diff] [blame] | 33 | if (xnn_initialize(nullptr /* allocator */) != xnn_status_success) { |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 34 | state.SkipWithError("failed to initialize XNNPACK"); |
| 35 | return; |
| 36 | } |
| 37 | |
| 38 | // Override microkernels chosen in xnn_initialize |
| 39 | for (size_t i = 0; i < XNN_MAX_F32_DWCONV_UKERNELS; i++) { |
| 40 | // Replace only the microkernel the matching kernel size. |
Marat Dukhan | aefaef3 | 2020-04-09 07:09:34 -0700 | [diff] [blame] | 41 | if (xnn_params.f32.dwconv[i].primary_tile == primary_tile) { |
Marat Dukhan | 99103dc | 2020-03-13 00:16:53 -0700 | [diff] [blame] | 42 | // Note: do not directly assign to xnn_params.f32.dwconv[i] because it breaks older gcc. |
Marat Dukhan | aefaef3 | 2020-04-09 07:09:34 -0700 | [diff] [blame] | 43 | xnn_params.f32.dwconv[i].minmax.unipass = xnn_dwconv_unipass_ukernel_function(dwconv); |
| 44 | xnn_params.f32.dwconv[i].channel_tile = channel_tile; |
| 45 | xnn_params.f32.dwconv[i].primary_tile = primary_tile; |
| 46 | xnn_params.f32.dwconv[i].incremental_tile = 0; |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 47 | break; |
| 48 | } |
| 49 | } |
| 50 | |
| 51 | auto execution_plan = model_factory(nullptr); |
| 52 | if (execution_plan.empty()) { |
| 53 | state.SkipWithError("failed to create a model"); |
| 54 | return; |
| 55 | } |
| 56 | |
| 57 | for (auto _ : state) { |
| 58 | for (const std::unique_ptr<xnn_operator, decltype(&xnn_delete_operator)>& op : execution_plan) { |
| 59 | xnn_status status = xnn_run_operator(op.get(), nullptr); |
| 60 | if (status != xnn_status_success) { |
| 61 | state.SkipWithError("failed to run a model"); |
| 62 | return; |
| 63 | } |
| 64 | } |
| 65 | } |
| 66 | state.counters["Freq"] = benchmark::utils::GetCurrentCpuFrequency(); |
| 67 | } |
| 68 | |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 69 | #if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY |
| 70 | static void f32_dwconv_up4x9__aarch64_neonfma(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 71 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 72 | xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma, |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 73 | 4 /* cr */, 9 /* mr */); |
| 74 | } |
| 75 | |
| 76 | static void f32_dwconv_up4x9__aarch64_neonfma_cortex_a55(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 77 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 78 | xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55, |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 79 | 4 /* cr */, 9 /* mr */); |
| 80 | } |
| 81 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 82 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__aarch64_neonfma); |
| 83 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 84 | #endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY |
| 85 | |
| 86 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 87 | static void f32_dwconv_up4x9__neon(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 88 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 89 | xnn_f32_dwconv_minmax_ukernel_up4x9__neon, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 90 | 4 /* cr */, 9 /* mr */, benchmark::utils::CheckNEON); |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 91 | } |
| 92 | |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 93 | static void f32_dwconv_up4x9__neon_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 94 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 95 | xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 96 | 4 /* cr */, 9 /* mr */, benchmark::utils::CheckNEON); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | static void f32_dwconv_up8x9__neon(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 100 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 101 | xnn_f32_dwconv_minmax_ukernel_up8x9__neon, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 102 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckNEON); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | static void f32_dwconv_up8x9__neon_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 106 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 107 | xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 108 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckNEON); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 109 | } |
| 110 | |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 111 | static void f32_dwconv_up4x9__neonfma(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 112 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 113 | xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 114 | 4 /* cr */, 9 /* mr */, benchmark::utils::CheckNEONFMA); |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 115 | } |
| 116 | |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 117 | static void f32_dwconv_up4x9__neonfma_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 118 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 119 | xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 120 | 4 /* cr */, 9 /* mr */, benchmark::utils::CheckNEONFMA); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 121 | } |
| 122 | |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 123 | static void f32_dwconv_up8x9__neonfma(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 124 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 125 | xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 126 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckNEONFMA); |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 127 | } |
| 128 | |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 129 | static void f32_dwconv_up8x9__neonfma_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 130 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 131 | xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 132 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckNEONFMA); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 133 | } |
| 134 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 135 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__neon); |
| 136 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__neon_acc2); |
| 137 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__neon); |
| 138 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__neon_acc2); |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 139 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 140 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__neonfma); |
| 141 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__neonfma_acc2); |
| 142 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__neonfma); |
| 143 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__neonfma_acc2); |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 144 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 145 | |
| 146 | |
| 147 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 148 | static void f32_dwconv_up4x9__sse(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 149 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 150 | xnn_f32_dwconv_minmax_ukernel_up4x9__sse, |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 151 | 4 /* cr */, 9 /* mr */); |
| 152 | } |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 153 | static void f32_dwconv_up4x9__sse_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 154 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 155 | xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2, |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 156 | 4 /* cr */, 9 /* mr */); |
| 157 | } |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 158 | static void f32_dwconv_up8x9__sse(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 159 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 160 | xnn_f32_dwconv_minmax_ukernel_up8x9__sse, |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 161 | 8 /* cr */, 9 /* mr */); |
| 162 | } |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 163 | static void f32_dwconv_up8x9__sse_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 164 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 165 | xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2, |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 166 | 8 /* cr */, 9 /* mr */); |
| 167 | } |
| 168 | |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 169 | static void f32_dwconv_up8x9__avx(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 170 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 171 | xnn_f32_dwconv_minmax_ukernel_up8x9__avx, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 172 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 173 | } |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 174 | static void f32_dwconv_up8x9__avx_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 175 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 176 | xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 177 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 178 | } |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 179 | static void f32_dwconv_up16x9__avx(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 180 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 181 | xnn_f32_dwconv_minmax_ukernel_up16x9__avx, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 182 | 16 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 183 | } |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 184 | static void f32_dwconv_up16x9__avx_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 185 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 186 | xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 187 | 16 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | static void f32_dwconv_up8x9__fma3(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 191 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 192 | xnn_f32_dwconv_minmax_ukernel_up8x9__fma3, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 193 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckFMA3); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 194 | } |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 195 | static void f32_dwconv_up8x9__fma3_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 196 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 197 | xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 198 | 8 /* cr */, 9 /* mr */, benchmark::utils::CheckFMA3); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 199 | } |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 200 | static void f32_dwconv_up16x9__fma3(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 201 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 202 | xnn_f32_dwconv_minmax_ukernel_up16x9__fma3, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 203 | 16 /* cr */, 9 /* mr */, benchmark::utils::CheckFMA3); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 204 | } |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 205 | static void f32_dwconv_up16x9__fma3_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 206 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 207 | xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2, |
Marat Dukhan | c8466f5 | 2019-11-25 18:01:10 -0800 | [diff] [blame] | 208 | 16 /* cr */, 9 /* mr */, benchmark::utils::CheckFMA3); |
Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame] | 209 | } |
| 210 | |
Marat Dukhan | 479f87e | 2019-11-27 15:17:06 -0800 | [diff] [blame] | 211 | static void f32_dwconv_up16x9__avx512f(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 212 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 213 | xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f, |
Marat Dukhan | 479f87e | 2019-11-27 15:17:06 -0800 | [diff] [blame] | 214 | 16 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX512F); |
| 215 | } |
| 216 | static void f32_dwconv_up16x9__avx512f_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 217 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 218 | xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2, |
Marat Dukhan | 479f87e | 2019-11-27 15:17:06 -0800 | [diff] [blame] | 219 | 16 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX512F); |
| 220 | } |
| 221 | static void f32_dwconv_up32x9__avx512f(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 222 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 223 | xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f, |
Marat Dukhan | 479f87e | 2019-11-27 15:17:06 -0800 | [diff] [blame] | 224 | 32 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX512F); |
| 225 | } |
| 226 | static void f32_dwconv_up32x9__avx512f_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 227 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 228 | xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2, |
Marat Dukhan | 479f87e | 2019-11-27 15:17:06 -0800 | [diff] [blame] | 229 | 32 /* cr */, 9 /* mr */, benchmark::utils::CheckAVX512F); |
| 230 | } |
| 231 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 232 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__sse); |
| 233 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__sse_acc2); |
| 234 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__sse); |
| 235 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__sse_acc2); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 236 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 237 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__avx); |
| 238 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__avx_acc2); |
| 239 | BENCHMARK_FP32_END2END(f32_dwconv_up16x9__avx); |
| 240 | BENCHMARK_FP32_END2END(f32_dwconv_up16x9__avx_acc2); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 241 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 242 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__fma3); |
| 243 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__fma3_acc2); |
| 244 | BENCHMARK_FP32_END2END(f32_dwconv_up16x9__fma3); |
| 245 | BENCHMARK_FP32_END2END(f32_dwconv_up16x9__fma3_acc2); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 246 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 247 | BENCHMARK_FP32_END2END(f32_dwconv_up16x9__avx512f); |
| 248 | BENCHMARK_FP32_END2END(f32_dwconv_up16x9__avx512f_acc2); |
| 249 | BENCHMARK_FP32_END2END(f32_dwconv_up32x9__avx512f); |
| 250 | BENCHMARK_FP32_END2END(f32_dwconv_up32x9__avx512f_acc2); |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 251 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 252 | |
Marat Dukhan | ac014d7 | 2020-06-16 08:36:47 -0700 | [diff] [blame] | 253 | #if XNN_ARCH_WASMSIMD |
| 254 | static void f32_dwconv_up4x9__wasmsimd_arm(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 255 | DWConvEnd2EndBenchmark(state, model, |
| 256 | xnn_f32_dwconv_minmax_ukernel_up4x9__wasmsimd_arm, |
| 257 | 4 /* cr */, 9 /* mr */); |
| 258 | } |
| 259 | |
| 260 | static void f32_dwconv_up4x9__wasmsimd_acc2_arm(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 261 | DWConvEnd2EndBenchmark(state, model, |
| 262 | xnn_f32_dwconv_minmax_ukernel_up4x9__wasmsimd_acc2_arm, |
| 263 | 4 /* cr */, 9 /* mr */); |
| 264 | } |
| 265 | |
| 266 | static void f32_dwconv_up8x9__wasmsimd_arm(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 267 | DWConvEnd2EndBenchmark(state, model, |
| 268 | xnn_f32_dwconv_minmax_ukernel_up8x9__wasmsimd_arm, |
| 269 | 8 /* cr */, 9 /* mr */); |
| 270 | } |
| 271 | |
| 272 | static void f32_dwconv_up8x9__wasmsimd_acc2_arm(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 273 | DWConvEnd2EndBenchmark(state, model, |
| 274 | xnn_f32_dwconv_minmax_ukernel_up8x9__wasmsimd_acc2_arm, |
| 275 | 8 /* cr */, 9 /* mr */); |
| 276 | } |
| 277 | |
| 278 | static void f32_dwconv_up4x9__wasmsimd_x86(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 279 | DWConvEnd2EndBenchmark(state, model, |
| 280 | xnn_f32_dwconv_minmax_ukernel_up4x9__wasmsimd_x86, |
| 281 | 4 /* cr */, 9 /* mr */); |
| 282 | } |
| 283 | |
| 284 | static void f32_dwconv_up4x9__wasmsimd_acc2_x86(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 285 | DWConvEnd2EndBenchmark(state, model, |
| 286 | xnn_f32_dwconv_minmax_ukernel_up4x9__wasmsimd_acc2_x86, |
| 287 | 4 /* cr */, 9 /* mr */); |
| 288 | } |
| 289 | |
| 290 | static void f32_dwconv_up8x9__wasmsimd_x86(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 291 | DWConvEnd2EndBenchmark(state, model, |
| 292 | xnn_f32_dwconv_minmax_ukernel_up8x9__wasmsimd_x86, |
| 293 | 8 /* cr */, 9 /* mr */); |
| 294 | } |
| 295 | |
| 296 | static void f32_dwconv_up8x9__wasmsimd_acc2_x86(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 297 | DWConvEnd2EndBenchmark(state, model, |
| 298 | xnn_f32_dwconv_minmax_ukernel_up8x9__wasmsimd_acc2_x86, |
| 299 | 8 /* cr */, 9 /* mr */); |
| 300 | } |
| 301 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 302 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__wasmsimd_arm); |
| 303 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__wasmsimd_acc2_arm); |
| 304 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__wasmsimd_arm); |
| 305 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__wasmsimd_acc2_arm); |
Marat Dukhan | ac014d7 | 2020-06-16 08:36:47 -0700 | [diff] [blame] | 306 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 307 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__wasmsimd_x86); |
| 308 | BENCHMARK_FP32_END2END(f32_dwconv_up4x9__wasmsimd_acc2_x86); |
| 309 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__wasmsimd_x86); |
| 310 | BENCHMARK_FP32_END2END(f32_dwconv_up8x9__wasmsimd_acc2_x86); |
Marat Dukhan | ac014d7 | 2020-06-16 08:36:47 -0700 | [diff] [blame] | 311 | #endif // XNN_ARCH_WASMSIMD |
| 312 | |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 313 | static void f32_dwconv_up1x9__scalar(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 314 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 315 | xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 316 | 1 /* cr */, 9 /* mr */); |
| 317 | } |
| 318 | |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 319 | static void f32_dwconv_up1x9__scalar_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 320 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 321 | xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 322 | 1 /* cr */, 9 /* mr */); |
| 323 | } |
| 324 | |
| 325 | static void f32_dwconv_up2x9__scalar(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 326 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 327 | xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 328 | 2 /* cr */, 9 /* mr */); |
| 329 | } |
| 330 | |
| 331 | static void f32_dwconv_up2x9__scalar_acc2(benchmark::State& state, models::ExecutionPlanFactory model) { |
| 332 | DWConvEnd2EndBenchmark(state, model, |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 333 | xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 334 | 2 /* cr */, 9 /* mr */); |
| 335 | } |
| 336 | |
Marat Dukhan | 270a2c4 | 2020-06-26 16:45:52 -0700 | [diff] [blame] | 337 | BENCHMARK_FP32_END2END(f32_dwconv_up1x9__scalar); |
| 338 | BENCHMARK_FP32_END2END(f32_dwconv_up1x9__scalar_acc2); |
| 339 | BENCHMARK_FP32_END2END(f32_dwconv_up2x9__scalar); |
| 340 | BENCHMARK_FP32_END2END(f32_dwconv_up2x9__scalar_acc2); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 341 | |
Marat Dukhan | ef4416e | 2019-10-31 13:44:40 -0700 | [diff] [blame] | 342 | #ifndef XNNPACK_BENCHMARK_NO_MAIN |
| 343 | BENCHMARK_MAIN(); |
| 344 | #endif |