Marat Dukhan | 17ec5f3 | 2019-11-22 13:34:16 -0800 | [diff] [blame^] | 1 | // Auto-generated file. Do not edit! |
| 2 | // Template: src/f32-dwconv/up-avx.c.in |
| 3 | // Generator: tools/xngen |
| 4 | // |
| 5 | // Copyright 2019 Google LLC |
| 6 | // |
| 7 | // This source code is licensed under the BSD-style license found in the |
| 8 | // LICENSE file in the root directory of this source tree. |
| 9 | |
| 10 | #include <assert.h> |
| 11 | |
| 12 | #include <immintrin.h> |
| 13 | |
| 14 | #include <xnnpack/dwconv.h> |
| 15 | |
| 16 | |
| 17 | static const int32_t mask_table[14] = {-1, -1, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0}; |
| 18 | |
| 19 | void xnn_f32_dwconv_ukernel_up16x25__fma3( |
| 20 | size_t channels, |
| 21 | size_t output_width, |
| 22 | const float** input, |
| 23 | const float* weights, |
| 24 | float* output, |
| 25 | size_t input_stride, |
| 26 | size_t output_increment, |
| 27 | const union xnn_f32_output_params params[restrict static 1]) |
| 28 | { |
| 29 | assert(channels != 0); |
| 30 | assert(output_width != 0); |
| 31 | |
| 32 | const __m256 vmax = _mm256_broadcast_ps((const __m128*) params->sse.max); |
| 33 | const __m256 vmin = _mm256_broadcast_ps((const __m128*) params->sse.min); |
| 34 | do { |
| 35 | const float* i0 = input[0]; |
| 36 | const float* i1 = input[1]; |
| 37 | const float* i2 = input[2]; |
| 38 | const float* i3 = input[3]; |
| 39 | const float* i4 = input[4]; |
| 40 | const float* i5 = input[5]; |
| 41 | const float* i6 = input[6]; |
| 42 | const float* i7 = input[7]; |
| 43 | const float* i8 = input[8]; |
| 44 | const float* i9 = input[9]; |
| 45 | const float* i10 = input[10]; |
| 46 | const float* i11 = input[11]; |
| 47 | const float* i12 = input[12]; |
| 48 | const float* i13 = input[13]; |
| 49 | const float* i14 = input[14]; |
| 50 | const float* i15 = input[15]; |
| 51 | const float* i16 = input[16]; |
| 52 | const float* i17 = input[17]; |
| 53 | const float* i18 = input[18]; |
| 54 | const float* i19 = input[19]; |
| 55 | const float* i20 = input[20]; |
| 56 | const float* i21 = input[21]; |
| 57 | const float* i22 = input[22]; |
| 58 | const float* i23 = input[23]; |
| 59 | const float* i24 = input[24]; |
| 60 | input = (const float**) ((uintptr_t) input + input_stride); |
| 61 | |
| 62 | size_t c = channels; |
| 63 | const float* w = weights; |
| 64 | for (; c >= 16; c -= 16) { |
| 65 | __m256 vacc01234567p0 = _mm256_load_ps(w); |
| 66 | __m256 vacc89ABCDEFp0 = _mm256_load_ps(w + 8); |
| 67 | |
| 68 | |
| 69 | const __m256 vi0x01234567 = _mm256_loadu_ps(i0); |
| 70 | const __m256 vi0x89ABCDEF = _mm256_loadu_ps(i0 + 8); |
| 71 | i0 += 16; |
| 72 | |
| 73 | const __m256 vk0x01234567 = _mm256_load_ps(w + 16); |
| 74 | const __m256 vk0x89ABCDEF = _mm256_load_ps(w + 24); |
| 75 | vacc01234567p0 = _mm256_fmadd_ps(vi0x01234567, vk0x01234567, vacc01234567p0); |
| 76 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi0x89ABCDEF, vk0x89ABCDEF, vacc89ABCDEFp0); |
| 77 | |
| 78 | const __m256 vi1x01234567 = _mm256_loadu_ps(i1); |
| 79 | const __m256 vi1x89ABCDEF = _mm256_loadu_ps(i1 + 8); |
| 80 | i1 += 16; |
| 81 | |
| 82 | const __m256 vk1x01234567 = _mm256_load_ps(w + 32); |
| 83 | const __m256 vk1x89ABCDEF = _mm256_load_ps(w + 40); |
| 84 | vacc01234567p0 = _mm256_fmadd_ps(vi1x01234567, vk1x01234567, vacc01234567p0); |
| 85 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi1x89ABCDEF, vk1x89ABCDEF, vacc89ABCDEFp0); |
| 86 | |
| 87 | const __m256 vi2x01234567 = _mm256_loadu_ps(i2); |
| 88 | const __m256 vi2x89ABCDEF = _mm256_loadu_ps(i2 + 8); |
| 89 | i2 += 16; |
| 90 | |
| 91 | const __m256 vk2x01234567 = _mm256_load_ps(w + 48); |
| 92 | const __m256 vk2x89ABCDEF = _mm256_load_ps(w + 56); |
| 93 | vacc01234567p0 = _mm256_fmadd_ps(vi2x01234567, vk2x01234567, vacc01234567p0); |
| 94 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi2x89ABCDEF, vk2x89ABCDEF, vacc89ABCDEFp0); |
| 95 | |
| 96 | const __m256 vi3x01234567 = _mm256_loadu_ps(i3); |
| 97 | const __m256 vi3x89ABCDEF = _mm256_loadu_ps(i3 + 8); |
| 98 | i3 += 16; |
| 99 | |
| 100 | const __m256 vk3x01234567 = _mm256_load_ps(w + 64); |
| 101 | const __m256 vk3x89ABCDEF = _mm256_load_ps(w + 72); |
| 102 | vacc01234567p0 = _mm256_fmadd_ps(vi3x01234567, vk3x01234567, vacc01234567p0); |
| 103 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi3x89ABCDEF, vk3x89ABCDEF, vacc89ABCDEFp0); |
| 104 | |
| 105 | const __m256 vi4x01234567 = _mm256_loadu_ps(i4); |
| 106 | const __m256 vi4x89ABCDEF = _mm256_loadu_ps(i4 + 8); |
| 107 | i4 += 16; |
| 108 | |
| 109 | const __m256 vk4x01234567 = _mm256_load_ps(w + 80); |
| 110 | const __m256 vk4x89ABCDEF = _mm256_load_ps(w + 88); |
| 111 | vacc01234567p0 = _mm256_fmadd_ps(vi4x01234567, vk4x01234567, vacc01234567p0); |
| 112 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi4x89ABCDEF, vk4x89ABCDEF, vacc89ABCDEFp0); |
| 113 | |
| 114 | const __m256 vi5x01234567 = _mm256_loadu_ps(i5); |
| 115 | const __m256 vi5x89ABCDEF = _mm256_loadu_ps(i5 + 8); |
| 116 | i5 += 16; |
| 117 | |
| 118 | const __m256 vk5x01234567 = _mm256_load_ps(w + 96); |
| 119 | const __m256 vk5x89ABCDEF = _mm256_load_ps(w + 104); |
| 120 | vacc01234567p0 = _mm256_fmadd_ps(vi5x01234567, vk5x01234567, vacc01234567p0); |
| 121 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi5x89ABCDEF, vk5x89ABCDEF, vacc89ABCDEFp0); |
| 122 | |
| 123 | const __m256 vi6x01234567 = _mm256_loadu_ps(i6); |
| 124 | const __m256 vi6x89ABCDEF = _mm256_loadu_ps(i6 + 8); |
| 125 | i6 += 16; |
| 126 | |
| 127 | const __m256 vk6x01234567 = _mm256_load_ps(w + 112); |
| 128 | const __m256 vk6x89ABCDEF = _mm256_load_ps(w + 120); |
| 129 | vacc01234567p0 = _mm256_fmadd_ps(vi6x01234567, vk6x01234567, vacc01234567p0); |
| 130 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi6x89ABCDEF, vk6x89ABCDEF, vacc89ABCDEFp0); |
| 131 | |
| 132 | const __m256 vi7x01234567 = _mm256_loadu_ps(i7); |
| 133 | const __m256 vi7x89ABCDEF = _mm256_loadu_ps(i7 + 8); |
| 134 | i7 += 16; |
| 135 | |
| 136 | const __m256 vk7x01234567 = _mm256_load_ps(w + 128); |
| 137 | const __m256 vk7x89ABCDEF = _mm256_load_ps(w + 136); |
| 138 | vacc01234567p0 = _mm256_fmadd_ps(vi7x01234567, vk7x01234567, vacc01234567p0); |
| 139 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi7x89ABCDEF, vk7x89ABCDEF, vacc89ABCDEFp0); |
| 140 | |
| 141 | const __m256 vi8x01234567 = _mm256_loadu_ps(i8); |
| 142 | const __m256 vi8x89ABCDEF = _mm256_loadu_ps(i8 + 8); |
| 143 | i8 += 16; |
| 144 | |
| 145 | const __m256 vk8x01234567 = _mm256_load_ps(w + 144); |
| 146 | const __m256 vk8x89ABCDEF = _mm256_load_ps(w + 152); |
| 147 | vacc01234567p0 = _mm256_fmadd_ps(vi8x01234567, vk8x01234567, vacc01234567p0); |
| 148 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi8x89ABCDEF, vk8x89ABCDEF, vacc89ABCDEFp0); |
| 149 | |
| 150 | const __m256 vi9x01234567 = _mm256_loadu_ps(i9); |
| 151 | const __m256 vi9x89ABCDEF = _mm256_loadu_ps(i9 + 8); |
| 152 | i9 += 16; |
| 153 | |
| 154 | const __m256 vk9x01234567 = _mm256_load_ps(w + 160); |
| 155 | const __m256 vk9x89ABCDEF = _mm256_load_ps(w + 168); |
| 156 | vacc01234567p0 = _mm256_fmadd_ps(vi9x01234567, vk9x01234567, vacc01234567p0); |
| 157 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi9x89ABCDEF, vk9x89ABCDEF, vacc89ABCDEFp0); |
| 158 | |
| 159 | const __m256 vi10x01234567 = _mm256_loadu_ps(i10); |
| 160 | const __m256 vi10x89ABCDEF = _mm256_loadu_ps(i10 + 8); |
| 161 | i10 += 16; |
| 162 | |
| 163 | const __m256 vk10x01234567 = _mm256_load_ps(w + 176); |
| 164 | const __m256 vk10x89ABCDEF = _mm256_load_ps(w + 184); |
| 165 | vacc01234567p0 = _mm256_fmadd_ps(vi10x01234567, vk10x01234567, vacc01234567p0); |
| 166 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi10x89ABCDEF, vk10x89ABCDEF, vacc89ABCDEFp0); |
| 167 | |
| 168 | const __m256 vi11x01234567 = _mm256_loadu_ps(i11); |
| 169 | const __m256 vi11x89ABCDEF = _mm256_loadu_ps(i11 + 8); |
| 170 | i11 += 16; |
| 171 | |
| 172 | const __m256 vk11x01234567 = _mm256_load_ps(w + 192); |
| 173 | const __m256 vk11x89ABCDEF = _mm256_load_ps(w + 200); |
| 174 | vacc01234567p0 = _mm256_fmadd_ps(vi11x01234567, vk11x01234567, vacc01234567p0); |
| 175 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi11x89ABCDEF, vk11x89ABCDEF, vacc89ABCDEFp0); |
| 176 | |
| 177 | const __m256 vi12x01234567 = _mm256_loadu_ps(i12); |
| 178 | const __m256 vi12x89ABCDEF = _mm256_loadu_ps(i12 + 8); |
| 179 | i12 += 16; |
| 180 | |
| 181 | const __m256 vk12x01234567 = _mm256_load_ps(w + 208); |
| 182 | const __m256 vk12x89ABCDEF = _mm256_load_ps(w + 216); |
| 183 | vacc01234567p0 = _mm256_fmadd_ps(vi12x01234567, vk12x01234567, vacc01234567p0); |
| 184 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi12x89ABCDEF, vk12x89ABCDEF, vacc89ABCDEFp0); |
| 185 | |
| 186 | const __m256 vi13x01234567 = _mm256_loadu_ps(i13); |
| 187 | const __m256 vi13x89ABCDEF = _mm256_loadu_ps(i13 + 8); |
| 188 | i13 += 16; |
| 189 | |
| 190 | const __m256 vk13x01234567 = _mm256_load_ps(w + 224); |
| 191 | const __m256 vk13x89ABCDEF = _mm256_load_ps(w + 232); |
| 192 | vacc01234567p0 = _mm256_fmadd_ps(vi13x01234567, vk13x01234567, vacc01234567p0); |
| 193 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi13x89ABCDEF, vk13x89ABCDEF, vacc89ABCDEFp0); |
| 194 | |
| 195 | const __m256 vi14x01234567 = _mm256_loadu_ps(i14); |
| 196 | const __m256 vi14x89ABCDEF = _mm256_loadu_ps(i14 + 8); |
| 197 | i14 += 16; |
| 198 | |
| 199 | const __m256 vk14x01234567 = _mm256_load_ps(w + 240); |
| 200 | const __m256 vk14x89ABCDEF = _mm256_load_ps(w + 248); |
| 201 | vacc01234567p0 = _mm256_fmadd_ps(vi14x01234567, vk14x01234567, vacc01234567p0); |
| 202 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi14x89ABCDEF, vk14x89ABCDEF, vacc89ABCDEFp0); |
| 203 | |
| 204 | const __m256 vi15x01234567 = _mm256_loadu_ps(i15); |
| 205 | const __m256 vi15x89ABCDEF = _mm256_loadu_ps(i15 + 8); |
| 206 | i15 += 16; |
| 207 | |
| 208 | const __m256 vk15x01234567 = _mm256_load_ps(w + 256); |
| 209 | const __m256 vk15x89ABCDEF = _mm256_load_ps(w + 264); |
| 210 | vacc01234567p0 = _mm256_fmadd_ps(vi15x01234567, vk15x01234567, vacc01234567p0); |
| 211 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi15x89ABCDEF, vk15x89ABCDEF, vacc89ABCDEFp0); |
| 212 | |
| 213 | const __m256 vi16x01234567 = _mm256_loadu_ps(i16); |
| 214 | const __m256 vi16x89ABCDEF = _mm256_loadu_ps(i16 + 8); |
| 215 | i16 += 16; |
| 216 | |
| 217 | const __m256 vk16x01234567 = _mm256_load_ps(w + 272); |
| 218 | const __m256 vk16x89ABCDEF = _mm256_load_ps(w + 280); |
| 219 | vacc01234567p0 = _mm256_fmadd_ps(vi16x01234567, vk16x01234567, vacc01234567p0); |
| 220 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi16x89ABCDEF, vk16x89ABCDEF, vacc89ABCDEFp0); |
| 221 | |
| 222 | const __m256 vi17x01234567 = _mm256_loadu_ps(i17); |
| 223 | const __m256 vi17x89ABCDEF = _mm256_loadu_ps(i17 + 8); |
| 224 | i17 += 16; |
| 225 | |
| 226 | const __m256 vk17x01234567 = _mm256_load_ps(w + 288); |
| 227 | const __m256 vk17x89ABCDEF = _mm256_load_ps(w + 296); |
| 228 | vacc01234567p0 = _mm256_fmadd_ps(vi17x01234567, vk17x01234567, vacc01234567p0); |
| 229 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi17x89ABCDEF, vk17x89ABCDEF, vacc89ABCDEFp0); |
| 230 | |
| 231 | const __m256 vi18x01234567 = _mm256_loadu_ps(i18); |
| 232 | const __m256 vi18x89ABCDEF = _mm256_loadu_ps(i18 + 8); |
| 233 | i18 += 16; |
| 234 | |
| 235 | const __m256 vk18x01234567 = _mm256_load_ps(w + 304); |
| 236 | const __m256 vk18x89ABCDEF = _mm256_load_ps(w + 312); |
| 237 | vacc01234567p0 = _mm256_fmadd_ps(vi18x01234567, vk18x01234567, vacc01234567p0); |
| 238 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi18x89ABCDEF, vk18x89ABCDEF, vacc89ABCDEFp0); |
| 239 | |
| 240 | const __m256 vi19x01234567 = _mm256_loadu_ps(i19); |
| 241 | const __m256 vi19x89ABCDEF = _mm256_loadu_ps(i19 + 8); |
| 242 | i19 += 16; |
| 243 | |
| 244 | const __m256 vk19x01234567 = _mm256_load_ps(w + 320); |
| 245 | const __m256 vk19x89ABCDEF = _mm256_load_ps(w + 328); |
| 246 | vacc01234567p0 = _mm256_fmadd_ps(vi19x01234567, vk19x01234567, vacc01234567p0); |
| 247 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi19x89ABCDEF, vk19x89ABCDEF, vacc89ABCDEFp0); |
| 248 | |
| 249 | const __m256 vi20x01234567 = _mm256_loadu_ps(i20); |
| 250 | const __m256 vi20x89ABCDEF = _mm256_loadu_ps(i20 + 8); |
| 251 | i20 += 16; |
| 252 | |
| 253 | const __m256 vk20x01234567 = _mm256_load_ps(w + 336); |
| 254 | const __m256 vk20x89ABCDEF = _mm256_load_ps(w + 344); |
| 255 | vacc01234567p0 = _mm256_fmadd_ps(vi20x01234567, vk20x01234567, vacc01234567p0); |
| 256 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi20x89ABCDEF, vk20x89ABCDEF, vacc89ABCDEFp0); |
| 257 | |
| 258 | const __m256 vi21x01234567 = _mm256_loadu_ps(i21); |
| 259 | const __m256 vi21x89ABCDEF = _mm256_loadu_ps(i21 + 8); |
| 260 | i21 += 16; |
| 261 | |
| 262 | const __m256 vk21x01234567 = _mm256_load_ps(w + 352); |
| 263 | const __m256 vk21x89ABCDEF = _mm256_load_ps(w + 360); |
| 264 | vacc01234567p0 = _mm256_fmadd_ps(vi21x01234567, vk21x01234567, vacc01234567p0); |
| 265 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi21x89ABCDEF, vk21x89ABCDEF, vacc89ABCDEFp0); |
| 266 | |
| 267 | const __m256 vi22x01234567 = _mm256_loadu_ps(i22); |
| 268 | const __m256 vi22x89ABCDEF = _mm256_loadu_ps(i22 + 8); |
| 269 | i22 += 16; |
| 270 | |
| 271 | const __m256 vk22x01234567 = _mm256_load_ps(w + 368); |
| 272 | const __m256 vk22x89ABCDEF = _mm256_load_ps(w + 376); |
| 273 | vacc01234567p0 = _mm256_fmadd_ps(vi22x01234567, vk22x01234567, vacc01234567p0); |
| 274 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi22x89ABCDEF, vk22x89ABCDEF, vacc89ABCDEFp0); |
| 275 | |
| 276 | const __m256 vi23x01234567 = _mm256_loadu_ps(i23); |
| 277 | const __m256 vi23x89ABCDEF = _mm256_loadu_ps(i23 + 8); |
| 278 | i23 += 16; |
| 279 | |
| 280 | const __m256 vk23x01234567 = _mm256_load_ps(w + 384); |
| 281 | const __m256 vk23x89ABCDEF = _mm256_load_ps(w + 392); |
| 282 | vacc01234567p0 = _mm256_fmadd_ps(vi23x01234567, vk23x01234567, vacc01234567p0); |
| 283 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi23x89ABCDEF, vk23x89ABCDEF, vacc89ABCDEFp0); |
| 284 | |
| 285 | const __m256 vi24x01234567 = _mm256_loadu_ps(i24); |
| 286 | const __m256 vi24x89ABCDEF = _mm256_loadu_ps(i24 + 8); |
| 287 | i24 += 16; |
| 288 | |
| 289 | const __m256 vk24x01234567 = _mm256_load_ps(w + 400); |
| 290 | const __m256 vk24x89ABCDEF = _mm256_load_ps(w + 408); |
| 291 | vacc01234567p0 = _mm256_fmadd_ps(vi24x01234567, vk24x01234567, vacc01234567p0); |
| 292 | vacc89ABCDEFp0 = _mm256_fmadd_ps(vi24x89ABCDEF, vk24x89ABCDEF, vacc89ABCDEFp0); |
| 293 | |
| 294 | w += 416; |
| 295 | |
| 296 | |
| 297 | __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin); |
| 298 | __m256 vacc89ABCDEF = _mm256_max_ps(vacc89ABCDEFp0, vmin); |
| 299 | vacc01234567 = _mm256_min_ps(vacc01234567, vmax); |
| 300 | vacc89ABCDEF = _mm256_min_ps(vacc89ABCDEF, vmax); |
| 301 | |
| 302 | _mm256_storeu_ps(output, vacc01234567); |
| 303 | _mm256_storeu_ps(output + 8, vacc89ABCDEF); |
| 304 | output += 16; |
| 305 | } |
| 306 | for (; c >= 8; c -= 8) { |
| 307 | __m256 vacc01234567p0 = _mm256_load_ps(w); |
| 308 | |
| 309 | const __m256 vi0x01234567 = _mm256_loadu_ps(i0); |
| 310 | i0 += 8; |
| 311 | |
| 312 | const __m256 vk0x01234567 = _mm256_load_ps(w + 16); |
| 313 | vacc01234567p0 = _mm256_fmadd_ps(vi0x01234567, vk0x01234567, vacc01234567p0); |
| 314 | |
| 315 | const __m256 vi1x01234567 = _mm256_loadu_ps(i1); |
| 316 | i1 += 8; |
| 317 | |
| 318 | const __m256 vk1x01234567 = _mm256_load_ps(w + 32); |
| 319 | vacc01234567p0 = _mm256_fmadd_ps(vi1x01234567, vk1x01234567, vacc01234567p0); |
| 320 | |
| 321 | const __m256 vi2x01234567 = _mm256_loadu_ps(i2); |
| 322 | i2 += 8; |
| 323 | |
| 324 | const __m256 vk2x01234567 = _mm256_load_ps(w + 48); |
| 325 | vacc01234567p0 = _mm256_fmadd_ps(vi2x01234567, vk2x01234567, vacc01234567p0); |
| 326 | |
| 327 | const __m256 vi3x01234567 = _mm256_loadu_ps(i3); |
| 328 | i3 += 8; |
| 329 | |
| 330 | const __m256 vk3x01234567 = _mm256_load_ps(w + 64); |
| 331 | vacc01234567p0 = _mm256_fmadd_ps(vi3x01234567, vk3x01234567, vacc01234567p0); |
| 332 | |
| 333 | const __m256 vi4x01234567 = _mm256_loadu_ps(i4); |
| 334 | i4 += 8; |
| 335 | |
| 336 | const __m256 vk4x01234567 = _mm256_load_ps(w + 80); |
| 337 | vacc01234567p0 = _mm256_fmadd_ps(vi4x01234567, vk4x01234567, vacc01234567p0); |
| 338 | |
| 339 | const __m256 vi5x01234567 = _mm256_loadu_ps(i5); |
| 340 | i5 += 8; |
| 341 | |
| 342 | const __m256 vk5x01234567 = _mm256_load_ps(w + 96); |
| 343 | vacc01234567p0 = _mm256_fmadd_ps(vi5x01234567, vk5x01234567, vacc01234567p0); |
| 344 | |
| 345 | const __m256 vi6x01234567 = _mm256_loadu_ps(i6); |
| 346 | i6 += 8; |
| 347 | |
| 348 | const __m256 vk6x01234567 = _mm256_load_ps(w + 112); |
| 349 | vacc01234567p0 = _mm256_fmadd_ps(vi6x01234567, vk6x01234567, vacc01234567p0); |
| 350 | |
| 351 | const __m256 vi7x01234567 = _mm256_loadu_ps(i7); |
| 352 | i7 += 8; |
| 353 | |
| 354 | const __m256 vk7x01234567 = _mm256_load_ps(w + 128); |
| 355 | vacc01234567p0 = _mm256_fmadd_ps(vi7x01234567, vk7x01234567, vacc01234567p0); |
| 356 | |
| 357 | const __m256 vi8x01234567 = _mm256_loadu_ps(i8); |
| 358 | i8 += 8; |
| 359 | |
| 360 | const __m256 vk8x01234567 = _mm256_load_ps(w + 144); |
| 361 | vacc01234567p0 = _mm256_fmadd_ps(vi8x01234567, vk8x01234567, vacc01234567p0); |
| 362 | |
| 363 | const __m256 vi9x01234567 = _mm256_loadu_ps(i9); |
| 364 | i9 += 8; |
| 365 | |
| 366 | const __m256 vk9x01234567 = _mm256_load_ps(w + 160); |
| 367 | vacc01234567p0 = _mm256_fmadd_ps(vi9x01234567, vk9x01234567, vacc01234567p0); |
| 368 | |
| 369 | const __m256 vi10x01234567 = _mm256_loadu_ps(i10); |
| 370 | i10 += 8; |
| 371 | |
| 372 | const __m256 vk10x01234567 = _mm256_load_ps(w + 176); |
| 373 | vacc01234567p0 = _mm256_fmadd_ps(vi10x01234567, vk10x01234567, vacc01234567p0); |
| 374 | |
| 375 | const __m256 vi11x01234567 = _mm256_loadu_ps(i11); |
| 376 | i11 += 8; |
| 377 | |
| 378 | const __m256 vk11x01234567 = _mm256_load_ps(w + 192); |
| 379 | vacc01234567p0 = _mm256_fmadd_ps(vi11x01234567, vk11x01234567, vacc01234567p0); |
| 380 | |
| 381 | const __m256 vi12x01234567 = _mm256_loadu_ps(i12); |
| 382 | i12 += 8; |
| 383 | |
| 384 | const __m256 vk12x01234567 = _mm256_load_ps(w + 208); |
| 385 | vacc01234567p0 = _mm256_fmadd_ps(vi12x01234567, vk12x01234567, vacc01234567p0); |
| 386 | |
| 387 | const __m256 vi13x01234567 = _mm256_loadu_ps(i13); |
| 388 | i13 += 8; |
| 389 | |
| 390 | const __m256 vk13x01234567 = _mm256_load_ps(w + 224); |
| 391 | vacc01234567p0 = _mm256_fmadd_ps(vi13x01234567, vk13x01234567, vacc01234567p0); |
| 392 | |
| 393 | const __m256 vi14x01234567 = _mm256_loadu_ps(i14); |
| 394 | i14 += 8; |
| 395 | |
| 396 | const __m256 vk14x01234567 = _mm256_load_ps(w + 240); |
| 397 | vacc01234567p0 = _mm256_fmadd_ps(vi14x01234567, vk14x01234567, vacc01234567p0); |
| 398 | |
| 399 | const __m256 vi15x01234567 = _mm256_loadu_ps(i15); |
| 400 | i15 += 8; |
| 401 | |
| 402 | const __m256 vk15x01234567 = _mm256_load_ps(w + 256); |
| 403 | vacc01234567p0 = _mm256_fmadd_ps(vi15x01234567, vk15x01234567, vacc01234567p0); |
| 404 | |
| 405 | const __m256 vi16x01234567 = _mm256_loadu_ps(i16); |
| 406 | i16 += 8; |
| 407 | |
| 408 | const __m256 vk16x01234567 = _mm256_load_ps(w + 272); |
| 409 | vacc01234567p0 = _mm256_fmadd_ps(vi16x01234567, vk16x01234567, vacc01234567p0); |
| 410 | |
| 411 | const __m256 vi17x01234567 = _mm256_loadu_ps(i17); |
| 412 | i17 += 8; |
| 413 | |
| 414 | const __m256 vk17x01234567 = _mm256_load_ps(w + 288); |
| 415 | vacc01234567p0 = _mm256_fmadd_ps(vi17x01234567, vk17x01234567, vacc01234567p0); |
| 416 | |
| 417 | const __m256 vi18x01234567 = _mm256_loadu_ps(i18); |
| 418 | i18 += 8; |
| 419 | |
| 420 | const __m256 vk18x01234567 = _mm256_load_ps(w + 304); |
| 421 | vacc01234567p0 = _mm256_fmadd_ps(vi18x01234567, vk18x01234567, vacc01234567p0); |
| 422 | |
| 423 | const __m256 vi19x01234567 = _mm256_loadu_ps(i19); |
| 424 | i19 += 8; |
| 425 | |
| 426 | const __m256 vk19x01234567 = _mm256_load_ps(w + 320); |
| 427 | vacc01234567p0 = _mm256_fmadd_ps(vi19x01234567, vk19x01234567, vacc01234567p0); |
| 428 | |
| 429 | const __m256 vi20x01234567 = _mm256_loadu_ps(i20); |
| 430 | i20 += 8; |
| 431 | |
| 432 | const __m256 vk20x01234567 = _mm256_load_ps(w + 336); |
| 433 | vacc01234567p0 = _mm256_fmadd_ps(vi20x01234567, vk20x01234567, vacc01234567p0); |
| 434 | |
| 435 | const __m256 vi21x01234567 = _mm256_loadu_ps(i21); |
| 436 | i21 += 8; |
| 437 | |
| 438 | const __m256 vk21x01234567 = _mm256_load_ps(w + 352); |
| 439 | vacc01234567p0 = _mm256_fmadd_ps(vi21x01234567, vk21x01234567, vacc01234567p0); |
| 440 | |
| 441 | const __m256 vi22x01234567 = _mm256_loadu_ps(i22); |
| 442 | i22 += 8; |
| 443 | |
| 444 | const __m256 vk22x01234567 = _mm256_load_ps(w + 368); |
| 445 | vacc01234567p0 = _mm256_fmadd_ps(vi22x01234567, vk22x01234567, vacc01234567p0); |
| 446 | |
| 447 | const __m256 vi23x01234567 = _mm256_loadu_ps(i23); |
| 448 | i23 += 8; |
| 449 | |
| 450 | const __m256 vk23x01234567 = _mm256_load_ps(w + 384); |
| 451 | vacc01234567p0 = _mm256_fmadd_ps(vi23x01234567, vk23x01234567, vacc01234567p0); |
| 452 | |
| 453 | const __m256 vi24x01234567 = _mm256_loadu_ps(i24); |
| 454 | i24 += 8; |
| 455 | |
| 456 | const __m256 vk24x01234567 = _mm256_load_ps(w + 400); |
| 457 | vacc01234567p0 = _mm256_fmadd_ps(vi24x01234567, vk24x01234567, vacc01234567p0); |
| 458 | |
| 459 | w += 8; |
| 460 | |
| 461 | |
| 462 | __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin); |
| 463 | vacc01234567 = _mm256_min_ps(vacc01234567, vmax); |
| 464 | |
| 465 | _mm256_storeu_ps(output, vacc01234567); |
| 466 | output += 8; |
| 467 | } |
| 468 | if XNN_UNLIKELY(c != 0) { |
| 469 | assert(c >= 1); |
| 470 | assert(c <= 7); |
| 471 | __m256i vmask = _mm256_loadu_si256((const __m256i*) &mask_table[7 - c]); |
| 472 | |
| 473 | __m256 vacc01234567p0 = _mm256_load_ps(w); |
| 474 | |
| 475 | const __m256 vi0x01234567 = _mm256_maskload_ps(i0, vmask); |
| 476 | const __m256 vk0x01234567 = _mm256_load_ps(w + 16); |
| 477 | vacc01234567p0 = _mm256_fmadd_ps(vi0x01234567, vk0x01234567, vacc01234567p0); |
| 478 | |
| 479 | const __m256 vi1x01234567 = _mm256_maskload_ps(i1, vmask); |
| 480 | const __m256 vk1x01234567 = _mm256_load_ps(w + 32); |
| 481 | vacc01234567p0 = _mm256_fmadd_ps(vi1x01234567, vk1x01234567, vacc01234567p0); |
| 482 | |
| 483 | const __m256 vi2x01234567 = _mm256_maskload_ps(i2, vmask); |
| 484 | const __m256 vk2x01234567 = _mm256_load_ps(w + 48); |
| 485 | vacc01234567p0 = _mm256_fmadd_ps(vi2x01234567, vk2x01234567, vacc01234567p0); |
| 486 | |
| 487 | const __m256 vi3x01234567 = _mm256_maskload_ps(i3, vmask); |
| 488 | const __m256 vk3x01234567 = _mm256_load_ps(w + 64); |
| 489 | vacc01234567p0 = _mm256_fmadd_ps(vi3x01234567, vk3x01234567, vacc01234567p0); |
| 490 | |
| 491 | const __m256 vi4x01234567 = _mm256_maskload_ps(i4, vmask); |
| 492 | const __m256 vk4x01234567 = _mm256_load_ps(w + 80); |
| 493 | vacc01234567p0 = _mm256_fmadd_ps(vi4x01234567, vk4x01234567, vacc01234567p0); |
| 494 | |
| 495 | const __m256 vi5x01234567 = _mm256_maskload_ps(i5, vmask); |
| 496 | const __m256 vk5x01234567 = _mm256_load_ps(w + 96); |
| 497 | vacc01234567p0 = _mm256_fmadd_ps(vi5x01234567, vk5x01234567, vacc01234567p0); |
| 498 | |
| 499 | const __m256 vi6x01234567 = _mm256_maskload_ps(i6, vmask); |
| 500 | const __m256 vk6x01234567 = _mm256_load_ps(w + 112); |
| 501 | vacc01234567p0 = _mm256_fmadd_ps(vi6x01234567, vk6x01234567, vacc01234567p0); |
| 502 | |
| 503 | const __m256 vi7x01234567 = _mm256_maskload_ps(i7, vmask); |
| 504 | const __m256 vk7x01234567 = _mm256_load_ps(w + 128); |
| 505 | vacc01234567p0 = _mm256_fmadd_ps(vi7x01234567, vk7x01234567, vacc01234567p0); |
| 506 | |
| 507 | const __m256 vi8x01234567 = _mm256_maskload_ps(i8, vmask); |
| 508 | const __m256 vk8x01234567 = _mm256_load_ps(w + 144); |
| 509 | vacc01234567p0 = _mm256_fmadd_ps(vi8x01234567, vk8x01234567, vacc01234567p0); |
| 510 | |
| 511 | const __m256 vi9x01234567 = _mm256_maskload_ps(i9, vmask); |
| 512 | const __m256 vk9x01234567 = _mm256_load_ps(w + 160); |
| 513 | vacc01234567p0 = _mm256_fmadd_ps(vi9x01234567, vk9x01234567, vacc01234567p0); |
| 514 | |
| 515 | const __m256 vi10x01234567 = _mm256_maskload_ps(i10, vmask); |
| 516 | const __m256 vk10x01234567 = _mm256_load_ps(w + 176); |
| 517 | vacc01234567p0 = _mm256_fmadd_ps(vi10x01234567, vk10x01234567, vacc01234567p0); |
| 518 | |
| 519 | const __m256 vi11x01234567 = _mm256_maskload_ps(i11, vmask); |
| 520 | const __m256 vk11x01234567 = _mm256_load_ps(w + 192); |
| 521 | vacc01234567p0 = _mm256_fmadd_ps(vi11x01234567, vk11x01234567, vacc01234567p0); |
| 522 | |
| 523 | const __m256 vi12x01234567 = _mm256_maskload_ps(i12, vmask); |
| 524 | const __m256 vk12x01234567 = _mm256_load_ps(w + 208); |
| 525 | vacc01234567p0 = _mm256_fmadd_ps(vi12x01234567, vk12x01234567, vacc01234567p0); |
| 526 | |
| 527 | const __m256 vi13x01234567 = _mm256_maskload_ps(i13, vmask); |
| 528 | const __m256 vk13x01234567 = _mm256_load_ps(w + 224); |
| 529 | vacc01234567p0 = _mm256_fmadd_ps(vi13x01234567, vk13x01234567, vacc01234567p0); |
| 530 | |
| 531 | const __m256 vi14x01234567 = _mm256_maskload_ps(i14, vmask); |
| 532 | const __m256 vk14x01234567 = _mm256_load_ps(w + 240); |
| 533 | vacc01234567p0 = _mm256_fmadd_ps(vi14x01234567, vk14x01234567, vacc01234567p0); |
| 534 | |
| 535 | const __m256 vi15x01234567 = _mm256_maskload_ps(i15, vmask); |
| 536 | const __m256 vk15x01234567 = _mm256_load_ps(w + 256); |
| 537 | vacc01234567p0 = _mm256_fmadd_ps(vi15x01234567, vk15x01234567, vacc01234567p0); |
| 538 | |
| 539 | const __m256 vi16x01234567 = _mm256_maskload_ps(i16, vmask); |
| 540 | const __m256 vk16x01234567 = _mm256_load_ps(w + 272); |
| 541 | vacc01234567p0 = _mm256_fmadd_ps(vi16x01234567, vk16x01234567, vacc01234567p0); |
| 542 | |
| 543 | const __m256 vi17x01234567 = _mm256_maskload_ps(i17, vmask); |
| 544 | const __m256 vk17x01234567 = _mm256_load_ps(w + 288); |
| 545 | vacc01234567p0 = _mm256_fmadd_ps(vi17x01234567, vk17x01234567, vacc01234567p0); |
| 546 | |
| 547 | const __m256 vi18x01234567 = _mm256_maskload_ps(i18, vmask); |
| 548 | const __m256 vk18x01234567 = _mm256_load_ps(w + 304); |
| 549 | vacc01234567p0 = _mm256_fmadd_ps(vi18x01234567, vk18x01234567, vacc01234567p0); |
| 550 | |
| 551 | const __m256 vi19x01234567 = _mm256_maskload_ps(i19, vmask); |
| 552 | const __m256 vk19x01234567 = _mm256_load_ps(w + 320); |
| 553 | vacc01234567p0 = _mm256_fmadd_ps(vi19x01234567, vk19x01234567, vacc01234567p0); |
| 554 | |
| 555 | const __m256 vi20x01234567 = _mm256_maskload_ps(i20, vmask); |
| 556 | const __m256 vk20x01234567 = _mm256_load_ps(w + 336); |
| 557 | vacc01234567p0 = _mm256_fmadd_ps(vi20x01234567, vk20x01234567, vacc01234567p0); |
| 558 | |
| 559 | const __m256 vi21x01234567 = _mm256_maskload_ps(i21, vmask); |
| 560 | const __m256 vk21x01234567 = _mm256_load_ps(w + 352); |
| 561 | vacc01234567p0 = _mm256_fmadd_ps(vi21x01234567, vk21x01234567, vacc01234567p0); |
| 562 | |
| 563 | const __m256 vi22x01234567 = _mm256_maskload_ps(i22, vmask); |
| 564 | const __m256 vk22x01234567 = _mm256_load_ps(w + 368); |
| 565 | vacc01234567p0 = _mm256_fmadd_ps(vi22x01234567, vk22x01234567, vacc01234567p0); |
| 566 | |
| 567 | const __m256 vi23x01234567 = _mm256_maskload_ps(i23, vmask); |
| 568 | const __m256 vk23x01234567 = _mm256_load_ps(w + 384); |
| 569 | vacc01234567p0 = _mm256_fmadd_ps(vi23x01234567, vk23x01234567, vacc01234567p0); |
| 570 | |
| 571 | const __m256 vi24x01234567 = _mm256_maskload_ps(i24, vmask); |
| 572 | const __m256 vk24x01234567 = _mm256_load_ps(w + 400); |
| 573 | vacc01234567p0 = _mm256_fmadd_ps(vi24x01234567, vk24x01234567, vacc01234567p0); |
| 574 | |
| 575 | |
| 576 | __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin); |
| 577 | vacc01234567 = _mm256_min_ps(vacc01234567, vmax); |
| 578 | |
| 579 | _mm256_maskstore_ps(output, vmask, vacc01234567); |
| 580 | output += c; |
| 581 | } |
| 582 | |
| 583 | output = (float*) ((uintptr_t) output + output_increment); |
| 584 | } while (--output_width != 0); |
| 585 | } |