Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1 | // Copyright (c) Facebook, Inc. and its affiliates. |
| 2 | // All rights reserved. |
| 3 | // |
| 4 | // Copyright 2019 Google LLC |
| 5 | // |
| 6 | // This source code is licensed under the BSD-style license found in the |
| 7 | // LICENSE file in the root directory of this source tree. |
| 8 | // |
| 9 | // Auto-generated file. Do not edit! |
| 10 | // Specification: test/f32-dwconv-minmax.yaml |
| 11 | // Generator: tools/generate-dwconv-test.py |
| 12 | |
| 13 | |
| 14 | #include <gtest/gtest.h> |
| 15 | |
| 16 | #include <xnnpack/common.h> |
| 17 | #include <xnnpack/isa-checks.h> |
| 18 | |
| 19 | #include <xnnpack/dwconv.h> |
| 20 | #include "dwconv-microkernel-tester.h" |
| 21 | |
| 22 | |
Marat Dukhan | d18cec3 | 2020-05-18 01:29:29 -0700 | [diff] [blame] | 23 | #if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 24 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 25 | TEST_REQUIRES_ARM_NEON_FMA; |
| 26 | DWConvMicrokernelTester() |
| 27 | .cr(4) |
| 28 | .kr(9) |
| 29 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 30 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 31 | } |
| 32 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 33 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 34 | TEST_REQUIRES_ARM_NEON_FMA; |
| 35 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 36 | DWConvMicrokernelTester() |
| 37 | .cr(4) |
| 38 | .kr(9) |
| 39 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 40 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 41 | } |
| 42 | } |
| 43 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 44 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 45 | TEST_REQUIRES_ARM_NEON_FMA; |
| 46 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 47 | DWConvMicrokernelTester() |
| 48 | .cr(4) |
| 49 | .kr(9) |
| 50 | .channels(channels) |
| 51 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 52 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 53 | } |
| 54 | } |
| 55 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 56 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 57 | TEST_REQUIRES_ARM_NEON_FMA; |
| 58 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 59 | DWConvMicrokernelTester() |
| 60 | .cr(4) |
| 61 | .kr(9) |
| 62 | .channels(channels) |
| 63 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 64 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 65 | } |
| 66 | } |
| 67 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 68 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 69 | TEST_REQUIRES_ARM_NEON_FMA; |
| 70 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 71 | DWConvMicrokernelTester() |
| 72 | .cr(4) |
| 73 | .kr(9) |
| 74 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 75 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 76 | } |
| 77 | } |
| 78 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 79 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 80 | TEST_REQUIRES_ARM_NEON_FMA; |
| 81 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 82 | DWConvMicrokernelTester() |
| 83 | .cr(4) |
| 84 | .kr(9) |
| 85 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 86 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 87 | } |
| 88 | } |
| 89 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 90 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 91 | TEST_REQUIRES_ARM_NEON_FMA; |
| 92 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 93 | DWConvMicrokernelTester() |
| 94 | .cr(4) |
| 95 | .kr(9) |
| 96 | .channels(channels) |
| 97 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 98 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 99 | } |
| 100 | } |
| 101 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 102 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 103 | TEST_REQUIRES_ARM_NEON_FMA; |
| 104 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 105 | DWConvMicrokernelTester() |
| 106 | .cr(4) |
| 107 | .kr(9) |
| 108 | .channels(channels) |
| 109 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 110 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 111 | } |
| 112 | } |
| 113 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 114 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 115 | TEST_REQUIRES_ARM_NEON_FMA; |
| 116 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 117 | DWConvMicrokernelTester() |
| 118 | .cr(4) |
| 119 | .kr(9) |
| 120 | .channels(channels) |
| 121 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 122 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 123 | } |
| 124 | } |
| 125 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 126 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 127 | TEST_REQUIRES_ARM_NEON_FMA; |
| 128 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 129 | for (size_t step = 2; step <= 9; step++) { |
| 130 | DWConvMicrokernelTester() |
| 131 | .cr(4) |
| 132 | .kr(9) |
| 133 | .channels(channels) |
| 134 | .width(3) |
| 135 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 136 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 137 | } |
| 138 | } |
| 139 | } |
| 140 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 141 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 142 | TEST_REQUIRES_ARM_NEON_FMA; |
| 143 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 144 | DWConvMicrokernelTester() |
| 145 | .cr(4) |
| 146 | .kr(9) |
| 147 | .channels(4) |
| 148 | .width(5) |
| 149 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 150 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 151 | } |
| 152 | } |
| 153 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 154 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 155 | TEST_REQUIRES_ARM_NEON_FMA; |
| 156 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 157 | DWConvMicrokernelTester() |
| 158 | .cr(4) |
| 159 | .kr(9) |
| 160 | .channels(channels) |
| 161 | .width(3) |
| 162 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 163 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 164 | } |
| 165 | } |
| 166 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 167 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 168 | TEST_REQUIRES_ARM_NEON_FMA; |
| 169 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 170 | DWConvMicrokernelTester() |
| 171 | .cr(4) |
| 172 | .kr(9) |
| 173 | .channels(channels) |
| 174 | .width(3) |
| 175 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 176 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 177 | } |
| 178 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 179 | |
| 180 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, input_offset) { |
| 181 | TEST_REQUIRES_ARM_NEON_FMA; |
| 182 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 183 | DWConvMicrokernelTester() |
| 184 | .cr(4) |
| 185 | .kr(9) |
| 186 | .channels(channels) |
| 187 | .input_offset(112) |
| 188 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA, zero) { |
| 193 | TEST_REQUIRES_ARM_NEON_FMA; |
| 194 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 195 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 196 | DWConvMicrokernelTester() |
| 197 | .cr(4) |
| 198 | .kr(9) |
| 199 | .channels(channels) |
| 200 | .input_offset(112) |
| 201 | .zero_index(mz) |
| 202 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma); |
| 203 | } |
| 204 | } |
| 205 | } |
Marat Dukhan | d18cec3 | 2020-05-18 01:29:29 -0700 | [diff] [blame] | 206 | #endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 207 | |
| 208 | |
| 209 | #if XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 210 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 211 | TEST_REQUIRES_ARM_NEON_FMA; |
| 212 | DWConvMicrokernelTester() |
| 213 | .cr(4) |
| 214 | .kr(9) |
| 215 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 216 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 217 | } |
| 218 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 219 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 220 | TEST_REQUIRES_ARM_NEON_FMA; |
| 221 | DWConvMicrokernelTester() |
| 222 | .cr(4) |
| 223 | .kr(9) |
| 224 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 225 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 226 | } |
| 227 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 228 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 229 | TEST_REQUIRES_ARM_NEON_FMA; |
| 230 | for (uint32_t channels = 12; channels < 64; channels += 12) { |
| 231 | DWConvMicrokernelTester() |
| 232 | .cr(4) |
| 233 | .kr(9) |
| 234 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 235 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 236 | } |
| 237 | } |
| 238 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 239 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 240 | TEST_REQUIRES_ARM_NEON_FMA; |
| 241 | for (uint32_t channels = 12; channels < 64; channels += 12) { |
| 242 | DWConvMicrokernelTester() |
| 243 | .cr(4) |
| 244 | .kr(9) |
| 245 | .channels(channels) |
| 246 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 247 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 248 | } |
| 249 | } |
| 250 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 251 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 252 | TEST_REQUIRES_ARM_NEON_FMA; |
| 253 | for (uint32_t channels = 12; channels < 64; channels += 12) { |
| 254 | DWConvMicrokernelTester() |
| 255 | .cr(4) |
| 256 | .kr(9) |
| 257 | .channels(channels) |
| 258 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 259 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 260 | } |
| 261 | } |
| 262 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 263 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 264 | TEST_REQUIRES_ARM_NEON_FMA; |
| 265 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 266 | DWConvMicrokernelTester() |
| 267 | .cr(4) |
| 268 | .kr(9) |
| 269 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 270 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 271 | } |
| 272 | } |
| 273 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 274 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 275 | TEST_REQUIRES_ARM_NEON_FMA; |
| 276 | for (uint32_t channels = 9; channels < 12; channels++) { |
| 277 | DWConvMicrokernelTester() |
| 278 | .cr(4) |
| 279 | .kr(9) |
| 280 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 281 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 282 | } |
| 283 | } |
| 284 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 285 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 286 | TEST_REQUIRES_ARM_NEON_FMA; |
| 287 | for (uint32_t channels = 9; channels < 12; channels++) { |
| 288 | DWConvMicrokernelTester() |
| 289 | .cr(4) |
| 290 | .kr(9) |
| 291 | .channels(channels) |
| 292 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 293 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 294 | } |
| 295 | } |
| 296 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 297 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 298 | TEST_REQUIRES_ARM_NEON_FMA; |
| 299 | for (uint32_t channels = 9; channels < 12; channels++) { |
| 300 | DWConvMicrokernelTester() |
| 301 | .cr(4) |
| 302 | .kr(9) |
| 303 | .channels(channels) |
| 304 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 305 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 306 | } |
| 307 | } |
| 308 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 309 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 310 | TEST_REQUIRES_ARM_NEON_FMA; |
| 311 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 312 | DWConvMicrokernelTester() |
| 313 | .cr(4) |
| 314 | .kr(9) |
| 315 | .channels(channels) |
| 316 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 317 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 318 | } |
| 319 | } |
| 320 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 321 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 322 | TEST_REQUIRES_ARM_NEON_FMA; |
| 323 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 324 | for (size_t step = 2; step <= 9; step++) { |
| 325 | DWConvMicrokernelTester() |
| 326 | .cr(4) |
| 327 | .kr(9) |
| 328 | .channels(channels) |
| 329 | .width(3) |
| 330 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 331 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 332 | } |
| 333 | } |
| 334 | } |
| 335 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 336 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 337 | TEST_REQUIRES_ARM_NEON_FMA; |
| 338 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 339 | DWConvMicrokernelTester() |
| 340 | .cr(4) |
| 341 | .kr(9) |
| 342 | .channels(4) |
| 343 | .width(5) |
| 344 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 345 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 346 | } |
| 347 | } |
| 348 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 349 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 350 | TEST_REQUIRES_ARM_NEON_FMA; |
| 351 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 352 | DWConvMicrokernelTester() |
| 353 | .cr(4) |
| 354 | .kr(9) |
| 355 | .channels(channels) |
| 356 | .width(3) |
| 357 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 358 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 359 | } |
| 360 | } |
| 361 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 362 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 363 | TEST_REQUIRES_ARM_NEON_FMA; |
| 364 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 365 | DWConvMicrokernelTester() |
| 366 | .cr(4) |
| 367 | .kr(9) |
| 368 | .channels(channels) |
| 369 | .width(3) |
| 370 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 371 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 372 | } |
| 373 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 374 | |
| 375 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, input_offset) { |
| 376 | TEST_REQUIRES_ARM_NEON_FMA; |
| 377 | for (uint32_t channels = 12; channels < 64; channels += 12) { |
| 378 | DWConvMicrokernelTester() |
| 379 | .cr(4) |
| 380 | .kr(9) |
| 381 | .channels(channels) |
| 382 | .input_offset(112) |
| 383 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | TEST(F32_DWCONV_MINMAX_UP4X9__AARCH64_NEONFMA_CORTEX_A55, zero) { |
| 388 | TEST_REQUIRES_ARM_NEON_FMA; |
| 389 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 390 | for (uint32_t channels = 12; channels < 64; channels += 12) { |
| 391 | DWConvMicrokernelTester() |
| 392 | .cr(4) |
| 393 | .kr(9) |
| 394 | .channels(channels) |
| 395 | .input_offset(112) |
| 396 | .zero_index(mz) |
| 397 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__aarch64_neonfma_cortex_a55); |
| 398 | } |
| 399 | } |
| 400 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 401 | #endif // XNN_ARCH_ARM64 && XNN_ENABLE_ASSEMBLY |
| 402 | |
| 403 | |
| 404 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 405 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_eq_4) { |
| 406 | TEST_REQUIRES_ARM_NEON_FMA; |
| 407 | DWConvMicrokernelTester() |
| 408 | .cr(4) |
| 409 | .kr(25) |
| 410 | .channels(4) |
| 411 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 412 | } |
| 413 | |
| 414 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_div_4) { |
| 415 | TEST_REQUIRES_ARM_NEON_FMA; |
| 416 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 417 | DWConvMicrokernelTester() |
| 418 | .cr(4) |
| 419 | .kr(25) |
| 420 | .channels(channels) |
| 421 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_div_4_with_qmin) { |
| 426 | TEST_REQUIRES_ARM_NEON_FMA; |
| 427 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 428 | DWConvMicrokernelTester() |
| 429 | .cr(4) |
| 430 | .kr(25) |
| 431 | .channels(channels) |
| 432 | .qmin(128) |
| 433 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_div_4_with_qmax) { |
| 438 | TEST_REQUIRES_ARM_NEON_FMA; |
| 439 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 440 | DWConvMicrokernelTester() |
| 441 | .cr(4) |
| 442 | .kr(25) |
| 443 | .channels(channels) |
| 444 | .qmax(128) |
| 445 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_lt_4) { |
| 450 | TEST_REQUIRES_ARM_NEON_FMA; |
| 451 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 452 | DWConvMicrokernelTester() |
| 453 | .cr(4) |
| 454 | .kr(25) |
| 455 | .channels(channels) |
| 456 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_gt_4) { |
| 461 | TEST_REQUIRES_ARM_NEON_FMA; |
| 462 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 463 | DWConvMicrokernelTester() |
| 464 | .cr(4) |
| 465 | .kr(25) |
| 466 | .channels(channels) |
| 467 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 468 | } |
| 469 | } |
| 470 | |
| 471 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_gt_4_with_qmin) { |
| 472 | TEST_REQUIRES_ARM_NEON_FMA; |
| 473 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 474 | DWConvMicrokernelTester() |
| 475 | .cr(4) |
| 476 | .kr(25) |
| 477 | .channels(channels) |
| 478 | .qmin(128) |
| 479 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 480 | } |
| 481 | } |
| 482 | |
| 483 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, c_gt_4_with_qmax) { |
| 484 | TEST_REQUIRES_ARM_NEON_FMA; |
| 485 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 486 | DWConvMicrokernelTester() |
| 487 | .cr(4) |
| 488 | .kr(25) |
| 489 | .channels(channels) |
| 490 | .qmax(128) |
| 491 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 492 | } |
| 493 | } |
| 494 | |
| 495 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, multipixel) { |
| 496 | TEST_REQUIRES_ARM_NEON_FMA; |
| 497 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 498 | DWConvMicrokernelTester() |
| 499 | .cr(4) |
| 500 | .kr(25) |
| 501 | .channels(channels) |
| 502 | .width(3) |
| 503 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 504 | } |
| 505 | } |
| 506 | |
| 507 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, multipixel_with_step) { |
| 508 | TEST_REQUIRES_ARM_NEON_FMA; |
| 509 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 510 | for (size_t step = 2; step <= 25; step++) { |
| 511 | DWConvMicrokernelTester() |
| 512 | .cr(4) |
| 513 | .kr(25) |
| 514 | .channels(channels) |
| 515 | .width(3) |
| 516 | .step(step) |
| 517 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 518 | } |
| 519 | } |
| 520 | } |
| 521 | |
| 522 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, multipixel_with_output_stride) { |
| 523 | TEST_REQUIRES_ARM_NEON_FMA; |
| 524 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 525 | DWConvMicrokernelTester() |
| 526 | .cr(4) |
| 527 | .kr(25) |
| 528 | .channels(4) |
| 529 | .width(5) |
| 530 | .output_stride(23) |
| 531 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 532 | } |
| 533 | } |
| 534 | |
| 535 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, multipixel_with_qmin) { |
| 536 | TEST_REQUIRES_ARM_NEON_FMA; |
| 537 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 538 | DWConvMicrokernelTester() |
| 539 | .cr(4) |
| 540 | .kr(25) |
| 541 | .channels(channels) |
| 542 | .width(3) |
| 543 | .qmin(128) |
| 544 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, multipixel_with_qmax) { |
| 549 | TEST_REQUIRES_ARM_NEON_FMA; |
| 550 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 551 | DWConvMicrokernelTester() |
| 552 | .cr(4) |
| 553 | .kr(25) |
| 554 | .channels(channels) |
| 555 | .width(3) |
| 556 | .qmax(128) |
| 557 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 558 | } |
| 559 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 560 | |
| 561 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, input_offset) { |
| 562 | TEST_REQUIRES_ARM_NEON_FMA; |
| 563 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 564 | DWConvMicrokernelTester() |
| 565 | .cr(4) |
| 566 | .kr(25) |
| 567 | .channels(channels) |
| 568 | .input_offset(112) |
| 569 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA, zero) { |
| 574 | TEST_REQUIRES_ARM_NEON_FMA; |
| 575 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 576 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 577 | DWConvMicrokernelTester() |
| 578 | .cr(4) |
| 579 | .kr(25) |
| 580 | .channels(channels) |
| 581 | .input_offset(112) |
| 582 | .zero_index(mz) |
| 583 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma); |
| 584 | } |
| 585 | } |
| 586 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 587 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 588 | |
| 589 | |
| 590 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 591 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_eq_4) { |
| 592 | TEST_REQUIRES_ARM_NEON_FMA; |
| 593 | DWConvMicrokernelTester() |
| 594 | .cr(4) |
| 595 | .kr(25) |
| 596 | .channels(4) |
| 597 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 598 | } |
| 599 | |
| 600 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_div_4) { |
| 601 | TEST_REQUIRES_ARM_NEON_FMA; |
| 602 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 603 | DWConvMicrokernelTester() |
| 604 | .cr(4) |
| 605 | .kr(25) |
| 606 | .channels(channels) |
| 607 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 608 | } |
| 609 | } |
| 610 | |
| 611 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_div_4_with_qmin) { |
| 612 | TEST_REQUIRES_ARM_NEON_FMA; |
| 613 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 614 | DWConvMicrokernelTester() |
| 615 | .cr(4) |
| 616 | .kr(25) |
| 617 | .channels(channels) |
| 618 | .qmin(128) |
| 619 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 620 | } |
| 621 | } |
| 622 | |
| 623 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_div_4_with_qmax) { |
| 624 | TEST_REQUIRES_ARM_NEON_FMA; |
| 625 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 626 | DWConvMicrokernelTester() |
| 627 | .cr(4) |
| 628 | .kr(25) |
| 629 | .channels(channels) |
| 630 | .qmax(128) |
| 631 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_lt_4) { |
| 636 | TEST_REQUIRES_ARM_NEON_FMA; |
| 637 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 638 | DWConvMicrokernelTester() |
| 639 | .cr(4) |
| 640 | .kr(25) |
| 641 | .channels(channels) |
| 642 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_gt_4) { |
| 647 | TEST_REQUIRES_ARM_NEON_FMA; |
| 648 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 649 | DWConvMicrokernelTester() |
| 650 | .cr(4) |
| 651 | .kr(25) |
| 652 | .channels(channels) |
| 653 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 654 | } |
| 655 | } |
| 656 | |
| 657 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_gt_4_with_qmin) { |
| 658 | TEST_REQUIRES_ARM_NEON_FMA; |
| 659 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 660 | DWConvMicrokernelTester() |
| 661 | .cr(4) |
| 662 | .kr(25) |
| 663 | .channels(channels) |
| 664 | .qmin(128) |
| 665 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 666 | } |
| 667 | } |
| 668 | |
| 669 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, c_gt_4_with_qmax) { |
| 670 | TEST_REQUIRES_ARM_NEON_FMA; |
| 671 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 672 | DWConvMicrokernelTester() |
| 673 | .cr(4) |
| 674 | .kr(25) |
| 675 | .channels(channels) |
| 676 | .qmax(128) |
| 677 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, multipixel) { |
| 682 | TEST_REQUIRES_ARM_NEON_FMA; |
| 683 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 684 | DWConvMicrokernelTester() |
| 685 | .cr(4) |
| 686 | .kr(25) |
| 687 | .channels(channels) |
| 688 | .width(3) |
| 689 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 690 | } |
| 691 | } |
| 692 | |
| 693 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, multipixel_with_step) { |
| 694 | TEST_REQUIRES_ARM_NEON_FMA; |
| 695 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 696 | for (size_t step = 2; step <= 25; step++) { |
| 697 | DWConvMicrokernelTester() |
| 698 | .cr(4) |
| 699 | .kr(25) |
| 700 | .channels(channels) |
| 701 | .width(3) |
| 702 | .step(step) |
| 703 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 704 | } |
| 705 | } |
| 706 | } |
| 707 | |
| 708 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, multipixel_with_output_stride) { |
| 709 | TEST_REQUIRES_ARM_NEON_FMA; |
| 710 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 711 | DWConvMicrokernelTester() |
| 712 | .cr(4) |
| 713 | .kr(25) |
| 714 | .channels(4) |
| 715 | .width(5) |
| 716 | .output_stride(23) |
| 717 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 718 | } |
| 719 | } |
| 720 | |
| 721 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, multipixel_with_qmin) { |
| 722 | TEST_REQUIRES_ARM_NEON_FMA; |
| 723 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 724 | DWConvMicrokernelTester() |
| 725 | .cr(4) |
| 726 | .kr(25) |
| 727 | .channels(channels) |
| 728 | .width(3) |
| 729 | .qmin(128) |
| 730 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 731 | } |
| 732 | } |
| 733 | |
| 734 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, multipixel_with_qmax) { |
| 735 | TEST_REQUIRES_ARM_NEON_FMA; |
| 736 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 737 | DWConvMicrokernelTester() |
| 738 | .cr(4) |
| 739 | .kr(25) |
| 740 | .channels(channels) |
| 741 | .width(3) |
| 742 | .qmax(128) |
| 743 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 744 | } |
| 745 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 746 | |
| 747 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, input_offset) { |
| 748 | TEST_REQUIRES_ARM_NEON_FMA; |
| 749 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 750 | DWConvMicrokernelTester() |
| 751 | .cr(4) |
| 752 | .kr(25) |
| 753 | .channels(channels) |
| 754 | .input_offset(112) |
| 755 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 756 | } |
| 757 | } |
| 758 | |
| 759 | TEST(F32_DWCONV_MINMAX_UP4X25__NEONFMA_ACC2, zero) { |
| 760 | TEST_REQUIRES_ARM_NEON_FMA; |
| 761 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 762 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 763 | DWConvMicrokernelTester() |
| 764 | .cr(4) |
| 765 | .kr(25) |
| 766 | .channels(channels) |
| 767 | .input_offset(112) |
| 768 | .zero_index(mz) |
| 769 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neonfma_acc2); |
| 770 | } |
| 771 | } |
| 772 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 773 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 774 | |
| 775 | |
| 776 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 777 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_eq_8) { |
| 778 | TEST_REQUIRES_ARM_NEON_FMA; |
| 779 | DWConvMicrokernelTester() |
| 780 | .cr(8) |
| 781 | .kr(25) |
| 782 | .channels(8) |
| 783 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 784 | } |
| 785 | |
| 786 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_div_8) { |
| 787 | TEST_REQUIRES_ARM_NEON_FMA; |
| 788 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 789 | DWConvMicrokernelTester() |
| 790 | .cr(8) |
| 791 | .kr(25) |
| 792 | .channels(channels) |
| 793 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_div_8_with_qmin) { |
| 798 | TEST_REQUIRES_ARM_NEON_FMA; |
| 799 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 800 | DWConvMicrokernelTester() |
| 801 | .cr(8) |
| 802 | .kr(25) |
| 803 | .channels(channels) |
| 804 | .qmin(128) |
| 805 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_div_8_with_qmax) { |
| 810 | TEST_REQUIRES_ARM_NEON_FMA; |
| 811 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 812 | DWConvMicrokernelTester() |
| 813 | .cr(8) |
| 814 | .kr(25) |
| 815 | .channels(channels) |
| 816 | .qmax(128) |
| 817 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 818 | } |
| 819 | } |
| 820 | |
| 821 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_lt_8) { |
| 822 | TEST_REQUIRES_ARM_NEON_FMA; |
| 823 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 824 | DWConvMicrokernelTester() |
| 825 | .cr(8) |
| 826 | .kr(25) |
| 827 | .channels(channels) |
| 828 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 829 | } |
| 830 | } |
| 831 | |
| 832 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_gt_8) { |
| 833 | TEST_REQUIRES_ARM_NEON_FMA; |
| 834 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 835 | DWConvMicrokernelTester() |
| 836 | .cr(8) |
| 837 | .kr(25) |
| 838 | .channels(channels) |
| 839 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 840 | } |
| 841 | } |
| 842 | |
| 843 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_gt_8_with_qmin) { |
| 844 | TEST_REQUIRES_ARM_NEON_FMA; |
| 845 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 846 | DWConvMicrokernelTester() |
| 847 | .cr(8) |
| 848 | .kr(25) |
| 849 | .channels(channels) |
| 850 | .qmin(128) |
| 851 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, c_gt_8_with_qmax) { |
| 856 | TEST_REQUIRES_ARM_NEON_FMA; |
| 857 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 858 | DWConvMicrokernelTester() |
| 859 | .cr(8) |
| 860 | .kr(25) |
| 861 | .channels(channels) |
| 862 | .qmax(128) |
| 863 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 864 | } |
| 865 | } |
| 866 | |
| 867 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, multipixel) { |
| 868 | TEST_REQUIRES_ARM_NEON_FMA; |
| 869 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 870 | DWConvMicrokernelTester() |
| 871 | .cr(8) |
| 872 | .kr(25) |
| 873 | .channels(channels) |
| 874 | .width(3) |
| 875 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 876 | } |
| 877 | } |
| 878 | |
| 879 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, multipixel_with_step) { |
| 880 | TEST_REQUIRES_ARM_NEON_FMA; |
| 881 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 882 | for (size_t step = 2; step <= 25; step++) { |
| 883 | DWConvMicrokernelTester() |
| 884 | .cr(8) |
| 885 | .kr(25) |
| 886 | .channels(channels) |
| 887 | .width(3) |
| 888 | .step(step) |
| 889 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 890 | } |
| 891 | } |
| 892 | } |
| 893 | |
| 894 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, multipixel_with_output_stride) { |
| 895 | TEST_REQUIRES_ARM_NEON_FMA; |
| 896 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 897 | DWConvMicrokernelTester() |
| 898 | .cr(8) |
| 899 | .kr(25) |
| 900 | .channels(8) |
| 901 | .width(5) |
| 902 | .output_stride(43) |
| 903 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 904 | } |
| 905 | } |
| 906 | |
| 907 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, multipixel_with_qmin) { |
| 908 | TEST_REQUIRES_ARM_NEON_FMA; |
| 909 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 910 | DWConvMicrokernelTester() |
| 911 | .cr(8) |
| 912 | .kr(25) |
| 913 | .channels(channels) |
| 914 | .width(3) |
| 915 | .qmin(128) |
| 916 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, multipixel_with_qmax) { |
| 921 | TEST_REQUIRES_ARM_NEON_FMA; |
| 922 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 923 | DWConvMicrokernelTester() |
| 924 | .cr(8) |
| 925 | .kr(25) |
| 926 | .channels(channels) |
| 927 | .width(3) |
| 928 | .qmax(128) |
| 929 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 930 | } |
| 931 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 932 | |
| 933 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, input_offset) { |
| 934 | TEST_REQUIRES_ARM_NEON_FMA; |
| 935 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 936 | DWConvMicrokernelTester() |
| 937 | .cr(8) |
| 938 | .kr(25) |
| 939 | .channels(channels) |
| 940 | .input_offset(176) |
| 941 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 942 | } |
| 943 | } |
| 944 | |
| 945 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA, zero) { |
| 946 | TEST_REQUIRES_ARM_NEON_FMA; |
| 947 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 948 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 949 | DWConvMicrokernelTester() |
| 950 | .cr(8) |
| 951 | .kr(25) |
| 952 | .channels(channels) |
| 953 | .input_offset(176) |
| 954 | .zero_index(mz) |
| 955 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma); |
| 956 | } |
| 957 | } |
| 958 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 959 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 960 | |
| 961 | |
| 962 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 963 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_eq_8) { |
| 964 | TEST_REQUIRES_ARM_NEON_FMA; |
| 965 | DWConvMicrokernelTester() |
| 966 | .cr(8) |
| 967 | .kr(25) |
| 968 | .channels(8) |
| 969 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 970 | } |
| 971 | |
| 972 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_div_8) { |
| 973 | TEST_REQUIRES_ARM_NEON_FMA; |
| 974 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 975 | DWConvMicrokernelTester() |
| 976 | .cr(8) |
| 977 | .kr(25) |
| 978 | .channels(channels) |
| 979 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 980 | } |
| 981 | } |
| 982 | |
| 983 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_div_8_with_qmin) { |
| 984 | TEST_REQUIRES_ARM_NEON_FMA; |
| 985 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 986 | DWConvMicrokernelTester() |
| 987 | .cr(8) |
| 988 | .kr(25) |
| 989 | .channels(channels) |
| 990 | .qmin(128) |
| 991 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 992 | } |
| 993 | } |
| 994 | |
| 995 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_div_8_with_qmax) { |
| 996 | TEST_REQUIRES_ARM_NEON_FMA; |
| 997 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 998 | DWConvMicrokernelTester() |
| 999 | .cr(8) |
| 1000 | .kr(25) |
| 1001 | .channels(channels) |
| 1002 | .qmax(128) |
| 1003 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1004 | } |
| 1005 | } |
| 1006 | |
| 1007 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_lt_8) { |
| 1008 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1009 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 1010 | DWConvMicrokernelTester() |
| 1011 | .cr(8) |
| 1012 | .kr(25) |
| 1013 | .channels(channels) |
| 1014 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1015 | } |
| 1016 | } |
| 1017 | |
| 1018 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_gt_8) { |
| 1019 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1020 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1021 | DWConvMicrokernelTester() |
| 1022 | .cr(8) |
| 1023 | .kr(25) |
| 1024 | .channels(channels) |
| 1025 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1026 | } |
| 1027 | } |
| 1028 | |
| 1029 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_gt_8_with_qmin) { |
| 1030 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1031 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1032 | DWConvMicrokernelTester() |
| 1033 | .cr(8) |
| 1034 | .kr(25) |
| 1035 | .channels(channels) |
| 1036 | .qmin(128) |
| 1037 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, c_gt_8_with_qmax) { |
| 1042 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1043 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1044 | DWConvMicrokernelTester() |
| 1045 | .cr(8) |
| 1046 | .kr(25) |
| 1047 | .channels(channels) |
| 1048 | .qmax(128) |
| 1049 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1050 | } |
| 1051 | } |
| 1052 | |
| 1053 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, multipixel) { |
| 1054 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1055 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1056 | DWConvMicrokernelTester() |
| 1057 | .cr(8) |
| 1058 | .kr(25) |
| 1059 | .channels(channels) |
| 1060 | .width(3) |
| 1061 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, multipixel_with_step) { |
| 1066 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1067 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1068 | for (size_t step = 2; step <= 25; step++) { |
| 1069 | DWConvMicrokernelTester() |
| 1070 | .cr(8) |
| 1071 | .kr(25) |
| 1072 | .channels(channels) |
| 1073 | .width(3) |
| 1074 | .step(step) |
| 1075 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1076 | } |
| 1077 | } |
| 1078 | } |
| 1079 | |
| 1080 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, multipixel_with_output_stride) { |
| 1081 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1082 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1083 | DWConvMicrokernelTester() |
| 1084 | .cr(8) |
| 1085 | .kr(25) |
| 1086 | .channels(8) |
| 1087 | .width(5) |
| 1088 | .output_stride(43) |
| 1089 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1090 | } |
| 1091 | } |
| 1092 | |
| 1093 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, multipixel_with_qmin) { |
| 1094 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1095 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1096 | DWConvMicrokernelTester() |
| 1097 | .cr(8) |
| 1098 | .kr(25) |
| 1099 | .channels(channels) |
| 1100 | .width(3) |
| 1101 | .qmin(128) |
| 1102 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1103 | } |
| 1104 | } |
| 1105 | |
| 1106 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, multipixel_with_qmax) { |
| 1107 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1108 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1109 | DWConvMicrokernelTester() |
| 1110 | .cr(8) |
| 1111 | .kr(25) |
| 1112 | .channels(channels) |
| 1113 | .width(3) |
| 1114 | .qmax(128) |
| 1115 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1116 | } |
| 1117 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 1118 | |
| 1119 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, input_offset) { |
| 1120 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1121 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1122 | DWConvMicrokernelTester() |
| 1123 | .cr(8) |
| 1124 | .kr(25) |
| 1125 | .channels(channels) |
| 1126 | .input_offset(176) |
| 1127 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1128 | } |
| 1129 | } |
| 1130 | |
| 1131 | TEST(F32_DWCONV_MINMAX_UP8X25__NEONFMA_ACC2, zero) { |
| 1132 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1133 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 1134 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1135 | DWConvMicrokernelTester() |
| 1136 | .cr(8) |
| 1137 | .kr(25) |
| 1138 | .channels(channels) |
| 1139 | .input_offset(176) |
| 1140 | .zero_index(mz) |
| 1141 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neonfma_acc2); |
| 1142 | } |
| 1143 | } |
| 1144 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 1145 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1146 | |
| 1147 | |
| 1148 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1149 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1150 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1151 | DWConvMicrokernelTester() |
| 1152 | .cr(4) |
| 1153 | .kr(9) |
| 1154 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1155 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1156 | } |
| 1157 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1158 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1159 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1160 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1161 | DWConvMicrokernelTester() |
| 1162 | .cr(4) |
| 1163 | .kr(9) |
| 1164 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1165 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1166 | } |
| 1167 | } |
| 1168 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1169 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1170 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1171 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1172 | DWConvMicrokernelTester() |
| 1173 | .cr(4) |
| 1174 | .kr(9) |
| 1175 | .channels(channels) |
| 1176 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1177 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1178 | } |
| 1179 | } |
| 1180 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1181 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1182 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1183 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1184 | DWConvMicrokernelTester() |
| 1185 | .cr(4) |
| 1186 | .kr(9) |
| 1187 | .channels(channels) |
| 1188 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1189 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1190 | } |
| 1191 | } |
| 1192 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1193 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1194 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1195 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 1196 | DWConvMicrokernelTester() |
| 1197 | .cr(4) |
| 1198 | .kr(9) |
| 1199 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1200 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1201 | } |
| 1202 | } |
| 1203 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1204 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1205 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1206 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1207 | DWConvMicrokernelTester() |
| 1208 | .cr(4) |
| 1209 | .kr(9) |
| 1210 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1211 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1212 | } |
| 1213 | } |
| 1214 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1215 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1216 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1217 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1218 | DWConvMicrokernelTester() |
| 1219 | .cr(4) |
| 1220 | .kr(9) |
| 1221 | .channels(channels) |
| 1222 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1223 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1224 | } |
| 1225 | } |
| 1226 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1227 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1228 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1229 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1230 | DWConvMicrokernelTester() |
| 1231 | .cr(4) |
| 1232 | .kr(9) |
| 1233 | .channels(channels) |
| 1234 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1235 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1236 | } |
| 1237 | } |
| 1238 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1239 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1240 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1241 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1242 | DWConvMicrokernelTester() |
| 1243 | .cr(4) |
| 1244 | .kr(9) |
| 1245 | .channels(channels) |
| 1246 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1247 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1248 | } |
| 1249 | } |
| 1250 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1251 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1252 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1253 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1254 | for (size_t step = 2; step <= 9; step++) { |
| 1255 | DWConvMicrokernelTester() |
| 1256 | .cr(4) |
| 1257 | .kr(9) |
| 1258 | .channels(channels) |
| 1259 | .width(3) |
| 1260 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1261 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1262 | } |
| 1263 | } |
| 1264 | } |
| 1265 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1266 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1267 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1268 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1269 | DWConvMicrokernelTester() |
| 1270 | .cr(4) |
| 1271 | .kr(9) |
| 1272 | .channels(4) |
| 1273 | .width(5) |
| 1274 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1275 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1276 | } |
| 1277 | } |
| 1278 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1279 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1280 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1281 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1282 | DWConvMicrokernelTester() |
| 1283 | .cr(4) |
| 1284 | .kr(9) |
| 1285 | .channels(channels) |
| 1286 | .width(3) |
| 1287 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1288 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1289 | } |
| 1290 | } |
| 1291 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1292 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1293 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1294 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1295 | DWConvMicrokernelTester() |
| 1296 | .cr(4) |
| 1297 | .kr(9) |
| 1298 | .channels(channels) |
| 1299 | .width(3) |
| 1300 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1301 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1302 | } |
| 1303 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 1304 | |
| 1305 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, input_offset) { |
| 1306 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1307 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1308 | DWConvMicrokernelTester() |
| 1309 | .cr(4) |
| 1310 | .kr(9) |
| 1311 | .channels(channels) |
| 1312 | .input_offset(112) |
| 1313 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
| 1314 | } |
| 1315 | } |
| 1316 | |
| 1317 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA, zero) { |
| 1318 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1319 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 1320 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1321 | DWConvMicrokernelTester() |
| 1322 | .cr(4) |
| 1323 | .kr(9) |
| 1324 | .channels(channels) |
| 1325 | .input_offset(112) |
| 1326 | .zero_index(mz) |
| 1327 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma); |
| 1328 | } |
| 1329 | } |
| 1330 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1331 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1332 | |
| 1333 | |
| 1334 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1335 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1336 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1337 | DWConvMicrokernelTester() |
| 1338 | .cr(4) |
| 1339 | .kr(9) |
| 1340 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1341 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1342 | } |
| 1343 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1344 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1345 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1346 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1347 | DWConvMicrokernelTester() |
| 1348 | .cr(4) |
| 1349 | .kr(9) |
| 1350 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1351 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1352 | } |
| 1353 | } |
| 1354 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1355 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1356 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1357 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1358 | DWConvMicrokernelTester() |
| 1359 | .cr(4) |
| 1360 | .kr(9) |
| 1361 | .channels(channels) |
| 1362 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1363 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1364 | } |
| 1365 | } |
| 1366 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1367 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1368 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1369 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1370 | DWConvMicrokernelTester() |
| 1371 | .cr(4) |
| 1372 | .kr(9) |
| 1373 | .channels(channels) |
| 1374 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1375 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1376 | } |
| 1377 | } |
| 1378 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1379 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1380 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1381 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 1382 | DWConvMicrokernelTester() |
| 1383 | .cr(4) |
| 1384 | .kr(9) |
| 1385 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1386 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1387 | } |
| 1388 | } |
| 1389 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1390 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1391 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1392 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1393 | DWConvMicrokernelTester() |
| 1394 | .cr(4) |
| 1395 | .kr(9) |
| 1396 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1397 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1398 | } |
| 1399 | } |
| 1400 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1401 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1402 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1403 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1404 | DWConvMicrokernelTester() |
| 1405 | .cr(4) |
| 1406 | .kr(9) |
| 1407 | .channels(channels) |
| 1408 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1409 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1410 | } |
| 1411 | } |
| 1412 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1413 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1414 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1415 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1416 | DWConvMicrokernelTester() |
| 1417 | .cr(4) |
| 1418 | .kr(9) |
| 1419 | .channels(channels) |
| 1420 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1421 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1422 | } |
| 1423 | } |
| 1424 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1425 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1426 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1427 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1428 | DWConvMicrokernelTester() |
| 1429 | .cr(4) |
| 1430 | .kr(9) |
| 1431 | .channels(channels) |
| 1432 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1433 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1434 | } |
| 1435 | } |
| 1436 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1437 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1438 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1439 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1440 | for (size_t step = 2; step <= 9; step++) { |
| 1441 | DWConvMicrokernelTester() |
| 1442 | .cr(4) |
| 1443 | .kr(9) |
| 1444 | .channels(channels) |
| 1445 | .width(3) |
| 1446 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1447 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1448 | } |
| 1449 | } |
| 1450 | } |
| 1451 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1452 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1453 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1454 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1455 | DWConvMicrokernelTester() |
| 1456 | .cr(4) |
| 1457 | .kr(9) |
| 1458 | .channels(4) |
| 1459 | .width(5) |
| 1460 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1461 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1462 | } |
| 1463 | } |
| 1464 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1465 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1466 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1467 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1468 | DWConvMicrokernelTester() |
| 1469 | .cr(4) |
| 1470 | .kr(9) |
| 1471 | .channels(channels) |
| 1472 | .width(3) |
| 1473 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1474 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1475 | } |
| 1476 | } |
| 1477 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1478 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1479 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1480 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1481 | DWConvMicrokernelTester() |
| 1482 | .cr(4) |
| 1483 | .kr(9) |
| 1484 | .channels(channels) |
| 1485 | .width(3) |
| 1486 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1487 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1488 | } |
| 1489 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 1490 | |
| 1491 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, input_offset) { |
| 1492 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1493 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1494 | DWConvMicrokernelTester() |
| 1495 | .cr(4) |
| 1496 | .kr(9) |
| 1497 | .channels(channels) |
| 1498 | .input_offset(112) |
| 1499 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | TEST(F32_DWCONV_MINMAX_UP4X9__NEONFMA_ACC2, zero) { |
| 1504 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1505 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 1506 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1507 | DWConvMicrokernelTester() |
| 1508 | .cr(4) |
| 1509 | .kr(9) |
| 1510 | .channels(channels) |
| 1511 | .input_offset(112) |
| 1512 | .zero_index(mz) |
| 1513 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neonfma_acc2); |
| 1514 | } |
| 1515 | } |
| 1516 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1517 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1518 | |
| 1519 | |
| 1520 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1521 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1522 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1523 | DWConvMicrokernelTester() |
| 1524 | .cr(8) |
| 1525 | .kr(9) |
| 1526 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1527 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1528 | } |
| 1529 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1530 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1531 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1532 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1533 | DWConvMicrokernelTester() |
| 1534 | .cr(8) |
| 1535 | .kr(9) |
| 1536 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1537 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1538 | } |
| 1539 | } |
| 1540 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1541 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1542 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1543 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1544 | DWConvMicrokernelTester() |
| 1545 | .cr(8) |
| 1546 | .kr(9) |
| 1547 | .channels(channels) |
| 1548 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1549 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1550 | } |
| 1551 | } |
| 1552 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1553 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1554 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1555 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1556 | DWConvMicrokernelTester() |
| 1557 | .cr(8) |
| 1558 | .kr(9) |
| 1559 | .channels(channels) |
| 1560 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1561 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1562 | } |
| 1563 | } |
| 1564 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1565 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1566 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1567 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 1568 | DWConvMicrokernelTester() |
| 1569 | .cr(8) |
| 1570 | .kr(9) |
| 1571 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1572 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1573 | } |
| 1574 | } |
| 1575 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1576 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1577 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1578 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1579 | DWConvMicrokernelTester() |
| 1580 | .cr(8) |
| 1581 | .kr(9) |
| 1582 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1583 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1584 | } |
| 1585 | } |
| 1586 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1587 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1588 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1589 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1590 | DWConvMicrokernelTester() |
| 1591 | .cr(8) |
| 1592 | .kr(9) |
| 1593 | .channels(channels) |
| 1594 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1595 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1596 | } |
| 1597 | } |
| 1598 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1599 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1600 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1601 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1602 | DWConvMicrokernelTester() |
| 1603 | .cr(8) |
| 1604 | .kr(9) |
| 1605 | .channels(channels) |
| 1606 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1607 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1608 | } |
| 1609 | } |
| 1610 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1611 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1612 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1613 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1614 | DWConvMicrokernelTester() |
| 1615 | .cr(8) |
| 1616 | .kr(9) |
| 1617 | .channels(channels) |
| 1618 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1619 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1620 | } |
| 1621 | } |
| 1622 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1623 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1624 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1625 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1626 | for (size_t step = 2; step <= 9; step++) { |
| 1627 | DWConvMicrokernelTester() |
| 1628 | .cr(8) |
| 1629 | .kr(9) |
| 1630 | .channels(channels) |
| 1631 | .width(3) |
| 1632 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1633 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1634 | } |
| 1635 | } |
| 1636 | } |
| 1637 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1638 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1639 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1640 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1641 | DWConvMicrokernelTester() |
| 1642 | .cr(8) |
| 1643 | .kr(9) |
| 1644 | .channels(8) |
| 1645 | .width(5) |
| 1646 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1647 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1648 | } |
| 1649 | } |
| 1650 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1651 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1652 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1653 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1654 | DWConvMicrokernelTester() |
| 1655 | .cr(8) |
| 1656 | .kr(9) |
| 1657 | .channels(channels) |
| 1658 | .width(3) |
| 1659 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1660 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1661 | } |
| 1662 | } |
| 1663 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1664 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1665 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1666 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1667 | DWConvMicrokernelTester() |
| 1668 | .cr(8) |
| 1669 | .kr(9) |
| 1670 | .channels(channels) |
| 1671 | .width(3) |
| 1672 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1673 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1674 | } |
| 1675 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 1676 | |
| 1677 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, input_offset) { |
| 1678 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1679 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1680 | DWConvMicrokernelTester() |
| 1681 | .cr(8) |
| 1682 | .kr(9) |
| 1683 | .channels(channels) |
| 1684 | .input_offset(176) |
| 1685 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
| 1686 | } |
| 1687 | } |
| 1688 | |
| 1689 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA, zero) { |
| 1690 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1691 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 1692 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1693 | DWConvMicrokernelTester() |
| 1694 | .cr(8) |
| 1695 | .kr(9) |
| 1696 | .channels(channels) |
| 1697 | .input_offset(176) |
| 1698 | .zero_index(mz) |
| 1699 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma); |
| 1700 | } |
| 1701 | } |
| 1702 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1703 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1704 | |
| 1705 | |
| 1706 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1707 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1708 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1709 | DWConvMicrokernelTester() |
| 1710 | .cr(8) |
| 1711 | .kr(9) |
| 1712 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1713 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1714 | } |
| 1715 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1716 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1717 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1718 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1719 | DWConvMicrokernelTester() |
| 1720 | .cr(8) |
| 1721 | .kr(9) |
| 1722 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1723 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1724 | } |
| 1725 | } |
| 1726 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1727 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1728 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1729 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1730 | DWConvMicrokernelTester() |
| 1731 | .cr(8) |
| 1732 | .kr(9) |
| 1733 | .channels(channels) |
| 1734 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1735 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1736 | } |
| 1737 | } |
| 1738 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1739 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1740 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1741 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1742 | DWConvMicrokernelTester() |
| 1743 | .cr(8) |
| 1744 | .kr(9) |
| 1745 | .channels(channels) |
| 1746 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1747 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1748 | } |
| 1749 | } |
| 1750 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1751 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1752 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1753 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 1754 | DWConvMicrokernelTester() |
| 1755 | .cr(8) |
| 1756 | .kr(9) |
| 1757 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1758 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1759 | } |
| 1760 | } |
| 1761 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1762 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1763 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1764 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1765 | DWConvMicrokernelTester() |
| 1766 | .cr(8) |
| 1767 | .kr(9) |
| 1768 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1769 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1770 | } |
| 1771 | } |
| 1772 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1773 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1774 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1775 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1776 | DWConvMicrokernelTester() |
| 1777 | .cr(8) |
| 1778 | .kr(9) |
| 1779 | .channels(channels) |
| 1780 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1781 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1782 | } |
| 1783 | } |
| 1784 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1785 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1786 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1787 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 1788 | DWConvMicrokernelTester() |
| 1789 | .cr(8) |
| 1790 | .kr(9) |
| 1791 | .channels(channels) |
| 1792 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1793 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1794 | } |
| 1795 | } |
| 1796 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1797 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1798 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1799 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1800 | DWConvMicrokernelTester() |
| 1801 | .cr(8) |
| 1802 | .kr(9) |
| 1803 | .channels(channels) |
| 1804 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1805 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1806 | } |
| 1807 | } |
| 1808 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1809 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1810 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1811 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1812 | for (size_t step = 2; step <= 9; step++) { |
| 1813 | DWConvMicrokernelTester() |
| 1814 | .cr(8) |
| 1815 | .kr(9) |
| 1816 | .channels(channels) |
| 1817 | .width(3) |
| 1818 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1819 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1820 | } |
| 1821 | } |
| 1822 | } |
| 1823 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1824 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1825 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1826 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1827 | DWConvMicrokernelTester() |
| 1828 | .cr(8) |
| 1829 | .kr(9) |
| 1830 | .channels(8) |
| 1831 | .width(5) |
| 1832 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1833 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1834 | } |
| 1835 | } |
| 1836 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1837 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1838 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1839 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1840 | DWConvMicrokernelTester() |
| 1841 | .cr(8) |
| 1842 | .kr(9) |
| 1843 | .channels(channels) |
| 1844 | .width(3) |
| 1845 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1846 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1847 | } |
| 1848 | } |
| 1849 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1850 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1851 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1852 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 1853 | DWConvMicrokernelTester() |
| 1854 | .cr(8) |
| 1855 | .kr(9) |
| 1856 | .channels(channels) |
| 1857 | .width(3) |
| 1858 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 1859 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1860 | } |
| 1861 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 1862 | |
| 1863 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, input_offset) { |
| 1864 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1865 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1866 | DWConvMicrokernelTester() |
| 1867 | .cr(8) |
| 1868 | .kr(9) |
| 1869 | .channels(channels) |
| 1870 | .input_offset(176) |
| 1871 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
| 1872 | } |
| 1873 | } |
| 1874 | |
| 1875 | TEST(F32_DWCONV_MINMAX_UP8X9__NEONFMA_ACC2, zero) { |
| 1876 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1877 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 1878 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 1879 | DWConvMicrokernelTester() |
| 1880 | .cr(8) |
| 1881 | .kr(9) |
| 1882 | .channels(channels) |
| 1883 | .input_offset(176) |
| 1884 | .zero_index(mz) |
| 1885 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neonfma_acc2); |
| 1886 | } |
| 1887 | } |
| 1888 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 1889 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 1890 | |
| 1891 | |
| 1892 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 1893 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_eq_4) { |
| 1894 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1895 | DWConvMicrokernelTester() |
| 1896 | .cr(4) |
| 1897 | .kr(4) |
| 1898 | .channels(4) |
| 1899 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1900 | } |
| 1901 | |
| 1902 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_div_4) { |
| 1903 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1904 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1905 | DWConvMicrokernelTester() |
| 1906 | .cr(4) |
| 1907 | .kr(4) |
| 1908 | .channels(channels) |
| 1909 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1910 | } |
| 1911 | } |
| 1912 | |
| 1913 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_div_4_with_qmin) { |
| 1914 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1915 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1916 | DWConvMicrokernelTester() |
| 1917 | .cr(4) |
| 1918 | .kr(4) |
| 1919 | .channels(channels) |
| 1920 | .qmin(128) |
| 1921 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1922 | } |
| 1923 | } |
| 1924 | |
| 1925 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_div_4_with_qmax) { |
| 1926 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1927 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 1928 | DWConvMicrokernelTester() |
| 1929 | .cr(4) |
| 1930 | .kr(4) |
| 1931 | .channels(channels) |
| 1932 | .qmax(128) |
| 1933 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1934 | } |
| 1935 | } |
| 1936 | |
| 1937 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_lt_4) { |
| 1938 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1939 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 1940 | DWConvMicrokernelTester() |
| 1941 | .cr(4) |
| 1942 | .kr(4) |
| 1943 | .channels(channels) |
| 1944 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1945 | } |
| 1946 | } |
| 1947 | |
| 1948 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_gt_4) { |
| 1949 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1950 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1951 | DWConvMicrokernelTester() |
| 1952 | .cr(4) |
| 1953 | .kr(4) |
| 1954 | .channels(channels) |
| 1955 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1956 | } |
| 1957 | } |
| 1958 | |
| 1959 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_gt_4_with_qmin) { |
| 1960 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1961 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1962 | DWConvMicrokernelTester() |
| 1963 | .cr(4) |
| 1964 | .kr(4) |
| 1965 | .channels(channels) |
| 1966 | .qmin(128) |
| 1967 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1968 | } |
| 1969 | } |
| 1970 | |
| 1971 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, c_gt_4_with_qmax) { |
| 1972 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1973 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 1974 | DWConvMicrokernelTester() |
| 1975 | .cr(4) |
| 1976 | .kr(4) |
| 1977 | .channels(channels) |
| 1978 | .qmax(128) |
| 1979 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1980 | } |
| 1981 | } |
| 1982 | |
| 1983 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, multipixel) { |
| 1984 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1985 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1986 | DWConvMicrokernelTester() |
| 1987 | .cr(4) |
| 1988 | .kr(4) |
| 1989 | .channels(channels) |
| 1990 | .width(3) |
| 1991 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 1992 | } |
| 1993 | } |
| 1994 | |
| 1995 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, multipixel_with_step) { |
| 1996 | TEST_REQUIRES_ARM_NEON_FMA; |
| 1997 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 1998 | for (size_t step = 2; step <= 4; step++) { |
| 1999 | DWConvMicrokernelTester() |
| 2000 | .cr(4) |
| 2001 | .kr(4) |
| 2002 | .channels(channels) |
| 2003 | .width(3) |
| 2004 | .step(step) |
| 2005 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 2006 | } |
| 2007 | } |
| 2008 | } |
| 2009 | |
| 2010 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, multipixel_with_output_stride) { |
| 2011 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2012 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2013 | DWConvMicrokernelTester() |
| 2014 | .cr(4) |
| 2015 | .kr(4) |
| 2016 | .channels(4) |
| 2017 | .width(5) |
| 2018 | .output_stride(23) |
| 2019 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 2020 | } |
| 2021 | } |
| 2022 | |
| 2023 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, multipixel_with_qmin) { |
| 2024 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2025 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2026 | DWConvMicrokernelTester() |
| 2027 | .cr(4) |
| 2028 | .kr(4) |
| 2029 | .channels(channels) |
| 2030 | .width(3) |
| 2031 | .qmin(128) |
| 2032 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 2033 | } |
| 2034 | } |
| 2035 | |
| 2036 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, multipixel_with_qmax) { |
| 2037 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2038 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2039 | DWConvMicrokernelTester() |
| 2040 | .cr(4) |
| 2041 | .kr(4) |
| 2042 | .channels(channels) |
| 2043 | .width(3) |
| 2044 | .qmax(128) |
| 2045 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 2046 | } |
| 2047 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 2048 | |
| 2049 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, input_offset) { |
| 2050 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2051 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2052 | DWConvMicrokernelTester() |
| 2053 | .cr(4) |
| 2054 | .kr(4) |
| 2055 | .channels(channels) |
| 2056 | .input_offset(112) |
| 2057 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 2058 | } |
| 2059 | } |
| 2060 | |
| 2061 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA, zero) { |
| 2062 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2063 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 2064 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2065 | DWConvMicrokernelTester() |
| 2066 | .cr(4) |
| 2067 | .kr(4) |
| 2068 | .channels(channels) |
| 2069 | .input_offset(112) |
| 2070 | .zero_index(mz) |
| 2071 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma); |
| 2072 | } |
| 2073 | } |
| 2074 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 2075 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2076 | |
| 2077 | |
| 2078 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2079 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_eq_4) { |
| 2080 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2081 | DWConvMicrokernelTester() |
| 2082 | .cr(4) |
| 2083 | .kr(4) |
| 2084 | .channels(4) |
| 2085 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2086 | } |
| 2087 | |
| 2088 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_div_4) { |
| 2089 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2090 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2091 | DWConvMicrokernelTester() |
| 2092 | .cr(4) |
| 2093 | .kr(4) |
| 2094 | .channels(channels) |
| 2095 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2096 | } |
| 2097 | } |
| 2098 | |
| 2099 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_div_4_with_qmin) { |
| 2100 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2101 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2102 | DWConvMicrokernelTester() |
| 2103 | .cr(4) |
| 2104 | .kr(4) |
| 2105 | .channels(channels) |
| 2106 | .qmin(128) |
| 2107 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2108 | } |
| 2109 | } |
| 2110 | |
| 2111 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_div_4_with_qmax) { |
| 2112 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2113 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2114 | DWConvMicrokernelTester() |
| 2115 | .cr(4) |
| 2116 | .kr(4) |
| 2117 | .channels(channels) |
| 2118 | .qmax(128) |
| 2119 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2120 | } |
| 2121 | } |
| 2122 | |
| 2123 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_lt_4) { |
| 2124 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2125 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 2126 | DWConvMicrokernelTester() |
| 2127 | .cr(4) |
| 2128 | .kr(4) |
| 2129 | .channels(channels) |
| 2130 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2131 | } |
| 2132 | } |
| 2133 | |
| 2134 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_gt_4) { |
| 2135 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2136 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2137 | DWConvMicrokernelTester() |
| 2138 | .cr(4) |
| 2139 | .kr(4) |
| 2140 | .channels(channels) |
| 2141 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2142 | } |
| 2143 | } |
| 2144 | |
| 2145 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_gt_4_with_qmin) { |
| 2146 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2147 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2148 | DWConvMicrokernelTester() |
| 2149 | .cr(4) |
| 2150 | .kr(4) |
| 2151 | .channels(channels) |
| 2152 | .qmin(128) |
| 2153 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2154 | } |
| 2155 | } |
| 2156 | |
| 2157 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, c_gt_4_with_qmax) { |
| 2158 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2159 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2160 | DWConvMicrokernelTester() |
| 2161 | .cr(4) |
| 2162 | .kr(4) |
| 2163 | .channels(channels) |
| 2164 | .qmax(128) |
| 2165 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2166 | } |
| 2167 | } |
| 2168 | |
| 2169 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, multipixel) { |
| 2170 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2171 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2172 | DWConvMicrokernelTester() |
| 2173 | .cr(4) |
| 2174 | .kr(4) |
| 2175 | .channels(channels) |
| 2176 | .width(3) |
| 2177 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2178 | } |
| 2179 | } |
| 2180 | |
| 2181 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, multipixel_with_step) { |
| 2182 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2183 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2184 | for (size_t step = 2; step <= 4; step++) { |
| 2185 | DWConvMicrokernelTester() |
| 2186 | .cr(4) |
| 2187 | .kr(4) |
| 2188 | .channels(channels) |
| 2189 | .width(3) |
| 2190 | .step(step) |
| 2191 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2192 | } |
| 2193 | } |
| 2194 | } |
| 2195 | |
| 2196 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, multipixel_with_output_stride) { |
| 2197 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2198 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2199 | DWConvMicrokernelTester() |
| 2200 | .cr(4) |
| 2201 | .kr(4) |
| 2202 | .channels(4) |
| 2203 | .width(5) |
| 2204 | .output_stride(23) |
| 2205 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2206 | } |
| 2207 | } |
| 2208 | |
| 2209 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, multipixel_with_qmin) { |
| 2210 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2211 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2212 | DWConvMicrokernelTester() |
| 2213 | .cr(4) |
| 2214 | .kr(4) |
| 2215 | .channels(channels) |
| 2216 | .width(3) |
| 2217 | .qmin(128) |
| 2218 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2219 | } |
| 2220 | } |
| 2221 | |
| 2222 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, multipixel_with_qmax) { |
| 2223 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2224 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2225 | DWConvMicrokernelTester() |
| 2226 | .cr(4) |
| 2227 | .kr(4) |
| 2228 | .channels(channels) |
| 2229 | .width(3) |
| 2230 | .qmax(128) |
| 2231 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2232 | } |
| 2233 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 2234 | |
| 2235 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, input_offset) { |
| 2236 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2237 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2238 | DWConvMicrokernelTester() |
| 2239 | .cr(4) |
| 2240 | .kr(4) |
| 2241 | .channels(channels) |
| 2242 | .input_offset(112) |
| 2243 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2244 | } |
| 2245 | } |
| 2246 | |
| 2247 | TEST(F32_DWCONV_MINMAX_UP4X4__NEONFMA_ACC2, zero) { |
| 2248 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2249 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 2250 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2251 | DWConvMicrokernelTester() |
| 2252 | .cr(4) |
| 2253 | .kr(4) |
| 2254 | .channels(channels) |
| 2255 | .input_offset(112) |
| 2256 | .zero_index(mz) |
| 2257 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neonfma_acc2); |
| 2258 | } |
| 2259 | } |
| 2260 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 2261 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2262 | |
| 2263 | |
| 2264 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2265 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_eq_8) { |
| 2266 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2267 | DWConvMicrokernelTester() |
| 2268 | .cr(8) |
| 2269 | .kr(4) |
| 2270 | .channels(8) |
| 2271 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2272 | } |
| 2273 | |
| 2274 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_div_8) { |
| 2275 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2276 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2277 | DWConvMicrokernelTester() |
| 2278 | .cr(8) |
| 2279 | .kr(4) |
| 2280 | .channels(channels) |
| 2281 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2282 | } |
| 2283 | } |
| 2284 | |
| 2285 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_div_8_with_qmin) { |
| 2286 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2287 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2288 | DWConvMicrokernelTester() |
| 2289 | .cr(8) |
| 2290 | .kr(4) |
| 2291 | .channels(channels) |
| 2292 | .qmin(128) |
| 2293 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2294 | } |
| 2295 | } |
| 2296 | |
| 2297 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_div_8_with_qmax) { |
| 2298 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2299 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2300 | DWConvMicrokernelTester() |
| 2301 | .cr(8) |
| 2302 | .kr(4) |
| 2303 | .channels(channels) |
| 2304 | .qmax(128) |
| 2305 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2306 | } |
| 2307 | } |
| 2308 | |
| 2309 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_lt_8) { |
| 2310 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2311 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 2312 | DWConvMicrokernelTester() |
| 2313 | .cr(8) |
| 2314 | .kr(4) |
| 2315 | .channels(channels) |
| 2316 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2317 | } |
| 2318 | } |
| 2319 | |
| 2320 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_gt_8) { |
| 2321 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2322 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 2323 | DWConvMicrokernelTester() |
| 2324 | .cr(8) |
| 2325 | .kr(4) |
| 2326 | .channels(channels) |
| 2327 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2328 | } |
| 2329 | } |
| 2330 | |
| 2331 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_gt_8_with_qmin) { |
| 2332 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2333 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 2334 | DWConvMicrokernelTester() |
| 2335 | .cr(8) |
| 2336 | .kr(4) |
| 2337 | .channels(channels) |
| 2338 | .qmin(128) |
| 2339 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2340 | } |
| 2341 | } |
| 2342 | |
| 2343 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, c_gt_8_with_qmax) { |
| 2344 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2345 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 2346 | DWConvMicrokernelTester() |
| 2347 | .cr(8) |
| 2348 | .kr(4) |
| 2349 | .channels(channels) |
| 2350 | .qmax(128) |
| 2351 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2352 | } |
| 2353 | } |
| 2354 | |
| 2355 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, multipixel) { |
| 2356 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2357 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2358 | DWConvMicrokernelTester() |
| 2359 | .cr(8) |
| 2360 | .kr(4) |
| 2361 | .channels(channels) |
| 2362 | .width(3) |
| 2363 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2364 | } |
| 2365 | } |
| 2366 | |
| 2367 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, multipixel_with_step) { |
| 2368 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2369 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2370 | for (size_t step = 2; step <= 4; step++) { |
| 2371 | DWConvMicrokernelTester() |
| 2372 | .cr(8) |
| 2373 | .kr(4) |
| 2374 | .channels(channels) |
| 2375 | .width(3) |
| 2376 | .step(step) |
| 2377 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2378 | } |
| 2379 | } |
| 2380 | } |
| 2381 | |
| 2382 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, multipixel_with_output_stride) { |
| 2383 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2384 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2385 | DWConvMicrokernelTester() |
| 2386 | .cr(8) |
| 2387 | .kr(4) |
| 2388 | .channels(8) |
| 2389 | .width(5) |
| 2390 | .output_stride(43) |
| 2391 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2392 | } |
| 2393 | } |
| 2394 | |
| 2395 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, multipixel_with_qmin) { |
| 2396 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2397 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2398 | DWConvMicrokernelTester() |
| 2399 | .cr(8) |
| 2400 | .kr(4) |
| 2401 | .channels(channels) |
| 2402 | .width(3) |
| 2403 | .qmin(128) |
| 2404 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2405 | } |
| 2406 | } |
| 2407 | |
| 2408 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, multipixel_with_qmax) { |
| 2409 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2410 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2411 | DWConvMicrokernelTester() |
| 2412 | .cr(8) |
| 2413 | .kr(4) |
| 2414 | .channels(channels) |
| 2415 | .width(3) |
| 2416 | .qmax(128) |
| 2417 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2418 | } |
| 2419 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 2420 | |
| 2421 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, input_offset) { |
| 2422 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2423 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2424 | DWConvMicrokernelTester() |
| 2425 | .cr(8) |
| 2426 | .kr(4) |
| 2427 | .channels(channels) |
| 2428 | .input_offset(176) |
| 2429 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2430 | } |
| 2431 | } |
| 2432 | |
| 2433 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA, zero) { |
| 2434 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2435 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 2436 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2437 | DWConvMicrokernelTester() |
| 2438 | .cr(8) |
| 2439 | .kr(4) |
| 2440 | .channels(channels) |
| 2441 | .input_offset(176) |
| 2442 | .zero_index(mz) |
| 2443 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma); |
| 2444 | } |
| 2445 | } |
| 2446 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 2447 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2448 | |
| 2449 | |
| 2450 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2451 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_eq_8) { |
| 2452 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2453 | DWConvMicrokernelTester() |
| 2454 | .cr(8) |
| 2455 | .kr(4) |
| 2456 | .channels(8) |
| 2457 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2458 | } |
| 2459 | |
| 2460 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_div_8) { |
| 2461 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2462 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2463 | DWConvMicrokernelTester() |
| 2464 | .cr(8) |
| 2465 | .kr(4) |
| 2466 | .channels(channels) |
| 2467 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2468 | } |
| 2469 | } |
| 2470 | |
| 2471 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_div_8_with_qmin) { |
| 2472 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2473 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2474 | DWConvMicrokernelTester() |
| 2475 | .cr(8) |
| 2476 | .kr(4) |
| 2477 | .channels(channels) |
| 2478 | .qmin(128) |
| 2479 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2480 | } |
| 2481 | } |
| 2482 | |
| 2483 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_div_8_with_qmax) { |
| 2484 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2485 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2486 | DWConvMicrokernelTester() |
| 2487 | .cr(8) |
| 2488 | .kr(4) |
| 2489 | .channels(channels) |
| 2490 | .qmax(128) |
| 2491 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2492 | } |
| 2493 | } |
| 2494 | |
| 2495 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_lt_8) { |
| 2496 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2497 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 2498 | DWConvMicrokernelTester() |
| 2499 | .cr(8) |
| 2500 | .kr(4) |
| 2501 | .channels(channels) |
| 2502 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2503 | } |
| 2504 | } |
| 2505 | |
| 2506 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_gt_8) { |
| 2507 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2508 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 2509 | DWConvMicrokernelTester() |
| 2510 | .cr(8) |
| 2511 | .kr(4) |
| 2512 | .channels(channels) |
| 2513 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2514 | } |
| 2515 | } |
| 2516 | |
| 2517 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_gt_8_with_qmin) { |
| 2518 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2519 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 2520 | DWConvMicrokernelTester() |
| 2521 | .cr(8) |
| 2522 | .kr(4) |
| 2523 | .channels(channels) |
| 2524 | .qmin(128) |
| 2525 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2526 | } |
| 2527 | } |
| 2528 | |
| 2529 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, c_gt_8_with_qmax) { |
| 2530 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2531 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 2532 | DWConvMicrokernelTester() |
| 2533 | .cr(8) |
| 2534 | .kr(4) |
| 2535 | .channels(channels) |
| 2536 | .qmax(128) |
| 2537 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2538 | } |
| 2539 | } |
| 2540 | |
| 2541 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, multipixel) { |
| 2542 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2543 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2544 | DWConvMicrokernelTester() |
| 2545 | .cr(8) |
| 2546 | .kr(4) |
| 2547 | .channels(channels) |
| 2548 | .width(3) |
| 2549 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2550 | } |
| 2551 | } |
| 2552 | |
| 2553 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, multipixel_with_step) { |
| 2554 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2555 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2556 | for (size_t step = 2; step <= 4; step++) { |
| 2557 | DWConvMicrokernelTester() |
| 2558 | .cr(8) |
| 2559 | .kr(4) |
| 2560 | .channels(channels) |
| 2561 | .width(3) |
| 2562 | .step(step) |
| 2563 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2564 | } |
| 2565 | } |
| 2566 | } |
| 2567 | |
| 2568 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, multipixel_with_output_stride) { |
| 2569 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2570 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2571 | DWConvMicrokernelTester() |
| 2572 | .cr(8) |
| 2573 | .kr(4) |
| 2574 | .channels(8) |
| 2575 | .width(5) |
| 2576 | .output_stride(43) |
| 2577 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2578 | } |
| 2579 | } |
| 2580 | |
| 2581 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, multipixel_with_qmin) { |
| 2582 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2583 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2584 | DWConvMicrokernelTester() |
| 2585 | .cr(8) |
| 2586 | .kr(4) |
| 2587 | .channels(channels) |
| 2588 | .width(3) |
| 2589 | .qmin(128) |
| 2590 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2591 | } |
| 2592 | } |
| 2593 | |
| 2594 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, multipixel_with_qmax) { |
| 2595 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2596 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 2597 | DWConvMicrokernelTester() |
| 2598 | .cr(8) |
| 2599 | .kr(4) |
| 2600 | .channels(channels) |
| 2601 | .width(3) |
| 2602 | .qmax(128) |
| 2603 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2604 | } |
| 2605 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 2606 | |
| 2607 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, input_offset) { |
| 2608 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2609 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2610 | DWConvMicrokernelTester() |
| 2611 | .cr(8) |
| 2612 | .kr(4) |
| 2613 | .channels(channels) |
| 2614 | .input_offset(176) |
| 2615 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2616 | } |
| 2617 | } |
| 2618 | |
| 2619 | TEST(F32_DWCONV_MINMAX_UP8X4__NEONFMA_ACC2, zero) { |
| 2620 | TEST_REQUIRES_ARM_NEON_FMA; |
| 2621 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 2622 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 2623 | DWConvMicrokernelTester() |
| 2624 | .cr(8) |
| 2625 | .kr(4) |
| 2626 | .channels(channels) |
| 2627 | .input_offset(176) |
| 2628 | .zero_index(mz) |
| 2629 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neonfma_acc2); |
| 2630 | } |
| 2631 | } |
| 2632 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 2633 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2634 | |
| 2635 | |
| 2636 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2637 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_eq_4) { |
| 2638 | TEST_REQUIRES_ARM_NEON; |
| 2639 | DWConvMicrokernelTester() |
| 2640 | .cr(4) |
| 2641 | .kr(25) |
| 2642 | .channels(4) |
| 2643 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2644 | } |
| 2645 | |
| 2646 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_div_4) { |
| 2647 | TEST_REQUIRES_ARM_NEON; |
| 2648 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2649 | DWConvMicrokernelTester() |
| 2650 | .cr(4) |
| 2651 | .kr(25) |
| 2652 | .channels(channels) |
| 2653 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2654 | } |
| 2655 | } |
| 2656 | |
| 2657 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_div_4_with_qmin) { |
| 2658 | TEST_REQUIRES_ARM_NEON; |
| 2659 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2660 | DWConvMicrokernelTester() |
| 2661 | .cr(4) |
| 2662 | .kr(25) |
| 2663 | .channels(channels) |
| 2664 | .qmin(128) |
| 2665 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2666 | } |
| 2667 | } |
| 2668 | |
| 2669 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_div_4_with_qmax) { |
| 2670 | TEST_REQUIRES_ARM_NEON; |
| 2671 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2672 | DWConvMicrokernelTester() |
| 2673 | .cr(4) |
| 2674 | .kr(25) |
| 2675 | .channels(channels) |
| 2676 | .qmax(128) |
| 2677 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2678 | } |
| 2679 | } |
| 2680 | |
| 2681 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_lt_4) { |
| 2682 | TEST_REQUIRES_ARM_NEON; |
| 2683 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 2684 | DWConvMicrokernelTester() |
| 2685 | .cr(4) |
| 2686 | .kr(25) |
| 2687 | .channels(channels) |
| 2688 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2689 | } |
| 2690 | } |
| 2691 | |
| 2692 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_gt_4) { |
| 2693 | TEST_REQUIRES_ARM_NEON; |
| 2694 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2695 | DWConvMicrokernelTester() |
| 2696 | .cr(4) |
| 2697 | .kr(25) |
| 2698 | .channels(channels) |
| 2699 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2700 | } |
| 2701 | } |
| 2702 | |
| 2703 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_gt_4_with_qmin) { |
| 2704 | TEST_REQUIRES_ARM_NEON; |
| 2705 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2706 | DWConvMicrokernelTester() |
| 2707 | .cr(4) |
| 2708 | .kr(25) |
| 2709 | .channels(channels) |
| 2710 | .qmin(128) |
| 2711 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2712 | } |
| 2713 | } |
| 2714 | |
| 2715 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, c_gt_4_with_qmax) { |
| 2716 | TEST_REQUIRES_ARM_NEON; |
| 2717 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2718 | DWConvMicrokernelTester() |
| 2719 | .cr(4) |
| 2720 | .kr(25) |
| 2721 | .channels(channels) |
| 2722 | .qmax(128) |
| 2723 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2724 | } |
| 2725 | } |
| 2726 | |
| 2727 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, multipixel) { |
| 2728 | TEST_REQUIRES_ARM_NEON; |
| 2729 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2730 | DWConvMicrokernelTester() |
| 2731 | .cr(4) |
| 2732 | .kr(25) |
| 2733 | .channels(channels) |
| 2734 | .width(3) |
| 2735 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2736 | } |
| 2737 | } |
| 2738 | |
| 2739 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, multipixel_with_step) { |
| 2740 | TEST_REQUIRES_ARM_NEON; |
| 2741 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2742 | for (size_t step = 2; step <= 25; step++) { |
| 2743 | DWConvMicrokernelTester() |
| 2744 | .cr(4) |
| 2745 | .kr(25) |
| 2746 | .channels(channels) |
| 2747 | .width(3) |
| 2748 | .step(step) |
| 2749 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2750 | } |
| 2751 | } |
| 2752 | } |
| 2753 | |
| 2754 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, multipixel_with_output_stride) { |
| 2755 | TEST_REQUIRES_ARM_NEON; |
| 2756 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2757 | DWConvMicrokernelTester() |
| 2758 | .cr(4) |
| 2759 | .kr(25) |
| 2760 | .channels(4) |
| 2761 | .width(5) |
| 2762 | .output_stride(23) |
| 2763 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2764 | } |
| 2765 | } |
| 2766 | |
| 2767 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, multipixel_with_qmin) { |
| 2768 | TEST_REQUIRES_ARM_NEON; |
| 2769 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2770 | DWConvMicrokernelTester() |
| 2771 | .cr(4) |
| 2772 | .kr(25) |
| 2773 | .channels(channels) |
| 2774 | .width(3) |
| 2775 | .qmin(128) |
| 2776 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2777 | } |
| 2778 | } |
| 2779 | |
| 2780 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, multipixel_with_qmax) { |
| 2781 | TEST_REQUIRES_ARM_NEON; |
| 2782 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2783 | DWConvMicrokernelTester() |
| 2784 | .cr(4) |
| 2785 | .kr(25) |
| 2786 | .channels(channels) |
| 2787 | .width(3) |
| 2788 | .qmax(128) |
| 2789 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2790 | } |
| 2791 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 2792 | |
| 2793 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, input_offset) { |
| 2794 | TEST_REQUIRES_ARM_NEON; |
| 2795 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2796 | DWConvMicrokernelTester() |
| 2797 | .cr(4) |
| 2798 | .kr(25) |
| 2799 | .channels(channels) |
| 2800 | .input_offset(112) |
| 2801 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2802 | } |
| 2803 | } |
| 2804 | |
| 2805 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON, zero) { |
| 2806 | TEST_REQUIRES_ARM_NEON; |
| 2807 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 2808 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2809 | DWConvMicrokernelTester() |
| 2810 | .cr(4) |
| 2811 | .kr(25) |
| 2812 | .channels(channels) |
| 2813 | .input_offset(112) |
| 2814 | .zero_index(mz) |
| 2815 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon); |
| 2816 | } |
| 2817 | } |
| 2818 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 2819 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2820 | |
| 2821 | |
| 2822 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 2823 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_eq_4) { |
| 2824 | TEST_REQUIRES_ARM_NEON; |
| 2825 | DWConvMicrokernelTester() |
| 2826 | .cr(4) |
| 2827 | .kr(25) |
| 2828 | .channels(4) |
| 2829 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2830 | } |
| 2831 | |
| 2832 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_div_4) { |
| 2833 | TEST_REQUIRES_ARM_NEON; |
| 2834 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2835 | DWConvMicrokernelTester() |
| 2836 | .cr(4) |
| 2837 | .kr(25) |
| 2838 | .channels(channels) |
| 2839 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2840 | } |
| 2841 | } |
| 2842 | |
| 2843 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_div_4_with_qmin) { |
| 2844 | TEST_REQUIRES_ARM_NEON; |
| 2845 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2846 | DWConvMicrokernelTester() |
| 2847 | .cr(4) |
| 2848 | .kr(25) |
| 2849 | .channels(channels) |
| 2850 | .qmin(128) |
| 2851 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2852 | } |
| 2853 | } |
| 2854 | |
| 2855 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_div_4_with_qmax) { |
| 2856 | TEST_REQUIRES_ARM_NEON; |
| 2857 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2858 | DWConvMicrokernelTester() |
| 2859 | .cr(4) |
| 2860 | .kr(25) |
| 2861 | .channels(channels) |
| 2862 | .qmax(128) |
| 2863 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2864 | } |
| 2865 | } |
| 2866 | |
| 2867 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_lt_4) { |
| 2868 | TEST_REQUIRES_ARM_NEON; |
| 2869 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 2870 | DWConvMicrokernelTester() |
| 2871 | .cr(4) |
| 2872 | .kr(25) |
| 2873 | .channels(channels) |
| 2874 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2875 | } |
| 2876 | } |
| 2877 | |
| 2878 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_gt_4) { |
| 2879 | TEST_REQUIRES_ARM_NEON; |
| 2880 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2881 | DWConvMicrokernelTester() |
| 2882 | .cr(4) |
| 2883 | .kr(25) |
| 2884 | .channels(channels) |
| 2885 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2886 | } |
| 2887 | } |
| 2888 | |
| 2889 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_gt_4_with_qmin) { |
| 2890 | TEST_REQUIRES_ARM_NEON; |
| 2891 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2892 | DWConvMicrokernelTester() |
| 2893 | .cr(4) |
| 2894 | .kr(25) |
| 2895 | .channels(channels) |
| 2896 | .qmin(128) |
| 2897 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2898 | } |
| 2899 | } |
| 2900 | |
| 2901 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, c_gt_4_with_qmax) { |
| 2902 | TEST_REQUIRES_ARM_NEON; |
| 2903 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 2904 | DWConvMicrokernelTester() |
| 2905 | .cr(4) |
| 2906 | .kr(25) |
| 2907 | .channels(channels) |
| 2908 | .qmax(128) |
| 2909 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2910 | } |
| 2911 | } |
| 2912 | |
| 2913 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, multipixel) { |
| 2914 | TEST_REQUIRES_ARM_NEON; |
| 2915 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2916 | DWConvMicrokernelTester() |
| 2917 | .cr(4) |
| 2918 | .kr(25) |
| 2919 | .channels(channels) |
| 2920 | .width(3) |
| 2921 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2922 | } |
| 2923 | } |
| 2924 | |
| 2925 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, multipixel_with_step) { |
| 2926 | TEST_REQUIRES_ARM_NEON; |
| 2927 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2928 | for (size_t step = 2; step <= 25; step++) { |
| 2929 | DWConvMicrokernelTester() |
| 2930 | .cr(4) |
| 2931 | .kr(25) |
| 2932 | .channels(channels) |
| 2933 | .width(3) |
| 2934 | .step(step) |
| 2935 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2936 | } |
| 2937 | } |
| 2938 | } |
| 2939 | |
| 2940 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, multipixel_with_output_stride) { |
| 2941 | TEST_REQUIRES_ARM_NEON; |
| 2942 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2943 | DWConvMicrokernelTester() |
| 2944 | .cr(4) |
| 2945 | .kr(25) |
| 2946 | .channels(4) |
| 2947 | .width(5) |
| 2948 | .output_stride(23) |
| 2949 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2950 | } |
| 2951 | } |
| 2952 | |
| 2953 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, multipixel_with_qmin) { |
| 2954 | TEST_REQUIRES_ARM_NEON; |
| 2955 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2956 | DWConvMicrokernelTester() |
| 2957 | .cr(4) |
| 2958 | .kr(25) |
| 2959 | .channels(channels) |
| 2960 | .width(3) |
| 2961 | .qmin(128) |
| 2962 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2963 | } |
| 2964 | } |
| 2965 | |
| 2966 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, multipixel_with_qmax) { |
| 2967 | TEST_REQUIRES_ARM_NEON; |
| 2968 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 2969 | DWConvMicrokernelTester() |
| 2970 | .cr(4) |
| 2971 | .kr(25) |
| 2972 | .channels(channels) |
| 2973 | .width(3) |
| 2974 | .qmax(128) |
| 2975 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2976 | } |
| 2977 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 2978 | |
| 2979 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, input_offset) { |
| 2980 | TEST_REQUIRES_ARM_NEON; |
| 2981 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2982 | DWConvMicrokernelTester() |
| 2983 | .cr(4) |
| 2984 | .kr(25) |
| 2985 | .channels(channels) |
| 2986 | .input_offset(112) |
| 2987 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 2988 | } |
| 2989 | } |
| 2990 | |
| 2991 | TEST(F32_DWCONV_MINMAX_UP4X25__NEON_ACC2, zero) { |
| 2992 | TEST_REQUIRES_ARM_NEON; |
| 2993 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 2994 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 2995 | DWConvMicrokernelTester() |
| 2996 | .cr(4) |
| 2997 | .kr(25) |
| 2998 | .channels(channels) |
| 2999 | .input_offset(112) |
| 3000 | .zero_index(mz) |
| 3001 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__neon_acc2); |
| 3002 | } |
| 3003 | } |
| 3004 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 3005 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3006 | |
| 3007 | |
| 3008 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3009 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_eq_8) { |
| 3010 | TEST_REQUIRES_ARM_NEON; |
| 3011 | DWConvMicrokernelTester() |
| 3012 | .cr(8) |
| 3013 | .kr(25) |
| 3014 | .channels(8) |
| 3015 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3016 | } |
| 3017 | |
| 3018 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_div_8) { |
| 3019 | TEST_REQUIRES_ARM_NEON; |
| 3020 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3021 | DWConvMicrokernelTester() |
| 3022 | .cr(8) |
| 3023 | .kr(25) |
| 3024 | .channels(channels) |
| 3025 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3026 | } |
| 3027 | } |
| 3028 | |
| 3029 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_div_8_with_qmin) { |
| 3030 | TEST_REQUIRES_ARM_NEON; |
| 3031 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3032 | DWConvMicrokernelTester() |
| 3033 | .cr(8) |
| 3034 | .kr(25) |
| 3035 | .channels(channels) |
| 3036 | .qmin(128) |
| 3037 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3038 | } |
| 3039 | } |
| 3040 | |
| 3041 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_div_8_with_qmax) { |
| 3042 | TEST_REQUIRES_ARM_NEON; |
| 3043 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3044 | DWConvMicrokernelTester() |
| 3045 | .cr(8) |
| 3046 | .kr(25) |
| 3047 | .channels(channels) |
| 3048 | .qmax(128) |
| 3049 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3050 | } |
| 3051 | } |
| 3052 | |
| 3053 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_lt_8) { |
| 3054 | TEST_REQUIRES_ARM_NEON; |
| 3055 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 3056 | DWConvMicrokernelTester() |
| 3057 | .cr(8) |
| 3058 | .kr(25) |
| 3059 | .channels(channels) |
| 3060 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3061 | } |
| 3062 | } |
| 3063 | |
| 3064 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_gt_8) { |
| 3065 | TEST_REQUIRES_ARM_NEON; |
| 3066 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3067 | DWConvMicrokernelTester() |
| 3068 | .cr(8) |
| 3069 | .kr(25) |
| 3070 | .channels(channels) |
| 3071 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3072 | } |
| 3073 | } |
| 3074 | |
| 3075 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_gt_8_with_qmin) { |
| 3076 | TEST_REQUIRES_ARM_NEON; |
| 3077 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3078 | DWConvMicrokernelTester() |
| 3079 | .cr(8) |
| 3080 | .kr(25) |
| 3081 | .channels(channels) |
| 3082 | .qmin(128) |
| 3083 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3084 | } |
| 3085 | } |
| 3086 | |
| 3087 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, c_gt_8_with_qmax) { |
| 3088 | TEST_REQUIRES_ARM_NEON; |
| 3089 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3090 | DWConvMicrokernelTester() |
| 3091 | .cr(8) |
| 3092 | .kr(25) |
| 3093 | .channels(channels) |
| 3094 | .qmax(128) |
| 3095 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3096 | } |
| 3097 | } |
| 3098 | |
| 3099 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, multipixel) { |
| 3100 | TEST_REQUIRES_ARM_NEON; |
| 3101 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3102 | DWConvMicrokernelTester() |
| 3103 | .cr(8) |
| 3104 | .kr(25) |
| 3105 | .channels(channels) |
| 3106 | .width(3) |
| 3107 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3108 | } |
| 3109 | } |
| 3110 | |
| 3111 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, multipixel_with_step) { |
| 3112 | TEST_REQUIRES_ARM_NEON; |
| 3113 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3114 | for (size_t step = 2; step <= 25; step++) { |
| 3115 | DWConvMicrokernelTester() |
| 3116 | .cr(8) |
| 3117 | .kr(25) |
| 3118 | .channels(channels) |
| 3119 | .width(3) |
| 3120 | .step(step) |
| 3121 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3122 | } |
| 3123 | } |
| 3124 | } |
| 3125 | |
| 3126 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, multipixel_with_output_stride) { |
| 3127 | TEST_REQUIRES_ARM_NEON; |
| 3128 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3129 | DWConvMicrokernelTester() |
| 3130 | .cr(8) |
| 3131 | .kr(25) |
| 3132 | .channels(8) |
| 3133 | .width(5) |
| 3134 | .output_stride(43) |
| 3135 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3136 | } |
| 3137 | } |
| 3138 | |
| 3139 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, multipixel_with_qmin) { |
| 3140 | TEST_REQUIRES_ARM_NEON; |
| 3141 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3142 | DWConvMicrokernelTester() |
| 3143 | .cr(8) |
| 3144 | .kr(25) |
| 3145 | .channels(channels) |
| 3146 | .width(3) |
| 3147 | .qmin(128) |
| 3148 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3149 | } |
| 3150 | } |
| 3151 | |
| 3152 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, multipixel_with_qmax) { |
| 3153 | TEST_REQUIRES_ARM_NEON; |
| 3154 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3155 | DWConvMicrokernelTester() |
| 3156 | .cr(8) |
| 3157 | .kr(25) |
| 3158 | .channels(channels) |
| 3159 | .width(3) |
| 3160 | .qmax(128) |
| 3161 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3162 | } |
| 3163 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 3164 | |
| 3165 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, input_offset) { |
| 3166 | TEST_REQUIRES_ARM_NEON; |
| 3167 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3168 | DWConvMicrokernelTester() |
| 3169 | .cr(8) |
| 3170 | .kr(25) |
| 3171 | .channels(channels) |
| 3172 | .input_offset(176) |
| 3173 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3174 | } |
| 3175 | } |
| 3176 | |
| 3177 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON, zero) { |
| 3178 | TEST_REQUIRES_ARM_NEON; |
| 3179 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 3180 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3181 | DWConvMicrokernelTester() |
| 3182 | .cr(8) |
| 3183 | .kr(25) |
| 3184 | .channels(channels) |
| 3185 | .input_offset(176) |
| 3186 | .zero_index(mz) |
| 3187 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon); |
| 3188 | } |
| 3189 | } |
| 3190 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 3191 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3192 | |
| 3193 | |
| 3194 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3195 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_eq_8) { |
| 3196 | TEST_REQUIRES_ARM_NEON; |
| 3197 | DWConvMicrokernelTester() |
| 3198 | .cr(8) |
| 3199 | .kr(25) |
| 3200 | .channels(8) |
| 3201 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3202 | } |
| 3203 | |
| 3204 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_div_8) { |
| 3205 | TEST_REQUIRES_ARM_NEON; |
| 3206 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3207 | DWConvMicrokernelTester() |
| 3208 | .cr(8) |
| 3209 | .kr(25) |
| 3210 | .channels(channels) |
| 3211 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3212 | } |
| 3213 | } |
| 3214 | |
| 3215 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_div_8_with_qmin) { |
| 3216 | TEST_REQUIRES_ARM_NEON; |
| 3217 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3218 | DWConvMicrokernelTester() |
| 3219 | .cr(8) |
| 3220 | .kr(25) |
| 3221 | .channels(channels) |
| 3222 | .qmin(128) |
| 3223 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3224 | } |
| 3225 | } |
| 3226 | |
| 3227 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_div_8_with_qmax) { |
| 3228 | TEST_REQUIRES_ARM_NEON; |
| 3229 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3230 | DWConvMicrokernelTester() |
| 3231 | .cr(8) |
| 3232 | .kr(25) |
| 3233 | .channels(channels) |
| 3234 | .qmax(128) |
| 3235 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3236 | } |
| 3237 | } |
| 3238 | |
| 3239 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_lt_8) { |
| 3240 | TEST_REQUIRES_ARM_NEON; |
| 3241 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 3242 | DWConvMicrokernelTester() |
| 3243 | .cr(8) |
| 3244 | .kr(25) |
| 3245 | .channels(channels) |
| 3246 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3247 | } |
| 3248 | } |
| 3249 | |
| 3250 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_gt_8) { |
| 3251 | TEST_REQUIRES_ARM_NEON; |
| 3252 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3253 | DWConvMicrokernelTester() |
| 3254 | .cr(8) |
| 3255 | .kr(25) |
| 3256 | .channels(channels) |
| 3257 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3258 | } |
| 3259 | } |
| 3260 | |
| 3261 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_gt_8_with_qmin) { |
| 3262 | TEST_REQUIRES_ARM_NEON; |
| 3263 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3264 | DWConvMicrokernelTester() |
| 3265 | .cr(8) |
| 3266 | .kr(25) |
| 3267 | .channels(channels) |
| 3268 | .qmin(128) |
| 3269 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3270 | } |
| 3271 | } |
| 3272 | |
| 3273 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, c_gt_8_with_qmax) { |
| 3274 | TEST_REQUIRES_ARM_NEON; |
| 3275 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3276 | DWConvMicrokernelTester() |
| 3277 | .cr(8) |
| 3278 | .kr(25) |
| 3279 | .channels(channels) |
| 3280 | .qmax(128) |
| 3281 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3282 | } |
| 3283 | } |
| 3284 | |
| 3285 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, multipixel) { |
| 3286 | TEST_REQUIRES_ARM_NEON; |
| 3287 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3288 | DWConvMicrokernelTester() |
| 3289 | .cr(8) |
| 3290 | .kr(25) |
| 3291 | .channels(channels) |
| 3292 | .width(3) |
| 3293 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3294 | } |
| 3295 | } |
| 3296 | |
| 3297 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, multipixel_with_step) { |
| 3298 | TEST_REQUIRES_ARM_NEON; |
| 3299 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3300 | for (size_t step = 2; step <= 25; step++) { |
| 3301 | DWConvMicrokernelTester() |
| 3302 | .cr(8) |
| 3303 | .kr(25) |
| 3304 | .channels(channels) |
| 3305 | .width(3) |
| 3306 | .step(step) |
| 3307 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3308 | } |
| 3309 | } |
| 3310 | } |
| 3311 | |
| 3312 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, multipixel_with_output_stride) { |
| 3313 | TEST_REQUIRES_ARM_NEON; |
| 3314 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3315 | DWConvMicrokernelTester() |
| 3316 | .cr(8) |
| 3317 | .kr(25) |
| 3318 | .channels(8) |
| 3319 | .width(5) |
| 3320 | .output_stride(43) |
| 3321 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3322 | } |
| 3323 | } |
| 3324 | |
| 3325 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, multipixel_with_qmin) { |
| 3326 | TEST_REQUIRES_ARM_NEON; |
| 3327 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3328 | DWConvMicrokernelTester() |
| 3329 | .cr(8) |
| 3330 | .kr(25) |
| 3331 | .channels(channels) |
| 3332 | .width(3) |
| 3333 | .qmin(128) |
| 3334 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3335 | } |
| 3336 | } |
| 3337 | |
| 3338 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, multipixel_with_qmax) { |
| 3339 | TEST_REQUIRES_ARM_NEON; |
| 3340 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3341 | DWConvMicrokernelTester() |
| 3342 | .cr(8) |
| 3343 | .kr(25) |
| 3344 | .channels(channels) |
| 3345 | .width(3) |
| 3346 | .qmax(128) |
| 3347 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3348 | } |
| 3349 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 3350 | |
| 3351 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, input_offset) { |
| 3352 | TEST_REQUIRES_ARM_NEON; |
| 3353 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3354 | DWConvMicrokernelTester() |
| 3355 | .cr(8) |
| 3356 | .kr(25) |
| 3357 | .channels(channels) |
| 3358 | .input_offset(176) |
| 3359 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3360 | } |
| 3361 | } |
| 3362 | |
| 3363 | TEST(F32_DWCONV_MINMAX_UP8X25__NEON_ACC2, zero) { |
| 3364 | TEST_REQUIRES_ARM_NEON; |
| 3365 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 3366 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3367 | DWConvMicrokernelTester() |
| 3368 | .cr(8) |
| 3369 | .kr(25) |
| 3370 | .channels(channels) |
| 3371 | .input_offset(176) |
| 3372 | .zero_index(mz) |
| 3373 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__neon_acc2); |
| 3374 | } |
| 3375 | } |
| 3376 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 3377 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3378 | |
| 3379 | |
| 3380 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3381 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3382 | TEST_REQUIRES_ARM_NEON; |
| 3383 | DWConvMicrokernelTester() |
| 3384 | .cr(4) |
| 3385 | .kr(9) |
| 3386 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3387 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3388 | } |
| 3389 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3390 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3391 | TEST_REQUIRES_ARM_NEON; |
| 3392 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3393 | DWConvMicrokernelTester() |
| 3394 | .cr(4) |
| 3395 | .kr(9) |
| 3396 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3397 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3398 | } |
| 3399 | } |
| 3400 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3401 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3402 | TEST_REQUIRES_ARM_NEON; |
| 3403 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3404 | DWConvMicrokernelTester() |
| 3405 | .cr(4) |
| 3406 | .kr(9) |
| 3407 | .channels(channels) |
| 3408 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3409 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3410 | } |
| 3411 | } |
| 3412 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3413 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3414 | TEST_REQUIRES_ARM_NEON; |
| 3415 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3416 | DWConvMicrokernelTester() |
| 3417 | .cr(4) |
| 3418 | .kr(9) |
| 3419 | .channels(channels) |
| 3420 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3421 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3422 | } |
| 3423 | } |
| 3424 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3425 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3426 | TEST_REQUIRES_ARM_NEON; |
| 3427 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 3428 | DWConvMicrokernelTester() |
| 3429 | .cr(4) |
| 3430 | .kr(9) |
| 3431 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3432 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3433 | } |
| 3434 | } |
| 3435 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3436 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3437 | TEST_REQUIRES_ARM_NEON; |
| 3438 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 3439 | DWConvMicrokernelTester() |
| 3440 | .cr(4) |
| 3441 | .kr(9) |
| 3442 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3443 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3444 | } |
| 3445 | } |
| 3446 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3447 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3448 | TEST_REQUIRES_ARM_NEON; |
| 3449 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 3450 | DWConvMicrokernelTester() |
| 3451 | .cr(4) |
| 3452 | .kr(9) |
| 3453 | .channels(channels) |
| 3454 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3455 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3456 | } |
| 3457 | } |
| 3458 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3459 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3460 | TEST_REQUIRES_ARM_NEON; |
| 3461 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 3462 | DWConvMicrokernelTester() |
| 3463 | .cr(4) |
| 3464 | .kr(9) |
| 3465 | .channels(channels) |
| 3466 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3467 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3468 | } |
| 3469 | } |
| 3470 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3471 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3472 | TEST_REQUIRES_ARM_NEON; |
| 3473 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3474 | DWConvMicrokernelTester() |
| 3475 | .cr(4) |
| 3476 | .kr(9) |
| 3477 | .channels(channels) |
| 3478 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3479 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3480 | } |
| 3481 | } |
| 3482 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3483 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3484 | TEST_REQUIRES_ARM_NEON; |
| 3485 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3486 | for (size_t step = 2; step <= 9; step++) { |
| 3487 | DWConvMicrokernelTester() |
| 3488 | .cr(4) |
| 3489 | .kr(9) |
| 3490 | .channels(channels) |
| 3491 | .width(3) |
| 3492 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3493 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3494 | } |
| 3495 | } |
| 3496 | } |
| 3497 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3498 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3499 | TEST_REQUIRES_ARM_NEON; |
| 3500 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3501 | DWConvMicrokernelTester() |
| 3502 | .cr(4) |
| 3503 | .kr(9) |
| 3504 | .channels(4) |
| 3505 | .width(5) |
| 3506 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3507 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3508 | } |
| 3509 | } |
| 3510 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3511 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3512 | TEST_REQUIRES_ARM_NEON; |
| 3513 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3514 | DWConvMicrokernelTester() |
| 3515 | .cr(4) |
| 3516 | .kr(9) |
| 3517 | .channels(channels) |
| 3518 | .width(3) |
| 3519 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3520 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3521 | } |
| 3522 | } |
| 3523 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3524 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3525 | TEST_REQUIRES_ARM_NEON; |
| 3526 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3527 | DWConvMicrokernelTester() |
| 3528 | .cr(4) |
| 3529 | .kr(9) |
| 3530 | .channels(channels) |
| 3531 | .width(3) |
| 3532 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3533 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3534 | } |
| 3535 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 3536 | |
| 3537 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, input_offset) { |
| 3538 | TEST_REQUIRES_ARM_NEON; |
| 3539 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3540 | DWConvMicrokernelTester() |
| 3541 | .cr(4) |
| 3542 | .kr(9) |
| 3543 | .channels(channels) |
| 3544 | .input_offset(112) |
| 3545 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
| 3546 | } |
| 3547 | } |
| 3548 | |
| 3549 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON, zero) { |
| 3550 | TEST_REQUIRES_ARM_NEON; |
| 3551 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 3552 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3553 | DWConvMicrokernelTester() |
| 3554 | .cr(4) |
| 3555 | .kr(9) |
| 3556 | .channels(channels) |
| 3557 | .input_offset(112) |
| 3558 | .zero_index(mz) |
| 3559 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon); |
| 3560 | } |
| 3561 | } |
| 3562 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3563 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3564 | |
| 3565 | |
| 3566 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3567 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3568 | TEST_REQUIRES_ARM_NEON; |
| 3569 | DWConvMicrokernelTester() |
| 3570 | .cr(4) |
| 3571 | .kr(9) |
| 3572 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3573 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3574 | } |
| 3575 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3576 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3577 | TEST_REQUIRES_ARM_NEON; |
| 3578 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3579 | DWConvMicrokernelTester() |
| 3580 | .cr(4) |
| 3581 | .kr(9) |
| 3582 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3583 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3584 | } |
| 3585 | } |
| 3586 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3587 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3588 | TEST_REQUIRES_ARM_NEON; |
| 3589 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3590 | DWConvMicrokernelTester() |
| 3591 | .cr(4) |
| 3592 | .kr(9) |
| 3593 | .channels(channels) |
| 3594 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3595 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3596 | } |
| 3597 | } |
| 3598 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3599 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3600 | TEST_REQUIRES_ARM_NEON; |
| 3601 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3602 | DWConvMicrokernelTester() |
| 3603 | .cr(4) |
| 3604 | .kr(9) |
| 3605 | .channels(channels) |
| 3606 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3607 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3608 | } |
| 3609 | } |
| 3610 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3611 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3612 | TEST_REQUIRES_ARM_NEON; |
| 3613 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 3614 | DWConvMicrokernelTester() |
| 3615 | .cr(4) |
| 3616 | .kr(9) |
| 3617 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3618 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3619 | } |
| 3620 | } |
| 3621 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3622 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3623 | TEST_REQUIRES_ARM_NEON; |
| 3624 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 3625 | DWConvMicrokernelTester() |
| 3626 | .cr(4) |
| 3627 | .kr(9) |
| 3628 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3629 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3630 | } |
| 3631 | } |
| 3632 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3633 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3634 | TEST_REQUIRES_ARM_NEON; |
| 3635 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 3636 | DWConvMicrokernelTester() |
| 3637 | .cr(4) |
| 3638 | .kr(9) |
| 3639 | .channels(channels) |
| 3640 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3641 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3642 | } |
| 3643 | } |
| 3644 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3645 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3646 | TEST_REQUIRES_ARM_NEON; |
| 3647 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 3648 | DWConvMicrokernelTester() |
| 3649 | .cr(4) |
| 3650 | .kr(9) |
| 3651 | .channels(channels) |
| 3652 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3653 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3654 | } |
| 3655 | } |
| 3656 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3657 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3658 | TEST_REQUIRES_ARM_NEON; |
| 3659 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3660 | DWConvMicrokernelTester() |
| 3661 | .cr(4) |
| 3662 | .kr(9) |
| 3663 | .channels(channels) |
| 3664 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3665 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3666 | } |
| 3667 | } |
| 3668 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3669 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3670 | TEST_REQUIRES_ARM_NEON; |
| 3671 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3672 | for (size_t step = 2; step <= 9; step++) { |
| 3673 | DWConvMicrokernelTester() |
| 3674 | .cr(4) |
| 3675 | .kr(9) |
| 3676 | .channels(channels) |
| 3677 | .width(3) |
| 3678 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3679 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3680 | } |
| 3681 | } |
| 3682 | } |
| 3683 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3684 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3685 | TEST_REQUIRES_ARM_NEON; |
| 3686 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3687 | DWConvMicrokernelTester() |
| 3688 | .cr(4) |
| 3689 | .kr(9) |
| 3690 | .channels(4) |
| 3691 | .width(5) |
| 3692 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3693 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3694 | } |
| 3695 | } |
| 3696 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3697 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3698 | TEST_REQUIRES_ARM_NEON; |
| 3699 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3700 | DWConvMicrokernelTester() |
| 3701 | .cr(4) |
| 3702 | .kr(9) |
| 3703 | .channels(channels) |
| 3704 | .width(3) |
| 3705 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3706 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3707 | } |
| 3708 | } |
| 3709 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3710 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3711 | TEST_REQUIRES_ARM_NEON; |
| 3712 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 3713 | DWConvMicrokernelTester() |
| 3714 | .cr(4) |
| 3715 | .kr(9) |
| 3716 | .channels(channels) |
| 3717 | .width(3) |
| 3718 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3719 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3720 | } |
| 3721 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 3722 | |
| 3723 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, input_offset) { |
| 3724 | TEST_REQUIRES_ARM_NEON; |
| 3725 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3726 | DWConvMicrokernelTester() |
| 3727 | .cr(4) |
| 3728 | .kr(9) |
| 3729 | .channels(channels) |
| 3730 | .input_offset(112) |
| 3731 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
| 3732 | } |
| 3733 | } |
| 3734 | |
| 3735 | TEST(F32_DWCONV_MINMAX_UP4X9__NEON_ACC2, zero) { |
| 3736 | TEST_REQUIRES_ARM_NEON; |
| 3737 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 3738 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 3739 | DWConvMicrokernelTester() |
| 3740 | .cr(4) |
| 3741 | .kr(9) |
| 3742 | .channels(channels) |
| 3743 | .input_offset(112) |
| 3744 | .zero_index(mz) |
| 3745 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__neon_acc2); |
| 3746 | } |
| 3747 | } |
| 3748 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3749 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3750 | |
| 3751 | |
| 3752 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3753 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3754 | TEST_REQUIRES_ARM_NEON; |
| 3755 | DWConvMicrokernelTester() |
| 3756 | .cr(8) |
| 3757 | .kr(9) |
| 3758 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3759 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3760 | } |
| 3761 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3762 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3763 | TEST_REQUIRES_ARM_NEON; |
| 3764 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3765 | DWConvMicrokernelTester() |
| 3766 | .cr(8) |
| 3767 | .kr(9) |
| 3768 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3769 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3770 | } |
| 3771 | } |
| 3772 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3773 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3774 | TEST_REQUIRES_ARM_NEON; |
| 3775 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3776 | DWConvMicrokernelTester() |
| 3777 | .cr(8) |
| 3778 | .kr(9) |
| 3779 | .channels(channels) |
| 3780 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3781 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3782 | } |
| 3783 | } |
| 3784 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3785 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3786 | TEST_REQUIRES_ARM_NEON; |
| 3787 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3788 | DWConvMicrokernelTester() |
| 3789 | .cr(8) |
| 3790 | .kr(9) |
| 3791 | .channels(channels) |
| 3792 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3793 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3794 | } |
| 3795 | } |
| 3796 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3797 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3798 | TEST_REQUIRES_ARM_NEON; |
| 3799 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 3800 | DWConvMicrokernelTester() |
| 3801 | .cr(8) |
| 3802 | .kr(9) |
| 3803 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3804 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3805 | } |
| 3806 | } |
| 3807 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3808 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3809 | TEST_REQUIRES_ARM_NEON; |
| 3810 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3811 | DWConvMicrokernelTester() |
| 3812 | .cr(8) |
| 3813 | .kr(9) |
| 3814 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3815 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3816 | } |
| 3817 | } |
| 3818 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3819 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3820 | TEST_REQUIRES_ARM_NEON; |
| 3821 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3822 | DWConvMicrokernelTester() |
| 3823 | .cr(8) |
| 3824 | .kr(9) |
| 3825 | .channels(channels) |
| 3826 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3827 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3828 | } |
| 3829 | } |
| 3830 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3831 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3832 | TEST_REQUIRES_ARM_NEON; |
| 3833 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3834 | DWConvMicrokernelTester() |
| 3835 | .cr(8) |
| 3836 | .kr(9) |
| 3837 | .channels(channels) |
| 3838 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3839 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3840 | } |
| 3841 | } |
| 3842 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3843 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3844 | TEST_REQUIRES_ARM_NEON; |
| 3845 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3846 | DWConvMicrokernelTester() |
| 3847 | .cr(8) |
| 3848 | .kr(9) |
| 3849 | .channels(channels) |
| 3850 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3851 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3852 | } |
| 3853 | } |
| 3854 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3855 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3856 | TEST_REQUIRES_ARM_NEON; |
| 3857 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3858 | for (size_t step = 2; step <= 9; step++) { |
| 3859 | DWConvMicrokernelTester() |
| 3860 | .cr(8) |
| 3861 | .kr(9) |
| 3862 | .channels(channels) |
| 3863 | .width(3) |
| 3864 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3865 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3866 | } |
| 3867 | } |
| 3868 | } |
| 3869 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3870 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3871 | TEST_REQUIRES_ARM_NEON; |
| 3872 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3873 | DWConvMicrokernelTester() |
| 3874 | .cr(8) |
| 3875 | .kr(9) |
| 3876 | .channels(8) |
| 3877 | .width(5) |
| 3878 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3879 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3880 | } |
| 3881 | } |
| 3882 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3883 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3884 | TEST_REQUIRES_ARM_NEON; |
| 3885 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3886 | DWConvMicrokernelTester() |
| 3887 | .cr(8) |
| 3888 | .kr(9) |
| 3889 | .channels(channels) |
| 3890 | .width(3) |
| 3891 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3892 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3893 | } |
| 3894 | } |
| 3895 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3896 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3897 | TEST_REQUIRES_ARM_NEON; |
| 3898 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 3899 | DWConvMicrokernelTester() |
| 3900 | .cr(8) |
| 3901 | .kr(9) |
| 3902 | .channels(channels) |
| 3903 | .width(3) |
| 3904 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3905 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3906 | } |
| 3907 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 3908 | |
| 3909 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, input_offset) { |
| 3910 | TEST_REQUIRES_ARM_NEON; |
| 3911 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3912 | DWConvMicrokernelTester() |
| 3913 | .cr(8) |
| 3914 | .kr(9) |
| 3915 | .channels(channels) |
| 3916 | .input_offset(176) |
| 3917 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
| 3918 | } |
| 3919 | } |
| 3920 | |
| 3921 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON, zero) { |
| 3922 | TEST_REQUIRES_ARM_NEON; |
| 3923 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 3924 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3925 | DWConvMicrokernelTester() |
| 3926 | .cr(8) |
| 3927 | .kr(9) |
| 3928 | .channels(channels) |
| 3929 | .input_offset(176) |
| 3930 | .zero_index(mz) |
| 3931 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon); |
| 3932 | } |
| 3933 | } |
| 3934 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3935 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 3936 | |
| 3937 | |
| 3938 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3939 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3940 | TEST_REQUIRES_ARM_NEON; |
| 3941 | DWConvMicrokernelTester() |
| 3942 | .cr(8) |
| 3943 | .kr(9) |
| 3944 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3945 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3946 | } |
| 3947 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3948 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3949 | TEST_REQUIRES_ARM_NEON; |
| 3950 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3951 | DWConvMicrokernelTester() |
| 3952 | .cr(8) |
| 3953 | .kr(9) |
| 3954 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3955 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3956 | } |
| 3957 | } |
| 3958 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3959 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3960 | TEST_REQUIRES_ARM_NEON; |
| 3961 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3962 | DWConvMicrokernelTester() |
| 3963 | .cr(8) |
| 3964 | .kr(9) |
| 3965 | .channels(channels) |
| 3966 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3967 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3968 | } |
| 3969 | } |
| 3970 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3971 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3972 | TEST_REQUIRES_ARM_NEON; |
| 3973 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 3974 | DWConvMicrokernelTester() |
| 3975 | .cr(8) |
| 3976 | .kr(9) |
| 3977 | .channels(channels) |
| 3978 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3979 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3980 | } |
| 3981 | } |
| 3982 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3983 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3984 | TEST_REQUIRES_ARM_NEON; |
| 3985 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 3986 | DWConvMicrokernelTester() |
| 3987 | .cr(8) |
| 3988 | .kr(9) |
| 3989 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3990 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3991 | } |
| 3992 | } |
| 3993 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 3994 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 3995 | TEST_REQUIRES_ARM_NEON; |
| 3996 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 3997 | DWConvMicrokernelTester() |
| 3998 | .cr(8) |
| 3999 | .kr(9) |
| 4000 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4001 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4002 | } |
| 4003 | } |
| 4004 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4005 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4006 | TEST_REQUIRES_ARM_NEON; |
| 4007 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4008 | DWConvMicrokernelTester() |
| 4009 | .cr(8) |
| 4010 | .kr(9) |
| 4011 | .channels(channels) |
| 4012 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4013 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4014 | } |
| 4015 | } |
| 4016 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4017 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4018 | TEST_REQUIRES_ARM_NEON; |
| 4019 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4020 | DWConvMicrokernelTester() |
| 4021 | .cr(8) |
| 4022 | .kr(9) |
| 4023 | .channels(channels) |
| 4024 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4025 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4026 | } |
| 4027 | } |
| 4028 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4029 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4030 | TEST_REQUIRES_ARM_NEON; |
| 4031 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4032 | DWConvMicrokernelTester() |
| 4033 | .cr(8) |
| 4034 | .kr(9) |
| 4035 | .channels(channels) |
| 4036 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4037 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4038 | } |
| 4039 | } |
| 4040 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4041 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4042 | TEST_REQUIRES_ARM_NEON; |
| 4043 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4044 | for (size_t step = 2; step <= 9; step++) { |
| 4045 | DWConvMicrokernelTester() |
| 4046 | .cr(8) |
| 4047 | .kr(9) |
| 4048 | .channels(channels) |
| 4049 | .width(3) |
| 4050 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4051 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4052 | } |
| 4053 | } |
| 4054 | } |
| 4055 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4056 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4057 | TEST_REQUIRES_ARM_NEON; |
| 4058 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4059 | DWConvMicrokernelTester() |
| 4060 | .cr(8) |
| 4061 | .kr(9) |
| 4062 | .channels(8) |
| 4063 | .width(5) |
| 4064 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4065 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4066 | } |
| 4067 | } |
| 4068 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4069 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4070 | TEST_REQUIRES_ARM_NEON; |
| 4071 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4072 | DWConvMicrokernelTester() |
| 4073 | .cr(8) |
| 4074 | .kr(9) |
| 4075 | .channels(channels) |
| 4076 | .width(3) |
| 4077 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4078 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4079 | } |
| 4080 | } |
| 4081 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4082 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4083 | TEST_REQUIRES_ARM_NEON; |
| 4084 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4085 | DWConvMicrokernelTester() |
| 4086 | .cr(8) |
| 4087 | .kr(9) |
| 4088 | .channels(channels) |
| 4089 | .width(3) |
| 4090 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4091 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4092 | } |
| 4093 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 4094 | |
| 4095 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, input_offset) { |
| 4096 | TEST_REQUIRES_ARM_NEON; |
| 4097 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4098 | DWConvMicrokernelTester() |
| 4099 | .cr(8) |
| 4100 | .kr(9) |
| 4101 | .channels(channels) |
| 4102 | .input_offset(176) |
| 4103 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
| 4104 | } |
| 4105 | } |
| 4106 | |
| 4107 | TEST(F32_DWCONV_MINMAX_UP8X9__NEON_ACC2, zero) { |
| 4108 | TEST_REQUIRES_ARM_NEON; |
| 4109 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 4110 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4111 | DWConvMicrokernelTester() |
| 4112 | .cr(8) |
| 4113 | .kr(9) |
| 4114 | .channels(channels) |
| 4115 | .input_offset(176) |
| 4116 | .zero_index(mz) |
| 4117 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__neon_acc2); |
| 4118 | } |
| 4119 | } |
| 4120 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4121 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4122 | |
| 4123 | |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 4124 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4125 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_eq_4) { |
| 4126 | TEST_REQUIRES_ARM_NEON; |
| 4127 | DWConvMicrokernelTester() |
| 4128 | .cr(4) |
| 4129 | .kr(4) |
| 4130 | .channels(4) |
| 4131 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4132 | } |
| 4133 | |
| 4134 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_div_4) { |
| 4135 | TEST_REQUIRES_ARM_NEON; |
| 4136 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4137 | DWConvMicrokernelTester() |
| 4138 | .cr(4) |
| 4139 | .kr(4) |
| 4140 | .channels(channels) |
| 4141 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4142 | } |
| 4143 | } |
| 4144 | |
| 4145 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_div_4_with_qmin) { |
| 4146 | TEST_REQUIRES_ARM_NEON; |
| 4147 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4148 | DWConvMicrokernelTester() |
| 4149 | .cr(4) |
| 4150 | .kr(4) |
| 4151 | .channels(channels) |
| 4152 | .qmin(128) |
| 4153 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4154 | } |
| 4155 | } |
| 4156 | |
| 4157 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_div_4_with_qmax) { |
| 4158 | TEST_REQUIRES_ARM_NEON; |
| 4159 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4160 | DWConvMicrokernelTester() |
| 4161 | .cr(4) |
| 4162 | .kr(4) |
| 4163 | .channels(channels) |
| 4164 | .qmax(128) |
| 4165 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4166 | } |
| 4167 | } |
| 4168 | |
| 4169 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_lt_4) { |
| 4170 | TEST_REQUIRES_ARM_NEON; |
| 4171 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 4172 | DWConvMicrokernelTester() |
| 4173 | .cr(4) |
| 4174 | .kr(4) |
| 4175 | .channels(channels) |
| 4176 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4177 | } |
| 4178 | } |
| 4179 | |
| 4180 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_gt_4) { |
| 4181 | TEST_REQUIRES_ARM_NEON; |
| 4182 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4183 | DWConvMicrokernelTester() |
| 4184 | .cr(4) |
| 4185 | .kr(4) |
| 4186 | .channels(channels) |
| 4187 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4188 | } |
| 4189 | } |
| 4190 | |
| 4191 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_gt_4_with_qmin) { |
| 4192 | TEST_REQUIRES_ARM_NEON; |
| 4193 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4194 | DWConvMicrokernelTester() |
| 4195 | .cr(4) |
| 4196 | .kr(4) |
| 4197 | .channels(channels) |
| 4198 | .qmin(128) |
| 4199 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4200 | } |
| 4201 | } |
| 4202 | |
| 4203 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, c_gt_4_with_qmax) { |
| 4204 | TEST_REQUIRES_ARM_NEON; |
| 4205 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4206 | DWConvMicrokernelTester() |
| 4207 | .cr(4) |
| 4208 | .kr(4) |
| 4209 | .channels(channels) |
| 4210 | .qmax(128) |
| 4211 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4212 | } |
| 4213 | } |
| 4214 | |
| 4215 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, multipixel) { |
| 4216 | TEST_REQUIRES_ARM_NEON; |
| 4217 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4218 | DWConvMicrokernelTester() |
| 4219 | .cr(4) |
| 4220 | .kr(4) |
| 4221 | .channels(channels) |
| 4222 | .width(3) |
| 4223 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4224 | } |
| 4225 | } |
| 4226 | |
| 4227 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, multipixel_with_step) { |
| 4228 | TEST_REQUIRES_ARM_NEON; |
| 4229 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4230 | for (size_t step = 2; step <= 4; step++) { |
| 4231 | DWConvMicrokernelTester() |
| 4232 | .cr(4) |
| 4233 | .kr(4) |
| 4234 | .channels(channels) |
| 4235 | .width(3) |
| 4236 | .step(step) |
| 4237 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4238 | } |
| 4239 | } |
| 4240 | } |
| 4241 | |
| 4242 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, multipixel_with_output_stride) { |
| 4243 | TEST_REQUIRES_ARM_NEON; |
| 4244 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4245 | DWConvMicrokernelTester() |
| 4246 | .cr(4) |
| 4247 | .kr(4) |
| 4248 | .channels(4) |
| 4249 | .width(5) |
| 4250 | .output_stride(23) |
| 4251 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4252 | } |
| 4253 | } |
| 4254 | |
| 4255 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, multipixel_with_qmin) { |
| 4256 | TEST_REQUIRES_ARM_NEON; |
| 4257 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4258 | DWConvMicrokernelTester() |
| 4259 | .cr(4) |
| 4260 | .kr(4) |
| 4261 | .channels(channels) |
| 4262 | .width(3) |
| 4263 | .qmin(128) |
| 4264 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4265 | } |
| 4266 | } |
| 4267 | |
| 4268 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, multipixel_with_qmax) { |
| 4269 | TEST_REQUIRES_ARM_NEON; |
| 4270 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4271 | DWConvMicrokernelTester() |
| 4272 | .cr(4) |
| 4273 | .kr(4) |
| 4274 | .channels(channels) |
| 4275 | .width(3) |
| 4276 | .qmax(128) |
| 4277 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4278 | } |
| 4279 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 4280 | |
| 4281 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, input_offset) { |
| 4282 | TEST_REQUIRES_ARM_NEON; |
| 4283 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4284 | DWConvMicrokernelTester() |
| 4285 | .cr(4) |
| 4286 | .kr(4) |
| 4287 | .channels(channels) |
| 4288 | .input_offset(112) |
| 4289 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4290 | } |
| 4291 | } |
| 4292 | |
| 4293 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON, zero) { |
| 4294 | TEST_REQUIRES_ARM_NEON; |
| 4295 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 4296 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4297 | DWConvMicrokernelTester() |
| 4298 | .cr(4) |
| 4299 | .kr(4) |
| 4300 | .channels(channels) |
| 4301 | .input_offset(112) |
| 4302 | .zero_index(mz) |
| 4303 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon); |
| 4304 | } |
| 4305 | } |
| 4306 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 4307 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4308 | |
| 4309 | |
| 4310 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4311 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_eq_4) { |
| 4312 | TEST_REQUIRES_ARM_NEON; |
| 4313 | DWConvMicrokernelTester() |
| 4314 | .cr(4) |
| 4315 | .kr(4) |
| 4316 | .channels(4) |
| 4317 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4318 | } |
| 4319 | |
| 4320 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_div_4) { |
| 4321 | TEST_REQUIRES_ARM_NEON; |
| 4322 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4323 | DWConvMicrokernelTester() |
| 4324 | .cr(4) |
| 4325 | .kr(4) |
| 4326 | .channels(channels) |
| 4327 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4328 | } |
| 4329 | } |
| 4330 | |
| 4331 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_div_4_with_qmin) { |
| 4332 | TEST_REQUIRES_ARM_NEON; |
| 4333 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4334 | DWConvMicrokernelTester() |
| 4335 | .cr(4) |
| 4336 | .kr(4) |
| 4337 | .channels(channels) |
| 4338 | .qmin(128) |
| 4339 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4340 | } |
| 4341 | } |
| 4342 | |
| 4343 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_div_4_with_qmax) { |
| 4344 | TEST_REQUIRES_ARM_NEON; |
| 4345 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4346 | DWConvMicrokernelTester() |
| 4347 | .cr(4) |
| 4348 | .kr(4) |
| 4349 | .channels(channels) |
| 4350 | .qmax(128) |
| 4351 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4352 | } |
| 4353 | } |
| 4354 | |
| 4355 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_lt_4) { |
| 4356 | TEST_REQUIRES_ARM_NEON; |
| 4357 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 4358 | DWConvMicrokernelTester() |
| 4359 | .cr(4) |
| 4360 | .kr(4) |
| 4361 | .channels(channels) |
| 4362 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4363 | } |
| 4364 | } |
| 4365 | |
| 4366 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_gt_4) { |
| 4367 | TEST_REQUIRES_ARM_NEON; |
| 4368 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4369 | DWConvMicrokernelTester() |
| 4370 | .cr(4) |
| 4371 | .kr(4) |
| 4372 | .channels(channels) |
| 4373 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4374 | } |
| 4375 | } |
| 4376 | |
| 4377 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_gt_4_with_qmin) { |
| 4378 | TEST_REQUIRES_ARM_NEON; |
| 4379 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4380 | DWConvMicrokernelTester() |
| 4381 | .cr(4) |
| 4382 | .kr(4) |
| 4383 | .channels(channels) |
| 4384 | .qmin(128) |
| 4385 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4386 | } |
| 4387 | } |
| 4388 | |
| 4389 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, c_gt_4_with_qmax) { |
| 4390 | TEST_REQUIRES_ARM_NEON; |
| 4391 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4392 | DWConvMicrokernelTester() |
| 4393 | .cr(4) |
| 4394 | .kr(4) |
| 4395 | .channels(channels) |
| 4396 | .qmax(128) |
| 4397 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4398 | } |
| 4399 | } |
| 4400 | |
| 4401 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, multipixel) { |
| 4402 | TEST_REQUIRES_ARM_NEON; |
| 4403 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4404 | DWConvMicrokernelTester() |
| 4405 | .cr(4) |
| 4406 | .kr(4) |
| 4407 | .channels(channels) |
| 4408 | .width(3) |
| 4409 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4410 | } |
| 4411 | } |
| 4412 | |
| 4413 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, multipixel_with_step) { |
| 4414 | TEST_REQUIRES_ARM_NEON; |
| 4415 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4416 | for (size_t step = 2; step <= 4; step++) { |
| 4417 | DWConvMicrokernelTester() |
| 4418 | .cr(4) |
| 4419 | .kr(4) |
| 4420 | .channels(channels) |
| 4421 | .width(3) |
| 4422 | .step(step) |
| 4423 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4424 | } |
| 4425 | } |
| 4426 | } |
| 4427 | |
| 4428 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, multipixel_with_output_stride) { |
| 4429 | TEST_REQUIRES_ARM_NEON; |
| 4430 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4431 | DWConvMicrokernelTester() |
| 4432 | .cr(4) |
| 4433 | .kr(4) |
| 4434 | .channels(4) |
| 4435 | .width(5) |
| 4436 | .output_stride(23) |
| 4437 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4438 | } |
| 4439 | } |
| 4440 | |
| 4441 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, multipixel_with_qmin) { |
| 4442 | TEST_REQUIRES_ARM_NEON; |
| 4443 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4444 | DWConvMicrokernelTester() |
| 4445 | .cr(4) |
| 4446 | .kr(4) |
| 4447 | .channels(channels) |
| 4448 | .width(3) |
| 4449 | .qmin(128) |
| 4450 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4451 | } |
| 4452 | } |
| 4453 | |
| 4454 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, multipixel_with_qmax) { |
| 4455 | TEST_REQUIRES_ARM_NEON; |
| 4456 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4457 | DWConvMicrokernelTester() |
| 4458 | .cr(4) |
| 4459 | .kr(4) |
| 4460 | .channels(channels) |
| 4461 | .width(3) |
| 4462 | .qmax(128) |
| 4463 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4464 | } |
| 4465 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 4466 | |
| 4467 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, input_offset) { |
| 4468 | TEST_REQUIRES_ARM_NEON; |
| 4469 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4470 | DWConvMicrokernelTester() |
| 4471 | .cr(4) |
| 4472 | .kr(4) |
| 4473 | .channels(channels) |
| 4474 | .input_offset(112) |
| 4475 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4476 | } |
| 4477 | } |
| 4478 | |
| 4479 | TEST(F32_DWCONV_MINMAX_UP4X4__NEON_ACC2, zero) { |
| 4480 | TEST_REQUIRES_ARM_NEON; |
| 4481 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 4482 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4483 | DWConvMicrokernelTester() |
| 4484 | .cr(4) |
| 4485 | .kr(4) |
| 4486 | .channels(channels) |
| 4487 | .input_offset(112) |
| 4488 | .zero_index(mz) |
| 4489 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__neon_acc2); |
| 4490 | } |
| 4491 | } |
| 4492 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 4493 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4494 | |
| 4495 | |
| 4496 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4497 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_eq_8) { |
| 4498 | TEST_REQUIRES_ARM_NEON; |
| 4499 | DWConvMicrokernelTester() |
| 4500 | .cr(8) |
| 4501 | .kr(4) |
| 4502 | .channels(8) |
| 4503 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4504 | } |
| 4505 | |
| 4506 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_div_8) { |
| 4507 | TEST_REQUIRES_ARM_NEON; |
| 4508 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4509 | DWConvMicrokernelTester() |
| 4510 | .cr(8) |
| 4511 | .kr(4) |
| 4512 | .channels(channels) |
| 4513 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4514 | } |
| 4515 | } |
| 4516 | |
| 4517 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_div_8_with_qmin) { |
| 4518 | TEST_REQUIRES_ARM_NEON; |
| 4519 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4520 | DWConvMicrokernelTester() |
| 4521 | .cr(8) |
| 4522 | .kr(4) |
| 4523 | .channels(channels) |
| 4524 | .qmin(128) |
| 4525 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4526 | } |
| 4527 | } |
| 4528 | |
| 4529 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_div_8_with_qmax) { |
| 4530 | TEST_REQUIRES_ARM_NEON; |
| 4531 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4532 | DWConvMicrokernelTester() |
| 4533 | .cr(8) |
| 4534 | .kr(4) |
| 4535 | .channels(channels) |
| 4536 | .qmax(128) |
| 4537 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4538 | } |
| 4539 | } |
| 4540 | |
| 4541 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_lt_8) { |
| 4542 | TEST_REQUIRES_ARM_NEON; |
| 4543 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 4544 | DWConvMicrokernelTester() |
| 4545 | .cr(8) |
| 4546 | .kr(4) |
| 4547 | .channels(channels) |
| 4548 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4549 | } |
| 4550 | } |
| 4551 | |
| 4552 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_gt_8) { |
| 4553 | TEST_REQUIRES_ARM_NEON; |
| 4554 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4555 | DWConvMicrokernelTester() |
| 4556 | .cr(8) |
| 4557 | .kr(4) |
| 4558 | .channels(channels) |
| 4559 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4560 | } |
| 4561 | } |
| 4562 | |
| 4563 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_gt_8_with_qmin) { |
| 4564 | TEST_REQUIRES_ARM_NEON; |
| 4565 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4566 | DWConvMicrokernelTester() |
| 4567 | .cr(8) |
| 4568 | .kr(4) |
| 4569 | .channels(channels) |
| 4570 | .qmin(128) |
| 4571 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4572 | } |
| 4573 | } |
| 4574 | |
| 4575 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, c_gt_8_with_qmax) { |
| 4576 | TEST_REQUIRES_ARM_NEON; |
| 4577 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4578 | DWConvMicrokernelTester() |
| 4579 | .cr(8) |
| 4580 | .kr(4) |
| 4581 | .channels(channels) |
| 4582 | .qmax(128) |
| 4583 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4584 | } |
| 4585 | } |
| 4586 | |
| 4587 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, multipixel) { |
| 4588 | TEST_REQUIRES_ARM_NEON; |
| 4589 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4590 | DWConvMicrokernelTester() |
| 4591 | .cr(8) |
| 4592 | .kr(4) |
| 4593 | .channels(channels) |
| 4594 | .width(3) |
| 4595 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4596 | } |
| 4597 | } |
| 4598 | |
| 4599 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, multipixel_with_step) { |
| 4600 | TEST_REQUIRES_ARM_NEON; |
| 4601 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4602 | for (size_t step = 2; step <= 4; step++) { |
| 4603 | DWConvMicrokernelTester() |
| 4604 | .cr(8) |
| 4605 | .kr(4) |
| 4606 | .channels(channels) |
| 4607 | .width(3) |
| 4608 | .step(step) |
| 4609 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4610 | } |
| 4611 | } |
| 4612 | } |
| 4613 | |
| 4614 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, multipixel_with_output_stride) { |
| 4615 | TEST_REQUIRES_ARM_NEON; |
| 4616 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4617 | DWConvMicrokernelTester() |
| 4618 | .cr(8) |
| 4619 | .kr(4) |
| 4620 | .channels(8) |
| 4621 | .width(5) |
| 4622 | .output_stride(43) |
| 4623 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4624 | } |
| 4625 | } |
| 4626 | |
| 4627 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, multipixel_with_qmin) { |
| 4628 | TEST_REQUIRES_ARM_NEON; |
| 4629 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4630 | DWConvMicrokernelTester() |
| 4631 | .cr(8) |
| 4632 | .kr(4) |
| 4633 | .channels(channels) |
| 4634 | .width(3) |
| 4635 | .qmin(128) |
| 4636 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4637 | } |
| 4638 | } |
| 4639 | |
| 4640 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, multipixel_with_qmax) { |
| 4641 | TEST_REQUIRES_ARM_NEON; |
| 4642 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4643 | DWConvMicrokernelTester() |
| 4644 | .cr(8) |
| 4645 | .kr(4) |
| 4646 | .channels(channels) |
| 4647 | .width(3) |
| 4648 | .qmax(128) |
| 4649 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4650 | } |
| 4651 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 4652 | |
| 4653 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, input_offset) { |
| 4654 | TEST_REQUIRES_ARM_NEON; |
| 4655 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4656 | DWConvMicrokernelTester() |
| 4657 | .cr(8) |
| 4658 | .kr(4) |
| 4659 | .channels(channels) |
| 4660 | .input_offset(176) |
| 4661 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4662 | } |
| 4663 | } |
| 4664 | |
| 4665 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON, zero) { |
| 4666 | TEST_REQUIRES_ARM_NEON; |
| 4667 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 4668 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4669 | DWConvMicrokernelTester() |
| 4670 | .cr(8) |
| 4671 | .kr(4) |
| 4672 | .channels(channels) |
| 4673 | .input_offset(176) |
| 4674 | .zero_index(mz) |
| 4675 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon); |
| 4676 | } |
| 4677 | } |
| 4678 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 4679 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4680 | |
| 4681 | |
| 4682 | #if XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4683 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_eq_8) { |
| 4684 | TEST_REQUIRES_ARM_NEON; |
| 4685 | DWConvMicrokernelTester() |
| 4686 | .cr(8) |
| 4687 | .kr(4) |
| 4688 | .channels(8) |
| 4689 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4690 | } |
| 4691 | |
| 4692 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_div_8) { |
| 4693 | TEST_REQUIRES_ARM_NEON; |
| 4694 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4695 | DWConvMicrokernelTester() |
| 4696 | .cr(8) |
| 4697 | .kr(4) |
| 4698 | .channels(channels) |
| 4699 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4700 | } |
| 4701 | } |
| 4702 | |
| 4703 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_div_8_with_qmin) { |
| 4704 | TEST_REQUIRES_ARM_NEON; |
| 4705 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4706 | DWConvMicrokernelTester() |
| 4707 | .cr(8) |
| 4708 | .kr(4) |
| 4709 | .channels(channels) |
| 4710 | .qmin(128) |
| 4711 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4712 | } |
| 4713 | } |
| 4714 | |
| 4715 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_div_8_with_qmax) { |
| 4716 | TEST_REQUIRES_ARM_NEON; |
| 4717 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4718 | DWConvMicrokernelTester() |
| 4719 | .cr(8) |
| 4720 | .kr(4) |
| 4721 | .channels(channels) |
| 4722 | .qmax(128) |
| 4723 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4724 | } |
| 4725 | } |
| 4726 | |
| 4727 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_lt_8) { |
| 4728 | TEST_REQUIRES_ARM_NEON; |
| 4729 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 4730 | DWConvMicrokernelTester() |
| 4731 | .cr(8) |
| 4732 | .kr(4) |
| 4733 | .channels(channels) |
| 4734 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4735 | } |
| 4736 | } |
| 4737 | |
| 4738 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_gt_8) { |
| 4739 | TEST_REQUIRES_ARM_NEON; |
| 4740 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4741 | DWConvMicrokernelTester() |
| 4742 | .cr(8) |
| 4743 | .kr(4) |
| 4744 | .channels(channels) |
| 4745 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4746 | } |
| 4747 | } |
| 4748 | |
| 4749 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_gt_8_with_qmin) { |
| 4750 | TEST_REQUIRES_ARM_NEON; |
| 4751 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4752 | DWConvMicrokernelTester() |
| 4753 | .cr(8) |
| 4754 | .kr(4) |
| 4755 | .channels(channels) |
| 4756 | .qmin(128) |
| 4757 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4758 | } |
| 4759 | } |
| 4760 | |
| 4761 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, c_gt_8_with_qmax) { |
| 4762 | TEST_REQUIRES_ARM_NEON; |
| 4763 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 4764 | DWConvMicrokernelTester() |
| 4765 | .cr(8) |
| 4766 | .kr(4) |
| 4767 | .channels(channels) |
| 4768 | .qmax(128) |
| 4769 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4770 | } |
| 4771 | } |
| 4772 | |
| 4773 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, multipixel) { |
| 4774 | TEST_REQUIRES_ARM_NEON; |
| 4775 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4776 | DWConvMicrokernelTester() |
| 4777 | .cr(8) |
| 4778 | .kr(4) |
| 4779 | .channels(channels) |
| 4780 | .width(3) |
| 4781 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4782 | } |
| 4783 | } |
| 4784 | |
| 4785 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, multipixel_with_step) { |
| 4786 | TEST_REQUIRES_ARM_NEON; |
| 4787 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4788 | for (size_t step = 2; step <= 4; step++) { |
| 4789 | DWConvMicrokernelTester() |
| 4790 | .cr(8) |
| 4791 | .kr(4) |
| 4792 | .channels(channels) |
| 4793 | .width(3) |
| 4794 | .step(step) |
| 4795 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4796 | } |
| 4797 | } |
| 4798 | } |
| 4799 | |
| 4800 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, multipixel_with_output_stride) { |
| 4801 | TEST_REQUIRES_ARM_NEON; |
| 4802 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4803 | DWConvMicrokernelTester() |
| 4804 | .cr(8) |
| 4805 | .kr(4) |
| 4806 | .channels(8) |
| 4807 | .width(5) |
| 4808 | .output_stride(43) |
| 4809 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4810 | } |
| 4811 | } |
| 4812 | |
| 4813 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, multipixel_with_qmin) { |
| 4814 | TEST_REQUIRES_ARM_NEON; |
| 4815 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4816 | DWConvMicrokernelTester() |
| 4817 | .cr(8) |
| 4818 | .kr(4) |
| 4819 | .channels(channels) |
| 4820 | .width(3) |
| 4821 | .qmin(128) |
| 4822 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4823 | } |
| 4824 | } |
| 4825 | |
| 4826 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, multipixel_with_qmax) { |
| 4827 | TEST_REQUIRES_ARM_NEON; |
| 4828 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 4829 | DWConvMicrokernelTester() |
| 4830 | .cr(8) |
| 4831 | .kr(4) |
| 4832 | .channels(channels) |
| 4833 | .width(3) |
| 4834 | .qmax(128) |
| 4835 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4836 | } |
| 4837 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 4838 | |
| 4839 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, input_offset) { |
| 4840 | TEST_REQUIRES_ARM_NEON; |
| 4841 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4842 | DWConvMicrokernelTester() |
| 4843 | .cr(8) |
| 4844 | .kr(4) |
| 4845 | .channels(channels) |
| 4846 | .input_offset(176) |
| 4847 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4848 | } |
| 4849 | } |
| 4850 | |
| 4851 | TEST(F32_DWCONV_MINMAX_UP8X4__NEON_ACC2, zero) { |
| 4852 | TEST_REQUIRES_ARM_NEON; |
| 4853 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 4854 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 4855 | DWConvMicrokernelTester() |
| 4856 | .cr(8) |
| 4857 | .kr(4) |
| 4858 | .channels(channels) |
| 4859 | .input_offset(176) |
| 4860 | .zero_index(mz) |
| 4861 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__neon_acc2); |
| 4862 | } |
| 4863 | } |
| 4864 | } |
Marat Dukhan | f5425ea | 2020-04-24 01:46:00 -0700 | [diff] [blame] | 4865 | #endif // XNN_ARCH_ARM || XNN_ARCH_ARM64 |
| 4866 | |
| 4867 | |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4868 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4869 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4870 | TEST_REQUIRES_X86_SSE; |
| 4871 | DWConvMicrokernelTester() |
| 4872 | .cr(4) |
| 4873 | .kr(25) |
| 4874 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4875 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4876 | } |
| 4877 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4878 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4879 | TEST_REQUIRES_X86_SSE; |
| 4880 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4881 | DWConvMicrokernelTester() |
| 4882 | .cr(4) |
| 4883 | .kr(25) |
| 4884 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4885 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4886 | } |
| 4887 | } |
| 4888 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4889 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4890 | TEST_REQUIRES_X86_SSE; |
| 4891 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4892 | DWConvMicrokernelTester() |
| 4893 | .cr(4) |
| 4894 | .kr(25) |
| 4895 | .channels(channels) |
| 4896 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4897 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4898 | } |
| 4899 | } |
| 4900 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4901 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4902 | TEST_REQUIRES_X86_SSE; |
| 4903 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 4904 | DWConvMicrokernelTester() |
| 4905 | .cr(4) |
| 4906 | .kr(25) |
| 4907 | .channels(channels) |
| 4908 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4909 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4910 | } |
| 4911 | } |
| 4912 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4913 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4914 | TEST_REQUIRES_X86_SSE; |
| 4915 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 4916 | DWConvMicrokernelTester() |
| 4917 | .cr(4) |
| 4918 | .kr(25) |
| 4919 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4920 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4921 | } |
| 4922 | } |
| 4923 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4924 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4925 | TEST_REQUIRES_X86_SSE; |
| 4926 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4927 | DWConvMicrokernelTester() |
| 4928 | .cr(4) |
| 4929 | .kr(25) |
| 4930 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4931 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4932 | } |
| 4933 | } |
| 4934 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4935 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4936 | TEST_REQUIRES_X86_SSE; |
| 4937 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4938 | DWConvMicrokernelTester() |
| 4939 | .cr(4) |
| 4940 | .kr(25) |
| 4941 | .channels(channels) |
| 4942 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4943 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4944 | } |
| 4945 | } |
| 4946 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4947 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4948 | TEST_REQUIRES_X86_SSE; |
| 4949 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 4950 | DWConvMicrokernelTester() |
| 4951 | .cr(4) |
| 4952 | .kr(25) |
| 4953 | .channels(channels) |
| 4954 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4955 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4956 | } |
| 4957 | } |
| 4958 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4959 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4960 | TEST_REQUIRES_X86_SSE; |
| 4961 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4962 | DWConvMicrokernelTester() |
| 4963 | .cr(4) |
| 4964 | .kr(25) |
| 4965 | .channels(channels) |
| 4966 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4967 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4968 | } |
| 4969 | } |
| 4970 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4971 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4972 | TEST_REQUIRES_X86_SSE; |
| 4973 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4974 | for (size_t step = 2; step <= 25; step++) { |
| 4975 | DWConvMicrokernelTester() |
| 4976 | .cr(4) |
| 4977 | .kr(25) |
| 4978 | .channels(channels) |
| 4979 | .width(3) |
| 4980 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4981 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4982 | } |
| 4983 | } |
| 4984 | } |
| 4985 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4986 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4987 | TEST_REQUIRES_X86_SSE; |
| 4988 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 4989 | DWConvMicrokernelTester() |
| 4990 | .cr(4) |
| 4991 | .kr(25) |
| 4992 | .channels(4) |
| 4993 | .width(5) |
| 4994 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4995 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 4996 | } |
| 4997 | } |
| 4998 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 4999 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5000 | TEST_REQUIRES_X86_SSE; |
| 5001 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5002 | DWConvMicrokernelTester() |
| 5003 | .cr(4) |
| 5004 | .kr(25) |
| 5005 | .channels(channels) |
| 5006 | .width(3) |
| 5007 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5008 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5009 | } |
| 5010 | } |
| 5011 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5012 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5013 | TEST_REQUIRES_X86_SSE; |
| 5014 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5015 | DWConvMicrokernelTester() |
| 5016 | .cr(4) |
| 5017 | .kr(25) |
| 5018 | .channels(channels) |
| 5019 | .width(3) |
| 5020 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5021 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5022 | } |
| 5023 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 5024 | |
| 5025 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, input_offset) { |
| 5026 | TEST_REQUIRES_X86_SSE; |
| 5027 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5028 | DWConvMicrokernelTester() |
| 5029 | .cr(4) |
| 5030 | .kr(25) |
| 5031 | .channels(channels) |
| 5032 | .input_offset(112) |
| 5033 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
| 5034 | } |
| 5035 | } |
| 5036 | |
| 5037 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE, zero) { |
| 5038 | TEST_REQUIRES_X86_SSE; |
| 5039 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 5040 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5041 | DWConvMicrokernelTester() |
| 5042 | .cr(4) |
| 5043 | .kr(25) |
| 5044 | .channels(channels) |
| 5045 | .input_offset(112) |
| 5046 | .zero_index(mz) |
| 5047 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse); |
| 5048 | } |
| 5049 | } |
| 5050 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5051 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5052 | |
| 5053 | |
| 5054 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5055 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5056 | TEST_REQUIRES_X86_SSE; |
| 5057 | DWConvMicrokernelTester() |
| 5058 | .cr(4) |
| 5059 | .kr(25) |
| 5060 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5061 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5062 | } |
| 5063 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5064 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5065 | TEST_REQUIRES_X86_SSE; |
| 5066 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5067 | DWConvMicrokernelTester() |
| 5068 | .cr(4) |
| 5069 | .kr(25) |
| 5070 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5071 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5072 | } |
| 5073 | } |
| 5074 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5075 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5076 | TEST_REQUIRES_X86_SSE; |
| 5077 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5078 | DWConvMicrokernelTester() |
| 5079 | .cr(4) |
| 5080 | .kr(25) |
| 5081 | .channels(channels) |
| 5082 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5083 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5084 | } |
| 5085 | } |
| 5086 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5087 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5088 | TEST_REQUIRES_X86_SSE; |
| 5089 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5090 | DWConvMicrokernelTester() |
| 5091 | .cr(4) |
| 5092 | .kr(25) |
| 5093 | .channels(channels) |
| 5094 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5095 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5096 | } |
| 5097 | } |
| 5098 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5099 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5100 | TEST_REQUIRES_X86_SSE; |
| 5101 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 5102 | DWConvMicrokernelTester() |
| 5103 | .cr(4) |
| 5104 | .kr(25) |
| 5105 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5106 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5107 | } |
| 5108 | } |
| 5109 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5110 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5111 | TEST_REQUIRES_X86_SSE; |
| 5112 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5113 | DWConvMicrokernelTester() |
| 5114 | .cr(4) |
| 5115 | .kr(25) |
| 5116 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5117 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5118 | } |
| 5119 | } |
| 5120 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5121 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5122 | TEST_REQUIRES_X86_SSE; |
| 5123 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5124 | DWConvMicrokernelTester() |
| 5125 | .cr(4) |
| 5126 | .kr(25) |
| 5127 | .channels(channels) |
| 5128 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5129 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5130 | } |
| 5131 | } |
| 5132 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5133 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5134 | TEST_REQUIRES_X86_SSE; |
| 5135 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5136 | DWConvMicrokernelTester() |
| 5137 | .cr(4) |
| 5138 | .kr(25) |
| 5139 | .channels(channels) |
| 5140 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5141 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5142 | } |
| 5143 | } |
| 5144 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5145 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5146 | TEST_REQUIRES_X86_SSE; |
| 5147 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5148 | DWConvMicrokernelTester() |
| 5149 | .cr(4) |
| 5150 | .kr(25) |
| 5151 | .channels(channels) |
| 5152 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5153 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5154 | } |
| 5155 | } |
| 5156 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5157 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5158 | TEST_REQUIRES_X86_SSE; |
| 5159 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5160 | for (size_t step = 2; step <= 25; step++) { |
| 5161 | DWConvMicrokernelTester() |
| 5162 | .cr(4) |
| 5163 | .kr(25) |
| 5164 | .channels(channels) |
| 5165 | .width(3) |
| 5166 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5167 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5168 | } |
| 5169 | } |
| 5170 | } |
| 5171 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5172 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5173 | TEST_REQUIRES_X86_SSE; |
| 5174 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5175 | DWConvMicrokernelTester() |
| 5176 | .cr(4) |
| 5177 | .kr(25) |
| 5178 | .channels(4) |
| 5179 | .width(5) |
| 5180 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5181 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5182 | } |
| 5183 | } |
| 5184 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5185 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5186 | TEST_REQUIRES_X86_SSE; |
| 5187 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5188 | DWConvMicrokernelTester() |
| 5189 | .cr(4) |
| 5190 | .kr(25) |
| 5191 | .channels(channels) |
| 5192 | .width(3) |
| 5193 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5194 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5195 | } |
| 5196 | } |
| 5197 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5198 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5199 | TEST_REQUIRES_X86_SSE; |
| 5200 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5201 | DWConvMicrokernelTester() |
| 5202 | .cr(4) |
| 5203 | .kr(25) |
| 5204 | .channels(channels) |
| 5205 | .width(3) |
| 5206 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5207 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5208 | } |
| 5209 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 5210 | |
| 5211 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, input_offset) { |
| 5212 | TEST_REQUIRES_X86_SSE; |
| 5213 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5214 | DWConvMicrokernelTester() |
| 5215 | .cr(4) |
| 5216 | .kr(25) |
| 5217 | .channels(channels) |
| 5218 | .input_offset(112) |
| 5219 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
| 5220 | } |
| 5221 | } |
| 5222 | |
| 5223 | TEST(F32_DWCONV_MINMAX_UP4X25__SSE_ACC2, zero) { |
| 5224 | TEST_REQUIRES_X86_SSE; |
| 5225 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 5226 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5227 | DWConvMicrokernelTester() |
| 5228 | .cr(4) |
| 5229 | .kr(25) |
| 5230 | .channels(channels) |
| 5231 | .input_offset(112) |
| 5232 | .zero_index(mz) |
| 5233 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__sse_acc2); |
| 5234 | } |
| 5235 | } |
| 5236 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5237 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5238 | |
| 5239 | |
| 5240 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5241 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5242 | TEST_REQUIRES_X86_SSE; |
| 5243 | DWConvMicrokernelTester() |
| 5244 | .cr(8) |
| 5245 | .kr(25) |
| 5246 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5247 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5248 | } |
| 5249 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5250 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5251 | TEST_REQUIRES_X86_SSE; |
| 5252 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5253 | DWConvMicrokernelTester() |
| 5254 | .cr(8) |
| 5255 | .kr(25) |
| 5256 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5257 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5258 | } |
| 5259 | } |
| 5260 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5261 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5262 | TEST_REQUIRES_X86_SSE; |
| 5263 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5264 | DWConvMicrokernelTester() |
| 5265 | .cr(8) |
| 5266 | .kr(25) |
| 5267 | .channels(channels) |
| 5268 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5269 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5270 | } |
| 5271 | } |
| 5272 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5273 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5274 | TEST_REQUIRES_X86_SSE; |
| 5275 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5276 | DWConvMicrokernelTester() |
| 5277 | .cr(8) |
| 5278 | .kr(25) |
| 5279 | .channels(channels) |
| 5280 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5281 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5282 | } |
| 5283 | } |
| 5284 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5285 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5286 | TEST_REQUIRES_X86_SSE; |
| 5287 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 5288 | DWConvMicrokernelTester() |
| 5289 | .cr(8) |
| 5290 | .kr(25) |
| 5291 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5292 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5293 | } |
| 5294 | } |
| 5295 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5296 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5297 | TEST_REQUIRES_X86_SSE; |
| 5298 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 5299 | DWConvMicrokernelTester() |
| 5300 | .cr(8) |
| 5301 | .kr(25) |
| 5302 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5303 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5304 | } |
| 5305 | } |
| 5306 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5307 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5308 | TEST_REQUIRES_X86_SSE; |
| 5309 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 5310 | DWConvMicrokernelTester() |
| 5311 | .cr(8) |
| 5312 | .kr(25) |
| 5313 | .channels(channels) |
| 5314 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5315 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5316 | } |
| 5317 | } |
| 5318 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5319 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5320 | TEST_REQUIRES_X86_SSE; |
| 5321 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 5322 | DWConvMicrokernelTester() |
| 5323 | .cr(8) |
| 5324 | .kr(25) |
| 5325 | .channels(channels) |
| 5326 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5327 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5328 | } |
| 5329 | } |
| 5330 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5331 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5332 | TEST_REQUIRES_X86_SSE; |
| 5333 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5334 | DWConvMicrokernelTester() |
| 5335 | .cr(8) |
| 5336 | .kr(25) |
| 5337 | .channels(channels) |
| 5338 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5339 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5340 | } |
| 5341 | } |
| 5342 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5343 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5344 | TEST_REQUIRES_X86_SSE; |
| 5345 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5346 | for (size_t step = 2; step <= 25; step++) { |
| 5347 | DWConvMicrokernelTester() |
| 5348 | .cr(8) |
| 5349 | .kr(25) |
| 5350 | .channels(channels) |
| 5351 | .width(3) |
| 5352 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5353 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5354 | } |
| 5355 | } |
| 5356 | } |
| 5357 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5358 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5359 | TEST_REQUIRES_X86_SSE; |
| 5360 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5361 | DWConvMicrokernelTester() |
| 5362 | .cr(8) |
| 5363 | .kr(25) |
| 5364 | .channels(8) |
| 5365 | .width(5) |
| 5366 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5367 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5368 | } |
| 5369 | } |
| 5370 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5371 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5372 | TEST_REQUIRES_X86_SSE; |
| 5373 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5374 | DWConvMicrokernelTester() |
| 5375 | .cr(8) |
| 5376 | .kr(25) |
| 5377 | .channels(channels) |
| 5378 | .width(3) |
| 5379 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5380 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5381 | } |
| 5382 | } |
| 5383 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5384 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5385 | TEST_REQUIRES_X86_SSE; |
| 5386 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5387 | DWConvMicrokernelTester() |
| 5388 | .cr(8) |
| 5389 | .kr(25) |
| 5390 | .channels(channels) |
| 5391 | .width(3) |
| 5392 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5393 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5394 | } |
| 5395 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 5396 | |
| 5397 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, input_offset) { |
| 5398 | TEST_REQUIRES_X86_SSE; |
| 5399 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5400 | DWConvMicrokernelTester() |
| 5401 | .cr(8) |
| 5402 | .kr(25) |
| 5403 | .channels(channels) |
| 5404 | .input_offset(176) |
| 5405 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
| 5406 | } |
| 5407 | } |
| 5408 | |
| 5409 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE, zero) { |
| 5410 | TEST_REQUIRES_X86_SSE; |
| 5411 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 5412 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5413 | DWConvMicrokernelTester() |
| 5414 | .cr(8) |
| 5415 | .kr(25) |
| 5416 | .channels(channels) |
| 5417 | .input_offset(176) |
| 5418 | .zero_index(mz) |
| 5419 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse); |
| 5420 | } |
| 5421 | } |
| 5422 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5423 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5424 | |
| 5425 | |
| 5426 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5427 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5428 | TEST_REQUIRES_X86_SSE; |
| 5429 | DWConvMicrokernelTester() |
| 5430 | .cr(8) |
| 5431 | .kr(25) |
| 5432 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5433 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5434 | } |
| 5435 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5436 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5437 | TEST_REQUIRES_X86_SSE; |
| 5438 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5439 | DWConvMicrokernelTester() |
| 5440 | .cr(8) |
| 5441 | .kr(25) |
| 5442 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5443 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5444 | } |
| 5445 | } |
| 5446 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5447 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5448 | TEST_REQUIRES_X86_SSE; |
| 5449 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5450 | DWConvMicrokernelTester() |
| 5451 | .cr(8) |
| 5452 | .kr(25) |
| 5453 | .channels(channels) |
| 5454 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5455 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5456 | } |
| 5457 | } |
| 5458 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5459 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5460 | TEST_REQUIRES_X86_SSE; |
| 5461 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5462 | DWConvMicrokernelTester() |
| 5463 | .cr(8) |
| 5464 | .kr(25) |
| 5465 | .channels(channels) |
| 5466 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5467 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5468 | } |
| 5469 | } |
| 5470 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5471 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5472 | TEST_REQUIRES_X86_SSE; |
| 5473 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 5474 | DWConvMicrokernelTester() |
| 5475 | .cr(8) |
| 5476 | .kr(25) |
| 5477 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5478 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5479 | } |
| 5480 | } |
| 5481 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5482 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5483 | TEST_REQUIRES_X86_SSE; |
| 5484 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 5485 | DWConvMicrokernelTester() |
| 5486 | .cr(8) |
| 5487 | .kr(25) |
| 5488 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5489 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5490 | } |
| 5491 | } |
| 5492 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5493 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5494 | TEST_REQUIRES_X86_SSE; |
| 5495 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 5496 | DWConvMicrokernelTester() |
| 5497 | .cr(8) |
| 5498 | .kr(25) |
| 5499 | .channels(channels) |
| 5500 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5501 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5502 | } |
| 5503 | } |
| 5504 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5505 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5506 | TEST_REQUIRES_X86_SSE; |
| 5507 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 5508 | DWConvMicrokernelTester() |
| 5509 | .cr(8) |
| 5510 | .kr(25) |
| 5511 | .channels(channels) |
| 5512 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5513 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5514 | } |
| 5515 | } |
| 5516 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5517 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5518 | TEST_REQUIRES_X86_SSE; |
| 5519 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5520 | DWConvMicrokernelTester() |
| 5521 | .cr(8) |
| 5522 | .kr(25) |
| 5523 | .channels(channels) |
| 5524 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5525 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5526 | } |
| 5527 | } |
| 5528 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5529 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5530 | TEST_REQUIRES_X86_SSE; |
| 5531 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5532 | for (size_t step = 2; step <= 25; step++) { |
| 5533 | DWConvMicrokernelTester() |
| 5534 | .cr(8) |
| 5535 | .kr(25) |
| 5536 | .channels(channels) |
| 5537 | .width(3) |
| 5538 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5539 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5540 | } |
| 5541 | } |
| 5542 | } |
| 5543 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5544 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5545 | TEST_REQUIRES_X86_SSE; |
| 5546 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5547 | DWConvMicrokernelTester() |
| 5548 | .cr(8) |
| 5549 | .kr(25) |
| 5550 | .channels(8) |
| 5551 | .width(5) |
| 5552 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5553 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5554 | } |
| 5555 | } |
| 5556 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5557 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5558 | TEST_REQUIRES_X86_SSE; |
| 5559 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5560 | DWConvMicrokernelTester() |
| 5561 | .cr(8) |
| 5562 | .kr(25) |
| 5563 | .channels(channels) |
| 5564 | .width(3) |
| 5565 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5566 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5567 | } |
| 5568 | } |
| 5569 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5570 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5571 | TEST_REQUIRES_X86_SSE; |
| 5572 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 5573 | DWConvMicrokernelTester() |
| 5574 | .cr(8) |
| 5575 | .kr(25) |
| 5576 | .channels(channels) |
| 5577 | .width(3) |
| 5578 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5579 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5580 | } |
| 5581 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 5582 | |
| 5583 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, input_offset) { |
| 5584 | TEST_REQUIRES_X86_SSE; |
| 5585 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5586 | DWConvMicrokernelTester() |
| 5587 | .cr(8) |
| 5588 | .kr(25) |
| 5589 | .channels(channels) |
| 5590 | .input_offset(176) |
| 5591 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
| 5592 | } |
| 5593 | } |
| 5594 | |
| 5595 | TEST(F32_DWCONV_MINMAX_UP8X25__SSE_ACC2, zero) { |
| 5596 | TEST_REQUIRES_X86_SSE; |
| 5597 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 5598 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5599 | DWConvMicrokernelTester() |
| 5600 | .cr(8) |
| 5601 | .kr(25) |
| 5602 | .channels(channels) |
| 5603 | .input_offset(176) |
| 5604 | .zero_index(mz) |
| 5605 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__sse_acc2); |
| 5606 | } |
| 5607 | } |
| 5608 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5609 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5610 | |
| 5611 | |
| 5612 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5613 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5614 | TEST_REQUIRES_X86_SSE; |
| 5615 | DWConvMicrokernelTester() |
| 5616 | .cr(4) |
| 5617 | .kr(9) |
| 5618 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5619 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5620 | } |
| 5621 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5622 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5623 | TEST_REQUIRES_X86_SSE; |
| 5624 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5625 | DWConvMicrokernelTester() |
| 5626 | .cr(4) |
| 5627 | .kr(9) |
| 5628 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5629 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5630 | } |
| 5631 | } |
| 5632 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5633 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5634 | TEST_REQUIRES_X86_SSE; |
| 5635 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5636 | DWConvMicrokernelTester() |
| 5637 | .cr(4) |
| 5638 | .kr(9) |
| 5639 | .channels(channels) |
| 5640 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5641 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5642 | } |
| 5643 | } |
| 5644 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5645 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5646 | TEST_REQUIRES_X86_SSE; |
| 5647 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5648 | DWConvMicrokernelTester() |
| 5649 | .cr(4) |
| 5650 | .kr(9) |
| 5651 | .channels(channels) |
| 5652 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5653 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5654 | } |
| 5655 | } |
| 5656 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5657 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5658 | TEST_REQUIRES_X86_SSE; |
| 5659 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 5660 | DWConvMicrokernelTester() |
| 5661 | .cr(4) |
| 5662 | .kr(9) |
| 5663 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5664 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5665 | } |
| 5666 | } |
| 5667 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5668 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5669 | TEST_REQUIRES_X86_SSE; |
| 5670 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5671 | DWConvMicrokernelTester() |
| 5672 | .cr(4) |
| 5673 | .kr(9) |
| 5674 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5675 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5676 | } |
| 5677 | } |
| 5678 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5679 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5680 | TEST_REQUIRES_X86_SSE; |
| 5681 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5682 | DWConvMicrokernelTester() |
| 5683 | .cr(4) |
| 5684 | .kr(9) |
| 5685 | .channels(channels) |
| 5686 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5687 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5688 | } |
| 5689 | } |
| 5690 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5691 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5692 | TEST_REQUIRES_X86_SSE; |
| 5693 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5694 | DWConvMicrokernelTester() |
| 5695 | .cr(4) |
| 5696 | .kr(9) |
| 5697 | .channels(channels) |
| 5698 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5699 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5700 | } |
| 5701 | } |
| 5702 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5703 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5704 | TEST_REQUIRES_X86_SSE; |
| 5705 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5706 | DWConvMicrokernelTester() |
| 5707 | .cr(4) |
| 5708 | .kr(9) |
| 5709 | .channels(channels) |
| 5710 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5711 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5712 | } |
| 5713 | } |
| 5714 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5715 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5716 | TEST_REQUIRES_X86_SSE; |
| 5717 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5718 | for (size_t step = 2; step <= 9; step++) { |
| 5719 | DWConvMicrokernelTester() |
| 5720 | .cr(4) |
| 5721 | .kr(9) |
| 5722 | .channels(channels) |
| 5723 | .width(3) |
| 5724 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5725 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5726 | } |
| 5727 | } |
| 5728 | } |
| 5729 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5730 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5731 | TEST_REQUIRES_X86_SSE; |
| 5732 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5733 | DWConvMicrokernelTester() |
| 5734 | .cr(4) |
| 5735 | .kr(9) |
| 5736 | .channels(4) |
| 5737 | .width(5) |
| 5738 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5739 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5740 | } |
| 5741 | } |
| 5742 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5743 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5744 | TEST_REQUIRES_X86_SSE; |
| 5745 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5746 | DWConvMicrokernelTester() |
| 5747 | .cr(4) |
| 5748 | .kr(9) |
| 5749 | .channels(channels) |
| 5750 | .width(3) |
| 5751 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5752 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5753 | } |
| 5754 | } |
| 5755 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5756 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5757 | TEST_REQUIRES_X86_SSE; |
| 5758 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5759 | DWConvMicrokernelTester() |
| 5760 | .cr(4) |
| 5761 | .kr(9) |
| 5762 | .channels(channels) |
| 5763 | .width(3) |
| 5764 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5765 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5766 | } |
| 5767 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 5768 | |
| 5769 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, input_offset) { |
| 5770 | TEST_REQUIRES_X86_SSE; |
| 5771 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5772 | DWConvMicrokernelTester() |
| 5773 | .cr(4) |
| 5774 | .kr(9) |
| 5775 | .channels(channels) |
| 5776 | .input_offset(112) |
| 5777 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
| 5778 | } |
| 5779 | } |
| 5780 | |
| 5781 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE, zero) { |
| 5782 | TEST_REQUIRES_X86_SSE; |
| 5783 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 5784 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5785 | DWConvMicrokernelTester() |
| 5786 | .cr(4) |
| 5787 | .kr(9) |
| 5788 | .channels(channels) |
| 5789 | .input_offset(112) |
| 5790 | .zero_index(mz) |
| 5791 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse); |
| 5792 | } |
| 5793 | } |
| 5794 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5795 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5796 | |
| 5797 | |
| 5798 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5799 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5800 | TEST_REQUIRES_X86_SSE; |
| 5801 | DWConvMicrokernelTester() |
| 5802 | .cr(4) |
| 5803 | .kr(9) |
| 5804 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5805 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5806 | } |
| 5807 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5808 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5809 | TEST_REQUIRES_X86_SSE; |
| 5810 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5811 | DWConvMicrokernelTester() |
| 5812 | .cr(4) |
| 5813 | .kr(9) |
| 5814 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5815 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5816 | } |
| 5817 | } |
| 5818 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5819 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5820 | TEST_REQUIRES_X86_SSE; |
| 5821 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5822 | DWConvMicrokernelTester() |
| 5823 | .cr(4) |
| 5824 | .kr(9) |
| 5825 | .channels(channels) |
| 5826 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5827 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5828 | } |
| 5829 | } |
| 5830 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5831 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5832 | TEST_REQUIRES_X86_SSE; |
| 5833 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5834 | DWConvMicrokernelTester() |
| 5835 | .cr(4) |
| 5836 | .kr(9) |
| 5837 | .channels(channels) |
| 5838 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5839 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5840 | } |
| 5841 | } |
| 5842 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5843 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5844 | TEST_REQUIRES_X86_SSE; |
| 5845 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 5846 | DWConvMicrokernelTester() |
| 5847 | .cr(4) |
| 5848 | .kr(9) |
| 5849 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5850 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5851 | } |
| 5852 | } |
| 5853 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5854 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5855 | TEST_REQUIRES_X86_SSE; |
| 5856 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5857 | DWConvMicrokernelTester() |
| 5858 | .cr(4) |
| 5859 | .kr(9) |
| 5860 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5861 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5862 | } |
| 5863 | } |
| 5864 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5865 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5866 | TEST_REQUIRES_X86_SSE; |
| 5867 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5868 | DWConvMicrokernelTester() |
| 5869 | .cr(4) |
| 5870 | .kr(9) |
| 5871 | .channels(channels) |
| 5872 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5873 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5874 | } |
| 5875 | } |
| 5876 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5877 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5878 | TEST_REQUIRES_X86_SSE; |
| 5879 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 5880 | DWConvMicrokernelTester() |
| 5881 | .cr(4) |
| 5882 | .kr(9) |
| 5883 | .channels(channels) |
| 5884 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5885 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5886 | } |
| 5887 | } |
| 5888 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5889 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5890 | TEST_REQUIRES_X86_SSE; |
| 5891 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5892 | DWConvMicrokernelTester() |
| 5893 | .cr(4) |
| 5894 | .kr(9) |
| 5895 | .channels(channels) |
| 5896 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5897 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5898 | } |
| 5899 | } |
| 5900 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5901 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5902 | TEST_REQUIRES_X86_SSE; |
| 5903 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5904 | for (size_t step = 2; step <= 9; step++) { |
| 5905 | DWConvMicrokernelTester() |
| 5906 | .cr(4) |
| 5907 | .kr(9) |
| 5908 | .channels(channels) |
| 5909 | .width(3) |
| 5910 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5911 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5912 | } |
| 5913 | } |
| 5914 | } |
| 5915 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5916 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5917 | TEST_REQUIRES_X86_SSE; |
| 5918 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5919 | DWConvMicrokernelTester() |
| 5920 | .cr(4) |
| 5921 | .kr(9) |
| 5922 | .channels(4) |
| 5923 | .width(5) |
| 5924 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5925 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5926 | } |
| 5927 | } |
| 5928 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5929 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5930 | TEST_REQUIRES_X86_SSE; |
| 5931 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5932 | DWConvMicrokernelTester() |
| 5933 | .cr(4) |
| 5934 | .kr(9) |
| 5935 | .channels(channels) |
| 5936 | .width(3) |
| 5937 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5938 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5939 | } |
| 5940 | } |
| 5941 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5942 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5943 | TEST_REQUIRES_X86_SSE; |
| 5944 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 5945 | DWConvMicrokernelTester() |
| 5946 | .cr(4) |
| 5947 | .kr(9) |
| 5948 | .channels(channels) |
| 5949 | .width(3) |
| 5950 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5951 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5952 | } |
| 5953 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 5954 | |
| 5955 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, input_offset) { |
| 5956 | TEST_REQUIRES_X86_SSE; |
| 5957 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5958 | DWConvMicrokernelTester() |
| 5959 | .cr(4) |
| 5960 | .kr(9) |
| 5961 | .channels(channels) |
| 5962 | .input_offset(112) |
| 5963 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
| 5964 | } |
| 5965 | } |
| 5966 | |
| 5967 | TEST(F32_DWCONV_MINMAX_UP4X9__SSE_ACC2, zero) { |
| 5968 | TEST_REQUIRES_X86_SSE; |
| 5969 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 5970 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 5971 | DWConvMicrokernelTester() |
| 5972 | .cr(4) |
| 5973 | .kr(9) |
| 5974 | .channels(channels) |
| 5975 | .input_offset(112) |
| 5976 | .zero_index(mz) |
| 5977 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__sse_acc2); |
| 5978 | } |
| 5979 | } |
| 5980 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5981 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 5982 | |
| 5983 | |
| 5984 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5985 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5986 | TEST_REQUIRES_X86_SSE; |
| 5987 | DWConvMicrokernelTester() |
| 5988 | .cr(8) |
| 5989 | .kr(9) |
| 5990 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5991 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5992 | } |
| 5993 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 5994 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 5995 | TEST_REQUIRES_X86_SSE; |
| 5996 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 5997 | DWConvMicrokernelTester() |
| 5998 | .cr(8) |
| 5999 | .kr(9) |
| 6000 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6001 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6002 | } |
| 6003 | } |
| 6004 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6005 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6006 | TEST_REQUIRES_X86_SSE; |
| 6007 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6008 | DWConvMicrokernelTester() |
| 6009 | .cr(8) |
| 6010 | .kr(9) |
| 6011 | .channels(channels) |
| 6012 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6013 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6014 | } |
| 6015 | } |
| 6016 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6017 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6018 | TEST_REQUIRES_X86_SSE; |
| 6019 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6020 | DWConvMicrokernelTester() |
| 6021 | .cr(8) |
| 6022 | .kr(9) |
| 6023 | .channels(channels) |
| 6024 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6025 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6026 | } |
| 6027 | } |
| 6028 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6029 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6030 | TEST_REQUIRES_X86_SSE; |
| 6031 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 6032 | DWConvMicrokernelTester() |
| 6033 | .cr(8) |
| 6034 | .kr(9) |
| 6035 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6036 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6037 | } |
| 6038 | } |
| 6039 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6040 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6041 | TEST_REQUIRES_X86_SSE; |
| 6042 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6043 | DWConvMicrokernelTester() |
| 6044 | .cr(8) |
| 6045 | .kr(9) |
| 6046 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6047 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6048 | } |
| 6049 | } |
| 6050 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6051 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6052 | TEST_REQUIRES_X86_SSE; |
| 6053 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6054 | DWConvMicrokernelTester() |
| 6055 | .cr(8) |
| 6056 | .kr(9) |
| 6057 | .channels(channels) |
| 6058 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6059 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6060 | } |
| 6061 | } |
| 6062 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6063 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6064 | TEST_REQUIRES_X86_SSE; |
| 6065 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6066 | DWConvMicrokernelTester() |
| 6067 | .cr(8) |
| 6068 | .kr(9) |
| 6069 | .channels(channels) |
| 6070 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6071 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6072 | } |
| 6073 | } |
| 6074 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6075 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6076 | TEST_REQUIRES_X86_SSE; |
| 6077 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6078 | DWConvMicrokernelTester() |
| 6079 | .cr(8) |
| 6080 | .kr(9) |
| 6081 | .channels(channels) |
| 6082 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6083 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6084 | } |
| 6085 | } |
| 6086 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6087 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6088 | TEST_REQUIRES_X86_SSE; |
| 6089 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6090 | for (size_t step = 2; step <= 9; step++) { |
| 6091 | DWConvMicrokernelTester() |
| 6092 | .cr(8) |
| 6093 | .kr(9) |
| 6094 | .channels(channels) |
| 6095 | .width(3) |
| 6096 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6097 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6098 | } |
| 6099 | } |
| 6100 | } |
| 6101 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6102 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6103 | TEST_REQUIRES_X86_SSE; |
| 6104 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6105 | DWConvMicrokernelTester() |
| 6106 | .cr(8) |
| 6107 | .kr(9) |
| 6108 | .channels(8) |
| 6109 | .width(5) |
| 6110 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6111 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6112 | } |
| 6113 | } |
| 6114 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6115 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6116 | TEST_REQUIRES_X86_SSE; |
| 6117 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6118 | DWConvMicrokernelTester() |
| 6119 | .cr(8) |
| 6120 | .kr(9) |
| 6121 | .channels(channels) |
| 6122 | .width(3) |
| 6123 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6124 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6125 | } |
| 6126 | } |
| 6127 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6128 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6129 | TEST_REQUIRES_X86_SSE; |
| 6130 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6131 | DWConvMicrokernelTester() |
| 6132 | .cr(8) |
| 6133 | .kr(9) |
| 6134 | .channels(channels) |
| 6135 | .width(3) |
| 6136 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6137 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6138 | } |
| 6139 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 6140 | |
| 6141 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, input_offset) { |
| 6142 | TEST_REQUIRES_X86_SSE; |
| 6143 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6144 | DWConvMicrokernelTester() |
| 6145 | .cr(8) |
| 6146 | .kr(9) |
| 6147 | .channels(channels) |
| 6148 | .input_offset(176) |
| 6149 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
| 6150 | } |
| 6151 | } |
| 6152 | |
| 6153 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE, zero) { |
| 6154 | TEST_REQUIRES_X86_SSE; |
| 6155 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 6156 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6157 | DWConvMicrokernelTester() |
| 6158 | .cr(8) |
| 6159 | .kr(9) |
| 6160 | .channels(channels) |
| 6161 | .input_offset(176) |
| 6162 | .zero_index(mz) |
| 6163 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse); |
| 6164 | } |
| 6165 | } |
| 6166 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6167 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6168 | |
| 6169 | |
| 6170 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6171 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6172 | TEST_REQUIRES_X86_SSE; |
| 6173 | DWConvMicrokernelTester() |
| 6174 | .cr(8) |
| 6175 | .kr(9) |
| 6176 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6177 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6178 | } |
| 6179 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6180 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6181 | TEST_REQUIRES_X86_SSE; |
| 6182 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6183 | DWConvMicrokernelTester() |
| 6184 | .cr(8) |
| 6185 | .kr(9) |
| 6186 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6187 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6188 | } |
| 6189 | } |
| 6190 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6191 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6192 | TEST_REQUIRES_X86_SSE; |
| 6193 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6194 | DWConvMicrokernelTester() |
| 6195 | .cr(8) |
| 6196 | .kr(9) |
| 6197 | .channels(channels) |
| 6198 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6199 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6200 | } |
| 6201 | } |
| 6202 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6203 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6204 | TEST_REQUIRES_X86_SSE; |
| 6205 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6206 | DWConvMicrokernelTester() |
| 6207 | .cr(8) |
| 6208 | .kr(9) |
| 6209 | .channels(channels) |
| 6210 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6211 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6212 | } |
| 6213 | } |
| 6214 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6215 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6216 | TEST_REQUIRES_X86_SSE; |
| 6217 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 6218 | DWConvMicrokernelTester() |
| 6219 | .cr(8) |
| 6220 | .kr(9) |
| 6221 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6222 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6223 | } |
| 6224 | } |
| 6225 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6226 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6227 | TEST_REQUIRES_X86_SSE; |
| 6228 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6229 | DWConvMicrokernelTester() |
| 6230 | .cr(8) |
| 6231 | .kr(9) |
| 6232 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6233 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6234 | } |
| 6235 | } |
| 6236 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6237 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6238 | TEST_REQUIRES_X86_SSE; |
| 6239 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6240 | DWConvMicrokernelTester() |
| 6241 | .cr(8) |
| 6242 | .kr(9) |
| 6243 | .channels(channels) |
| 6244 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6245 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6246 | } |
| 6247 | } |
| 6248 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6249 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6250 | TEST_REQUIRES_X86_SSE; |
| 6251 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6252 | DWConvMicrokernelTester() |
| 6253 | .cr(8) |
| 6254 | .kr(9) |
| 6255 | .channels(channels) |
| 6256 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6257 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6258 | } |
| 6259 | } |
| 6260 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6261 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6262 | TEST_REQUIRES_X86_SSE; |
| 6263 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6264 | DWConvMicrokernelTester() |
| 6265 | .cr(8) |
| 6266 | .kr(9) |
| 6267 | .channels(channels) |
| 6268 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6269 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6270 | } |
| 6271 | } |
| 6272 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6273 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6274 | TEST_REQUIRES_X86_SSE; |
| 6275 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6276 | for (size_t step = 2; step <= 9; step++) { |
| 6277 | DWConvMicrokernelTester() |
| 6278 | .cr(8) |
| 6279 | .kr(9) |
| 6280 | .channels(channels) |
| 6281 | .width(3) |
| 6282 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6283 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6284 | } |
| 6285 | } |
| 6286 | } |
| 6287 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6288 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6289 | TEST_REQUIRES_X86_SSE; |
| 6290 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6291 | DWConvMicrokernelTester() |
| 6292 | .cr(8) |
| 6293 | .kr(9) |
| 6294 | .channels(8) |
| 6295 | .width(5) |
| 6296 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6297 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6298 | } |
| 6299 | } |
| 6300 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6301 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6302 | TEST_REQUIRES_X86_SSE; |
| 6303 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6304 | DWConvMicrokernelTester() |
| 6305 | .cr(8) |
| 6306 | .kr(9) |
| 6307 | .channels(channels) |
| 6308 | .width(3) |
| 6309 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6310 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6311 | } |
| 6312 | } |
| 6313 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6314 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6315 | TEST_REQUIRES_X86_SSE; |
| 6316 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6317 | DWConvMicrokernelTester() |
| 6318 | .cr(8) |
| 6319 | .kr(9) |
| 6320 | .channels(channels) |
| 6321 | .width(3) |
| 6322 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6323 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6324 | } |
| 6325 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 6326 | |
| 6327 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, input_offset) { |
| 6328 | TEST_REQUIRES_X86_SSE; |
| 6329 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6330 | DWConvMicrokernelTester() |
| 6331 | .cr(8) |
| 6332 | .kr(9) |
| 6333 | .channels(channels) |
| 6334 | .input_offset(176) |
| 6335 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
| 6336 | } |
| 6337 | } |
| 6338 | |
| 6339 | TEST(F32_DWCONV_MINMAX_UP8X9__SSE_ACC2, zero) { |
| 6340 | TEST_REQUIRES_X86_SSE; |
| 6341 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 6342 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6343 | DWConvMicrokernelTester() |
| 6344 | .cr(8) |
| 6345 | .kr(9) |
| 6346 | .channels(channels) |
| 6347 | .input_offset(176) |
| 6348 | .zero_index(mz) |
| 6349 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__sse_acc2); |
| 6350 | } |
| 6351 | } |
| 6352 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6353 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6354 | |
| 6355 | |
| 6356 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6357 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6358 | TEST_REQUIRES_X86_SSE; |
| 6359 | DWConvMicrokernelTester() |
| 6360 | .cr(4) |
| 6361 | .kr(4) |
| 6362 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6363 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6364 | } |
| 6365 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6366 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6367 | TEST_REQUIRES_X86_SSE; |
| 6368 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6369 | DWConvMicrokernelTester() |
| 6370 | .cr(4) |
| 6371 | .kr(4) |
| 6372 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6373 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6374 | } |
| 6375 | } |
| 6376 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6377 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6378 | TEST_REQUIRES_X86_SSE; |
| 6379 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6380 | DWConvMicrokernelTester() |
| 6381 | .cr(4) |
| 6382 | .kr(4) |
| 6383 | .channels(channels) |
| 6384 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6385 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6386 | } |
| 6387 | } |
| 6388 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6389 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6390 | TEST_REQUIRES_X86_SSE; |
| 6391 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6392 | DWConvMicrokernelTester() |
| 6393 | .cr(4) |
| 6394 | .kr(4) |
| 6395 | .channels(channels) |
| 6396 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6397 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6398 | } |
| 6399 | } |
| 6400 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6401 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6402 | TEST_REQUIRES_X86_SSE; |
| 6403 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 6404 | DWConvMicrokernelTester() |
| 6405 | .cr(4) |
| 6406 | .kr(4) |
| 6407 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6408 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6409 | } |
| 6410 | } |
| 6411 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6412 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6413 | TEST_REQUIRES_X86_SSE; |
| 6414 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 6415 | DWConvMicrokernelTester() |
| 6416 | .cr(4) |
| 6417 | .kr(4) |
| 6418 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6419 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6420 | } |
| 6421 | } |
| 6422 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6423 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6424 | TEST_REQUIRES_X86_SSE; |
| 6425 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 6426 | DWConvMicrokernelTester() |
| 6427 | .cr(4) |
| 6428 | .kr(4) |
| 6429 | .channels(channels) |
| 6430 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6431 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6432 | } |
| 6433 | } |
| 6434 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6435 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6436 | TEST_REQUIRES_X86_SSE; |
| 6437 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 6438 | DWConvMicrokernelTester() |
| 6439 | .cr(4) |
| 6440 | .kr(4) |
| 6441 | .channels(channels) |
| 6442 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6443 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6444 | } |
| 6445 | } |
| 6446 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6447 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6448 | TEST_REQUIRES_X86_SSE; |
| 6449 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6450 | DWConvMicrokernelTester() |
| 6451 | .cr(4) |
| 6452 | .kr(4) |
| 6453 | .channels(channels) |
| 6454 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6455 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6456 | } |
| 6457 | } |
| 6458 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6459 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6460 | TEST_REQUIRES_X86_SSE; |
| 6461 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6462 | for (size_t step = 2; step <= 4; step++) { |
| 6463 | DWConvMicrokernelTester() |
| 6464 | .cr(4) |
| 6465 | .kr(4) |
| 6466 | .channels(channels) |
| 6467 | .width(3) |
| 6468 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6469 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6470 | } |
| 6471 | } |
| 6472 | } |
| 6473 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6474 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6475 | TEST_REQUIRES_X86_SSE; |
| 6476 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6477 | DWConvMicrokernelTester() |
| 6478 | .cr(4) |
| 6479 | .kr(4) |
| 6480 | .channels(4) |
| 6481 | .width(5) |
| 6482 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6483 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6484 | } |
| 6485 | } |
| 6486 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6487 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6488 | TEST_REQUIRES_X86_SSE; |
| 6489 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6490 | DWConvMicrokernelTester() |
| 6491 | .cr(4) |
| 6492 | .kr(4) |
| 6493 | .channels(channels) |
| 6494 | .width(3) |
| 6495 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6496 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6497 | } |
| 6498 | } |
| 6499 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6500 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6501 | TEST_REQUIRES_X86_SSE; |
| 6502 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6503 | DWConvMicrokernelTester() |
| 6504 | .cr(4) |
| 6505 | .kr(4) |
| 6506 | .channels(channels) |
| 6507 | .width(3) |
| 6508 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6509 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6510 | } |
| 6511 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 6512 | |
| 6513 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, input_offset) { |
| 6514 | TEST_REQUIRES_X86_SSE; |
| 6515 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6516 | DWConvMicrokernelTester() |
| 6517 | .cr(4) |
| 6518 | .kr(4) |
| 6519 | .channels(channels) |
| 6520 | .input_offset(112) |
| 6521 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
| 6522 | } |
| 6523 | } |
| 6524 | |
| 6525 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE, zero) { |
| 6526 | TEST_REQUIRES_X86_SSE; |
| 6527 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 6528 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6529 | DWConvMicrokernelTester() |
| 6530 | .cr(4) |
| 6531 | .kr(4) |
| 6532 | .channels(channels) |
| 6533 | .input_offset(112) |
| 6534 | .zero_index(mz) |
| 6535 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse); |
| 6536 | } |
| 6537 | } |
| 6538 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6539 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6540 | |
| 6541 | |
| 6542 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6543 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6544 | TEST_REQUIRES_X86_SSE; |
| 6545 | DWConvMicrokernelTester() |
| 6546 | .cr(4) |
| 6547 | .kr(4) |
| 6548 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6549 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6550 | } |
| 6551 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6552 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6553 | TEST_REQUIRES_X86_SSE; |
| 6554 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6555 | DWConvMicrokernelTester() |
| 6556 | .cr(4) |
| 6557 | .kr(4) |
| 6558 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6559 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6560 | } |
| 6561 | } |
| 6562 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6563 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6564 | TEST_REQUIRES_X86_SSE; |
| 6565 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6566 | DWConvMicrokernelTester() |
| 6567 | .cr(4) |
| 6568 | .kr(4) |
| 6569 | .channels(channels) |
| 6570 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6571 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6572 | } |
| 6573 | } |
| 6574 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6575 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6576 | TEST_REQUIRES_X86_SSE; |
| 6577 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6578 | DWConvMicrokernelTester() |
| 6579 | .cr(4) |
| 6580 | .kr(4) |
| 6581 | .channels(channels) |
| 6582 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6583 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6584 | } |
| 6585 | } |
| 6586 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6587 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6588 | TEST_REQUIRES_X86_SSE; |
| 6589 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 6590 | DWConvMicrokernelTester() |
| 6591 | .cr(4) |
| 6592 | .kr(4) |
| 6593 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6594 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6595 | } |
| 6596 | } |
| 6597 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6598 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6599 | TEST_REQUIRES_X86_SSE; |
| 6600 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 6601 | DWConvMicrokernelTester() |
| 6602 | .cr(4) |
| 6603 | .kr(4) |
| 6604 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6605 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6606 | } |
| 6607 | } |
| 6608 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6609 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6610 | TEST_REQUIRES_X86_SSE; |
| 6611 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 6612 | DWConvMicrokernelTester() |
| 6613 | .cr(4) |
| 6614 | .kr(4) |
| 6615 | .channels(channels) |
| 6616 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6617 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6618 | } |
| 6619 | } |
| 6620 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6621 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6622 | TEST_REQUIRES_X86_SSE; |
| 6623 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 6624 | DWConvMicrokernelTester() |
| 6625 | .cr(4) |
| 6626 | .kr(4) |
| 6627 | .channels(channels) |
| 6628 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6629 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6630 | } |
| 6631 | } |
| 6632 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6633 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6634 | TEST_REQUIRES_X86_SSE; |
| 6635 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6636 | DWConvMicrokernelTester() |
| 6637 | .cr(4) |
| 6638 | .kr(4) |
| 6639 | .channels(channels) |
| 6640 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6641 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6642 | } |
| 6643 | } |
| 6644 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6645 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6646 | TEST_REQUIRES_X86_SSE; |
| 6647 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6648 | for (size_t step = 2; step <= 4; step++) { |
| 6649 | DWConvMicrokernelTester() |
| 6650 | .cr(4) |
| 6651 | .kr(4) |
| 6652 | .channels(channels) |
| 6653 | .width(3) |
| 6654 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6655 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6656 | } |
| 6657 | } |
| 6658 | } |
| 6659 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6660 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6661 | TEST_REQUIRES_X86_SSE; |
| 6662 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6663 | DWConvMicrokernelTester() |
| 6664 | .cr(4) |
| 6665 | .kr(4) |
| 6666 | .channels(4) |
| 6667 | .width(5) |
| 6668 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6669 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6670 | } |
| 6671 | } |
| 6672 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6673 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6674 | TEST_REQUIRES_X86_SSE; |
| 6675 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6676 | DWConvMicrokernelTester() |
| 6677 | .cr(4) |
| 6678 | .kr(4) |
| 6679 | .channels(channels) |
| 6680 | .width(3) |
| 6681 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6682 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6683 | } |
| 6684 | } |
| 6685 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6686 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6687 | TEST_REQUIRES_X86_SSE; |
| 6688 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 6689 | DWConvMicrokernelTester() |
| 6690 | .cr(4) |
| 6691 | .kr(4) |
| 6692 | .channels(channels) |
| 6693 | .width(3) |
| 6694 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6695 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6696 | } |
| 6697 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 6698 | |
| 6699 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, input_offset) { |
| 6700 | TEST_REQUIRES_X86_SSE; |
| 6701 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6702 | DWConvMicrokernelTester() |
| 6703 | .cr(4) |
| 6704 | .kr(4) |
| 6705 | .channels(channels) |
| 6706 | .input_offset(112) |
| 6707 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
| 6708 | } |
| 6709 | } |
| 6710 | |
| 6711 | TEST(F32_DWCONV_MINMAX_UP4X4__SSE_ACC2, zero) { |
| 6712 | TEST_REQUIRES_X86_SSE; |
| 6713 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 6714 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 6715 | DWConvMicrokernelTester() |
| 6716 | .cr(4) |
| 6717 | .kr(4) |
| 6718 | .channels(channels) |
| 6719 | .input_offset(112) |
| 6720 | .zero_index(mz) |
| 6721 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__sse_acc2); |
| 6722 | } |
| 6723 | } |
| 6724 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6725 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6726 | |
| 6727 | |
| 6728 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6729 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6730 | TEST_REQUIRES_X86_SSE; |
| 6731 | DWConvMicrokernelTester() |
| 6732 | .cr(8) |
| 6733 | .kr(4) |
| 6734 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6735 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6736 | } |
| 6737 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6738 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6739 | TEST_REQUIRES_X86_SSE; |
| 6740 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6741 | DWConvMicrokernelTester() |
| 6742 | .cr(8) |
| 6743 | .kr(4) |
| 6744 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6745 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6746 | } |
| 6747 | } |
| 6748 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6749 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6750 | TEST_REQUIRES_X86_SSE; |
| 6751 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6752 | DWConvMicrokernelTester() |
| 6753 | .cr(8) |
| 6754 | .kr(4) |
| 6755 | .channels(channels) |
| 6756 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6757 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6758 | } |
| 6759 | } |
| 6760 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6761 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6762 | TEST_REQUIRES_X86_SSE; |
| 6763 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6764 | DWConvMicrokernelTester() |
| 6765 | .cr(8) |
| 6766 | .kr(4) |
| 6767 | .channels(channels) |
| 6768 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6769 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6770 | } |
| 6771 | } |
| 6772 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6773 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6774 | TEST_REQUIRES_X86_SSE; |
| 6775 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 6776 | DWConvMicrokernelTester() |
| 6777 | .cr(8) |
| 6778 | .kr(4) |
| 6779 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6780 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6781 | } |
| 6782 | } |
| 6783 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6784 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6785 | TEST_REQUIRES_X86_SSE; |
| 6786 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6787 | DWConvMicrokernelTester() |
| 6788 | .cr(8) |
| 6789 | .kr(4) |
| 6790 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6791 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6792 | } |
| 6793 | } |
| 6794 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6795 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6796 | TEST_REQUIRES_X86_SSE; |
| 6797 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6798 | DWConvMicrokernelTester() |
| 6799 | .cr(8) |
| 6800 | .kr(4) |
| 6801 | .channels(channels) |
| 6802 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6803 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6804 | } |
| 6805 | } |
| 6806 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6807 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6808 | TEST_REQUIRES_X86_SSE; |
| 6809 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6810 | DWConvMicrokernelTester() |
| 6811 | .cr(8) |
| 6812 | .kr(4) |
| 6813 | .channels(channels) |
| 6814 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6815 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6816 | } |
| 6817 | } |
| 6818 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6819 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6820 | TEST_REQUIRES_X86_SSE; |
| 6821 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6822 | DWConvMicrokernelTester() |
| 6823 | .cr(8) |
| 6824 | .kr(4) |
| 6825 | .channels(channels) |
| 6826 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6827 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6828 | } |
| 6829 | } |
| 6830 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6831 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6832 | TEST_REQUIRES_X86_SSE; |
| 6833 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6834 | for (size_t step = 2; step <= 4; step++) { |
| 6835 | DWConvMicrokernelTester() |
| 6836 | .cr(8) |
| 6837 | .kr(4) |
| 6838 | .channels(channels) |
| 6839 | .width(3) |
| 6840 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6841 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6842 | } |
| 6843 | } |
| 6844 | } |
| 6845 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6846 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6847 | TEST_REQUIRES_X86_SSE; |
| 6848 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6849 | DWConvMicrokernelTester() |
| 6850 | .cr(8) |
| 6851 | .kr(4) |
| 6852 | .channels(8) |
| 6853 | .width(5) |
| 6854 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6855 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6856 | } |
| 6857 | } |
| 6858 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6859 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6860 | TEST_REQUIRES_X86_SSE; |
| 6861 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6862 | DWConvMicrokernelTester() |
| 6863 | .cr(8) |
| 6864 | .kr(4) |
| 6865 | .channels(channels) |
| 6866 | .width(3) |
| 6867 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6868 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6869 | } |
| 6870 | } |
| 6871 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6872 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6873 | TEST_REQUIRES_X86_SSE; |
| 6874 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 6875 | DWConvMicrokernelTester() |
| 6876 | .cr(8) |
| 6877 | .kr(4) |
| 6878 | .channels(channels) |
| 6879 | .width(3) |
| 6880 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6881 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6882 | } |
| 6883 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 6884 | |
| 6885 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, input_offset) { |
| 6886 | TEST_REQUIRES_X86_SSE; |
| 6887 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6888 | DWConvMicrokernelTester() |
| 6889 | .cr(8) |
| 6890 | .kr(4) |
| 6891 | .channels(channels) |
| 6892 | .input_offset(176) |
| 6893 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
| 6894 | } |
| 6895 | } |
| 6896 | |
| 6897 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE, zero) { |
| 6898 | TEST_REQUIRES_X86_SSE; |
| 6899 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 6900 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6901 | DWConvMicrokernelTester() |
| 6902 | .cr(8) |
| 6903 | .kr(4) |
| 6904 | .channels(channels) |
| 6905 | .input_offset(176) |
| 6906 | .zero_index(mz) |
| 6907 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse); |
| 6908 | } |
| 6909 | } |
| 6910 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6911 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 6912 | |
| 6913 | |
| 6914 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6915 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6916 | TEST_REQUIRES_X86_SSE; |
| 6917 | DWConvMicrokernelTester() |
| 6918 | .cr(8) |
| 6919 | .kr(4) |
| 6920 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6921 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6922 | } |
| 6923 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6924 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6925 | TEST_REQUIRES_X86_SSE; |
| 6926 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6927 | DWConvMicrokernelTester() |
| 6928 | .cr(8) |
| 6929 | .kr(4) |
| 6930 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6931 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6932 | } |
| 6933 | } |
| 6934 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6935 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6936 | TEST_REQUIRES_X86_SSE; |
| 6937 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6938 | DWConvMicrokernelTester() |
| 6939 | .cr(8) |
| 6940 | .kr(4) |
| 6941 | .channels(channels) |
| 6942 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6943 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6944 | } |
| 6945 | } |
| 6946 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6947 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6948 | TEST_REQUIRES_X86_SSE; |
| 6949 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 6950 | DWConvMicrokernelTester() |
| 6951 | .cr(8) |
| 6952 | .kr(4) |
| 6953 | .channels(channels) |
| 6954 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6955 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6956 | } |
| 6957 | } |
| 6958 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6959 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6960 | TEST_REQUIRES_X86_SSE; |
| 6961 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 6962 | DWConvMicrokernelTester() |
| 6963 | .cr(8) |
| 6964 | .kr(4) |
| 6965 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6966 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6967 | } |
| 6968 | } |
| 6969 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6970 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6971 | TEST_REQUIRES_X86_SSE; |
| 6972 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6973 | DWConvMicrokernelTester() |
| 6974 | .cr(8) |
| 6975 | .kr(4) |
| 6976 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6977 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6978 | } |
| 6979 | } |
| 6980 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6981 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6982 | TEST_REQUIRES_X86_SSE; |
| 6983 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6984 | DWConvMicrokernelTester() |
| 6985 | .cr(8) |
| 6986 | .kr(4) |
| 6987 | .channels(channels) |
| 6988 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6989 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6990 | } |
| 6991 | } |
| 6992 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 6993 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 6994 | TEST_REQUIRES_X86_SSE; |
| 6995 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 6996 | DWConvMicrokernelTester() |
| 6997 | .cr(8) |
| 6998 | .kr(4) |
| 6999 | .channels(channels) |
| 7000 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7001 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7002 | } |
| 7003 | } |
| 7004 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7005 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7006 | TEST_REQUIRES_X86_SSE; |
| 7007 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7008 | DWConvMicrokernelTester() |
| 7009 | .cr(8) |
| 7010 | .kr(4) |
| 7011 | .channels(channels) |
| 7012 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7013 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7014 | } |
| 7015 | } |
| 7016 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7017 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7018 | TEST_REQUIRES_X86_SSE; |
| 7019 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7020 | for (size_t step = 2; step <= 4; step++) { |
| 7021 | DWConvMicrokernelTester() |
| 7022 | .cr(8) |
| 7023 | .kr(4) |
| 7024 | .channels(channels) |
| 7025 | .width(3) |
| 7026 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7027 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7028 | } |
| 7029 | } |
| 7030 | } |
| 7031 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7032 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7033 | TEST_REQUIRES_X86_SSE; |
| 7034 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7035 | DWConvMicrokernelTester() |
| 7036 | .cr(8) |
| 7037 | .kr(4) |
| 7038 | .channels(8) |
| 7039 | .width(5) |
| 7040 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7041 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7042 | } |
| 7043 | } |
| 7044 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7045 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7046 | TEST_REQUIRES_X86_SSE; |
| 7047 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7048 | DWConvMicrokernelTester() |
| 7049 | .cr(8) |
| 7050 | .kr(4) |
| 7051 | .channels(channels) |
| 7052 | .width(3) |
| 7053 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7054 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7055 | } |
| 7056 | } |
| 7057 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7058 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7059 | TEST_REQUIRES_X86_SSE; |
| 7060 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7061 | DWConvMicrokernelTester() |
| 7062 | .cr(8) |
| 7063 | .kr(4) |
| 7064 | .channels(channels) |
| 7065 | .width(3) |
| 7066 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7067 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7068 | } |
| 7069 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 7070 | |
| 7071 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, input_offset) { |
| 7072 | TEST_REQUIRES_X86_SSE; |
| 7073 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7074 | DWConvMicrokernelTester() |
| 7075 | .cr(8) |
| 7076 | .kr(4) |
| 7077 | .channels(channels) |
| 7078 | .input_offset(176) |
| 7079 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
| 7080 | } |
| 7081 | } |
| 7082 | |
| 7083 | TEST(F32_DWCONV_MINMAX_UP8X4__SSE_ACC2, zero) { |
| 7084 | TEST_REQUIRES_X86_SSE; |
| 7085 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 7086 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7087 | DWConvMicrokernelTester() |
| 7088 | .cr(8) |
| 7089 | .kr(4) |
| 7090 | .channels(channels) |
| 7091 | .input_offset(176) |
| 7092 | .zero_index(mz) |
| 7093 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__sse_acc2); |
| 7094 | } |
| 7095 | } |
| 7096 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7097 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 7098 | |
| 7099 | |
| 7100 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7101 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7102 | TEST_REQUIRES_X86_AVX; |
| 7103 | DWConvMicrokernelTester() |
| 7104 | .cr(8) |
| 7105 | .kr(25) |
| 7106 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7107 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7108 | } |
| 7109 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7110 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7111 | TEST_REQUIRES_X86_AVX; |
| 7112 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7113 | DWConvMicrokernelTester() |
| 7114 | .cr(8) |
| 7115 | .kr(25) |
| 7116 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7117 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7118 | } |
| 7119 | } |
| 7120 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7121 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7122 | TEST_REQUIRES_X86_AVX; |
| 7123 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7124 | DWConvMicrokernelTester() |
| 7125 | .cr(8) |
| 7126 | .kr(25) |
| 7127 | .channels(channels) |
| 7128 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7129 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7130 | } |
| 7131 | } |
| 7132 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7133 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7134 | TEST_REQUIRES_X86_AVX; |
| 7135 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7136 | DWConvMicrokernelTester() |
| 7137 | .cr(8) |
| 7138 | .kr(25) |
| 7139 | .channels(channels) |
| 7140 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7141 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7142 | } |
| 7143 | } |
| 7144 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7145 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7146 | TEST_REQUIRES_X86_AVX; |
| 7147 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 7148 | DWConvMicrokernelTester() |
| 7149 | .cr(8) |
| 7150 | .kr(25) |
| 7151 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7152 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7153 | } |
| 7154 | } |
| 7155 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7156 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7157 | TEST_REQUIRES_X86_AVX; |
| 7158 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7159 | DWConvMicrokernelTester() |
| 7160 | .cr(8) |
| 7161 | .kr(25) |
| 7162 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7163 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7164 | } |
| 7165 | } |
| 7166 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7167 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7168 | TEST_REQUIRES_X86_AVX; |
| 7169 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7170 | DWConvMicrokernelTester() |
| 7171 | .cr(8) |
| 7172 | .kr(25) |
| 7173 | .channels(channels) |
| 7174 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7175 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7176 | } |
| 7177 | } |
| 7178 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7179 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7180 | TEST_REQUIRES_X86_AVX; |
| 7181 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7182 | DWConvMicrokernelTester() |
| 7183 | .cr(8) |
| 7184 | .kr(25) |
| 7185 | .channels(channels) |
| 7186 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7187 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7188 | } |
| 7189 | } |
| 7190 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7191 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7192 | TEST_REQUIRES_X86_AVX; |
| 7193 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7194 | DWConvMicrokernelTester() |
| 7195 | .cr(8) |
| 7196 | .kr(25) |
| 7197 | .channels(channels) |
| 7198 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7199 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7200 | } |
| 7201 | } |
| 7202 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7203 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7204 | TEST_REQUIRES_X86_AVX; |
| 7205 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7206 | for (size_t step = 2; step <= 25; step++) { |
| 7207 | DWConvMicrokernelTester() |
| 7208 | .cr(8) |
| 7209 | .kr(25) |
| 7210 | .channels(channels) |
| 7211 | .width(3) |
| 7212 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7213 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7214 | } |
| 7215 | } |
| 7216 | } |
| 7217 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7218 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7219 | TEST_REQUIRES_X86_AVX; |
| 7220 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7221 | DWConvMicrokernelTester() |
| 7222 | .cr(8) |
| 7223 | .kr(25) |
| 7224 | .channels(8) |
| 7225 | .width(5) |
| 7226 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7227 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7228 | } |
| 7229 | } |
| 7230 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7231 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7232 | TEST_REQUIRES_X86_AVX; |
| 7233 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7234 | DWConvMicrokernelTester() |
| 7235 | .cr(8) |
| 7236 | .kr(25) |
| 7237 | .channels(channels) |
| 7238 | .width(3) |
| 7239 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7240 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7241 | } |
| 7242 | } |
| 7243 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7244 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7245 | TEST_REQUIRES_X86_AVX; |
| 7246 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7247 | DWConvMicrokernelTester() |
| 7248 | .cr(8) |
| 7249 | .kr(25) |
| 7250 | .channels(channels) |
| 7251 | .width(3) |
| 7252 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7253 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7254 | } |
| 7255 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 7256 | |
| 7257 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, input_offset) { |
| 7258 | TEST_REQUIRES_X86_AVX; |
| 7259 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7260 | DWConvMicrokernelTester() |
| 7261 | .cr(8) |
| 7262 | .kr(25) |
| 7263 | .channels(channels) |
| 7264 | .input_offset(176) |
| 7265 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
| 7266 | } |
| 7267 | } |
| 7268 | |
| 7269 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX, zero) { |
| 7270 | TEST_REQUIRES_X86_AVX; |
| 7271 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 7272 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7273 | DWConvMicrokernelTester() |
| 7274 | .cr(8) |
| 7275 | .kr(25) |
| 7276 | .channels(channels) |
| 7277 | .input_offset(176) |
| 7278 | .zero_index(mz) |
| 7279 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx); |
| 7280 | } |
| 7281 | } |
| 7282 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7283 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 7284 | |
| 7285 | |
| 7286 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7287 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7288 | TEST_REQUIRES_X86_AVX; |
| 7289 | DWConvMicrokernelTester() |
| 7290 | .cr(8) |
| 7291 | .kr(25) |
| 7292 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7293 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7294 | } |
| 7295 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7296 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7297 | TEST_REQUIRES_X86_AVX; |
| 7298 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7299 | DWConvMicrokernelTester() |
| 7300 | .cr(8) |
| 7301 | .kr(25) |
| 7302 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7303 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7304 | } |
| 7305 | } |
| 7306 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7307 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7308 | TEST_REQUIRES_X86_AVX; |
| 7309 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7310 | DWConvMicrokernelTester() |
| 7311 | .cr(8) |
| 7312 | .kr(25) |
| 7313 | .channels(channels) |
| 7314 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7315 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7316 | } |
| 7317 | } |
| 7318 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7319 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7320 | TEST_REQUIRES_X86_AVX; |
| 7321 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7322 | DWConvMicrokernelTester() |
| 7323 | .cr(8) |
| 7324 | .kr(25) |
| 7325 | .channels(channels) |
| 7326 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7327 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7328 | } |
| 7329 | } |
| 7330 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7331 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7332 | TEST_REQUIRES_X86_AVX; |
| 7333 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 7334 | DWConvMicrokernelTester() |
| 7335 | .cr(8) |
| 7336 | .kr(25) |
| 7337 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7338 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7339 | } |
| 7340 | } |
| 7341 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7342 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7343 | TEST_REQUIRES_X86_AVX; |
| 7344 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7345 | DWConvMicrokernelTester() |
| 7346 | .cr(8) |
| 7347 | .kr(25) |
| 7348 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7349 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7350 | } |
| 7351 | } |
| 7352 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7353 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7354 | TEST_REQUIRES_X86_AVX; |
| 7355 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7356 | DWConvMicrokernelTester() |
| 7357 | .cr(8) |
| 7358 | .kr(25) |
| 7359 | .channels(channels) |
| 7360 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7361 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7362 | } |
| 7363 | } |
| 7364 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7365 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7366 | TEST_REQUIRES_X86_AVX; |
| 7367 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7368 | DWConvMicrokernelTester() |
| 7369 | .cr(8) |
| 7370 | .kr(25) |
| 7371 | .channels(channels) |
| 7372 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7373 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7374 | } |
| 7375 | } |
| 7376 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7377 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7378 | TEST_REQUIRES_X86_AVX; |
| 7379 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7380 | DWConvMicrokernelTester() |
| 7381 | .cr(8) |
| 7382 | .kr(25) |
| 7383 | .channels(channels) |
| 7384 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7385 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7386 | } |
| 7387 | } |
| 7388 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7389 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7390 | TEST_REQUIRES_X86_AVX; |
| 7391 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7392 | for (size_t step = 2; step <= 25; step++) { |
| 7393 | DWConvMicrokernelTester() |
| 7394 | .cr(8) |
| 7395 | .kr(25) |
| 7396 | .channels(channels) |
| 7397 | .width(3) |
| 7398 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7399 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7400 | } |
| 7401 | } |
| 7402 | } |
| 7403 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7404 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7405 | TEST_REQUIRES_X86_AVX; |
| 7406 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7407 | DWConvMicrokernelTester() |
| 7408 | .cr(8) |
| 7409 | .kr(25) |
| 7410 | .channels(8) |
| 7411 | .width(5) |
| 7412 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7413 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7414 | } |
| 7415 | } |
| 7416 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7417 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7418 | TEST_REQUIRES_X86_AVX; |
| 7419 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7420 | DWConvMicrokernelTester() |
| 7421 | .cr(8) |
| 7422 | .kr(25) |
| 7423 | .channels(channels) |
| 7424 | .width(3) |
| 7425 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7426 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7427 | } |
| 7428 | } |
| 7429 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7430 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7431 | TEST_REQUIRES_X86_AVX; |
| 7432 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7433 | DWConvMicrokernelTester() |
| 7434 | .cr(8) |
| 7435 | .kr(25) |
| 7436 | .channels(channels) |
| 7437 | .width(3) |
| 7438 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7439 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7440 | } |
| 7441 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 7442 | |
| 7443 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, input_offset) { |
| 7444 | TEST_REQUIRES_X86_AVX; |
| 7445 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7446 | DWConvMicrokernelTester() |
| 7447 | .cr(8) |
| 7448 | .kr(25) |
| 7449 | .channels(channels) |
| 7450 | .input_offset(176) |
| 7451 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
| 7452 | } |
| 7453 | } |
| 7454 | |
| 7455 | TEST(F32_DWCONV_MINMAX_UP8X25__AVX_ACC2, zero) { |
| 7456 | TEST_REQUIRES_X86_AVX; |
| 7457 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 7458 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7459 | DWConvMicrokernelTester() |
| 7460 | .cr(8) |
| 7461 | .kr(25) |
| 7462 | .channels(channels) |
| 7463 | .input_offset(176) |
| 7464 | .zero_index(mz) |
| 7465 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__avx_acc2); |
| 7466 | } |
| 7467 | } |
| 7468 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7469 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 7470 | |
| 7471 | |
| 7472 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7473 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7474 | TEST_REQUIRES_X86_AVX; |
| 7475 | DWConvMicrokernelTester() |
| 7476 | .cr(16) |
| 7477 | .kr(25) |
| 7478 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7479 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7480 | } |
| 7481 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7482 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7483 | TEST_REQUIRES_X86_AVX; |
| 7484 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7485 | DWConvMicrokernelTester() |
| 7486 | .cr(16) |
| 7487 | .kr(25) |
| 7488 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7489 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7490 | } |
| 7491 | } |
| 7492 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7493 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7494 | TEST_REQUIRES_X86_AVX; |
| 7495 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7496 | DWConvMicrokernelTester() |
| 7497 | .cr(16) |
| 7498 | .kr(25) |
| 7499 | .channels(channels) |
| 7500 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7501 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7502 | } |
| 7503 | } |
| 7504 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7505 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7506 | TEST_REQUIRES_X86_AVX; |
| 7507 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7508 | DWConvMicrokernelTester() |
| 7509 | .cr(16) |
| 7510 | .kr(25) |
| 7511 | .channels(channels) |
| 7512 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7513 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7514 | } |
| 7515 | } |
| 7516 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7517 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7518 | TEST_REQUIRES_X86_AVX; |
| 7519 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 7520 | DWConvMicrokernelTester() |
| 7521 | .cr(16) |
| 7522 | .kr(25) |
| 7523 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7524 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7525 | } |
| 7526 | } |
| 7527 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7528 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7529 | TEST_REQUIRES_X86_AVX; |
| 7530 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 7531 | DWConvMicrokernelTester() |
| 7532 | .cr(16) |
| 7533 | .kr(25) |
| 7534 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7535 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7536 | } |
| 7537 | } |
| 7538 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7539 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7540 | TEST_REQUIRES_X86_AVX; |
| 7541 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 7542 | DWConvMicrokernelTester() |
| 7543 | .cr(16) |
| 7544 | .kr(25) |
| 7545 | .channels(channels) |
| 7546 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7547 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7548 | } |
| 7549 | } |
| 7550 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7551 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7552 | TEST_REQUIRES_X86_AVX; |
| 7553 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 7554 | DWConvMicrokernelTester() |
| 7555 | .cr(16) |
| 7556 | .kr(25) |
| 7557 | .channels(channels) |
| 7558 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7559 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7560 | } |
| 7561 | } |
| 7562 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7563 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7564 | TEST_REQUIRES_X86_AVX; |
| 7565 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7566 | DWConvMicrokernelTester() |
| 7567 | .cr(16) |
| 7568 | .kr(25) |
| 7569 | .channels(channels) |
| 7570 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7571 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7572 | } |
| 7573 | } |
| 7574 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7575 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7576 | TEST_REQUIRES_X86_AVX; |
| 7577 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7578 | for (size_t step = 2; step <= 25; step++) { |
| 7579 | DWConvMicrokernelTester() |
| 7580 | .cr(16) |
| 7581 | .kr(25) |
| 7582 | .channels(channels) |
| 7583 | .width(3) |
| 7584 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7585 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7586 | } |
| 7587 | } |
| 7588 | } |
| 7589 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7590 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7591 | TEST_REQUIRES_X86_AVX; |
| 7592 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7593 | DWConvMicrokernelTester() |
| 7594 | .cr(16) |
| 7595 | .kr(25) |
| 7596 | .channels(16) |
| 7597 | .width(5) |
| 7598 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7599 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7600 | } |
| 7601 | } |
| 7602 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7603 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7604 | TEST_REQUIRES_X86_AVX; |
| 7605 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7606 | DWConvMicrokernelTester() |
| 7607 | .cr(16) |
| 7608 | .kr(25) |
| 7609 | .channels(channels) |
| 7610 | .width(3) |
| 7611 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7612 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7613 | } |
| 7614 | } |
| 7615 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7616 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7617 | TEST_REQUIRES_X86_AVX; |
| 7618 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7619 | DWConvMicrokernelTester() |
| 7620 | .cr(16) |
| 7621 | .kr(25) |
| 7622 | .channels(channels) |
| 7623 | .width(3) |
| 7624 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7625 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7626 | } |
| 7627 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 7628 | |
| 7629 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, input_offset) { |
| 7630 | TEST_REQUIRES_X86_AVX; |
| 7631 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7632 | DWConvMicrokernelTester() |
| 7633 | .cr(16) |
| 7634 | .kr(25) |
| 7635 | .channels(channels) |
| 7636 | .input_offset(304) |
| 7637 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
| 7638 | } |
| 7639 | } |
| 7640 | |
| 7641 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX, zero) { |
| 7642 | TEST_REQUIRES_X86_AVX; |
| 7643 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 7644 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7645 | DWConvMicrokernelTester() |
| 7646 | .cr(16) |
| 7647 | .kr(25) |
| 7648 | .channels(channels) |
| 7649 | .input_offset(304) |
| 7650 | .zero_index(mz) |
| 7651 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx); |
| 7652 | } |
| 7653 | } |
| 7654 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7655 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 7656 | |
| 7657 | |
| 7658 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7659 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7660 | TEST_REQUIRES_X86_AVX; |
| 7661 | DWConvMicrokernelTester() |
| 7662 | .cr(16) |
| 7663 | .kr(25) |
| 7664 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7665 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7666 | } |
| 7667 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7668 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7669 | TEST_REQUIRES_X86_AVX; |
| 7670 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7671 | DWConvMicrokernelTester() |
| 7672 | .cr(16) |
| 7673 | .kr(25) |
| 7674 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7675 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7676 | } |
| 7677 | } |
| 7678 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7679 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7680 | TEST_REQUIRES_X86_AVX; |
| 7681 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7682 | DWConvMicrokernelTester() |
| 7683 | .cr(16) |
| 7684 | .kr(25) |
| 7685 | .channels(channels) |
| 7686 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7687 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7688 | } |
| 7689 | } |
| 7690 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7691 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7692 | TEST_REQUIRES_X86_AVX; |
| 7693 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7694 | DWConvMicrokernelTester() |
| 7695 | .cr(16) |
| 7696 | .kr(25) |
| 7697 | .channels(channels) |
| 7698 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7699 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7700 | } |
| 7701 | } |
| 7702 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7703 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7704 | TEST_REQUIRES_X86_AVX; |
| 7705 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 7706 | DWConvMicrokernelTester() |
| 7707 | .cr(16) |
| 7708 | .kr(25) |
| 7709 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7710 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7711 | } |
| 7712 | } |
| 7713 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7714 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7715 | TEST_REQUIRES_X86_AVX; |
| 7716 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 7717 | DWConvMicrokernelTester() |
| 7718 | .cr(16) |
| 7719 | .kr(25) |
| 7720 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7721 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7722 | } |
| 7723 | } |
| 7724 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7725 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7726 | TEST_REQUIRES_X86_AVX; |
| 7727 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 7728 | DWConvMicrokernelTester() |
| 7729 | .cr(16) |
| 7730 | .kr(25) |
| 7731 | .channels(channels) |
| 7732 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7733 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7734 | } |
| 7735 | } |
| 7736 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7737 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7738 | TEST_REQUIRES_X86_AVX; |
| 7739 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 7740 | DWConvMicrokernelTester() |
| 7741 | .cr(16) |
| 7742 | .kr(25) |
| 7743 | .channels(channels) |
| 7744 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7745 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7746 | } |
| 7747 | } |
| 7748 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7749 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7750 | TEST_REQUIRES_X86_AVX; |
| 7751 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7752 | DWConvMicrokernelTester() |
| 7753 | .cr(16) |
| 7754 | .kr(25) |
| 7755 | .channels(channels) |
| 7756 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7757 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7758 | } |
| 7759 | } |
| 7760 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7761 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7762 | TEST_REQUIRES_X86_AVX; |
| 7763 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7764 | for (size_t step = 2; step <= 25; step++) { |
| 7765 | DWConvMicrokernelTester() |
| 7766 | .cr(16) |
| 7767 | .kr(25) |
| 7768 | .channels(channels) |
| 7769 | .width(3) |
| 7770 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7771 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7772 | } |
| 7773 | } |
| 7774 | } |
| 7775 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7776 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7777 | TEST_REQUIRES_X86_AVX; |
| 7778 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7779 | DWConvMicrokernelTester() |
| 7780 | .cr(16) |
| 7781 | .kr(25) |
| 7782 | .channels(16) |
| 7783 | .width(5) |
| 7784 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7785 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7786 | } |
| 7787 | } |
| 7788 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7789 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7790 | TEST_REQUIRES_X86_AVX; |
| 7791 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7792 | DWConvMicrokernelTester() |
| 7793 | .cr(16) |
| 7794 | .kr(25) |
| 7795 | .channels(channels) |
| 7796 | .width(3) |
| 7797 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7798 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7799 | } |
| 7800 | } |
| 7801 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7802 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7803 | TEST_REQUIRES_X86_AVX; |
| 7804 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 7805 | DWConvMicrokernelTester() |
| 7806 | .cr(16) |
| 7807 | .kr(25) |
| 7808 | .channels(channels) |
| 7809 | .width(3) |
| 7810 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7811 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7812 | } |
| 7813 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 7814 | |
| 7815 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, input_offset) { |
| 7816 | TEST_REQUIRES_X86_AVX; |
| 7817 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7818 | DWConvMicrokernelTester() |
| 7819 | .cr(16) |
| 7820 | .kr(25) |
| 7821 | .channels(channels) |
| 7822 | .input_offset(304) |
| 7823 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
| 7824 | } |
| 7825 | } |
| 7826 | |
| 7827 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX_ACC2, zero) { |
| 7828 | TEST_REQUIRES_X86_AVX; |
| 7829 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 7830 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 7831 | DWConvMicrokernelTester() |
| 7832 | .cr(16) |
| 7833 | .kr(25) |
| 7834 | .channels(channels) |
| 7835 | .input_offset(304) |
| 7836 | .zero_index(mz) |
| 7837 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx_acc2); |
| 7838 | } |
| 7839 | } |
| 7840 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7841 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 7842 | |
| 7843 | |
| 7844 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7845 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7846 | TEST_REQUIRES_X86_AVX; |
| 7847 | DWConvMicrokernelTester() |
| 7848 | .cr(8) |
| 7849 | .kr(9) |
| 7850 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7851 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7852 | } |
| 7853 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7854 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7855 | TEST_REQUIRES_X86_AVX; |
| 7856 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7857 | DWConvMicrokernelTester() |
| 7858 | .cr(8) |
| 7859 | .kr(9) |
| 7860 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7861 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7862 | } |
| 7863 | } |
| 7864 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7865 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7866 | TEST_REQUIRES_X86_AVX; |
| 7867 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7868 | DWConvMicrokernelTester() |
| 7869 | .cr(8) |
| 7870 | .kr(9) |
| 7871 | .channels(channels) |
| 7872 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7873 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7874 | } |
| 7875 | } |
| 7876 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7877 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7878 | TEST_REQUIRES_X86_AVX; |
| 7879 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 7880 | DWConvMicrokernelTester() |
| 7881 | .cr(8) |
| 7882 | .kr(9) |
| 7883 | .channels(channels) |
| 7884 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7885 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7886 | } |
| 7887 | } |
| 7888 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7889 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7890 | TEST_REQUIRES_X86_AVX; |
| 7891 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 7892 | DWConvMicrokernelTester() |
| 7893 | .cr(8) |
| 7894 | .kr(9) |
| 7895 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7896 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7897 | } |
| 7898 | } |
| 7899 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7900 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7901 | TEST_REQUIRES_X86_AVX; |
| 7902 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7903 | DWConvMicrokernelTester() |
| 7904 | .cr(8) |
| 7905 | .kr(9) |
| 7906 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7907 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7908 | } |
| 7909 | } |
| 7910 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7911 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7912 | TEST_REQUIRES_X86_AVX; |
| 7913 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7914 | DWConvMicrokernelTester() |
| 7915 | .cr(8) |
| 7916 | .kr(9) |
| 7917 | .channels(channels) |
| 7918 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7919 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7920 | } |
| 7921 | } |
| 7922 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7923 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7924 | TEST_REQUIRES_X86_AVX; |
| 7925 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 7926 | DWConvMicrokernelTester() |
| 7927 | .cr(8) |
| 7928 | .kr(9) |
| 7929 | .channels(channels) |
| 7930 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7931 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7932 | } |
| 7933 | } |
| 7934 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7935 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7936 | TEST_REQUIRES_X86_AVX; |
| 7937 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7938 | DWConvMicrokernelTester() |
| 7939 | .cr(8) |
| 7940 | .kr(9) |
| 7941 | .channels(channels) |
| 7942 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7943 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7944 | } |
| 7945 | } |
| 7946 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7947 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7948 | TEST_REQUIRES_X86_AVX; |
| 7949 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7950 | for (size_t step = 2; step <= 9; step++) { |
| 7951 | DWConvMicrokernelTester() |
| 7952 | .cr(8) |
| 7953 | .kr(9) |
| 7954 | .channels(channels) |
| 7955 | .width(3) |
| 7956 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7957 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7958 | } |
| 7959 | } |
| 7960 | } |
| 7961 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7962 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7963 | TEST_REQUIRES_X86_AVX; |
| 7964 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7965 | DWConvMicrokernelTester() |
| 7966 | .cr(8) |
| 7967 | .kr(9) |
| 7968 | .channels(8) |
| 7969 | .width(5) |
| 7970 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7971 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7972 | } |
| 7973 | } |
| 7974 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7975 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7976 | TEST_REQUIRES_X86_AVX; |
| 7977 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7978 | DWConvMicrokernelTester() |
| 7979 | .cr(8) |
| 7980 | .kr(9) |
| 7981 | .channels(channels) |
| 7982 | .width(3) |
| 7983 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7984 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7985 | } |
| 7986 | } |
| 7987 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7988 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7989 | TEST_REQUIRES_X86_AVX; |
| 7990 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 7991 | DWConvMicrokernelTester() |
| 7992 | .cr(8) |
| 7993 | .kr(9) |
| 7994 | .channels(channels) |
| 7995 | .width(3) |
| 7996 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 7997 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 7998 | } |
| 7999 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 8000 | |
| 8001 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, input_offset) { |
| 8002 | TEST_REQUIRES_X86_AVX; |
| 8003 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8004 | DWConvMicrokernelTester() |
| 8005 | .cr(8) |
| 8006 | .kr(9) |
| 8007 | .channels(channels) |
| 8008 | .input_offset(176) |
| 8009 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
| 8010 | } |
| 8011 | } |
| 8012 | |
| 8013 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX, zero) { |
| 8014 | TEST_REQUIRES_X86_AVX; |
| 8015 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 8016 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8017 | DWConvMicrokernelTester() |
| 8018 | .cr(8) |
| 8019 | .kr(9) |
| 8020 | .channels(channels) |
| 8021 | .input_offset(176) |
| 8022 | .zero_index(mz) |
| 8023 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx); |
| 8024 | } |
| 8025 | } |
| 8026 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8027 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 8028 | |
| 8029 | |
| 8030 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8031 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8032 | TEST_REQUIRES_X86_AVX; |
| 8033 | DWConvMicrokernelTester() |
| 8034 | .cr(8) |
| 8035 | .kr(9) |
| 8036 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8037 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8038 | } |
| 8039 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8040 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8041 | TEST_REQUIRES_X86_AVX; |
| 8042 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8043 | DWConvMicrokernelTester() |
| 8044 | .cr(8) |
| 8045 | .kr(9) |
| 8046 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8047 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8048 | } |
| 8049 | } |
| 8050 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8051 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8052 | TEST_REQUIRES_X86_AVX; |
| 8053 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8054 | DWConvMicrokernelTester() |
| 8055 | .cr(8) |
| 8056 | .kr(9) |
| 8057 | .channels(channels) |
| 8058 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8059 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8060 | } |
| 8061 | } |
| 8062 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8063 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8064 | TEST_REQUIRES_X86_AVX; |
| 8065 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8066 | DWConvMicrokernelTester() |
| 8067 | .cr(8) |
| 8068 | .kr(9) |
| 8069 | .channels(channels) |
| 8070 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8071 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8072 | } |
| 8073 | } |
| 8074 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8075 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8076 | TEST_REQUIRES_X86_AVX; |
| 8077 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 8078 | DWConvMicrokernelTester() |
| 8079 | .cr(8) |
| 8080 | .kr(9) |
| 8081 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8082 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8083 | } |
| 8084 | } |
| 8085 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8086 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8087 | TEST_REQUIRES_X86_AVX; |
| 8088 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8089 | DWConvMicrokernelTester() |
| 8090 | .cr(8) |
| 8091 | .kr(9) |
| 8092 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8093 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8094 | } |
| 8095 | } |
| 8096 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8097 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8098 | TEST_REQUIRES_X86_AVX; |
| 8099 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8100 | DWConvMicrokernelTester() |
| 8101 | .cr(8) |
| 8102 | .kr(9) |
| 8103 | .channels(channels) |
| 8104 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8105 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8106 | } |
| 8107 | } |
| 8108 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8109 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8110 | TEST_REQUIRES_X86_AVX; |
| 8111 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8112 | DWConvMicrokernelTester() |
| 8113 | .cr(8) |
| 8114 | .kr(9) |
| 8115 | .channels(channels) |
| 8116 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8117 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8118 | } |
| 8119 | } |
| 8120 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8121 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8122 | TEST_REQUIRES_X86_AVX; |
| 8123 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8124 | DWConvMicrokernelTester() |
| 8125 | .cr(8) |
| 8126 | .kr(9) |
| 8127 | .channels(channels) |
| 8128 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8129 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8130 | } |
| 8131 | } |
| 8132 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8133 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8134 | TEST_REQUIRES_X86_AVX; |
| 8135 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8136 | for (size_t step = 2; step <= 9; step++) { |
| 8137 | DWConvMicrokernelTester() |
| 8138 | .cr(8) |
| 8139 | .kr(9) |
| 8140 | .channels(channels) |
| 8141 | .width(3) |
| 8142 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8143 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8144 | } |
| 8145 | } |
| 8146 | } |
| 8147 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8148 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8149 | TEST_REQUIRES_X86_AVX; |
| 8150 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8151 | DWConvMicrokernelTester() |
| 8152 | .cr(8) |
| 8153 | .kr(9) |
| 8154 | .channels(8) |
| 8155 | .width(5) |
| 8156 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8157 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8158 | } |
| 8159 | } |
| 8160 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8161 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8162 | TEST_REQUIRES_X86_AVX; |
| 8163 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8164 | DWConvMicrokernelTester() |
| 8165 | .cr(8) |
| 8166 | .kr(9) |
| 8167 | .channels(channels) |
| 8168 | .width(3) |
| 8169 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8170 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8171 | } |
| 8172 | } |
| 8173 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8174 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8175 | TEST_REQUIRES_X86_AVX; |
| 8176 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8177 | DWConvMicrokernelTester() |
| 8178 | .cr(8) |
| 8179 | .kr(9) |
| 8180 | .channels(channels) |
| 8181 | .width(3) |
| 8182 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8183 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8184 | } |
| 8185 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 8186 | |
| 8187 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, input_offset) { |
| 8188 | TEST_REQUIRES_X86_AVX; |
| 8189 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8190 | DWConvMicrokernelTester() |
| 8191 | .cr(8) |
| 8192 | .kr(9) |
| 8193 | .channels(channels) |
| 8194 | .input_offset(176) |
| 8195 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
| 8196 | } |
| 8197 | } |
| 8198 | |
| 8199 | TEST(F32_DWCONV_MINMAX_UP8X9__AVX_ACC2, zero) { |
| 8200 | TEST_REQUIRES_X86_AVX; |
| 8201 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 8202 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8203 | DWConvMicrokernelTester() |
| 8204 | .cr(8) |
| 8205 | .kr(9) |
| 8206 | .channels(channels) |
| 8207 | .input_offset(176) |
| 8208 | .zero_index(mz) |
| 8209 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__avx_acc2); |
| 8210 | } |
| 8211 | } |
| 8212 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8213 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 8214 | |
| 8215 | |
| 8216 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8217 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8218 | TEST_REQUIRES_X86_AVX; |
| 8219 | DWConvMicrokernelTester() |
| 8220 | .cr(16) |
| 8221 | .kr(9) |
| 8222 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8223 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8224 | } |
| 8225 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8226 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8227 | TEST_REQUIRES_X86_AVX; |
| 8228 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8229 | DWConvMicrokernelTester() |
| 8230 | .cr(16) |
| 8231 | .kr(9) |
| 8232 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8233 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8234 | } |
| 8235 | } |
| 8236 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8237 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8238 | TEST_REQUIRES_X86_AVX; |
| 8239 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8240 | DWConvMicrokernelTester() |
| 8241 | .cr(16) |
| 8242 | .kr(9) |
| 8243 | .channels(channels) |
| 8244 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8245 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8246 | } |
| 8247 | } |
| 8248 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8249 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8250 | TEST_REQUIRES_X86_AVX; |
| 8251 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8252 | DWConvMicrokernelTester() |
| 8253 | .cr(16) |
| 8254 | .kr(9) |
| 8255 | .channels(channels) |
| 8256 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8257 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8258 | } |
| 8259 | } |
| 8260 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8261 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8262 | TEST_REQUIRES_X86_AVX; |
| 8263 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 8264 | DWConvMicrokernelTester() |
| 8265 | .cr(16) |
| 8266 | .kr(9) |
| 8267 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8268 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8269 | } |
| 8270 | } |
| 8271 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8272 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8273 | TEST_REQUIRES_X86_AVX; |
| 8274 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 8275 | DWConvMicrokernelTester() |
| 8276 | .cr(16) |
| 8277 | .kr(9) |
| 8278 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8279 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8280 | } |
| 8281 | } |
| 8282 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8283 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8284 | TEST_REQUIRES_X86_AVX; |
| 8285 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 8286 | DWConvMicrokernelTester() |
| 8287 | .cr(16) |
| 8288 | .kr(9) |
| 8289 | .channels(channels) |
| 8290 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8291 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8292 | } |
| 8293 | } |
| 8294 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8295 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8296 | TEST_REQUIRES_X86_AVX; |
| 8297 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 8298 | DWConvMicrokernelTester() |
| 8299 | .cr(16) |
| 8300 | .kr(9) |
| 8301 | .channels(channels) |
| 8302 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8303 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8304 | } |
| 8305 | } |
| 8306 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8307 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8308 | TEST_REQUIRES_X86_AVX; |
| 8309 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8310 | DWConvMicrokernelTester() |
| 8311 | .cr(16) |
| 8312 | .kr(9) |
| 8313 | .channels(channels) |
| 8314 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8315 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8316 | } |
| 8317 | } |
| 8318 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8319 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8320 | TEST_REQUIRES_X86_AVX; |
| 8321 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8322 | for (size_t step = 2; step <= 9; step++) { |
| 8323 | DWConvMicrokernelTester() |
| 8324 | .cr(16) |
| 8325 | .kr(9) |
| 8326 | .channels(channels) |
| 8327 | .width(3) |
| 8328 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8329 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8330 | } |
| 8331 | } |
| 8332 | } |
| 8333 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8334 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8335 | TEST_REQUIRES_X86_AVX; |
| 8336 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8337 | DWConvMicrokernelTester() |
| 8338 | .cr(16) |
| 8339 | .kr(9) |
| 8340 | .channels(16) |
| 8341 | .width(5) |
| 8342 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8343 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8344 | } |
| 8345 | } |
| 8346 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8347 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8348 | TEST_REQUIRES_X86_AVX; |
| 8349 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8350 | DWConvMicrokernelTester() |
| 8351 | .cr(16) |
| 8352 | .kr(9) |
| 8353 | .channels(channels) |
| 8354 | .width(3) |
| 8355 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8356 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8357 | } |
| 8358 | } |
| 8359 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8360 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8361 | TEST_REQUIRES_X86_AVX; |
| 8362 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8363 | DWConvMicrokernelTester() |
| 8364 | .cr(16) |
| 8365 | .kr(9) |
| 8366 | .channels(channels) |
| 8367 | .width(3) |
| 8368 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8369 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8370 | } |
| 8371 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 8372 | |
| 8373 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, input_offset) { |
| 8374 | TEST_REQUIRES_X86_AVX; |
| 8375 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8376 | DWConvMicrokernelTester() |
| 8377 | .cr(16) |
| 8378 | .kr(9) |
| 8379 | .channels(channels) |
| 8380 | .input_offset(304) |
| 8381 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
| 8382 | } |
| 8383 | } |
| 8384 | |
| 8385 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX, zero) { |
| 8386 | TEST_REQUIRES_X86_AVX; |
| 8387 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 8388 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8389 | DWConvMicrokernelTester() |
| 8390 | .cr(16) |
| 8391 | .kr(9) |
| 8392 | .channels(channels) |
| 8393 | .input_offset(304) |
| 8394 | .zero_index(mz) |
| 8395 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx); |
| 8396 | } |
| 8397 | } |
| 8398 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8399 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 8400 | |
| 8401 | |
| 8402 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8403 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8404 | TEST_REQUIRES_X86_AVX; |
| 8405 | DWConvMicrokernelTester() |
| 8406 | .cr(16) |
| 8407 | .kr(9) |
| 8408 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8409 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8410 | } |
| 8411 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8412 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8413 | TEST_REQUIRES_X86_AVX; |
| 8414 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8415 | DWConvMicrokernelTester() |
| 8416 | .cr(16) |
| 8417 | .kr(9) |
| 8418 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8419 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8420 | } |
| 8421 | } |
| 8422 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8423 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8424 | TEST_REQUIRES_X86_AVX; |
| 8425 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8426 | DWConvMicrokernelTester() |
| 8427 | .cr(16) |
| 8428 | .kr(9) |
| 8429 | .channels(channels) |
| 8430 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8431 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8432 | } |
| 8433 | } |
| 8434 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8435 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8436 | TEST_REQUIRES_X86_AVX; |
| 8437 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8438 | DWConvMicrokernelTester() |
| 8439 | .cr(16) |
| 8440 | .kr(9) |
| 8441 | .channels(channels) |
| 8442 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8443 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8444 | } |
| 8445 | } |
| 8446 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8447 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8448 | TEST_REQUIRES_X86_AVX; |
| 8449 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 8450 | DWConvMicrokernelTester() |
| 8451 | .cr(16) |
| 8452 | .kr(9) |
| 8453 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8454 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8455 | } |
| 8456 | } |
| 8457 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8458 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8459 | TEST_REQUIRES_X86_AVX; |
| 8460 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 8461 | DWConvMicrokernelTester() |
| 8462 | .cr(16) |
| 8463 | .kr(9) |
| 8464 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8465 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8466 | } |
| 8467 | } |
| 8468 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8469 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8470 | TEST_REQUIRES_X86_AVX; |
| 8471 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 8472 | DWConvMicrokernelTester() |
| 8473 | .cr(16) |
| 8474 | .kr(9) |
| 8475 | .channels(channels) |
| 8476 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8477 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8478 | } |
| 8479 | } |
| 8480 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8481 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8482 | TEST_REQUIRES_X86_AVX; |
| 8483 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 8484 | DWConvMicrokernelTester() |
| 8485 | .cr(16) |
| 8486 | .kr(9) |
| 8487 | .channels(channels) |
| 8488 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8489 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8490 | } |
| 8491 | } |
| 8492 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8493 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8494 | TEST_REQUIRES_X86_AVX; |
| 8495 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8496 | DWConvMicrokernelTester() |
| 8497 | .cr(16) |
| 8498 | .kr(9) |
| 8499 | .channels(channels) |
| 8500 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8501 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8502 | } |
| 8503 | } |
| 8504 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8505 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8506 | TEST_REQUIRES_X86_AVX; |
| 8507 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8508 | for (size_t step = 2; step <= 9; step++) { |
| 8509 | DWConvMicrokernelTester() |
| 8510 | .cr(16) |
| 8511 | .kr(9) |
| 8512 | .channels(channels) |
| 8513 | .width(3) |
| 8514 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8515 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8516 | } |
| 8517 | } |
| 8518 | } |
| 8519 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8520 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8521 | TEST_REQUIRES_X86_AVX; |
| 8522 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8523 | DWConvMicrokernelTester() |
| 8524 | .cr(16) |
| 8525 | .kr(9) |
| 8526 | .channels(16) |
| 8527 | .width(5) |
| 8528 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8529 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8530 | } |
| 8531 | } |
| 8532 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8533 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8534 | TEST_REQUIRES_X86_AVX; |
| 8535 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8536 | DWConvMicrokernelTester() |
| 8537 | .cr(16) |
| 8538 | .kr(9) |
| 8539 | .channels(channels) |
| 8540 | .width(3) |
| 8541 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8542 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8543 | } |
| 8544 | } |
| 8545 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8546 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8547 | TEST_REQUIRES_X86_AVX; |
| 8548 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 8549 | DWConvMicrokernelTester() |
| 8550 | .cr(16) |
| 8551 | .kr(9) |
| 8552 | .channels(channels) |
| 8553 | .width(3) |
| 8554 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8555 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8556 | } |
| 8557 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 8558 | |
| 8559 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, input_offset) { |
| 8560 | TEST_REQUIRES_X86_AVX; |
| 8561 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8562 | DWConvMicrokernelTester() |
| 8563 | .cr(16) |
| 8564 | .kr(9) |
| 8565 | .channels(channels) |
| 8566 | .input_offset(304) |
| 8567 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
| 8568 | } |
| 8569 | } |
| 8570 | |
| 8571 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX_ACC2, zero) { |
| 8572 | TEST_REQUIRES_X86_AVX; |
| 8573 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 8574 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8575 | DWConvMicrokernelTester() |
| 8576 | .cr(16) |
| 8577 | .kr(9) |
| 8578 | .channels(channels) |
| 8579 | .input_offset(304) |
| 8580 | .zero_index(mz) |
| 8581 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx_acc2); |
| 8582 | } |
| 8583 | } |
| 8584 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8585 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 8586 | |
| 8587 | |
| 8588 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8589 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8590 | TEST_REQUIRES_X86_AVX; |
| 8591 | DWConvMicrokernelTester() |
| 8592 | .cr(8) |
| 8593 | .kr(4) |
| 8594 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8595 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8596 | } |
| 8597 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8598 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8599 | TEST_REQUIRES_X86_AVX; |
| 8600 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8601 | DWConvMicrokernelTester() |
| 8602 | .cr(8) |
| 8603 | .kr(4) |
| 8604 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8605 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8606 | } |
| 8607 | } |
| 8608 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8609 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8610 | TEST_REQUIRES_X86_AVX; |
| 8611 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8612 | DWConvMicrokernelTester() |
| 8613 | .cr(8) |
| 8614 | .kr(4) |
| 8615 | .channels(channels) |
| 8616 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8617 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8618 | } |
| 8619 | } |
| 8620 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8621 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8622 | TEST_REQUIRES_X86_AVX; |
| 8623 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8624 | DWConvMicrokernelTester() |
| 8625 | .cr(8) |
| 8626 | .kr(4) |
| 8627 | .channels(channels) |
| 8628 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8629 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8630 | } |
| 8631 | } |
| 8632 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8633 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8634 | TEST_REQUIRES_X86_AVX; |
| 8635 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 8636 | DWConvMicrokernelTester() |
| 8637 | .cr(8) |
| 8638 | .kr(4) |
| 8639 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8640 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8641 | } |
| 8642 | } |
| 8643 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8644 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8645 | TEST_REQUIRES_X86_AVX; |
| 8646 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8647 | DWConvMicrokernelTester() |
| 8648 | .cr(8) |
| 8649 | .kr(4) |
| 8650 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8651 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8652 | } |
| 8653 | } |
| 8654 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8655 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8656 | TEST_REQUIRES_X86_AVX; |
| 8657 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8658 | DWConvMicrokernelTester() |
| 8659 | .cr(8) |
| 8660 | .kr(4) |
| 8661 | .channels(channels) |
| 8662 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8663 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8664 | } |
| 8665 | } |
| 8666 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8667 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8668 | TEST_REQUIRES_X86_AVX; |
| 8669 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8670 | DWConvMicrokernelTester() |
| 8671 | .cr(8) |
| 8672 | .kr(4) |
| 8673 | .channels(channels) |
| 8674 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8675 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8676 | } |
| 8677 | } |
| 8678 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8679 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8680 | TEST_REQUIRES_X86_AVX; |
| 8681 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8682 | DWConvMicrokernelTester() |
| 8683 | .cr(8) |
| 8684 | .kr(4) |
| 8685 | .channels(channels) |
| 8686 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8687 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8688 | } |
| 8689 | } |
| 8690 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8691 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8692 | TEST_REQUIRES_X86_AVX; |
| 8693 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8694 | for (size_t step = 2; step <= 4; step++) { |
| 8695 | DWConvMicrokernelTester() |
| 8696 | .cr(8) |
| 8697 | .kr(4) |
| 8698 | .channels(channels) |
| 8699 | .width(3) |
| 8700 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8701 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8702 | } |
| 8703 | } |
| 8704 | } |
| 8705 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8706 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8707 | TEST_REQUIRES_X86_AVX; |
| 8708 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8709 | DWConvMicrokernelTester() |
| 8710 | .cr(8) |
| 8711 | .kr(4) |
| 8712 | .channels(8) |
| 8713 | .width(5) |
| 8714 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8715 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8716 | } |
| 8717 | } |
| 8718 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8719 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8720 | TEST_REQUIRES_X86_AVX; |
| 8721 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8722 | DWConvMicrokernelTester() |
| 8723 | .cr(8) |
| 8724 | .kr(4) |
| 8725 | .channels(channels) |
| 8726 | .width(3) |
| 8727 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8728 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8729 | } |
| 8730 | } |
| 8731 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8732 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8733 | TEST_REQUIRES_X86_AVX; |
| 8734 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8735 | DWConvMicrokernelTester() |
| 8736 | .cr(8) |
| 8737 | .kr(4) |
| 8738 | .channels(channels) |
| 8739 | .width(3) |
| 8740 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8741 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8742 | } |
| 8743 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 8744 | |
| 8745 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, input_offset) { |
| 8746 | TEST_REQUIRES_X86_AVX; |
| 8747 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8748 | DWConvMicrokernelTester() |
| 8749 | .cr(8) |
| 8750 | .kr(4) |
| 8751 | .channels(channels) |
| 8752 | .input_offset(176) |
| 8753 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
| 8754 | } |
| 8755 | } |
| 8756 | |
| 8757 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX, zero) { |
| 8758 | TEST_REQUIRES_X86_AVX; |
| 8759 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 8760 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8761 | DWConvMicrokernelTester() |
| 8762 | .cr(8) |
| 8763 | .kr(4) |
| 8764 | .channels(channels) |
| 8765 | .input_offset(176) |
| 8766 | .zero_index(mz) |
| 8767 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx); |
| 8768 | } |
| 8769 | } |
| 8770 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8771 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 8772 | |
| 8773 | |
| 8774 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8775 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8776 | TEST_REQUIRES_X86_AVX; |
| 8777 | DWConvMicrokernelTester() |
| 8778 | .cr(8) |
| 8779 | .kr(4) |
| 8780 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8781 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8782 | } |
| 8783 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8784 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8785 | TEST_REQUIRES_X86_AVX; |
| 8786 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8787 | DWConvMicrokernelTester() |
| 8788 | .cr(8) |
| 8789 | .kr(4) |
| 8790 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8791 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8792 | } |
| 8793 | } |
| 8794 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8795 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8796 | TEST_REQUIRES_X86_AVX; |
| 8797 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8798 | DWConvMicrokernelTester() |
| 8799 | .cr(8) |
| 8800 | .kr(4) |
| 8801 | .channels(channels) |
| 8802 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8803 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8804 | } |
| 8805 | } |
| 8806 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8807 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8808 | TEST_REQUIRES_X86_AVX; |
| 8809 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8810 | DWConvMicrokernelTester() |
| 8811 | .cr(8) |
| 8812 | .kr(4) |
| 8813 | .channels(channels) |
| 8814 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8815 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8816 | } |
| 8817 | } |
| 8818 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8819 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8820 | TEST_REQUIRES_X86_AVX; |
| 8821 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 8822 | DWConvMicrokernelTester() |
| 8823 | .cr(8) |
| 8824 | .kr(4) |
| 8825 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8826 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8827 | } |
| 8828 | } |
| 8829 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8830 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8831 | TEST_REQUIRES_X86_AVX; |
| 8832 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8833 | DWConvMicrokernelTester() |
| 8834 | .cr(8) |
| 8835 | .kr(4) |
| 8836 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8837 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8838 | } |
| 8839 | } |
| 8840 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8841 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8842 | TEST_REQUIRES_X86_AVX; |
| 8843 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8844 | DWConvMicrokernelTester() |
| 8845 | .cr(8) |
| 8846 | .kr(4) |
| 8847 | .channels(channels) |
| 8848 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8849 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8850 | } |
| 8851 | } |
| 8852 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8853 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8854 | TEST_REQUIRES_X86_AVX; |
| 8855 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 8856 | DWConvMicrokernelTester() |
| 8857 | .cr(8) |
| 8858 | .kr(4) |
| 8859 | .channels(channels) |
| 8860 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8861 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8862 | } |
| 8863 | } |
| 8864 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8865 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8866 | TEST_REQUIRES_X86_AVX; |
| 8867 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8868 | DWConvMicrokernelTester() |
| 8869 | .cr(8) |
| 8870 | .kr(4) |
| 8871 | .channels(channels) |
| 8872 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8873 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8874 | } |
| 8875 | } |
| 8876 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8877 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8878 | TEST_REQUIRES_X86_AVX; |
| 8879 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8880 | for (size_t step = 2; step <= 4; step++) { |
| 8881 | DWConvMicrokernelTester() |
| 8882 | .cr(8) |
| 8883 | .kr(4) |
| 8884 | .channels(channels) |
| 8885 | .width(3) |
| 8886 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8887 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8888 | } |
| 8889 | } |
| 8890 | } |
| 8891 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8892 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8893 | TEST_REQUIRES_X86_AVX; |
| 8894 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8895 | DWConvMicrokernelTester() |
| 8896 | .cr(8) |
| 8897 | .kr(4) |
| 8898 | .channels(8) |
| 8899 | .width(5) |
| 8900 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8901 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8902 | } |
| 8903 | } |
| 8904 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8905 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8906 | TEST_REQUIRES_X86_AVX; |
| 8907 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8908 | DWConvMicrokernelTester() |
| 8909 | .cr(8) |
| 8910 | .kr(4) |
| 8911 | .channels(channels) |
| 8912 | .width(3) |
| 8913 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8914 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8915 | } |
| 8916 | } |
| 8917 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8918 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8919 | TEST_REQUIRES_X86_AVX; |
| 8920 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 8921 | DWConvMicrokernelTester() |
| 8922 | .cr(8) |
| 8923 | .kr(4) |
| 8924 | .channels(channels) |
| 8925 | .width(3) |
| 8926 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8927 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8928 | } |
| 8929 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 8930 | |
| 8931 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, input_offset) { |
| 8932 | TEST_REQUIRES_X86_AVX; |
| 8933 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8934 | DWConvMicrokernelTester() |
| 8935 | .cr(8) |
| 8936 | .kr(4) |
| 8937 | .channels(channels) |
| 8938 | .input_offset(176) |
| 8939 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
| 8940 | } |
| 8941 | } |
| 8942 | |
| 8943 | TEST(F32_DWCONV_MINMAX_UP8X4__AVX_ACC2, zero) { |
| 8944 | TEST_REQUIRES_X86_AVX; |
| 8945 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 8946 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 8947 | DWConvMicrokernelTester() |
| 8948 | .cr(8) |
| 8949 | .kr(4) |
| 8950 | .channels(channels) |
| 8951 | .input_offset(176) |
| 8952 | .zero_index(mz) |
| 8953 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__avx_acc2); |
| 8954 | } |
| 8955 | } |
| 8956 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8957 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 8958 | |
| 8959 | |
| 8960 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8961 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8962 | TEST_REQUIRES_X86_AVX; |
| 8963 | DWConvMicrokernelTester() |
| 8964 | .cr(16) |
| 8965 | .kr(4) |
| 8966 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8967 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8968 | } |
| 8969 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8970 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8971 | TEST_REQUIRES_X86_AVX; |
| 8972 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8973 | DWConvMicrokernelTester() |
| 8974 | .cr(16) |
| 8975 | .kr(4) |
| 8976 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8977 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8978 | } |
| 8979 | } |
| 8980 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8981 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8982 | TEST_REQUIRES_X86_AVX; |
| 8983 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8984 | DWConvMicrokernelTester() |
| 8985 | .cr(16) |
| 8986 | .kr(4) |
| 8987 | .channels(channels) |
| 8988 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8989 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8990 | } |
| 8991 | } |
| 8992 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 8993 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 8994 | TEST_REQUIRES_X86_AVX; |
| 8995 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 8996 | DWConvMicrokernelTester() |
| 8997 | .cr(16) |
| 8998 | .kr(4) |
| 8999 | .channels(channels) |
| 9000 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9001 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9002 | } |
| 9003 | } |
| 9004 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9005 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9006 | TEST_REQUIRES_X86_AVX; |
| 9007 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 9008 | DWConvMicrokernelTester() |
| 9009 | .cr(16) |
| 9010 | .kr(4) |
| 9011 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9012 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9013 | } |
| 9014 | } |
| 9015 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9016 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9017 | TEST_REQUIRES_X86_AVX; |
| 9018 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9019 | DWConvMicrokernelTester() |
| 9020 | .cr(16) |
| 9021 | .kr(4) |
| 9022 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9023 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9024 | } |
| 9025 | } |
| 9026 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9027 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9028 | TEST_REQUIRES_X86_AVX; |
| 9029 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9030 | DWConvMicrokernelTester() |
| 9031 | .cr(16) |
| 9032 | .kr(4) |
| 9033 | .channels(channels) |
| 9034 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9035 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9036 | } |
| 9037 | } |
| 9038 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9039 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9040 | TEST_REQUIRES_X86_AVX; |
| 9041 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9042 | DWConvMicrokernelTester() |
| 9043 | .cr(16) |
| 9044 | .kr(4) |
| 9045 | .channels(channels) |
| 9046 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9047 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9048 | } |
| 9049 | } |
| 9050 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9051 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9052 | TEST_REQUIRES_X86_AVX; |
| 9053 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9054 | DWConvMicrokernelTester() |
| 9055 | .cr(16) |
| 9056 | .kr(4) |
| 9057 | .channels(channels) |
| 9058 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9059 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9060 | } |
| 9061 | } |
| 9062 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9063 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9064 | TEST_REQUIRES_X86_AVX; |
| 9065 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9066 | for (size_t step = 2; step <= 4; step++) { |
| 9067 | DWConvMicrokernelTester() |
| 9068 | .cr(16) |
| 9069 | .kr(4) |
| 9070 | .channels(channels) |
| 9071 | .width(3) |
| 9072 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9073 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9074 | } |
| 9075 | } |
| 9076 | } |
| 9077 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9078 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9079 | TEST_REQUIRES_X86_AVX; |
| 9080 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9081 | DWConvMicrokernelTester() |
| 9082 | .cr(16) |
| 9083 | .kr(4) |
| 9084 | .channels(16) |
| 9085 | .width(5) |
| 9086 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9087 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9088 | } |
| 9089 | } |
| 9090 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9091 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9092 | TEST_REQUIRES_X86_AVX; |
| 9093 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9094 | DWConvMicrokernelTester() |
| 9095 | .cr(16) |
| 9096 | .kr(4) |
| 9097 | .channels(channels) |
| 9098 | .width(3) |
| 9099 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9100 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9101 | } |
| 9102 | } |
| 9103 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9104 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9105 | TEST_REQUIRES_X86_AVX; |
| 9106 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9107 | DWConvMicrokernelTester() |
| 9108 | .cr(16) |
| 9109 | .kr(4) |
| 9110 | .channels(channels) |
| 9111 | .width(3) |
| 9112 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9113 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9114 | } |
| 9115 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 9116 | |
| 9117 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, input_offset) { |
| 9118 | TEST_REQUIRES_X86_AVX; |
| 9119 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9120 | DWConvMicrokernelTester() |
| 9121 | .cr(16) |
| 9122 | .kr(4) |
| 9123 | .channels(channels) |
| 9124 | .input_offset(304) |
| 9125 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
| 9126 | } |
| 9127 | } |
| 9128 | |
| 9129 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX, zero) { |
| 9130 | TEST_REQUIRES_X86_AVX; |
| 9131 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 9132 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9133 | DWConvMicrokernelTester() |
| 9134 | .cr(16) |
| 9135 | .kr(4) |
| 9136 | .channels(channels) |
| 9137 | .input_offset(304) |
| 9138 | .zero_index(mz) |
| 9139 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx); |
| 9140 | } |
| 9141 | } |
| 9142 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9143 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 9144 | |
| 9145 | |
| 9146 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9147 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9148 | TEST_REQUIRES_X86_AVX; |
| 9149 | DWConvMicrokernelTester() |
| 9150 | .cr(16) |
| 9151 | .kr(4) |
| 9152 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9153 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9154 | } |
| 9155 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9156 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9157 | TEST_REQUIRES_X86_AVX; |
| 9158 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9159 | DWConvMicrokernelTester() |
| 9160 | .cr(16) |
| 9161 | .kr(4) |
| 9162 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9163 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9164 | } |
| 9165 | } |
| 9166 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9167 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9168 | TEST_REQUIRES_X86_AVX; |
| 9169 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9170 | DWConvMicrokernelTester() |
| 9171 | .cr(16) |
| 9172 | .kr(4) |
| 9173 | .channels(channels) |
| 9174 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9175 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9176 | } |
| 9177 | } |
| 9178 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9179 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9180 | TEST_REQUIRES_X86_AVX; |
| 9181 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9182 | DWConvMicrokernelTester() |
| 9183 | .cr(16) |
| 9184 | .kr(4) |
| 9185 | .channels(channels) |
| 9186 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9187 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9188 | } |
| 9189 | } |
| 9190 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9191 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9192 | TEST_REQUIRES_X86_AVX; |
| 9193 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 9194 | DWConvMicrokernelTester() |
| 9195 | .cr(16) |
| 9196 | .kr(4) |
| 9197 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9198 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9199 | } |
| 9200 | } |
| 9201 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9202 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9203 | TEST_REQUIRES_X86_AVX; |
| 9204 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9205 | DWConvMicrokernelTester() |
| 9206 | .cr(16) |
| 9207 | .kr(4) |
| 9208 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9209 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9210 | } |
| 9211 | } |
| 9212 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9213 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9214 | TEST_REQUIRES_X86_AVX; |
| 9215 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9216 | DWConvMicrokernelTester() |
| 9217 | .cr(16) |
| 9218 | .kr(4) |
| 9219 | .channels(channels) |
| 9220 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9221 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9222 | } |
| 9223 | } |
| 9224 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9225 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9226 | TEST_REQUIRES_X86_AVX; |
| 9227 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9228 | DWConvMicrokernelTester() |
| 9229 | .cr(16) |
| 9230 | .kr(4) |
| 9231 | .channels(channels) |
| 9232 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9233 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9234 | } |
| 9235 | } |
| 9236 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9237 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9238 | TEST_REQUIRES_X86_AVX; |
| 9239 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9240 | DWConvMicrokernelTester() |
| 9241 | .cr(16) |
| 9242 | .kr(4) |
| 9243 | .channels(channels) |
| 9244 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9245 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9246 | } |
| 9247 | } |
| 9248 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9249 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9250 | TEST_REQUIRES_X86_AVX; |
| 9251 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9252 | for (size_t step = 2; step <= 4; step++) { |
| 9253 | DWConvMicrokernelTester() |
| 9254 | .cr(16) |
| 9255 | .kr(4) |
| 9256 | .channels(channels) |
| 9257 | .width(3) |
| 9258 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9259 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9260 | } |
| 9261 | } |
| 9262 | } |
| 9263 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9264 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9265 | TEST_REQUIRES_X86_AVX; |
| 9266 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9267 | DWConvMicrokernelTester() |
| 9268 | .cr(16) |
| 9269 | .kr(4) |
| 9270 | .channels(16) |
| 9271 | .width(5) |
| 9272 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9273 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9274 | } |
| 9275 | } |
| 9276 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9277 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9278 | TEST_REQUIRES_X86_AVX; |
| 9279 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9280 | DWConvMicrokernelTester() |
| 9281 | .cr(16) |
| 9282 | .kr(4) |
| 9283 | .channels(channels) |
| 9284 | .width(3) |
| 9285 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9286 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9287 | } |
| 9288 | } |
| 9289 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9290 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9291 | TEST_REQUIRES_X86_AVX; |
| 9292 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9293 | DWConvMicrokernelTester() |
| 9294 | .cr(16) |
| 9295 | .kr(4) |
| 9296 | .channels(channels) |
| 9297 | .width(3) |
| 9298 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9299 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9300 | } |
| 9301 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 9302 | |
| 9303 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, input_offset) { |
| 9304 | TEST_REQUIRES_X86_AVX; |
| 9305 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9306 | DWConvMicrokernelTester() |
| 9307 | .cr(16) |
| 9308 | .kr(4) |
| 9309 | .channels(channels) |
| 9310 | .input_offset(304) |
| 9311 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
| 9312 | } |
| 9313 | } |
| 9314 | |
| 9315 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX_ACC2, zero) { |
| 9316 | TEST_REQUIRES_X86_AVX; |
| 9317 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 9318 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9319 | DWConvMicrokernelTester() |
| 9320 | .cr(16) |
| 9321 | .kr(4) |
| 9322 | .channels(channels) |
| 9323 | .input_offset(304) |
| 9324 | .zero_index(mz) |
| 9325 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx_acc2); |
| 9326 | } |
| 9327 | } |
| 9328 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9329 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 9330 | |
| 9331 | |
| 9332 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9333 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9334 | TEST_REQUIRES_X86_FMA3; |
| 9335 | DWConvMicrokernelTester() |
| 9336 | .cr(8) |
| 9337 | .kr(25) |
| 9338 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9339 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9340 | } |
| 9341 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9342 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9343 | TEST_REQUIRES_X86_FMA3; |
| 9344 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9345 | DWConvMicrokernelTester() |
| 9346 | .cr(8) |
| 9347 | .kr(25) |
| 9348 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9349 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9350 | } |
| 9351 | } |
| 9352 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9353 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9354 | TEST_REQUIRES_X86_FMA3; |
| 9355 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9356 | DWConvMicrokernelTester() |
| 9357 | .cr(8) |
| 9358 | .kr(25) |
| 9359 | .channels(channels) |
| 9360 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9361 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9362 | } |
| 9363 | } |
| 9364 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9365 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9366 | TEST_REQUIRES_X86_FMA3; |
| 9367 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9368 | DWConvMicrokernelTester() |
| 9369 | .cr(8) |
| 9370 | .kr(25) |
| 9371 | .channels(channels) |
| 9372 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9373 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9374 | } |
| 9375 | } |
| 9376 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9377 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9378 | TEST_REQUIRES_X86_FMA3; |
| 9379 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 9380 | DWConvMicrokernelTester() |
| 9381 | .cr(8) |
| 9382 | .kr(25) |
| 9383 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9384 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9385 | } |
| 9386 | } |
| 9387 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9388 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9389 | TEST_REQUIRES_X86_FMA3; |
| 9390 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 9391 | DWConvMicrokernelTester() |
| 9392 | .cr(8) |
| 9393 | .kr(25) |
| 9394 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9395 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9396 | } |
| 9397 | } |
| 9398 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9399 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9400 | TEST_REQUIRES_X86_FMA3; |
| 9401 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 9402 | DWConvMicrokernelTester() |
| 9403 | .cr(8) |
| 9404 | .kr(25) |
| 9405 | .channels(channels) |
| 9406 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9407 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9408 | } |
| 9409 | } |
| 9410 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9411 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9412 | TEST_REQUIRES_X86_FMA3; |
| 9413 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 9414 | DWConvMicrokernelTester() |
| 9415 | .cr(8) |
| 9416 | .kr(25) |
| 9417 | .channels(channels) |
| 9418 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9419 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9420 | } |
| 9421 | } |
| 9422 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9423 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9424 | TEST_REQUIRES_X86_FMA3; |
| 9425 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9426 | DWConvMicrokernelTester() |
| 9427 | .cr(8) |
| 9428 | .kr(25) |
| 9429 | .channels(channels) |
| 9430 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9431 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9432 | } |
| 9433 | } |
| 9434 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9435 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9436 | TEST_REQUIRES_X86_FMA3; |
| 9437 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9438 | for (size_t step = 2; step <= 25; step++) { |
| 9439 | DWConvMicrokernelTester() |
| 9440 | .cr(8) |
| 9441 | .kr(25) |
| 9442 | .channels(channels) |
| 9443 | .width(3) |
| 9444 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9445 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9446 | } |
| 9447 | } |
| 9448 | } |
| 9449 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9450 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9451 | TEST_REQUIRES_X86_FMA3; |
| 9452 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9453 | DWConvMicrokernelTester() |
| 9454 | .cr(8) |
| 9455 | .kr(25) |
| 9456 | .channels(8) |
| 9457 | .width(5) |
| 9458 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9459 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9460 | } |
| 9461 | } |
| 9462 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9463 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9464 | TEST_REQUIRES_X86_FMA3; |
| 9465 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9466 | DWConvMicrokernelTester() |
| 9467 | .cr(8) |
| 9468 | .kr(25) |
| 9469 | .channels(channels) |
| 9470 | .width(3) |
| 9471 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9472 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9473 | } |
| 9474 | } |
| 9475 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9476 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9477 | TEST_REQUIRES_X86_FMA3; |
| 9478 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9479 | DWConvMicrokernelTester() |
| 9480 | .cr(8) |
| 9481 | .kr(25) |
| 9482 | .channels(channels) |
| 9483 | .width(3) |
| 9484 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9485 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9486 | } |
| 9487 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 9488 | |
| 9489 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, input_offset) { |
| 9490 | TEST_REQUIRES_X86_FMA3; |
| 9491 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9492 | DWConvMicrokernelTester() |
| 9493 | .cr(8) |
| 9494 | .kr(25) |
| 9495 | .channels(channels) |
| 9496 | .input_offset(176) |
| 9497 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
| 9498 | } |
| 9499 | } |
| 9500 | |
| 9501 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3, zero) { |
| 9502 | TEST_REQUIRES_X86_FMA3; |
| 9503 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 9504 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9505 | DWConvMicrokernelTester() |
| 9506 | .cr(8) |
| 9507 | .kr(25) |
| 9508 | .channels(channels) |
| 9509 | .input_offset(176) |
| 9510 | .zero_index(mz) |
| 9511 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3); |
| 9512 | } |
| 9513 | } |
| 9514 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9515 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 9516 | |
| 9517 | |
| 9518 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9519 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9520 | TEST_REQUIRES_X86_FMA3; |
| 9521 | DWConvMicrokernelTester() |
| 9522 | .cr(8) |
| 9523 | .kr(25) |
| 9524 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9525 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9526 | } |
| 9527 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9528 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9529 | TEST_REQUIRES_X86_FMA3; |
| 9530 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9531 | DWConvMicrokernelTester() |
| 9532 | .cr(8) |
| 9533 | .kr(25) |
| 9534 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9535 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9536 | } |
| 9537 | } |
| 9538 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9539 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9540 | TEST_REQUIRES_X86_FMA3; |
| 9541 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9542 | DWConvMicrokernelTester() |
| 9543 | .cr(8) |
| 9544 | .kr(25) |
| 9545 | .channels(channels) |
| 9546 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9547 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9548 | } |
| 9549 | } |
| 9550 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9551 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9552 | TEST_REQUIRES_X86_FMA3; |
| 9553 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9554 | DWConvMicrokernelTester() |
| 9555 | .cr(8) |
| 9556 | .kr(25) |
| 9557 | .channels(channels) |
| 9558 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9559 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9560 | } |
| 9561 | } |
| 9562 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9563 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9564 | TEST_REQUIRES_X86_FMA3; |
| 9565 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 9566 | DWConvMicrokernelTester() |
| 9567 | .cr(8) |
| 9568 | .kr(25) |
| 9569 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9570 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9571 | } |
| 9572 | } |
| 9573 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9574 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9575 | TEST_REQUIRES_X86_FMA3; |
| 9576 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 9577 | DWConvMicrokernelTester() |
| 9578 | .cr(8) |
| 9579 | .kr(25) |
| 9580 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9581 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9582 | } |
| 9583 | } |
| 9584 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9585 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9586 | TEST_REQUIRES_X86_FMA3; |
| 9587 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 9588 | DWConvMicrokernelTester() |
| 9589 | .cr(8) |
| 9590 | .kr(25) |
| 9591 | .channels(channels) |
| 9592 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9593 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9594 | } |
| 9595 | } |
| 9596 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9597 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9598 | TEST_REQUIRES_X86_FMA3; |
| 9599 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 9600 | DWConvMicrokernelTester() |
| 9601 | .cr(8) |
| 9602 | .kr(25) |
| 9603 | .channels(channels) |
| 9604 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9605 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9606 | } |
| 9607 | } |
| 9608 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9609 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9610 | TEST_REQUIRES_X86_FMA3; |
| 9611 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9612 | DWConvMicrokernelTester() |
| 9613 | .cr(8) |
| 9614 | .kr(25) |
| 9615 | .channels(channels) |
| 9616 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9617 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9618 | } |
| 9619 | } |
| 9620 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9621 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9622 | TEST_REQUIRES_X86_FMA3; |
| 9623 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9624 | for (size_t step = 2; step <= 25; step++) { |
| 9625 | DWConvMicrokernelTester() |
| 9626 | .cr(8) |
| 9627 | .kr(25) |
| 9628 | .channels(channels) |
| 9629 | .width(3) |
| 9630 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9631 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9632 | } |
| 9633 | } |
| 9634 | } |
| 9635 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9636 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9637 | TEST_REQUIRES_X86_FMA3; |
| 9638 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9639 | DWConvMicrokernelTester() |
| 9640 | .cr(8) |
| 9641 | .kr(25) |
| 9642 | .channels(8) |
| 9643 | .width(5) |
| 9644 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9645 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9646 | } |
| 9647 | } |
| 9648 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9649 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9650 | TEST_REQUIRES_X86_FMA3; |
| 9651 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9652 | DWConvMicrokernelTester() |
| 9653 | .cr(8) |
| 9654 | .kr(25) |
| 9655 | .channels(channels) |
| 9656 | .width(3) |
| 9657 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9658 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9659 | } |
| 9660 | } |
| 9661 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9662 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9663 | TEST_REQUIRES_X86_FMA3; |
| 9664 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 9665 | DWConvMicrokernelTester() |
| 9666 | .cr(8) |
| 9667 | .kr(25) |
| 9668 | .channels(channels) |
| 9669 | .width(3) |
| 9670 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9671 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9672 | } |
| 9673 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 9674 | |
| 9675 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, input_offset) { |
| 9676 | TEST_REQUIRES_X86_FMA3; |
| 9677 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9678 | DWConvMicrokernelTester() |
| 9679 | .cr(8) |
| 9680 | .kr(25) |
| 9681 | .channels(channels) |
| 9682 | .input_offset(176) |
| 9683 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
| 9684 | } |
| 9685 | } |
| 9686 | |
| 9687 | TEST(F32_DWCONV_MINMAX_UP8X25__FMA3_ACC2, zero) { |
| 9688 | TEST_REQUIRES_X86_FMA3; |
| 9689 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 9690 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 9691 | DWConvMicrokernelTester() |
| 9692 | .cr(8) |
| 9693 | .kr(25) |
| 9694 | .channels(channels) |
| 9695 | .input_offset(176) |
| 9696 | .zero_index(mz) |
| 9697 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__fma3_acc2); |
| 9698 | } |
| 9699 | } |
| 9700 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9701 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 9702 | |
| 9703 | |
| 9704 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9705 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9706 | TEST_REQUIRES_X86_FMA3; |
| 9707 | DWConvMicrokernelTester() |
| 9708 | .cr(16) |
| 9709 | .kr(25) |
| 9710 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9711 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9712 | } |
| 9713 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9714 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9715 | TEST_REQUIRES_X86_FMA3; |
| 9716 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9717 | DWConvMicrokernelTester() |
| 9718 | .cr(16) |
| 9719 | .kr(25) |
| 9720 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9721 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9722 | } |
| 9723 | } |
| 9724 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9725 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9726 | TEST_REQUIRES_X86_FMA3; |
| 9727 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9728 | DWConvMicrokernelTester() |
| 9729 | .cr(16) |
| 9730 | .kr(25) |
| 9731 | .channels(channels) |
| 9732 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9733 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9734 | } |
| 9735 | } |
| 9736 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9737 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9738 | TEST_REQUIRES_X86_FMA3; |
| 9739 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9740 | DWConvMicrokernelTester() |
| 9741 | .cr(16) |
| 9742 | .kr(25) |
| 9743 | .channels(channels) |
| 9744 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9745 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9746 | } |
| 9747 | } |
| 9748 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9749 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9750 | TEST_REQUIRES_X86_FMA3; |
| 9751 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 9752 | DWConvMicrokernelTester() |
| 9753 | .cr(16) |
| 9754 | .kr(25) |
| 9755 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9756 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9757 | } |
| 9758 | } |
| 9759 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9760 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9761 | TEST_REQUIRES_X86_FMA3; |
| 9762 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9763 | DWConvMicrokernelTester() |
| 9764 | .cr(16) |
| 9765 | .kr(25) |
| 9766 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9767 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9768 | } |
| 9769 | } |
| 9770 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9771 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9772 | TEST_REQUIRES_X86_FMA3; |
| 9773 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9774 | DWConvMicrokernelTester() |
| 9775 | .cr(16) |
| 9776 | .kr(25) |
| 9777 | .channels(channels) |
| 9778 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9779 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9780 | } |
| 9781 | } |
| 9782 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9783 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9784 | TEST_REQUIRES_X86_FMA3; |
| 9785 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9786 | DWConvMicrokernelTester() |
| 9787 | .cr(16) |
| 9788 | .kr(25) |
| 9789 | .channels(channels) |
| 9790 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9791 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9792 | } |
| 9793 | } |
| 9794 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9795 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9796 | TEST_REQUIRES_X86_FMA3; |
| 9797 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9798 | DWConvMicrokernelTester() |
| 9799 | .cr(16) |
| 9800 | .kr(25) |
| 9801 | .channels(channels) |
| 9802 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9803 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9804 | } |
| 9805 | } |
| 9806 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9807 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9808 | TEST_REQUIRES_X86_FMA3; |
| 9809 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9810 | for (size_t step = 2; step <= 25; step++) { |
| 9811 | DWConvMicrokernelTester() |
| 9812 | .cr(16) |
| 9813 | .kr(25) |
| 9814 | .channels(channels) |
| 9815 | .width(3) |
| 9816 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9817 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9818 | } |
| 9819 | } |
| 9820 | } |
| 9821 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9822 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9823 | TEST_REQUIRES_X86_FMA3; |
| 9824 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9825 | DWConvMicrokernelTester() |
| 9826 | .cr(16) |
| 9827 | .kr(25) |
| 9828 | .channels(16) |
| 9829 | .width(5) |
| 9830 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9831 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9832 | } |
| 9833 | } |
| 9834 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9835 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9836 | TEST_REQUIRES_X86_FMA3; |
| 9837 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9838 | DWConvMicrokernelTester() |
| 9839 | .cr(16) |
| 9840 | .kr(25) |
| 9841 | .channels(channels) |
| 9842 | .width(3) |
| 9843 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9844 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9845 | } |
| 9846 | } |
| 9847 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9848 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9849 | TEST_REQUIRES_X86_FMA3; |
| 9850 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9851 | DWConvMicrokernelTester() |
| 9852 | .cr(16) |
| 9853 | .kr(25) |
| 9854 | .channels(channels) |
| 9855 | .width(3) |
| 9856 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9857 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9858 | } |
| 9859 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 9860 | |
| 9861 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, input_offset) { |
| 9862 | TEST_REQUIRES_X86_FMA3; |
| 9863 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9864 | DWConvMicrokernelTester() |
| 9865 | .cr(16) |
| 9866 | .kr(25) |
| 9867 | .channels(channels) |
| 9868 | .input_offset(304) |
| 9869 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
| 9870 | } |
| 9871 | } |
| 9872 | |
| 9873 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3, zero) { |
| 9874 | TEST_REQUIRES_X86_FMA3; |
| 9875 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 9876 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9877 | DWConvMicrokernelTester() |
| 9878 | .cr(16) |
| 9879 | .kr(25) |
| 9880 | .channels(channels) |
| 9881 | .input_offset(304) |
| 9882 | .zero_index(mz) |
| 9883 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3); |
| 9884 | } |
| 9885 | } |
| 9886 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9887 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 9888 | |
| 9889 | |
| 9890 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9891 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9892 | TEST_REQUIRES_X86_FMA3; |
| 9893 | DWConvMicrokernelTester() |
| 9894 | .cr(16) |
| 9895 | .kr(25) |
| 9896 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9897 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9898 | } |
| 9899 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9900 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9901 | TEST_REQUIRES_X86_FMA3; |
| 9902 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9903 | DWConvMicrokernelTester() |
| 9904 | .cr(16) |
| 9905 | .kr(25) |
| 9906 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9907 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9908 | } |
| 9909 | } |
| 9910 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9911 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9912 | TEST_REQUIRES_X86_FMA3; |
| 9913 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9914 | DWConvMicrokernelTester() |
| 9915 | .cr(16) |
| 9916 | .kr(25) |
| 9917 | .channels(channels) |
| 9918 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9919 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9920 | } |
| 9921 | } |
| 9922 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9923 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9924 | TEST_REQUIRES_X86_FMA3; |
| 9925 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 9926 | DWConvMicrokernelTester() |
| 9927 | .cr(16) |
| 9928 | .kr(25) |
| 9929 | .channels(channels) |
| 9930 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9931 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9932 | } |
| 9933 | } |
| 9934 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9935 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9936 | TEST_REQUIRES_X86_FMA3; |
| 9937 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 9938 | DWConvMicrokernelTester() |
| 9939 | .cr(16) |
| 9940 | .kr(25) |
| 9941 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9942 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9943 | } |
| 9944 | } |
| 9945 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9946 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9947 | TEST_REQUIRES_X86_FMA3; |
| 9948 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9949 | DWConvMicrokernelTester() |
| 9950 | .cr(16) |
| 9951 | .kr(25) |
| 9952 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9953 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9954 | } |
| 9955 | } |
| 9956 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9957 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9958 | TEST_REQUIRES_X86_FMA3; |
| 9959 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9960 | DWConvMicrokernelTester() |
| 9961 | .cr(16) |
| 9962 | .kr(25) |
| 9963 | .channels(channels) |
| 9964 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9965 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9966 | } |
| 9967 | } |
| 9968 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9969 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9970 | TEST_REQUIRES_X86_FMA3; |
| 9971 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 9972 | DWConvMicrokernelTester() |
| 9973 | .cr(16) |
| 9974 | .kr(25) |
| 9975 | .channels(channels) |
| 9976 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9977 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9978 | } |
| 9979 | } |
| 9980 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9981 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9982 | TEST_REQUIRES_X86_FMA3; |
| 9983 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9984 | DWConvMicrokernelTester() |
| 9985 | .cr(16) |
| 9986 | .kr(25) |
| 9987 | .channels(channels) |
| 9988 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9989 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9990 | } |
| 9991 | } |
| 9992 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 9993 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 9994 | TEST_REQUIRES_X86_FMA3; |
| 9995 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 9996 | for (size_t step = 2; step <= 25; step++) { |
| 9997 | DWConvMicrokernelTester() |
| 9998 | .cr(16) |
| 9999 | .kr(25) |
| 10000 | .channels(channels) |
| 10001 | .width(3) |
| 10002 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10003 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10004 | } |
| 10005 | } |
| 10006 | } |
| 10007 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10008 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10009 | TEST_REQUIRES_X86_FMA3; |
| 10010 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10011 | DWConvMicrokernelTester() |
| 10012 | .cr(16) |
| 10013 | .kr(25) |
| 10014 | .channels(16) |
| 10015 | .width(5) |
| 10016 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10017 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10018 | } |
| 10019 | } |
| 10020 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10021 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10022 | TEST_REQUIRES_X86_FMA3; |
| 10023 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10024 | DWConvMicrokernelTester() |
| 10025 | .cr(16) |
| 10026 | .kr(25) |
| 10027 | .channels(channels) |
| 10028 | .width(3) |
| 10029 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10030 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10031 | } |
| 10032 | } |
| 10033 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10034 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10035 | TEST_REQUIRES_X86_FMA3; |
| 10036 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10037 | DWConvMicrokernelTester() |
| 10038 | .cr(16) |
| 10039 | .kr(25) |
| 10040 | .channels(channels) |
| 10041 | .width(3) |
| 10042 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10043 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10044 | } |
| 10045 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 10046 | |
| 10047 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, input_offset) { |
| 10048 | TEST_REQUIRES_X86_FMA3; |
| 10049 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10050 | DWConvMicrokernelTester() |
| 10051 | .cr(16) |
| 10052 | .kr(25) |
| 10053 | .channels(channels) |
| 10054 | .input_offset(304) |
| 10055 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
| 10056 | } |
| 10057 | } |
| 10058 | |
| 10059 | TEST(F32_DWCONV_MINMAX_UP16X25__FMA3_ACC2, zero) { |
| 10060 | TEST_REQUIRES_X86_FMA3; |
| 10061 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 10062 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10063 | DWConvMicrokernelTester() |
| 10064 | .cr(16) |
| 10065 | .kr(25) |
| 10066 | .channels(channels) |
| 10067 | .input_offset(304) |
| 10068 | .zero_index(mz) |
| 10069 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__fma3_acc2); |
| 10070 | } |
| 10071 | } |
| 10072 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10073 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 10074 | |
| 10075 | |
| 10076 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10077 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10078 | TEST_REQUIRES_X86_FMA3; |
| 10079 | DWConvMicrokernelTester() |
| 10080 | .cr(8) |
| 10081 | .kr(9) |
| 10082 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10083 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10084 | } |
| 10085 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10086 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10087 | TEST_REQUIRES_X86_FMA3; |
| 10088 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10089 | DWConvMicrokernelTester() |
| 10090 | .cr(8) |
| 10091 | .kr(9) |
| 10092 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10093 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10094 | } |
| 10095 | } |
| 10096 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10097 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10098 | TEST_REQUIRES_X86_FMA3; |
| 10099 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10100 | DWConvMicrokernelTester() |
| 10101 | .cr(8) |
| 10102 | .kr(9) |
| 10103 | .channels(channels) |
| 10104 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10105 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10106 | } |
| 10107 | } |
| 10108 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10109 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10110 | TEST_REQUIRES_X86_FMA3; |
| 10111 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10112 | DWConvMicrokernelTester() |
| 10113 | .cr(8) |
| 10114 | .kr(9) |
| 10115 | .channels(channels) |
| 10116 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10117 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10118 | } |
| 10119 | } |
| 10120 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10121 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10122 | TEST_REQUIRES_X86_FMA3; |
| 10123 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 10124 | DWConvMicrokernelTester() |
| 10125 | .cr(8) |
| 10126 | .kr(9) |
| 10127 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10128 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10129 | } |
| 10130 | } |
| 10131 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10132 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10133 | TEST_REQUIRES_X86_FMA3; |
| 10134 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10135 | DWConvMicrokernelTester() |
| 10136 | .cr(8) |
| 10137 | .kr(9) |
| 10138 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10139 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10140 | } |
| 10141 | } |
| 10142 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10143 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10144 | TEST_REQUIRES_X86_FMA3; |
| 10145 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10146 | DWConvMicrokernelTester() |
| 10147 | .cr(8) |
| 10148 | .kr(9) |
| 10149 | .channels(channels) |
| 10150 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10151 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10152 | } |
| 10153 | } |
| 10154 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10155 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10156 | TEST_REQUIRES_X86_FMA3; |
| 10157 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10158 | DWConvMicrokernelTester() |
| 10159 | .cr(8) |
| 10160 | .kr(9) |
| 10161 | .channels(channels) |
| 10162 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10163 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10164 | } |
| 10165 | } |
| 10166 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10167 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10168 | TEST_REQUIRES_X86_FMA3; |
| 10169 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10170 | DWConvMicrokernelTester() |
| 10171 | .cr(8) |
| 10172 | .kr(9) |
| 10173 | .channels(channels) |
| 10174 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10175 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10176 | } |
| 10177 | } |
| 10178 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10179 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10180 | TEST_REQUIRES_X86_FMA3; |
| 10181 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10182 | for (size_t step = 2; step <= 9; step++) { |
| 10183 | DWConvMicrokernelTester() |
| 10184 | .cr(8) |
| 10185 | .kr(9) |
| 10186 | .channels(channels) |
| 10187 | .width(3) |
| 10188 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10189 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10190 | } |
| 10191 | } |
| 10192 | } |
| 10193 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10194 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10195 | TEST_REQUIRES_X86_FMA3; |
| 10196 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10197 | DWConvMicrokernelTester() |
| 10198 | .cr(8) |
| 10199 | .kr(9) |
| 10200 | .channels(8) |
| 10201 | .width(5) |
| 10202 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10203 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10204 | } |
| 10205 | } |
| 10206 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10207 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10208 | TEST_REQUIRES_X86_FMA3; |
| 10209 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10210 | DWConvMicrokernelTester() |
| 10211 | .cr(8) |
| 10212 | .kr(9) |
| 10213 | .channels(channels) |
| 10214 | .width(3) |
| 10215 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10216 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10217 | } |
| 10218 | } |
| 10219 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10220 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10221 | TEST_REQUIRES_X86_FMA3; |
| 10222 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10223 | DWConvMicrokernelTester() |
| 10224 | .cr(8) |
| 10225 | .kr(9) |
| 10226 | .channels(channels) |
| 10227 | .width(3) |
| 10228 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10229 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10230 | } |
| 10231 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 10232 | |
| 10233 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, input_offset) { |
| 10234 | TEST_REQUIRES_X86_FMA3; |
| 10235 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10236 | DWConvMicrokernelTester() |
| 10237 | .cr(8) |
| 10238 | .kr(9) |
| 10239 | .channels(channels) |
| 10240 | .input_offset(176) |
| 10241 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
| 10242 | } |
| 10243 | } |
| 10244 | |
| 10245 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3, zero) { |
| 10246 | TEST_REQUIRES_X86_FMA3; |
| 10247 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 10248 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10249 | DWConvMicrokernelTester() |
| 10250 | .cr(8) |
| 10251 | .kr(9) |
| 10252 | .channels(channels) |
| 10253 | .input_offset(176) |
| 10254 | .zero_index(mz) |
| 10255 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3); |
| 10256 | } |
| 10257 | } |
| 10258 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10259 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 10260 | |
| 10261 | |
| 10262 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10263 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10264 | TEST_REQUIRES_X86_FMA3; |
| 10265 | DWConvMicrokernelTester() |
| 10266 | .cr(8) |
| 10267 | .kr(9) |
| 10268 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10269 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10270 | } |
| 10271 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10272 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10273 | TEST_REQUIRES_X86_FMA3; |
| 10274 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10275 | DWConvMicrokernelTester() |
| 10276 | .cr(8) |
| 10277 | .kr(9) |
| 10278 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10279 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10280 | } |
| 10281 | } |
| 10282 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10283 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10284 | TEST_REQUIRES_X86_FMA3; |
| 10285 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10286 | DWConvMicrokernelTester() |
| 10287 | .cr(8) |
| 10288 | .kr(9) |
| 10289 | .channels(channels) |
| 10290 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10291 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10292 | } |
| 10293 | } |
| 10294 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10295 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10296 | TEST_REQUIRES_X86_FMA3; |
| 10297 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10298 | DWConvMicrokernelTester() |
| 10299 | .cr(8) |
| 10300 | .kr(9) |
| 10301 | .channels(channels) |
| 10302 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10303 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10304 | } |
| 10305 | } |
| 10306 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10307 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10308 | TEST_REQUIRES_X86_FMA3; |
| 10309 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 10310 | DWConvMicrokernelTester() |
| 10311 | .cr(8) |
| 10312 | .kr(9) |
| 10313 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10314 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10315 | } |
| 10316 | } |
| 10317 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10318 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10319 | TEST_REQUIRES_X86_FMA3; |
| 10320 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10321 | DWConvMicrokernelTester() |
| 10322 | .cr(8) |
| 10323 | .kr(9) |
| 10324 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10325 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10326 | } |
| 10327 | } |
| 10328 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10329 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10330 | TEST_REQUIRES_X86_FMA3; |
| 10331 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10332 | DWConvMicrokernelTester() |
| 10333 | .cr(8) |
| 10334 | .kr(9) |
| 10335 | .channels(channels) |
| 10336 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10337 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10338 | } |
| 10339 | } |
| 10340 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10341 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10342 | TEST_REQUIRES_X86_FMA3; |
| 10343 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10344 | DWConvMicrokernelTester() |
| 10345 | .cr(8) |
| 10346 | .kr(9) |
| 10347 | .channels(channels) |
| 10348 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10349 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10350 | } |
| 10351 | } |
| 10352 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10353 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10354 | TEST_REQUIRES_X86_FMA3; |
| 10355 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10356 | DWConvMicrokernelTester() |
| 10357 | .cr(8) |
| 10358 | .kr(9) |
| 10359 | .channels(channels) |
| 10360 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10361 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10362 | } |
| 10363 | } |
| 10364 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10365 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10366 | TEST_REQUIRES_X86_FMA3; |
| 10367 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10368 | for (size_t step = 2; step <= 9; step++) { |
| 10369 | DWConvMicrokernelTester() |
| 10370 | .cr(8) |
| 10371 | .kr(9) |
| 10372 | .channels(channels) |
| 10373 | .width(3) |
| 10374 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10375 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10376 | } |
| 10377 | } |
| 10378 | } |
| 10379 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10380 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10381 | TEST_REQUIRES_X86_FMA3; |
| 10382 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10383 | DWConvMicrokernelTester() |
| 10384 | .cr(8) |
| 10385 | .kr(9) |
| 10386 | .channels(8) |
| 10387 | .width(5) |
| 10388 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10389 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10390 | } |
| 10391 | } |
| 10392 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10393 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10394 | TEST_REQUIRES_X86_FMA3; |
| 10395 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10396 | DWConvMicrokernelTester() |
| 10397 | .cr(8) |
| 10398 | .kr(9) |
| 10399 | .channels(channels) |
| 10400 | .width(3) |
| 10401 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10402 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10403 | } |
| 10404 | } |
| 10405 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10406 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10407 | TEST_REQUIRES_X86_FMA3; |
| 10408 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10409 | DWConvMicrokernelTester() |
| 10410 | .cr(8) |
| 10411 | .kr(9) |
| 10412 | .channels(channels) |
| 10413 | .width(3) |
| 10414 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10415 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10416 | } |
| 10417 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 10418 | |
| 10419 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, input_offset) { |
| 10420 | TEST_REQUIRES_X86_FMA3; |
| 10421 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10422 | DWConvMicrokernelTester() |
| 10423 | .cr(8) |
| 10424 | .kr(9) |
| 10425 | .channels(channels) |
| 10426 | .input_offset(176) |
| 10427 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
| 10428 | } |
| 10429 | } |
| 10430 | |
| 10431 | TEST(F32_DWCONV_MINMAX_UP8X9__FMA3_ACC2, zero) { |
| 10432 | TEST_REQUIRES_X86_FMA3; |
| 10433 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 10434 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10435 | DWConvMicrokernelTester() |
| 10436 | .cr(8) |
| 10437 | .kr(9) |
| 10438 | .channels(channels) |
| 10439 | .input_offset(176) |
| 10440 | .zero_index(mz) |
| 10441 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__fma3_acc2); |
| 10442 | } |
| 10443 | } |
| 10444 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10445 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 10446 | |
| 10447 | |
| 10448 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10449 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10450 | TEST_REQUIRES_X86_FMA3; |
| 10451 | DWConvMicrokernelTester() |
| 10452 | .cr(16) |
| 10453 | .kr(9) |
| 10454 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10455 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10456 | } |
| 10457 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10458 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10459 | TEST_REQUIRES_X86_FMA3; |
| 10460 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10461 | DWConvMicrokernelTester() |
| 10462 | .cr(16) |
| 10463 | .kr(9) |
| 10464 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10465 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10466 | } |
| 10467 | } |
| 10468 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10469 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10470 | TEST_REQUIRES_X86_FMA3; |
| 10471 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10472 | DWConvMicrokernelTester() |
| 10473 | .cr(16) |
| 10474 | .kr(9) |
| 10475 | .channels(channels) |
| 10476 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10477 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10478 | } |
| 10479 | } |
| 10480 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10481 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10482 | TEST_REQUIRES_X86_FMA3; |
| 10483 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10484 | DWConvMicrokernelTester() |
| 10485 | .cr(16) |
| 10486 | .kr(9) |
| 10487 | .channels(channels) |
| 10488 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10489 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10490 | } |
| 10491 | } |
| 10492 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10493 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10494 | TEST_REQUIRES_X86_FMA3; |
| 10495 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 10496 | DWConvMicrokernelTester() |
| 10497 | .cr(16) |
| 10498 | .kr(9) |
| 10499 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10500 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10501 | } |
| 10502 | } |
| 10503 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10504 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10505 | TEST_REQUIRES_X86_FMA3; |
| 10506 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 10507 | DWConvMicrokernelTester() |
| 10508 | .cr(16) |
| 10509 | .kr(9) |
| 10510 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10511 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10512 | } |
| 10513 | } |
| 10514 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10515 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10516 | TEST_REQUIRES_X86_FMA3; |
| 10517 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 10518 | DWConvMicrokernelTester() |
| 10519 | .cr(16) |
| 10520 | .kr(9) |
| 10521 | .channels(channels) |
| 10522 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10523 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10524 | } |
| 10525 | } |
| 10526 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10527 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10528 | TEST_REQUIRES_X86_FMA3; |
| 10529 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 10530 | DWConvMicrokernelTester() |
| 10531 | .cr(16) |
| 10532 | .kr(9) |
| 10533 | .channels(channels) |
| 10534 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10535 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10536 | } |
| 10537 | } |
| 10538 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10539 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10540 | TEST_REQUIRES_X86_FMA3; |
| 10541 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10542 | DWConvMicrokernelTester() |
| 10543 | .cr(16) |
| 10544 | .kr(9) |
| 10545 | .channels(channels) |
| 10546 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10547 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10548 | } |
| 10549 | } |
| 10550 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10551 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10552 | TEST_REQUIRES_X86_FMA3; |
| 10553 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10554 | for (size_t step = 2; step <= 9; step++) { |
| 10555 | DWConvMicrokernelTester() |
| 10556 | .cr(16) |
| 10557 | .kr(9) |
| 10558 | .channels(channels) |
| 10559 | .width(3) |
| 10560 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10561 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10562 | } |
| 10563 | } |
| 10564 | } |
| 10565 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10566 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10567 | TEST_REQUIRES_X86_FMA3; |
| 10568 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10569 | DWConvMicrokernelTester() |
| 10570 | .cr(16) |
| 10571 | .kr(9) |
| 10572 | .channels(16) |
| 10573 | .width(5) |
| 10574 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10575 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10576 | } |
| 10577 | } |
| 10578 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10579 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10580 | TEST_REQUIRES_X86_FMA3; |
| 10581 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10582 | DWConvMicrokernelTester() |
| 10583 | .cr(16) |
| 10584 | .kr(9) |
| 10585 | .channels(channels) |
| 10586 | .width(3) |
| 10587 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10588 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10589 | } |
| 10590 | } |
| 10591 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10592 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10593 | TEST_REQUIRES_X86_FMA3; |
| 10594 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10595 | DWConvMicrokernelTester() |
| 10596 | .cr(16) |
| 10597 | .kr(9) |
| 10598 | .channels(channels) |
| 10599 | .width(3) |
| 10600 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10601 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10602 | } |
| 10603 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 10604 | |
| 10605 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, input_offset) { |
| 10606 | TEST_REQUIRES_X86_FMA3; |
| 10607 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10608 | DWConvMicrokernelTester() |
| 10609 | .cr(16) |
| 10610 | .kr(9) |
| 10611 | .channels(channels) |
| 10612 | .input_offset(304) |
| 10613 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
| 10614 | } |
| 10615 | } |
| 10616 | |
| 10617 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3, zero) { |
| 10618 | TEST_REQUIRES_X86_FMA3; |
| 10619 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 10620 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10621 | DWConvMicrokernelTester() |
| 10622 | .cr(16) |
| 10623 | .kr(9) |
| 10624 | .channels(channels) |
| 10625 | .input_offset(304) |
| 10626 | .zero_index(mz) |
| 10627 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3); |
| 10628 | } |
| 10629 | } |
| 10630 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10631 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 10632 | |
| 10633 | |
| 10634 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10635 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10636 | TEST_REQUIRES_X86_FMA3; |
| 10637 | DWConvMicrokernelTester() |
| 10638 | .cr(16) |
| 10639 | .kr(9) |
| 10640 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10641 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10642 | } |
| 10643 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10644 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10645 | TEST_REQUIRES_X86_FMA3; |
| 10646 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10647 | DWConvMicrokernelTester() |
| 10648 | .cr(16) |
| 10649 | .kr(9) |
| 10650 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10651 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10652 | } |
| 10653 | } |
| 10654 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10655 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10656 | TEST_REQUIRES_X86_FMA3; |
| 10657 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10658 | DWConvMicrokernelTester() |
| 10659 | .cr(16) |
| 10660 | .kr(9) |
| 10661 | .channels(channels) |
| 10662 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10663 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10664 | } |
| 10665 | } |
| 10666 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10667 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10668 | TEST_REQUIRES_X86_FMA3; |
| 10669 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10670 | DWConvMicrokernelTester() |
| 10671 | .cr(16) |
| 10672 | .kr(9) |
| 10673 | .channels(channels) |
| 10674 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10675 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10676 | } |
| 10677 | } |
| 10678 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10679 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10680 | TEST_REQUIRES_X86_FMA3; |
| 10681 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 10682 | DWConvMicrokernelTester() |
| 10683 | .cr(16) |
| 10684 | .kr(9) |
| 10685 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10686 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10687 | } |
| 10688 | } |
| 10689 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10690 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10691 | TEST_REQUIRES_X86_FMA3; |
| 10692 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 10693 | DWConvMicrokernelTester() |
| 10694 | .cr(16) |
| 10695 | .kr(9) |
| 10696 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10697 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10698 | } |
| 10699 | } |
| 10700 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10701 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10702 | TEST_REQUIRES_X86_FMA3; |
| 10703 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 10704 | DWConvMicrokernelTester() |
| 10705 | .cr(16) |
| 10706 | .kr(9) |
| 10707 | .channels(channels) |
| 10708 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10709 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10710 | } |
| 10711 | } |
| 10712 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10713 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10714 | TEST_REQUIRES_X86_FMA3; |
| 10715 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 10716 | DWConvMicrokernelTester() |
| 10717 | .cr(16) |
| 10718 | .kr(9) |
| 10719 | .channels(channels) |
| 10720 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10721 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10722 | } |
| 10723 | } |
| 10724 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10725 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10726 | TEST_REQUIRES_X86_FMA3; |
| 10727 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10728 | DWConvMicrokernelTester() |
| 10729 | .cr(16) |
| 10730 | .kr(9) |
| 10731 | .channels(channels) |
| 10732 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10733 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10734 | } |
| 10735 | } |
| 10736 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10737 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10738 | TEST_REQUIRES_X86_FMA3; |
| 10739 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10740 | for (size_t step = 2; step <= 9; step++) { |
| 10741 | DWConvMicrokernelTester() |
| 10742 | .cr(16) |
| 10743 | .kr(9) |
| 10744 | .channels(channels) |
| 10745 | .width(3) |
| 10746 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10747 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10748 | } |
| 10749 | } |
| 10750 | } |
| 10751 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10752 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10753 | TEST_REQUIRES_X86_FMA3; |
| 10754 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10755 | DWConvMicrokernelTester() |
| 10756 | .cr(16) |
| 10757 | .kr(9) |
| 10758 | .channels(16) |
| 10759 | .width(5) |
| 10760 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10761 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10762 | } |
| 10763 | } |
| 10764 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10765 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10766 | TEST_REQUIRES_X86_FMA3; |
| 10767 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10768 | DWConvMicrokernelTester() |
| 10769 | .cr(16) |
| 10770 | .kr(9) |
| 10771 | .channels(channels) |
| 10772 | .width(3) |
| 10773 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10774 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10775 | } |
| 10776 | } |
| 10777 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10778 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10779 | TEST_REQUIRES_X86_FMA3; |
| 10780 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 10781 | DWConvMicrokernelTester() |
| 10782 | .cr(16) |
| 10783 | .kr(9) |
| 10784 | .channels(channels) |
| 10785 | .width(3) |
| 10786 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10787 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10788 | } |
| 10789 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 10790 | |
| 10791 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, input_offset) { |
| 10792 | TEST_REQUIRES_X86_FMA3; |
| 10793 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10794 | DWConvMicrokernelTester() |
| 10795 | .cr(16) |
| 10796 | .kr(9) |
| 10797 | .channels(channels) |
| 10798 | .input_offset(304) |
| 10799 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
| 10800 | } |
| 10801 | } |
| 10802 | |
| 10803 | TEST(F32_DWCONV_MINMAX_UP16X9__FMA3_ACC2, zero) { |
| 10804 | TEST_REQUIRES_X86_FMA3; |
| 10805 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 10806 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 10807 | DWConvMicrokernelTester() |
| 10808 | .cr(16) |
| 10809 | .kr(9) |
| 10810 | .channels(channels) |
| 10811 | .input_offset(304) |
| 10812 | .zero_index(mz) |
| 10813 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__fma3_acc2); |
| 10814 | } |
| 10815 | } |
| 10816 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10817 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 10818 | |
| 10819 | |
| 10820 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10821 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10822 | TEST_REQUIRES_X86_FMA3; |
| 10823 | DWConvMicrokernelTester() |
| 10824 | .cr(8) |
| 10825 | .kr(4) |
| 10826 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10827 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10828 | } |
| 10829 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10830 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10831 | TEST_REQUIRES_X86_FMA3; |
| 10832 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10833 | DWConvMicrokernelTester() |
| 10834 | .cr(8) |
| 10835 | .kr(4) |
| 10836 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10837 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10838 | } |
| 10839 | } |
| 10840 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10841 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10842 | TEST_REQUIRES_X86_FMA3; |
| 10843 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10844 | DWConvMicrokernelTester() |
| 10845 | .cr(8) |
| 10846 | .kr(4) |
| 10847 | .channels(channels) |
| 10848 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10849 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10850 | } |
| 10851 | } |
| 10852 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10853 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10854 | TEST_REQUIRES_X86_FMA3; |
| 10855 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10856 | DWConvMicrokernelTester() |
| 10857 | .cr(8) |
| 10858 | .kr(4) |
| 10859 | .channels(channels) |
| 10860 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10861 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10862 | } |
| 10863 | } |
| 10864 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10865 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10866 | TEST_REQUIRES_X86_FMA3; |
| 10867 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 10868 | DWConvMicrokernelTester() |
| 10869 | .cr(8) |
| 10870 | .kr(4) |
| 10871 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10872 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10873 | } |
| 10874 | } |
| 10875 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10876 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10877 | TEST_REQUIRES_X86_FMA3; |
| 10878 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10879 | DWConvMicrokernelTester() |
| 10880 | .cr(8) |
| 10881 | .kr(4) |
| 10882 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10883 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10884 | } |
| 10885 | } |
| 10886 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10887 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10888 | TEST_REQUIRES_X86_FMA3; |
| 10889 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10890 | DWConvMicrokernelTester() |
| 10891 | .cr(8) |
| 10892 | .kr(4) |
| 10893 | .channels(channels) |
| 10894 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10895 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10896 | } |
| 10897 | } |
| 10898 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10899 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10900 | TEST_REQUIRES_X86_FMA3; |
| 10901 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 10902 | DWConvMicrokernelTester() |
| 10903 | .cr(8) |
| 10904 | .kr(4) |
| 10905 | .channels(channels) |
| 10906 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10907 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10908 | } |
| 10909 | } |
| 10910 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10911 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10912 | TEST_REQUIRES_X86_FMA3; |
| 10913 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10914 | DWConvMicrokernelTester() |
| 10915 | .cr(8) |
| 10916 | .kr(4) |
| 10917 | .channels(channels) |
| 10918 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10919 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10920 | } |
| 10921 | } |
| 10922 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10923 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10924 | TEST_REQUIRES_X86_FMA3; |
| 10925 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10926 | for (size_t step = 2; step <= 4; step++) { |
| 10927 | DWConvMicrokernelTester() |
| 10928 | .cr(8) |
| 10929 | .kr(4) |
| 10930 | .channels(channels) |
| 10931 | .width(3) |
| 10932 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10933 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10934 | } |
| 10935 | } |
| 10936 | } |
| 10937 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10938 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10939 | TEST_REQUIRES_X86_FMA3; |
| 10940 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10941 | DWConvMicrokernelTester() |
| 10942 | .cr(8) |
| 10943 | .kr(4) |
| 10944 | .channels(8) |
| 10945 | .width(5) |
| 10946 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10947 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10948 | } |
| 10949 | } |
| 10950 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10951 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10952 | TEST_REQUIRES_X86_FMA3; |
| 10953 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10954 | DWConvMicrokernelTester() |
| 10955 | .cr(8) |
| 10956 | .kr(4) |
| 10957 | .channels(channels) |
| 10958 | .width(3) |
| 10959 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10960 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10961 | } |
| 10962 | } |
| 10963 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10964 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10965 | TEST_REQUIRES_X86_FMA3; |
| 10966 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 10967 | DWConvMicrokernelTester() |
| 10968 | .cr(8) |
| 10969 | .kr(4) |
| 10970 | .channels(channels) |
| 10971 | .width(3) |
| 10972 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 10973 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 10974 | } |
| 10975 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 10976 | |
| 10977 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, input_offset) { |
| 10978 | TEST_REQUIRES_X86_FMA3; |
| 10979 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10980 | DWConvMicrokernelTester() |
| 10981 | .cr(8) |
| 10982 | .kr(4) |
| 10983 | .channels(channels) |
| 10984 | .input_offset(176) |
| 10985 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
| 10986 | } |
| 10987 | } |
| 10988 | |
| 10989 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3, zero) { |
| 10990 | TEST_REQUIRES_X86_FMA3; |
| 10991 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 10992 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 10993 | DWConvMicrokernelTester() |
| 10994 | .cr(8) |
| 10995 | .kr(4) |
| 10996 | .channels(channels) |
| 10997 | .input_offset(176) |
| 10998 | .zero_index(mz) |
| 10999 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3); |
| 11000 | } |
| 11001 | } |
| 11002 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11003 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 11004 | |
| 11005 | |
| 11006 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11007 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11008 | TEST_REQUIRES_X86_FMA3; |
| 11009 | DWConvMicrokernelTester() |
| 11010 | .cr(8) |
| 11011 | .kr(4) |
| 11012 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11013 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11014 | } |
| 11015 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11016 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11017 | TEST_REQUIRES_X86_FMA3; |
| 11018 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 11019 | DWConvMicrokernelTester() |
| 11020 | .cr(8) |
| 11021 | .kr(4) |
| 11022 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11023 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11024 | } |
| 11025 | } |
| 11026 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11027 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11028 | TEST_REQUIRES_X86_FMA3; |
| 11029 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 11030 | DWConvMicrokernelTester() |
| 11031 | .cr(8) |
| 11032 | .kr(4) |
| 11033 | .channels(channels) |
| 11034 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11035 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11036 | } |
| 11037 | } |
| 11038 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11039 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11040 | TEST_REQUIRES_X86_FMA3; |
| 11041 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 11042 | DWConvMicrokernelTester() |
| 11043 | .cr(8) |
| 11044 | .kr(4) |
| 11045 | .channels(channels) |
| 11046 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11047 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11048 | } |
| 11049 | } |
| 11050 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11051 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11052 | TEST_REQUIRES_X86_FMA3; |
| 11053 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 11054 | DWConvMicrokernelTester() |
| 11055 | .cr(8) |
| 11056 | .kr(4) |
| 11057 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11058 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11059 | } |
| 11060 | } |
| 11061 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11062 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11063 | TEST_REQUIRES_X86_FMA3; |
| 11064 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 11065 | DWConvMicrokernelTester() |
| 11066 | .cr(8) |
| 11067 | .kr(4) |
| 11068 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11069 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11070 | } |
| 11071 | } |
| 11072 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11073 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11074 | TEST_REQUIRES_X86_FMA3; |
| 11075 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 11076 | DWConvMicrokernelTester() |
| 11077 | .cr(8) |
| 11078 | .kr(4) |
| 11079 | .channels(channels) |
| 11080 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11081 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11082 | } |
| 11083 | } |
| 11084 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11085 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11086 | TEST_REQUIRES_X86_FMA3; |
| 11087 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 11088 | DWConvMicrokernelTester() |
| 11089 | .cr(8) |
| 11090 | .kr(4) |
| 11091 | .channels(channels) |
| 11092 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11093 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11094 | } |
| 11095 | } |
| 11096 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11097 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11098 | TEST_REQUIRES_X86_FMA3; |
| 11099 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 11100 | DWConvMicrokernelTester() |
| 11101 | .cr(8) |
| 11102 | .kr(4) |
| 11103 | .channels(channels) |
| 11104 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11105 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11106 | } |
| 11107 | } |
| 11108 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11109 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11110 | TEST_REQUIRES_X86_FMA3; |
| 11111 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 11112 | for (size_t step = 2; step <= 4; step++) { |
| 11113 | DWConvMicrokernelTester() |
| 11114 | .cr(8) |
| 11115 | .kr(4) |
| 11116 | .channels(channels) |
| 11117 | .width(3) |
| 11118 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11119 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11120 | } |
| 11121 | } |
| 11122 | } |
| 11123 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11124 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11125 | TEST_REQUIRES_X86_FMA3; |
| 11126 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 11127 | DWConvMicrokernelTester() |
| 11128 | .cr(8) |
| 11129 | .kr(4) |
| 11130 | .channels(8) |
| 11131 | .width(5) |
| 11132 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11133 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11134 | } |
| 11135 | } |
| 11136 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11137 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11138 | TEST_REQUIRES_X86_FMA3; |
| 11139 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 11140 | DWConvMicrokernelTester() |
| 11141 | .cr(8) |
| 11142 | .kr(4) |
| 11143 | .channels(channels) |
| 11144 | .width(3) |
| 11145 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11146 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11147 | } |
| 11148 | } |
| 11149 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11150 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11151 | TEST_REQUIRES_X86_FMA3; |
| 11152 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 11153 | DWConvMicrokernelTester() |
| 11154 | .cr(8) |
| 11155 | .kr(4) |
| 11156 | .channels(channels) |
| 11157 | .width(3) |
| 11158 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11159 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11160 | } |
| 11161 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 11162 | |
| 11163 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, input_offset) { |
| 11164 | TEST_REQUIRES_X86_FMA3; |
| 11165 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 11166 | DWConvMicrokernelTester() |
| 11167 | .cr(8) |
| 11168 | .kr(4) |
| 11169 | .channels(channels) |
| 11170 | .input_offset(176) |
| 11171 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
| 11172 | } |
| 11173 | } |
| 11174 | |
| 11175 | TEST(F32_DWCONV_MINMAX_UP8X4__FMA3_ACC2, zero) { |
| 11176 | TEST_REQUIRES_X86_FMA3; |
| 11177 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 11178 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 11179 | DWConvMicrokernelTester() |
| 11180 | .cr(8) |
| 11181 | .kr(4) |
| 11182 | .channels(channels) |
| 11183 | .input_offset(176) |
| 11184 | .zero_index(mz) |
| 11185 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__fma3_acc2); |
| 11186 | } |
| 11187 | } |
| 11188 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11189 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 11190 | |
| 11191 | |
| 11192 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11193 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11194 | TEST_REQUIRES_X86_FMA3; |
| 11195 | DWConvMicrokernelTester() |
| 11196 | .cr(16) |
| 11197 | .kr(4) |
| 11198 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11199 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11200 | } |
| 11201 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11202 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11203 | TEST_REQUIRES_X86_FMA3; |
| 11204 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11205 | DWConvMicrokernelTester() |
| 11206 | .cr(16) |
| 11207 | .kr(4) |
| 11208 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11209 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11210 | } |
| 11211 | } |
| 11212 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11213 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11214 | TEST_REQUIRES_X86_FMA3; |
| 11215 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11216 | DWConvMicrokernelTester() |
| 11217 | .cr(16) |
| 11218 | .kr(4) |
| 11219 | .channels(channels) |
| 11220 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11221 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11222 | } |
| 11223 | } |
| 11224 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11225 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11226 | TEST_REQUIRES_X86_FMA3; |
| 11227 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11228 | DWConvMicrokernelTester() |
| 11229 | .cr(16) |
| 11230 | .kr(4) |
| 11231 | .channels(channels) |
| 11232 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11233 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11234 | } |
| 11235 | } |
| 11236 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11237 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11238 | TEST_REQUIRES_X86_FMA3; |
| 11239 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 11240 | DWConvMicrokernelTester() |
| 11241 | .cr(16) |
| 11242 | .kr(4) |
| 11243 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11244 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11245 | } |
| 11246 | } |
| 11247 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11248 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11249 | TEST_REQUIRES_X86_FMA3; |
| 11250 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11251 | DWConvMicrokernelTester() |
| 11252 | .cr(16) |
| 11253 | .kr(4) |
| 11254 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11255 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11256 | } |
| 11257 | } |
| 11258 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11259 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11260 | TEST_REQUIRES_X86_FMA3; |
| 11261 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11262 | DWConvMicrokernelTester() |
| 11263 | .cr(16) |
| 11264 | .kr(4) |
| 11265 | .channels(channels) |
| 11266 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11267 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11268 | } |
| 11269 | } |
| 11270 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11271 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11272 | TEST_REQUIRES_X86_FMA3; |
| 11273 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11274 | DWConvMicrokernelTester() |
| 11275 | .cr(16) |
| 11276 | .kr(4) |
| 11277 | .channels(channels) |
| 11278 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11279 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11280 | } |
| 11281 | } |
| 11282 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11283 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11284 | TEST_REQUIRES_X86_FMA3; |
| 11285 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11286 | DWConvMicrokernelTester() |
| 11287 | .cr(16) |
| 11288 | .kr(4) |
| 11289 | .channels(channels) |
| 11290 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11291 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11292 | } |
| 11293 | } |
| 11294 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11295 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11296 | TEST_REQUIRES_X86_FMA3; |
| 11297 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11298 | for (size_t step = 2; step <= 4; step++) { |
| 11299 | DWConvMicrokernelTester() |
| 11300 | .cr(16) |
| 11301 | .kr(4) |
| 11302 | .channels(channels) |
| 11303 | .width(3) |
| 11304 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11305 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11306 | } |
| 11307 | } |
| 11308 | } |
| 11309 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11310 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11311 | TEST_REQUIRES_X86_FMA3; |
| 11312 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11313 | DWConvMicrokernelTester() |
| 11314 | .cr(16) |
| 11315 | .kr(4) |
| 11316 | .channels(16) |
| 11317 | .width(5) |
| 11318 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11319 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11320 | } |
| 11321 | } |
| 11322 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11323 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11324 | TEST_REQUIRES_X86_FMA3; |
| 11325 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11326 | DWConvMicrokernelTester() |
| 11327 | .cr(16) |
| 11328 | .kr(4) |
| 11329 | .channels(channels) |
| 11330 | .width(3) |
| 11331 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11332 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11333 | } |
| 11334 | } |
| 11335 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11336 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11337 | TEST_REQUIRES_X86_FMA3; |
| 11338 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11339 | DWConvMicrokernelTester() |
| 11340 | .cr(16) |
| 11341 | .kr(4) |
| 11342 | .channels(channels) |
| 11343 | .width(3) |
| 11344 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11345 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11346 | } |
| 11347 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 11348 | |
| 11349 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, input_offset) { |
| 11350 | TEST_REQUIRES_X86_FMA3; |
| 11351 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11352 | DWConvMicrokernelTester() |
| 11353 | .cr(16) |
| 11354 | .kr(4) |
| 11355 | .channels(channels) |
| 11356 | .input_offset(304) |
| 11357 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
| 11358 | } |
| 11359 | } |
| 11360 | |
| 11361 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3, zero) { |
| 11362 | TEST_REQUIRES_X86_FMA3; |
| 11363 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 11364 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11365 | DWConvMicrokernelTester() |
| 11366 | .cr(16) |
| 11367 | .kr(4) |
| 11368 | .channels(channels) |
| 11369 | .input_offset(304) |
| 11370 | .zero_index(mz) |
| 11371 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3); |
| 11372 | } |
| 11373 | } |
| 11374 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11375 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 11376 | |
| 11377 | |
| 11378 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11379 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11380 | TEST_REQUIRES_X86_FMA3; |
| 11381 | DWConvMicrokernelTester() |
| 11382 | .cr(16) |
| 11383 | .kr(4) |
| 11384 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11385 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11386 | } |
| 11387 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11388 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11389 | TEST_REQUIRES_X86_FMA3; |
| 11390 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11391 | DWConvMicrokernelTester() |
| 11392 | .cr(16) |
| 11393 | .kr(4) |
| 11394 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11395 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11396 | } |
| 11397 | } |
| 11398 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11399 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11400 | TEST_REQUIRES_X86_FMA3; |
| 11401 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11402 | DWConvMicrokernelTester() |
| 11403 | .cr(16) |
| 11404 | .kr(4) |
| 11405 | .channels(channels) |
| 11406 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11407 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11408 | } |
| 11409 | } |
| 11410 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11411 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11412 | TEST_REQUIRES_X86_FMA3; |
| 11413 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11414 | DWConvMicrokernelTester() |
| 11415 | .cr(16) |
| 11416 | .kr(4) |
| 11417 | .channels(channels) |
| 11418 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11419 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11420 | } |
| 11421 | } |
| 11422 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11423 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11424 | TEST_REQUIRES_X86_FMA3; |
| 11425 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 11426 | DWConvMicrokernelTester() |
| 11427 | .cr(16) |
| 11428 | .kr(4) |
| 11429 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11430 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11431 | } |
| 11432 | } |
| 11433 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11434 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11435 | TEST_REQUIRES_X86_FMA3; |
| 11436 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11437 | DWConvMicrokernelTester() |
| 11438 | .cr(16) |
| 11439 | .kr(4) |
| 11440 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11441 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11442 | } |
| 11443 | } |
| 11444 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11445 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11446 | TEST_REQUIRES_X86_FMA3; |
| 11447 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11448 | DWConvMicrokernelTester() |
| 11449 | .cr(16) |
| 11450 | .kr(4) |
| 11451 | .channels(channels) |
| 11452 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11453 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11454 | } |
| 11455 | } |
| 11456 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11457 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11458 | TEST_REQUIRES_X86_FMA3; |
| 11459 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11460 | DWConvMicrokernelTester() |
| 11461 | .cr(16) |
| 11462 | .kr(4) |
| 11463 | .channels(channels) |
| 11464 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11465 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11466 | } |
| 11467 | } |
| 11468 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11469 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11470 | TEST_REQUIRES_X86_FMA3; |
| 11471 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11472 | DWConvMicrokernelTester() |
| 11473 | .cr(16) |
| 11474 | .kr(4) |
| 11475 | .channels(channels) |
| 11476 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11477 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11478 | } |
| 11479 | } |
| 11480 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11481 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11482 | TEST_REQUIRES_X86_FMA3; |
| 11483 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11484 | for (size_t step = 2; step <= 4; step++) { |
| 11485 | DWConvMicrokernelTester() |
| 11486 | .cr(16) |
| 11487 | .kr(4) |
| 11488 | .channels(channels) |
| 11489 | .width(3) |
| 11490 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11491 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11492 | } |
| 11493 | } |
| 11494 | } |
| 11495 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11496 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11497 | TEST_REQUIRES_X86_FMA3; |
| 11498 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11499 | DWConvMicrokernelTester() |
| 11500 | .cr(16) |
| 11501 | .kr(4) |
| 11502 | .channels(16) |
| 11503 | .width(5) |
| 11504 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11505 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11506 | } |
| 11507 | } |
| 11508 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11509 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11510 | TEST_REQUIRES_X86_FMA3; |
| 11511 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11512 | DWConvMicrokernelTester() |
| 11513 | .cr(16) |
| 11514 | .kr(4) |
| 11515 | .channels(channels) |
| 11516 | .width(3) |
| 11517 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11518 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11519 | } |
| 11520 | } |
| 11521 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11522 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11523 | TEST_REQUIRES_X86_FMA3; |
| 11524 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11525 | DWConvMicrokernelTester() |
| 11526 | .cr(16) |
| 11527 | .kr(4) |
| 11528 | .channels(channels) |
| 11529 | .width(3) |
| 11530 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11531 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11532 | } |
| 11533 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 11534 | |
| 11535 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, input_offset) { |
| 11536 | TEST_REQUIRES_X86_FMA3; |
| 11537 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11538 | DWConvMicrokernelTester() |
| 11539 | .cr(16) |
| 11540 | .kr(4) |
| 11541 | .channels(channels) |
| 11542 | .input_offset(304) |
| 11543 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
| 11544 | } |
| 11545 | } |
| 11546 | |
| 11547 | TEST(F32_DWCONV_MINMAX_UP16X4__FMA3_ACC2, zero) { |
| 11548 | TEST_REQUIRES_X86_FMA3; |
| 11549 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 11550 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11551 | DWConvMicrokernelTester() |
| 11552 | .cr(16) |
| 11553 | .kr(4) |
| 11554 | .channels(channels) |
| 11555 | .input_offset(304) |
| 11556 | .zero_index(mz) |
| 11557 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__fma3_acc2); |
| 11558 | } |
| 11559 | } |
| 11560 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11561 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 11562 | |
| 11563 | |
| 11564 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11565 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11566 | TEST_REQUIRES_X86_AVX512F; |
| 11567 | DWConvMicrokernelTester() |
| 11568 | .cr(16) |
| 11569 | .kr(25) |
| 11570 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11571 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11572 | } |
| 11573 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11574 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11575 | TEST_REQUIRES_X86_AVX512F; |
| 11576 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11577 | DWConvMicrokernelTester() |
| 11578 | .cr(16) |
| 11579 | .kr(25) |
| 11580 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11581 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11582 | } |
| 11583 | } |
| 11584 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11585 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11586 | TEST_REQUIRES_X86_AVX512F; |
| 11587 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11588 | DWConvMicrokernelTester() |
| 11589 | .cr(16) |
| 11590 | .kr(25) |
| 11591 | .channels(channels) |
| 11592 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11593 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11594 | } |
| 11595 | } |
| 11596 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11597 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11598 | TEST_REQUIRES_X86_AVX512F; |
| 11599 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11600 | DWConvMicrokernelTester() |
| 11601 | .cr(16) |
| 11602 | .kr(25) |
| 11603 | .channels(channels) |
| 11604 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11605 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11606 | } |
| 11607 | } |
| 11608 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11609 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11610 | TEST_REQUIRES_X86_AVX512F; |
| 11611 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 11612 | DWConvMicrokernelTester() |
| 11613 | .cr(16) |
| 11614 | .kr(25) |
| 11615 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11616 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11617 | } |
| 11618 | } |
| 11619 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11620 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11621 | TEST_REQUIRES_X86_AVX512F; |
| 11622 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11623 | DWConvMicrokernelTester() |
| 11624 | .cr(16) |
| 11625 | .kr(25) |
| 11626 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11627 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11628 | } |
| 11629 | } |
| 11630 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11631 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11632 | TEST_REQUIRES_X86_AVX512F; |
| 11633 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11634 | DWConvMicrokernelTester() |
| 11635 | .cr(16) |
| 11636 | .kr(25) |
| 11637 | .channels(channels) |
| 11638 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11639 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11640 | } |
| 11641 | } |
| 11642 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11643 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11644 | TEST_REQUIRES_X86_AVX512F; |
| 11645 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11646 | DWConvMicrokernelTester() |
| 11647 | .cr(16) |
| 11648 | .kr(25) |
| 11649 | .channels(channels) |
| 11650 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11651 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11652 | } |
| 11653 | } |
| 11654 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11655 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11656 | TEST_REQUIRES_X86_AVX512F; |
| 11657 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11658 | DWConvMicrokernelTester() |
| 11659 | .cr(16) |
| 11660 | .kr(25) |
| 11661 | .channels(channels) |
| 11662 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11663 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11664 | } |
| 11665 | } |
| 11666 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11667 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11668 | TEST_REQUIRES_X86_AVX512F; |
| 11669 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11670 | for (size_t step = 2; step <= 25; step++) { |
| 11671 | DWConvMicrokernelTester() |
| 11672 | .cr(16) |
| 11673 | .kr(25) |
| 11674 | .channels(channels) |
| 11675 | .width(3) |
| 11676 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11677 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11678 | } |
| 11679 | } |
| 11680 | } |
| 11681 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11682 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11683 | TEST_REQUIRES_X86_AVX512F; |
| 11684 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11685 | DWConvMicrokernelTester() |
| 11686 | .cr(16) |
| 11687 | .kr(25) |
| 11688 | .channels(16) |
| 11689 | .width(5) |
| 11690 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11691 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11692 | } |
| 11693 | } |
| 11694 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11695 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11696 | TEST_REQUIRES_X86_AVX512F; |
| 11697 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11698 | DWConvMicrokernelTester() |
| 11699 | .cr(16) |
| 11700 | .kr(25) |
| 11701 | .channels(channels) |
| 11702 | .width(3) |
| 11703 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11704 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11705 | } |
| 11706 | } |
| 11707 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11708 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11709 | TEST_REQUIRES_X86_AVX512F; |
| 11710 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11711 | DWConvMicrokernelTester() |
| 11712 | .cr(16) |
| 11713 | .kr(25) |
| 11714 | .channels(channels) |
| 11715 | .width(3) |
| 11716 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11717 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11718 | } |
| 11719 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 11720 | |
| 11721 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, input_offset) { |
| 11722 | TEST_REQUIRES_X86_AVX512F; |
| 11723 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11724 | DWConvMicrokernelTester() |
| 11725 | .cr(16) |
| 11726 | .kr(25) |
| 11727 | .channels(channels) |
| 11728 | .input_offset(304) |
| 11729 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
| 11730 | } |
| 11731 | } |
| 11732 | |
| 11733 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F, zero) { |
| 11734 | TEST_REQUIRES_X86_AVX512F; |
| 11735 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 11736 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11737 | DWConvMicrokernelTester() |
| 11738 | .cr(16) |
| 11739 | .kr(25) |
| 11740 | .channels(channels) |
| 11741 | .input_offset(304) |
| 11742 | .zero_index(mz) |
| 11743 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f); |
| 11744 | } |
| 11745 | } |
| 11746 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11747 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 11748 | |
| 11749 | |
| 11750 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11751 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11752 | TEST_REQUIRES_X86_AVX512F; |
| 11753 | DWConvMicrokernelTester() |
| 11754 | .cr(16) |
| 11755 | .kr(25) |
| 11756 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11757 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11758 | } |
| 11759 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11760 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11761 | TEST_REQUIRES_X86_AVX512F; |
| 11762 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11763 | DWConvMicrokernelTester() |
| 11764 | .cr(16) |
| 11765 | .kr(25) |
| 11766 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11767 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11768 | } |
| 11769 | } |
| 11770 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11771 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11772 | TEST_REQUIRES_X86_AVX512F; |
| 11773 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11774 | DWConvMicrokernelTester() |
| 11775 | .cr(16) |
| 11776 | .kr(25) |
| 11777 | .channels(channels) |
| 11778 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11779 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11780 | } |
| 11781 | } |
| 11782 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11783 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11784 | TEST_REQUIRES_X86_AVX512F; |
| 11785 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11786 | DWConvMicrokernelTester() |
| 11787 | .cr(16) |
| 11788 | .kr(25) |
| 11789 | .channels(channels) |
| 11790 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11791 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11792 | } |
| 11793 | } |
| 11794 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11795 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11796 | TEST_REQUIRES_X86_AVX512F; |
| 11797 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 11798 | DWConvMicrokernelTester() |
| 11799 | .cr(16) |
| 11800 | .kr(25) |
| 11801 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11802 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11803 | } |
| 11804 | } |
| 11805 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11806 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11807 | TEST_REQUIRES_X86_AVX512F; |
| 11808 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11809 | DWConvMicrokernelTester() |
| 11810 | .cr(16) |
| 11811 | .kr(25) |
| 11812 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11813 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11814 | } |
| 11815 | } |
| 11816 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11817 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11818 | TEST_REQUIRES_X86_AVX512F; |
| 11819 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11820 | DWConvMicrokernelTester() |
| 11821 | .cr(16) |
| 11822 | .kr(25) |
| 11823 | .channels(channels) |
| 11824 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11825 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11826 | } |
| 11827 | } |
| 11828 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11829 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11830 | TEST_REQUIRES_X86_AVX512F; |
| 11831 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 11832 | DWConvMicrokernelTester() |
| 11833 | .cr(16) |
| 11834 | .kr(25) |
| 11835 | .channels(channels) |
| 11836 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11837 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11838 | } |
| 11839 | } |
| 11840 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11841 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11842 | TEST_REQUIRES_X86_AVX512F; |
| 11843 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11844 | DWConvMicrokernelTester() |
| 11845 | .cr(16) |
| 11846 | .kr(25) |
| 11847 | .channels(channels) |
| 11848 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11849 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11850 | } |
| 11851 | } |
| 11852 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11853 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11854 | TEST_REQUIRES_X86_AVX512F; |
| 11855 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11856 | for (size_t step = 2; step <= 25; step++) { |
| 11857 | DWConvMicrokernelTester() |
| 11858 | .cr(16) |
| 11859 | .kr(25) |
| 11860 | .channels(channels) |
| 11861 | .width(3) |
| 11862 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11863 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11864 | } |
| 11865 | } |
| 11866 | } |
| 11867 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11868 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11869 | TEST_REQUIRES_X86_AVX512F; |
| 11870 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11871 | DWConvMicrokernelTester() |
| 11872 | .cr(16) |
| 11873 | .kr(25) |
| 11874 | .channels(16) |
| 11875 | .width(5) |
| 11876 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11877 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11878 | } |
| 11879 | } |
| 11880 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11881 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11882 | TEST_REQUIRES_X86_AVX512F; |
| 11883 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11884 | DWConvMicrokernelTester() |
| 11885 | .cr(16) |
| 11886 | .kr(25) |
| 11887 | .channels(channels) |
| 11888 | .width(3) |
| 11889 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11890 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11891 | } |
| 11892 | } |
| 11893 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11894 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11895 | TEST_REQUIRES_X86_AVX512F; |
| 11896 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 11897 | DWConvMicrokernelTester() |
| 11898 | .cr(16) |
| 11899 | .kr(25) |
| 11900 | .channels(channels) |
| 11901 | .width(3) |
| 11902 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11903 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11904 | } |
| 11905 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 11906 | |
| 11907 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, input_offset) { |
| 11908 | TEST_REQUIRES_X86_AVX512F; |
| 11909 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11910 | DWConvMicrokernelTester() |
| 11911 | .cr(16) |
| 11912 | .kr(25) |
| 11913 | .channels(channels) |
| 11914 | .input_offset(304) |
| 11915 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
| 11916 | } |
| 11917 | } |
| 11918 | |
| 11919 | TEST(F32_DWCONV_MINMAX_UP16X25__AVX512F_ACC2, zero) { |
| 11920 | TEST_REQUIRES_X86_AVX512F; |
| 11921 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 11922 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 11923 | DWConvMicrokernelTester() |
| 11924 | .cr(16) |
| 11925 | .kr(25) |
| 11926 | .channels(channels) |
| 11927 | .input_offset(304) |
| 11928 | .zero_index(mz) |
| 11929 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x25__avx512f_acc2); |
| 11930 | } |
| 11931 | } |
| 11932 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11933 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 11934 | |
| 11935 | |
| 11936 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11937 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_eq_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11938 | TEST_REQUIRES_X86_AVX512F; |
| 11939 | DWConvMicrokernelTester() |
| 11940 | .cr(32) |
| 11941 | .kr(25) |
| 11942 | .channels(32) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11943 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11944 | } |
| 11945 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11946 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_div_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11947 | TEST_REQUIRES_X86_AVX512F; |
| 11948 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 11949 | DWConvMicrokernelTester() |
| 11950 | .cr(32) |
| 11951 | .kr(25) |
| 11952 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11953 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11954 | } |
| 11955 | } |
| 11956 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11957 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_div_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11958 | TEST_REQUIRES_X86_AVX512F; |
| 11959 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 11960 | DWConvMicrokernelTester() |
| 11961 | .cr(32) |
| 11962 | .kr(25) |
| 11963 | .channels(channels) |
| 11964 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11965 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11966 | } |
| 11967 | } |
| 11968 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11969 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_div_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11970 | TEST_REQUIRES_X86_AVX512F; |
| 11971 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 11972 | DWConvMicrokernelTester() |
| 11973 | .cr(32) |
| 11974 | .kr(25) |
| 11975 | .channels(channels) |
| 11976 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11977 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11978 | } |
| 11979 | } |
| 11980 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11981 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_lt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11982 | TEST_REQUIRES_X86_AVX512F; |
| 11983 | for (uint32_t channels = 1; channels < 32; channels++) { |
| 11984 | DWConvMicrokernelTester() |
| 11985 | .cr(32) |
| 11986 | .kr(25) |
| 11987 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11988 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11989 | } |
| 11990 | } |
| 11991 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11992 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_gt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 11993 | TEST_REQUIRES_X86_AVX512F; |
| 11994 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 11995 | DWConvMicrokernelTester() |
| 11996 | .cr(32) |
| 11997 | .kr(25) |
| 11998 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 11999 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12000 | } |
| 12001 | } |
| 12002 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12003 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_gt_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12004 | TEST_REQUIRES_X86_AVX512F; |
| 12005 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12006 | DWConvMicrokernelTester() |
| 12007 | .cr(32) |
| 12008 | .kr(25) |
| 12009 | .channels(channels) |
| 12010 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12011 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12012 | } |
| 12013 | } |
| 12014 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12015 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, c_gt_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12016 | TEST_REQUIRES_X86_AVX512F; |
| 12017 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12018 | DWConvMicrokernelTester() |
| 12019 | .cr(32) |
| 12020 | .kr(25) |
| 12021 | .channels(channels) |
| 12022 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12023 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12024 | } |
| 12025 | } |
| 12026 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12027 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12028 | TEST_REQUIRES_X86_AVX512F; |
| 12029 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12030 | DWConvMicrokernelTester() |
| 12031 | .cr(32) |
| 12032 | .kr(25) |
| 12033 | .channels(channels) |
| 12034 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12035 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12036 | } |
| 12037 | } |
| 12038 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12039 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12040 | TEST_REQUIRES_X86_AVX512F; |
| 12041 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12042 | for (size_t step = 2; step <= 25; step++) { |
| 12043 | DWConvMicrokernelTester() |
| 12044 | .cr(32) |
| 12045 | .kr(25) |
| 12046 | .channels(channels) |
| 12047 | .width(3) |
| 12048 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12049 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12050 | } |
| 12051 | } |
| 12052 | } |
| 12053 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12054 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12055 | TEST_REQUIRES_X86_AVX512F; |
| 12056 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12057 | DWConvMicrokernelTester() |
| 12058 | .cr(32) |
| 12059 | .kr(25) |
| 12060 | .channels(32) |
| 12061 | .width(5) |
| 12062 | .output_stride(163) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12063 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12064 | } |
| 12065 | } |
| 12066 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12067 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12068 | TEST_REQUIRES_X86_AVX512F; |
| 12069 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12070 | DWConvMicrokernelTester() |
| 12071 | .cr(32) |
| 12072 | .kr(25) |
| 12073 | .channels(channels) |
| 12074 | .width(3) |
| 12075 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12076 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12077 | } |
| 12078 | } |
| 12079 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12080 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12081 | TEST_REQUIRES_X86_AVX512F; |
| 12082 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12083 | DWConvMicrokernelTester() |
| 12084 | .cr(32) |
| 12085 | .kr(25) |
| 12086 | .channels(channels) |
| 12087 | .width(3) |
| 12088 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12089 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12090 | } |
| 12091 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 12092 | |
| 12093 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, input_offset) { |
| 12094 | TEST_REQUIRES_X86_AVX512F; |
| 12095 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12096 | DWConvMicrokernelTester() |
| 12097 | .cr(32) |
| 12098 | .kr(25) |
| 12099 | .channels(channels) |
| 12100 | .input_offset(592) |
| 12101 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
| 12102 | } |
| 12103 | } |
| 12104 | |
| 12105 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F, zero) { |
| 12106 | TEST_REQUIRES_X86_AVX512F; |
| 12107 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 12108 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12109 | DWConvMicrokernelTester() |
| 12110 | .cr(32) |
| 12111 | .kr(25) |
| 12112 | .channels(channels) |
| 12113 | .input_offset(592) |
| 12114 | .zero_index(mz) |
| 12115 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f); |
| 12116 | } |
| 12117 | } |
| 12118 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12119 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 12120 | |
| 12121 | |
| 12122 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12123 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_eq_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12124 | TEST_REQUIRES_X86_AVX512F; |
| 12125 | DWConvMicrokernelTester() |
| 12126 | .cr(32) |
| 12127 | .kr(25) |
| 12128 | .channels(32) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12129 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12130 | } |
| 12131 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12132 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_div_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12133 | TEST_REQUIRES_X86_AVX512F; |
| 12134 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12135 | DWConvMicrokernelTester() |
| 12136 | .cr(32) |
| 12137 | .kr(25) |
| 12138 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12139 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12140 | } |
| 12141 | } |
| 12142 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12143 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_div_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12144 | TEST_REQUIRES_X86_AVX512F; |
| 12145 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12146 | DWConvMicrokernelTester() |
| 12147 | .cr(32) |
| 12148 | .kr(25) |
| 12149 | .channels(channels) |
| 12150 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12151 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12152 | } |
| 12153 | } |
| 12154 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12155 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_div_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12156 | TEST_REQUIRES_X86_AVX512F; |
| 12157 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12158 | DWConvMicrokernelTester() |
| 12159 | .cr(32) |
| 12160 | .kr(25) |
| 12161 | .channels(channels) |
| 12162 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12163 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12164 | } |
| 12165 | } |
| 12166 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12167 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_lt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12168 | TEST_REQUIRES_X86_AVX512F; |
| 12169 | for (uint32_t channels = 1; channels < 32; channels++) { |
| 12170 | DWConvMicrokernelTester() |
| 12171 | .cr(32) |
| 12172 | .kr(25) |
| 12173 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12174 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12175 | } |
| 12176 | } |
| 12177 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12178 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_gt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12179 | TEST_REQUIRES_X86_AVX512F; |
| 12180 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12181 | DWConvMicrokernelTester() |
| 12182 | .cr(32) |
| 12183 | .kr(25) |
| 12184 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12185 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12186 | } |
| 12187 | } |
| 12188 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12189 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_gt_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12190 | TEST_REQUIRES_X86_AVX512F; |
| 12191 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12192 | DWConvMicrokernelTester() |
| 12193 | .cr(32) |
| 12194 | .kr(25) |
| 12195 | .channels(channels) |
| 12196 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12197 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12198 | } |
| 12199 | } |
| 12200 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12201 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, c_gt_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12202 | TEST_REQUIRES_X86_AVX512F; |
| 12203 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12204 | DWConvMicrokernelTester() |
| 12205 | .cr(32) |
| 12206 | .kr(25) |
| 12207 | .channels(channels) |
| 12208 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12209 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12210 | } |
| 12211 | } |
| 12212 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12213 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12214 | TEST_REQUIRES_X86_AVX512F; |
| 12215 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12216 | DWConvMicrokernelTester() |
| 12217 | .cr(32) |
| 12218 | .kr(25) |
| 12219 | .channels(channels) |
| 12220 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12221 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12222 | } |
| 12223 | } |
| 12224 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12225 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12226 | TEST_REQUIRES_X86_AVX512F; |
| 12227 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12228 | for (size_t step = 2; step <= 25; step++) { |
| 12229 | DWConvMicrokernelTester() |
| 12230 | .cr(32) |
| 12231 | .kr(25) |
| 12232 | .channels(channels) |
| 12233 | .width(3) |
| 12234 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12235 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12236 | } |
| 12237 | } |
| 12238 | } |
| 12239 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12240 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12241 | TEST_REQUIRES_X86_AVX512F; |
| 12242 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12243 | DWConvMicrokernelTester() |
| 12244 | .cr(32) |
| 12245 | .kr(25) |
| 12246 | .channels(32) |
| 12247 | .width(5) |
| 12248 | .output_stride(163) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12249 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12250 | } |
| 12251 | } |
| 12252 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12253 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12254 | TEST_REQUIRES_X86_AVX512F; |
| 12255 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12256 | DWConvMicrokernelTester() |
| 12257 | .cr(32) |
| 12258 | .kr(25) |
| 12259 | .channels(channels) |
| 12260 | .width(3) |
| 12261 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12262 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12263 | } |
| 12264 | } |
| 12265 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12266 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12267 | TEST_REQUIRES_X86_AVX512F; |
| 12268 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12269 | DWConvMicrokernelTester() |
| 12270 | .cr(32) |
| 12271 | .kr(25) |
| 12272 | .channels(channels) |
| 12273 | .width(3) |
| 12274 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12275 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12276 | } |
| 12277 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 12278 | |
| 12279 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, input_offset) { |
| 12280 | TEST_REQUIRES_X86_AVX512F; |
| 12281 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12282 | DWConvMicrokernelTester() |
| 12283 | .cr(32) |
| 12284 | .kr(25) |
| 12285 | .channels(channels) |
| 12286 | .input_offset(592) |
| 12287 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
| 12288 | } |
| 12289 | } |
| 12290 | |
| 12291 | TEST(F32_DWCONV_MINMAX_UP32X25__AVX512F_ACC2, zero) { |
| 12292 | TEST_REQUIRES_X86_AVX512F; |
| 12293 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 12294 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12295 | DWConvMicrokernelTester() |
| 12296 | .cr(32) |
| 12297 | .kr(25) |
| 12298 | .channels(channels) |
| 12299 | .input_offset(592) |
| 12300 | .zero_index(mz) |
| 12301 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x25__avx512f_acc2); |
| 12302 | } |
| 12303 | } |
| 12304 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12305 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 12306 | |
| 12307 | |
| 12308 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12309 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12310 | TEST_REQUIRES_X86_AVX512F; |
| 12311 | DWConvMicrokernelTester() |
| 12312 | .cr(16) |
| 12313 | .kr(9) |
| 12314 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12315 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12316 | } |
| 12317 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12318 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12319 | TEST_REQUIRES_X86_AVX512F; |
| 12320 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12321 | DWConvMicrokernelTester() |
| 12322 | .cr(16) |
| 12323 | .kr(9) |
| 12324 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12325 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12326 | } |
| 12327 | } |
| 12328 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12329 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12330 | TEST_REQUIRES_X86_AVX512F; |
| 12331 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12332 | DWConvMicrokernelTester() |
| 12333 | .cr(16) |
| 12334 | .kr(9) |
| 12335 | .channels(channels) |
| 12336 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12337 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12338 | } |
| 12339 | } |
| 12340 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12341 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12342 | TEST_REQUIRES_X86_AVX512F; |
| 12343 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12344 | DWConvMicrokernelTester() |
| 12345 | .cr(16) |
| 12346 | .kr(9) |
| 12347 | .channels(channels) |
| 12348 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12349 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12350 | } |
| 12351 | } |
| 12352 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12353 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12354 | TEST_REQUIRES_X86_AVX512F; |
| 12355 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 12356 | DWConvMicrokernelTester() |
| 12357 | .cr(16) |
| 12358 | .kr(9) |
| 12359 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12360 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12361 | } |
| 12362 | } |
| 12363 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12364 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12365 | TEST_REQUIRES_X86_AVX512F; |
| 12366 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 12367 | DWConvMicrokernelTester() |
| 12368 | .cr(16) |
| 12369 | .kr(9) |
| 12370 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12371 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12372 | } |
| 12373 | } |
| 12374 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12375 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12376 | TEST_REQUIRES_X86_AVX512F; |
| 12377 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 12378 | DWConvMicrokernelTester() |
| 12379 | .cr(16) |
| 12380 | .kr(9) |
| 12381 | .channels(channels) |
| 12382 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12383 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12384 | } |
| 12385 | } |
| 12386 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12387 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12388 | TEST_REQUIRES_X86_AVX512F; |
| 12389 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 12390 | DWConvMicrokernelTester() |
| 12391 | .cr(16) |
| 12392 | .kr(9) |
| 12393 | .channels(channels) |
| 12394 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12395 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12396 | } |
| 12397 | } |
| 12398 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12399 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12400 | TEST_REQUIRES_X86_AVX512F; |
| 12401 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12402 | DWConvMicrokernelTester() |
| 12403 | .cr(16) |
| 12404 | .kr(9) |
| 12405 | .channels(channels) |
| 12406 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12407 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12408 | } |
| 12409 | } |
| 12410 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12411 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12412 | TEST_REQUIRES_X86_AVX512F; |
| 12413 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12414 | for (size_t step = 2; step <= 9; step++) { |
| 12415 | DWConvMicrokernelTester() |
| 12416 | .cr(16) |
| 12417 | .kr(9) |
| 12418 | .channels(channels) |
| 12419 | .width(3) |
| 12420 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12421 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12422 | } |
| 12423 | } |
| 12424 | } |
| 12425 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12426 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12427 | TEST_REQUIRES_X86_AVX512F; |
| 12428 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12429 | DWConvMicrokernelTester() |
| 12430 | .cr(16) |
| 12431 | .kr(9) |
| 12432 | .channels(16) |
| 12433 | .width(5) |
| 12434 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12435 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12436 | } |
| 12437 | } |
| 12438 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12439 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12440 | TEST_REQUIRES_X86_AVX512F; |
| 12441 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12442 | DWConvMicrokernelTester() |
| 12443 | .cr(16) |
| 12444 | .kr(9) |
| 12445 | .channels(channels) |
| 12446 | .width(3) |
| 12447 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12448 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12449 | } |
| 12450 | } |
| 12451 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12452 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12453 | TEST_REQUIRES_X86_AVX512F; |
| 12454 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12455 | DWConvMicrokernelTester() |
| 12456 | .cr(16) |
| 12457 | .kr(9) |
| 12458 | .channels(channels) |
| 12459 | .width(3) |
| 12460 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12461 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12462 | } |
| 12463 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 12464 | |
| 12465 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, input_offset) { |
| 12466 | TEST_REQUIRES_X86_AVX512F; |
| 12467 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12468 | DWConvMicrokernelTester() |
| 12469 | .cr(16) |
| 12470 | .kr(9) |
| 12471 | .channels(channels) |
| 12472 | .input_offset(304) |
| 12473 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
| 12474 | } |
| 12475 | } |
| 12476 | |
| 12477 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F, zero) { |
| 12478 | TEST_REQUIRES_X86_AVX512F; |
| 12479 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 12480 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12481 | DWConvMicrokernelTester() |
| 12482 | .cr(16) |
| 12483 | .kr(9) |
| 12484 | .channels(channels) |
| 12485 | .input_offset(304) |
| 12486 | .zero_index(mz) |
| 12487 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f); |
| 12488 | } |
| 12489 | } |
| 12490 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12491 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 12492 | |
| 12493 | |
| 12494 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12495 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12496 | TEST_REQUIRES_X86_AVX512F; |
| 12497 | DWConvMicrokernelTester() |
| 12498 | .cr(16) |
| 12499 | .kr(9) |
| 12500 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12501 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12502 | } |
| 12503 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12504 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12505 | TEST_REQUIRES_X86_AVX512F; |
| 12506 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12507 | DWConvMicrokernelTester() |
| 12508 | .cr(16) |
| 12509 | .kr(9) |
| 12510 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12511 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12512 | } |
| 12513 | } |
| 12514 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12515 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12516 | TEST_REQUIRES_X86_AVX512F; |
| 12517 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12518 | DWConvMicrokernelTester() |
| 12519 | .cr(16) |
| 12520 | .kr(9) |
| 12521 | .channels(channels) |
| 12522 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12523 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12524 | } |
| 12525 | } |
| 12526 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12527 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12528 | TEST_REQUIRES_X86_AVX512F; |
| 12529 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12530 | DWConvMicrokernelTester() |
| 12531 | .cr(16) |
| 12532 | .kr(9) |
| 12533 | .channels(channels) |
| 12534 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12535 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12536 | } |
| 12537 | } |
| 12538 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12539 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12540 | TEST_REQUIRES_X86_AVX512F; |
| 12541 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 12542 | DWConvMicrokernelTester() |
| 12543 | .cr(16) |
| 12544 | .kr(9) |
| 12545 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12546 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12547 | } |
| 12548 | } |
| 12549 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12550 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12551 | TEST_REQUIRES_X86_AVX512F; |
| 12552 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 12553 | DWConvMicrokernelTester() |
| 12554 | .cr(16) |
| 12555 | .kr(9) |
| 12556 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12557 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12558 | } |
| 12559 | } |
| 12560 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12561 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12562 | TEST_REQUIRES_X86_AVX512F; |
| 12563 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 12564 | DWConvMicrokernelTester() |
| 12565 | .cr(16) |
| 12566 | .kr(9) |
| 12567 | .channels(channels) |
| 12568 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12569 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12570 | } |
| 12571 | } |
| 12572 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12573 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12574 | TEST_REQUIRES_X86_AVX512F; |
| 12575 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 12576 | DWConvMicrokernelTester() |
| 12577 | .cr(16) |
| 12578 | .kr(9) |
| 12579 | .channels(channels) |
| 12580 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12581 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12582 | } |
| 12583 | } |
| 12584 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12585 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12586 | TEST_REQUIRES_X86_AVX512F; |
| 12587 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12588 | DWConvMicrokernelTester() |
| 12589 | .cr(16) |
| 12590 | .kr(9) |
| 12591 | .channels(channels) |
| 12592 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12593 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12594 | } |
| 12595 | } |
| 12596 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12597 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12598 | TEST_REQUIRES_X86_AVX512F; |
| 12599 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12600 | for (size_t step = 2; step <= 9; step++) { |
| 12601 | DWConvMicrokernelTester() |
| 12602 | .cr(16) |
| 12603 | .kr(9) |
| 12604 | .channels(channels) |
| 12605 | .width(3) |
| 12606 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12607 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12608 | } |
| 12609 | } |
| 12610 | } |
| 12611 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12612 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12613 | TEST_REQUIRES_X86_AVX512F; |
| 12614 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12615 | DWConvMicrokernelTester() |
| 12616 | .cr(16) |
| 12617 | .kr(9) |
| 12618 | .channels(16) |
| 12619 | .width(5) |
| 12620 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12621 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12622 | } |
| 12623 | } |
| 12624 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12625 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12626 | TEST_REQUIRES_X86_AVX512F; |
| 12627 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12628 | DWConvMicrokernelTester() |
| 12629 | .cr(16) |
| 12630 | .kr(9) |
| 12631 | .channels(channels) |
| 12632 | .width(3) |
| 12633 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12634 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12635 | } |
| 12636 | } |
| 12637 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12638 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12639 | TEST_REQUIRES_X86_AVX512F; |
| 12640 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 12641 | DWConvMicrokernelTester() |
| 12642 | .cr(16) |
| 12643 | .kr(9) |
| 12644 | .channels(channels) |
| 12645 | .width(3) |
| 12646 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12647 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12648 | } |
| 12649 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 12650 | |
| 12651 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, input_offset) { |
| 12652 | TEST_REQUIRES_X86_AVX512F; |
| 12653 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12654 | DWConvMicrokernelTester() |
| 12655 | .cr(16) |
| 12656 | .kr(9) |
| 12657 | .channels(channels) |
| 12658 | .input_offset(304) |
| 12659 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
| 12660 | } |
| 12661 | } |
| 12662 | |
| 12663 | TEST(F32_DWCONV_MINMAX_UP16X9__AVX512F_ACC2, zero) { |
| 12664 | TEST_REQUIRES_X86_AVX512F; |
| 12665 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 12666 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 12667 | DWConvMicrokernelTester() |
| 12668 | .cr(16) |
| 12669 | .kr(9) |
| 12670 | .channels(channels) |
| 12671 | .input_offset(304) |
| 12672 | .zero_index(mz) |
| 12673 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x9__avx512f_acc2); |
| 12674 | } |
| 12675 | } |
| 12676 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12677 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 12678 | |
| 12679 | |
| 12680 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12681 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_eq_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12682 | TEST_REQUIRES_X86_AVX512F; |
| 12683 | DWConvMicrokernelTester() |
| 12684 | .cr(32) |
| 12685 | .kr(9) |
| 12686 | .channels(32) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12687 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12688 | } |
| 12689 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12690 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_div_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12691 | TEST_REQUIRES_X86_AVX512F; |
| 12692 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12693 | DWConvMicrokernelTester() |
| 12694 | .cr(32) |
| 12695 | .kr(9) |
| 12696 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12697 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12698 | } |
| 12699 | } |
| 12700 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12701 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_div_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12702 | TEST_REQUIRES_X86_AVX512F; |
| 12703 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12704 | DWConvMicrokernelTester() |
| 12705 | .cr(32) |
| 12706 | .kr(9) |
| 12707 | .channels(channels) |
| 12708 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12709 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12710 | } |
| 12711 | } |
| 12712 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12713 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_div_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12714 | TEST_REQUIRES_X86_AVX512F; |
| 12715 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12716 | DWConvMicrokernelTester() |
| 12717 | .cr(32) |
| 12718 | .kr(9) |
| 12719 | .channels(channels) |
| 12720 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12721 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12722 | } |
| 12723 | } |
| 12724 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12725 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_lt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12726 | TEST_REQUIRES_X86_AVX512F; |
| 12727 | for (uint32_t channels = 1; channels < 32; channels++) { |
| 12728 | DWConvMicrokernelTester() |
| 12729 | .cr(32) |
| 12730 | .kr(9) |
| 12731 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12732 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12733 | } |
| 12734 | } |
| 12735 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12736 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_gt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12737 | TEST_REQUIRES_X86_AVX512F; |
| 12738 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12739 | DWConvMicrokernelTester() |
| 12740 | .cr(32) |
| 12741 | .kr(9) |
| 12742 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12743 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12744 | } |
| 12745 | } |
| 12746 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12747 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_gt_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12748 | TEST_REQUIRES_X86_AVX512F; |
| 12749 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12750 | DWConvMicrokernelTester() |
| 12751 | .cr(32) |
| 12752 | .kr(9) |
| 12753 | .channels(channels) |
| 12754 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12755 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12756 | } |
| 12757 | } |
| 12758 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12759 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, c_gt_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12760 | TEST_REQUIRES_X86_AVX512F; |
| 12761 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12762 | DWConvMicrokernelTester() |
| 12763 | .cr(32) |
| 12764 | .kr(9) |
| 12765 | .channels(channels) |
| 12766 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12767 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12768 | } |
| 12769 | } |
| 12770 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12771 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12772 | TEST_REQUIRES_X86_AVX512F; |
| 12773 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12774 | DWConvMicrokernelTester() |
| 12775 | .cr(32) |
| 12776 | .kr(9) |
| 12777 | .channels(channels) |
| 12778 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12779 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12780 | } |
| 12781 | } |
| 12782 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12783 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12784 | TEST_REQUIRES_X86_AVX512F; |
| 12785 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12786 | for (size_t step = 2; step <= 9; step++) { |
| 12787 | DWConvMicrokernelTester() |
| 12788 | .cr(32) |
| 12789 | .kr(9) |
| 12790 | .channels(channels) |
| 12791 | .width(3) |
| 12792 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12793 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12794 | } |
| 12795 | } |
| 12796 | } |
| 12797 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12798 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12799 | TEST_REQUIRES_X86_AVX512F; |
| 12800 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12801 | DWConvMicrokernelTester() |
| 12802 | .cr(32) |
| 12803 | .kr(9) |
| 12804 | .channels(32) |
| 12805 | .width(5) |
| 12806 | .output_stride(163) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12807 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12808 | } |
| 12809 | } |
| 12810 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12811 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12812 | TEST_REQUIRES_X86_AVX512F; |
| 12813 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12814 | DWConvMicrokernelTester() |
| 12815 | .cr(32) |
| 12816 | .kr(9) |
| 12817 | .channels(channels) |
| 12818 | .width(3) |
| 12819 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12820 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12821 | } |
| 12822 | } |
| 12823 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12824 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12825 | TEST_REQUIRES_X86_AVX512F; |
| 12826 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12827 | DWConvMicrokernelTester() |
| 12828 | .cr(32) |
| 12829 | .kr(9) |
| 12830 | .channels(channels) |
| 12831 | .width(3) |
| 12832 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12833 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12834 | } |
| 12835 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 12836 | |
| 12837 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, input_offset) { |
| 12838 | TEST_REQUIRES_X86_AVX512F; |
| 12839 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12840 | DWConvMicrokernelTester() |
| 12841 | .cr(32) |
| 12842 | .kr(9) |
| 12843 | .channels(channels) |
| 12844 | .input_offset(592) |
| 12845 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
| 12846 | } |
| 12847 | } |
| 12848 | |
| 12849 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F, zero) { |
| 12850 | TEST_REQUIRES_X86_AVX512F; |
| 12851 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 12852 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12853 | DWConvMicrokernelTester() |
| 12854 | .cr(32) |
| 12855 | .kr(9) |
| 12856 | .channels(channels) |
| 12857 | .input_offset(592) |
| 12858 | .zero_index(mz) |
| 12859 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f); |
| 12860 | } |
| 12861 | } |
| 12862 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12863 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 12864 | |
| 12865 | |
| 12866 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12867 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_eq_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12868 | TEST_REQUIRES_X86_AVX512F; |
| 12869 | DWConvMicrokernelTester() |
| 12870 | .cr(32) |
| 12871 | .kr(9) |
| 12872 | .channels(32) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12873 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12874 | } |
| 12875 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12876 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_div_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12877 | TEST_REQUIRES_X86_AVX512F; |
| 12878 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12879 | DWConvMicrokernelTester() |
| 12880 | .cr(32) |
| 12881 | .kr(9) |
| 12882 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12883 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12884 | } |
| 12885 | } |
| 12886 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12887 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_div_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12888 | TEST_REQUIRES_X86_AVX512F; |
| 12889 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12890 | DWConvMicrokernelTester() |
| 12891 | .cr(32) |
| 12892 | .kr(9) |
| 12893 | .channels(channels) |
| 12894 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12895 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12896 | } |
| 12897 | } |
| 12898 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12899 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_div_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12900 | TEST_REQUIRES_X86_AVX512F; |
| 12901 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 12902 | DWConvMicrokernelTester() |
| 12903 | .cr(32) |
| 12904 | .kr(9) |
| 12905 | .channels(channels) |
| 12906 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12907 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12908 | } |
| 12909 | } |
| 12910 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12911 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_lt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12912 | TEST_REQUIRES_X86_AVX512F; |
| 12913 | for (uint32_t channels = 1; channels < 32; channels++) { |
| 12914 | DWConvMicrokernelTester() |
| 12915 | .cr(32) |
| 12916 | .kr(9) |
| 12917 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12918 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12919 | } |
| 12920 | } |
| 12921 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12922 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_gt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12923 | TEST_REQUIRES_X86_AVX512F; |
| 12924 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12925 | DWConvMicrokernelTester() |
| 12926 | .cr(32) |
| 12927 | .kr(9) |
| 12928 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12929 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12930 | } |
| 12931 | } |
| 12932 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12933 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_gt_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12934 | TEST_REQUIRES_X86_AVX512F; |
| 12935 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12936 | DWConvMicrokernelTester() |
| 12937 | .cr(32) |
| 12938 | .kr(9) |
| 12939 | .channels(channels) |
| 12940 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12941 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12942 | } |
| 12943 | } |
| 12944 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12945 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, c_gt_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12946 | TEST_REQUIRES_X86_AVX512F; |
| 12947 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 12948 | DWConvMicrokernelTester() |
| 12949 | .cr(32) |
| 12950 | .kr(9) |
| 12951 | .channels(channels) |
| 12952 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12953 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12954 | } |
| 12955 | } |
| 12956 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12957 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12958 | TEST_REQUIRES_X86_AVX512F; |
| 12959 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12960 | DWConvMicrokernelTester() |
| 12961 | .cr(32) |
| 12962 | .kr(9) |
| 12963 | .channels(channels) |
| 12964 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12965 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12966 | } |
| 12967 | } |
| 12968 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12969 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12970 | TEST_REQUIRES_X86_AVX512F; |
| 12971 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12972 | for (size_t step = 2; step <= 9; step++) { |
| 12973 | DWConvMicrokernelTester() |
| 12974 | .cr(32) |
| 12975 | .kr(9) |
| 12976 | .channels(channels) |
| 12977 | .width(3) |
| 12978 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12979 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12980 | } |
| 12981 | } |
| 12982 | } |
| 12983 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12984 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12985 | TEST_REQUIRES_X86_AVX512F; |
| 12986 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 12987 | DWConvMicrokernelTester() |
| 12988 | .cr(32) |
| 12989 | .kr(9) |
| 12990 | .channels(32) |
| 12991 | .width(5) |
| 12992 | .output_stride(163) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12993 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12994 | } |
| 12995 | } |
| 12996 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 12997 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 12998 | TEST_REQUIRES_X86_AVX512F; |
| 12999 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13000 | DWConvMicrokernelTester() |
| 13001 | .cr(32) |
| 13002 | .kr(9) |
| 13003 | .channels(channels) |
| 13004 | .width(3) |
| 13005 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13006 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13007 | } |
| 13008 | } |
| 13009 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13010 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13011 | TEST_REQUIRES_X86_AVX512F; |
| 13012 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13013 | DWConvMicrokernelTester() |
| 13014 | .cr(32) |
| 13015 | .kr(9) |
| 13016 | .channels(channels) |
| 13017 | .width(3) |
| 13018 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13019 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13020 | } |
| 13021 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 13022 | |
| 13023 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, input_offset) { |
| 13024 | TEST_REQUIRES_X86_AVX512F; |
| 13025 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13026 | DWConvMicrokernelTester() |
| 13027 | .cr(32) |
| 13028 | .kr(9) |
| 13029 | .channels(channels) |
| 13030 | .input_offset(592) |
| 13031 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
| 13032 | } |
| 13033 | } |
| 13034 | |
| 13035 | TEST(F32_DWCONV_MINMAX_UP32X9__AVX512F_ACC2, zero) { |
| 13036 | TEST_REQUIRES_X86_AVX512F; |
| 13037 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 13038 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13039 | DWConvMicrokernelTester() |
| 13040 | .cr(32) |
| 13041 | .kr(9) |
| 13042 | .channels(channels) |
| 13043 | .input_offset(592) |
| 13044 | .zero_index(mz) |
| 13045 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x9__avx512f_acc2); |
| 13046 | } |
| 13047 | } |
| 13048 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13049 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 13050 | |
| 13051 | |
| 13052 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13053 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13054 | TEST_REQUIRES_X86_AVX512F; |
| 13055 | DWConvMicrokernelTester() |
| 13056 | .cr(16) |
| 13057 | .kr(4) |
| 13058 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13059 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13060 | } |
| 13061 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13062 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13063 | TEST_REQUIRES_X86_AVX512F; |
| 13064 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13065 | DWConvMicrokernelTester() |
| 13066 | .cr(16) |
| 13067 | .kr(4) |
| 13068 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13069 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13070 | } |
| 13071 | } |
| 13072 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13073 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13074 | TEST_REQUIRES_X86_AVX512F; |
| 13075 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13076 | DWConvMicrokernelTester() |
| 13077 | .cr(16) |
| 13078 | .kr(4) |
| 13079 | .channels(channels) |
| 13080 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13081 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13082 | } |
| 13083 | } |
| 13084 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13085 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13086 | TEST_REQUIRES_X86_AVX512F; |
| 13087 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13088 | DWConvMicrokernelTester() |
| 13089 | .cr(16) |
| 13090 | .kr(4) |
| 13091 | .channels(channels) |
| 13092 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13093 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13094 | } |
| 13095 | } |
| 13096 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13097 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13098 | TEST_REQUIRES_X86_AVX512F; |
| 13099 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 13100 | DWConvMicrokernelTester() |
| 13101 | .cr(16) |
| 13102 | .kr(4) |
| 13103 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13104 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13105 | } |
| 13106 | } |
| 13107 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13108 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13109 | TEST_REQUIRES_X86_AVX512F; |
| 13110 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 13111 | DWConvMicrokernelTester() |
| 13112 | .cr(16) |
| 13113 | .kr(4) |
| 13114 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13115 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13116 | } |
| 13117 | } |
| 13118 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13119 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13120 | TEST_REQUIRES_X86_AVX512F; |
| 13121 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 13122 | DWConvMicrokernelTester() |
| 13123 | .cr(16) |
| 13124 | .kr(4) |
| 13125 | .channels(channels) |
| 13126 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13127 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13128 | } |
| 13129 | } |
| 13130 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13131 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13132 | TEST_REQUIRES_X86_AVX512F; |
| 13133 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 13134 | DWConvMicrokernelTester() |
| 13135 | .cr(16) |
| 13136 | .kr(4) |
| 13137 | .channels(channels) |
| 13138 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13139 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13140 | } |
| 13141 | } |
| 13142 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13143 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13144 | TEST_REQUIRES_X86_AVX512F; |
| 13145 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13146 | DWConvMicrokernelTester() |
| 13147 | .cr(16) |
| 13148 | .kr(4) |
| 13149 | .channels(channels) |
| 13150 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13151 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13152 | } |
| 13153 | } |
| 13154 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13155 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13156 | TEST_REQUIRES_X86_AVX512F; |
| 13157 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13158 | for (size_t step = 2; step <= 4; step++) { |
| 13159 | DWConvMicrokernelTester() |
| 13160 | .cr(16) |
| 13161 | .kr(4) |
| 13162 | .channels(channels) |
| 13163 | .width(3) |
| 13164 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13165 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13166 | } |
| 13167 | } |
| 13168 | } |
| 13169 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13170 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13171 | TEST_REQUIRES_X86_AVX512F; |
| 13172 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13173 | DWConvMicrokernelTester() |
| 13174 | .cr(16) |
| 13175 | .kr(4) |
| 13176 | .channels(16) |
| 13177 | .width(5) |
| 13178 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13179 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13180 | } |
| 13181 | } |
| 13182 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13183 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13184 | TEST_REQUIRES_X86_AVX512F; |
| 13185 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13186 | DWConvMicrokernelTester() |
| 13187 | .cr(16) |
| 13188 | .kr(4) |
| 13189 | .channels(channels) |
| 13190 | .width(3) |
| 13191 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13192 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13193 | } |
| 13194 | } |
| 13195 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13196 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13197 | TEST_REQUIRES_X86_AVX512F; |
| 13198 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13199 | DWConvMicrokernelTester() |
| 13200 | .cr(16) |
| 13201 | .kr(4) |
| 13202 | .channels(channels) |
| 13203 | .width(3) |
| 13204 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13205 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13206 | } |
| 13207 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 13208 | |
| 13209 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, input_offset) { |
| 13210 | TEST_REQUIRES_X86_AVX512F; |
| 13211 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13212 | DWConvMicrokernelTester() |
| 13213 | .cr(16) |
| 13214 | .kr(4) |
| 13215 | .channels(channels) |
| 13216 | .input_offset(304) |
| 13217 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
| 13218 | } |
| 13219 | } |
| 13220 | |
| 13221 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F, zero) { |
| 13222 | TEST_REQUIRES_X86_AVX512F; |
| 13223 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 13224 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13225 | DWConvMicrokernelTester() |
| 13226 | .cr(16) |
| 13227 | .kr(4) |
| 13228 | .channels(channels) |
| 13229 | .input_offset(304) |
| 13230 | .zero_index(mz) |
| 13231 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f); |
| 13232 | } |
| 13233 | } |
| 13234 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13235 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 13236 | |
| 13237 | |
| 13238 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13239 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_eq_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13240 | TEST_REQUIRES_X86_AVX512F; |
| 13241 | DWConvMicrokernelTester() |
| 13242 | .cr(16) |
| 13243 | .kr(4) |
| 13244 | .channels(16) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13245 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13246 | } |
| 13247 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13248 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_div_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13249 | TEST_REQUIRES_X86_AVX512F; |
| 13250 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13251 | DWConvMicrokernelTester() |
| 13252 | .cr(16) |
| 13253 | .kr(4) |
| 13254 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13255 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13256 | } |
| 13257 | } |
| 13258 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13259 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_div_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13260 | TEST_REQUIRES_X86_AVX512F; |
| 13261 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13262 | DWConvMicrokernelTester() |
| 13263 | .cr(16) |
| 13264 | .kr(4) |
| 13265 | .channels(channels) |
| 13266 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13267 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13268 | } |
| 13269 | } |
| 13270 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13271 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_div_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13272 | TEST_REQUIRES_X86_AVX512F; |
| 13273 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13274 | DWConvMicrokernelTester() |
| 13275 | .cr(16) |
| 13276 | .kr(4) |
| 13277 | .channels(channels) |
| 13278 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13279 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13280 | } |
| 13281 | } |
| 13282 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13283 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_lt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13284 | TEST_REQUIRES_X86_AVX512F; |
| 13285 | for (uint32_t channels = 1; channels < 16; channels++) { |
| 13286 | DWConvMicrokernelTester() |
| 13287 | .cr(16) |
| 13288 | .kr(4) |
| 13289 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13290 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13291 | } |
| 13292 | } |
| 13293 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13294 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_gt_16) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13295 | TEST_REQUIRES_X86_AVX512F; |
| 13296 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 13297 | DWConvMicrokernelTester() |
| 13298 | .cr(16) |
| 13299 | .kr(4) |
| 13300 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13301 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13302 | } |
| 13303 | } |
| 13304 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13305 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_gt_16_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13306 | TEST_REQUIRES_X86_AVX512F; |
| 13307 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 13308 | DWConvMicrokernelTester() |
| 13309 | .cr(16) |
| 13310 | .kr(4) |
| 13311 | .channels(channels) |
| 13312 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13313 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13314 | } |
| 13315 | } |
| 13316 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13317 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, c_gt_16_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13318 | TEST_REQUIRES_X86_AVX512F; |
| 13319 | for (uint32_t channels = 17; channels < 32; channels++) { |
| 13320 | DWConvMicrokernelTester() |
| 13321 | .cr(16) |
| 13322 | .kr(4) |
| 13323 | .channels(channels) |
| 13324 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13325 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13326 | } |
| 13327 | } |
| 13328 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13329 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13330 | TEST_REQUIRES_X86_AVX512F; |
| 13331 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13332 | DWConvMicrokernelTester() |
| 13333 | .cr(16) |
| 13334 | .kr(4) |
| 13335 | .channels(channels) |
| 13336 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13337 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13338 | } |
| 13339 | } |
| 13340 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13341 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13342 | TEST_REQUIRES_X86_AVX512F; |
| 13343 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13344 | for (size_t step = 2; step <= 4; step++) { |
| 13345 | DWConvMicrokernelTester() |
| 13346 | .cr(16) |
| 13347 | .kr(4) |
| 13348 | .channels(channels) |
| 13349 | .width(3) |
| 13350 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13351 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13352 | } |
| 13353 | } |
| 13354 | } |
| 13355 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13356 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13357 | TEST_REQUIRES_X86_AVX512F; |
| 13358 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13359 | DWConvMicrokernelTester() |
| 13360 | .cr(16) |
| 13361 | .kr(4) |
| 13362 | .channels(16) |
| 13363 | .width(5) |
| 13364 | .output_stride(83) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13365 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13366 | } |
| 13367 | } |
| 13368 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13369 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13370 | TEST_REQUIRES_X86_AVX512F; |
| 13371 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13372 | DWConvMicrokernelTester() |
| 13373 | .cr(16) |
| 13374 | .kr(4) |
| 13375 | .channels(channels) |
| 13376 | .width(3) |
| 13377 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13378 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13379 | } |
| 13380 | } |
| 13381 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13382 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13383 | TEST_REQUIRES_X86_AVX512F; |
| 13384 | for (size_t channels = 1; channels <= 80; channels += 15) { |
| 13385 | DWConvMicrokernelTester() |
| 13386 | .cr(16) |
| 13387 | .kr(4) |
| 13388 | .channels(channels) |
| 13389 | .width(3) |
| 13390 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13391 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13392 | } |
| 13393 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 13394 | |
| 13395 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, input_offset) { |
| 13396 | TEST_REQUIRES_X86_AVX512F; |
| 13397 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13398 | DWConvMicrokernelTester() |
| 13399 | .cr(16) |
| 13400 | .kr(4) |
| 13401 | .channels(channels) |
| 13402 | .input_offset(304) |
| 13403 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
| 13404 | } |
| 13405 | } |
| 13406 | |
| 13407 | TEST(F32_DWCONV_MINMAX_UP16X4__AVX512F_ACC2, zero) { |
| 13408 | TEST_REQUIRES_X86_AVX512F; |
| 13409 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 13410 | for (uint32_t channels = 32; channels < 256; channels += 48) { |
| 13411 | DWConvMicrokernelTester() |
| 13412 | .cr(16) |
| 13413 | .kr(4) |
| 13414 | .channels(channels) |
| 13415 | .input_offset(304) |
| 13416 | .zero_index(mz) |
| 13417 | .Test(xnn_f32_dwconv_minmax_ukernel_up16x4__avx512f_acc2); |
| 13418 | } |
| 13419 | } |
| 13420 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13421 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 13422 | |
| 13423 | |
| 13424 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13425 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_eq_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13426 | TEST_REQUIRES_X86_AVX512F; |
| 13427 | DWConvMicrokernelTester() |
| 13428 | .cr(32) |
| 13429 | .kr(4) |
| 13430 | .channels(32) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13431 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13432 | } |
| 13433 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13434 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_div_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13435 | TEST_REQUIRES_X86_AVX512F; |
| 13436 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13437 | DWConvMicrokernelTester() |
| 13438 | .cr(32) |
| 13439 | .kr(4) |
| 13440 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13441 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13442 | } |
| 13443 | } |
| 13444 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13445 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_div_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13446 | TEST_REQUIRES_X86_AVX512F; |
| 13447 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13448 | DWConvMicrokernelTester() |
| 13449 | .cr(32) |
| 13450 | .kr(4) |
| 13451 | .channels(channels) |
| 13452 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13453 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13454 | } |
| 13455 | } |
| 13456 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13457 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_div_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13458 | TEST_REQUIRES_X86_AVX512F; |
| 13459 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13460 | DWConvMicrokernelTester() |
| 13461 | .cr(32) |
| 13462 | .kr(4) |
| 13463 | .channels(channels) |
| 13464 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13465 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13466 | } |
| 13467 | } |
| 13468 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13469 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_lt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13470 | TEST_REQUIRES_X86_AVX512F; |
| 13471 | for (uint32_t channels = 1; channels < 32; channels++) { |
| 13472 | DWConvMicrokernelTester() |
| 13473 | .cr(32) |
| 13474 | .kr(4) |
| 13475 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13476 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13477 | } |
| 13478 | } |
| 13479 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13480 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_gt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13481 | TEST_REQUIRES_X86_AVX512F; |
| 13482 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 13483 | DWConvMicrokernelTester() |
| 13484 | .cr(32) |
| 13485 | .kr(4) |
| 13486 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13487 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13488 | } |
| 13489 | } |
| 13490 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13491 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_gt_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13492 | TEST_REQUIRES_X86_AVX512F; |
| 13493 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 13494 | DWConvMicrokernelTester() |
| 13495 | .cr(32) |
| 13496 | .kr(4) |
| 13497 | .channels(channels) |
| 13498 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13499 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13500 | } |
| 13501 | } |
| 13502 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13503 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, c_gt_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13504 | TEST_REQUIRES_X86_AVX512F; |
| 13505 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 13506 | DWConvMicrokernelTester() |
| 13507 | .cr(32) |
| 13508 | .kr(4) |
| 13509 | .channels(channels) |
| 13510 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13511 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13512 | } |
| 13513 | } |
| 13514 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13515 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13516 | TEST_REQUIRES_X86_AVX512F; |
| 13517 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13518 | DWConvMicrokernelTester() |
| 13519 | .cr(32) |
| 13520 | .kr(4) |
| 13521 | .channels(channels) |
| 13522 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13523 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13524 | } |
| 13525 | } |
| 13526 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13527 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13528 | TEST_REQUIRES_X86_AVX512F; |
| 13529 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13530 | for (size_t step = 2; step <= 4; step++) { |
| 13531 | DWConvMicrokernelTester() |
| 13532 | .cr(32) |
| 13533 | .kr(4) |
| 13534 | .channels(channels) |
| 13535 | .width(3) |
| 13536 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13537 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13538 | } |
| 13539 | } |
| 13540 | } |
| 13541 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13542 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13543 | TEST_REQUIRES_X86_AVX512F; |
| 13544 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13545 | DWConvMicrokernelTester() |
| 13546 | .cr(32) |
| 13547 | .kr(4) |
| 13548 | .channels(32) |
| 13549 | .width(5) |
| 13550 | .output_stride(163) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13551 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13552 | } |
| 13553 | } |
| 13554 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13555 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13556 | TEST_REQUIRES_X86_AVX512F; |
| 13557 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13558 | DWConvMicrokernelTester() |
| 13559 | .cr(32) |
| 13560 | .kr(4) |
| 13561 | .channels(channels) |
| 13562 | .width(3) |
| 13563 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13564 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13565 | } |
| 13566 | } |
| 13567 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13568 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13569 | TEST_REQUIRES_X86_AVX512F; |
| 13570 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13571 | DWConvMicrokernelTester() |
| 13572 | .cr(32) |
| 13573 | .kr(4) |
| 13574 | .channels(channels) |
| 13575 | .width(3) |
| 13576 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13577 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13578 | } |
| 13579 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 13580 | |
| 13581 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, input_offset) { |
| 13582 | TEST_REQUIRES_X86_AVX512F; |
| 13583 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13584 | DWConvMicrokernelTester() |
| 13585 | .cr(32) |
| 13586 | .kr(4) |
| 13587 | .channels(channels) |
| 13588 | .input_offset(592) |
| 13589 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
| 13590 | } |
| 13591 | } |
| 13592 | |
| 13593 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F, zero) { |
| 13594 | TEST_REQUIRES_X86_AVX512F; |
| 13595 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 13596 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13597 | DWConvMicrokernelTester() |
| 13598 | .cr(32) |
| 13599 | .kr(4) |
| 13600 | .channels(channels) |
| 13601 | .input_offset(592) |
| 13602 | .zero_index(mz) |
| 13603 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f); |
| 13604 | } |
| 13605 | } |
| 13606 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13607 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 13608 | |
| 13609 | |
| 13610 | #if XNN_ARCH_X86 || XNN_ARCH_X86_64 |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13611 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_eq_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13612 | TEST_REQUIRES_X86_AVX512F; |
| 13613 | DWConvMicrokernelTester() |
| 13614 | .cr(32) |
| 13615 | .kr(4) |
| 13616 | .channels(32) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13617 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13618 | } |
| 13619 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13620 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_div_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13621 | TEST_REQUIRES_X86_AVX512F; |
| 13622 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13623 | DWConvMicrokernelTester() |
| 13624 | .cr(32) |
| 13625 | .kr(4) |
| 13626 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13627 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13628 | } |
| 13629 | } |
| 13630 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13631 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_div_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13632 | TEST_REQUIRES_X86_AVX512F; |
| 13633 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13634 | DWConvMicrokernelTester() |
| 13635 | .cr(32) |
| 13636 | .kr(4) |
| 13637 | .channels(channels) |
| 13638 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13639 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13640 | } |
| 13641 | } |
| 13642 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13643 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_div_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13644 | TEST_REQUIRES_X86_AVX512F; |
| 13645 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13646 | DWConvMicrokernelTester() |
| 13647 | .cr(32) |
| 13648 | .kr(4) |
| 13649 | .channels(channels) |
| 13650 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13651 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13652 | } |
| 13653 | } |
| 13654 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13655 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_lt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13656 | TEST_REQUIRES_X86_AVX512F; |
| 13657 | for (uint32_t channels = 1; channels < 32; channels++) { |
| 13658 | DWConvMicrokernelTester() |
| 13659 | .cr(32) |
| 13660 | .kr(4) |
| 13661 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13662 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13663 | } |
| 13664 | } |
| 13665 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13666 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_gt_32) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13667 | TEST_REQUIRES_X86_AVX512F; |
| 13668 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 13669 | DWConvMicrokernelTester() |
| 13670 | .cr(32) |
| 13671 | .kr(4) |
| 13672 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13673 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13674 | } |
| 13675 | } |
| 13676 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13677 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_gt_32_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13678 | TEST_REQUIRES_X86_AVX512F; |
| 13679 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 13680 | DWConvMicrokernelTester() |
| 13681 | .cr(32) |
| 13682 | .kr(4) |
| 13683 | .channels(channels) |
| 13684 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13685 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13686 | } |
| 13687 | } |
| 13688 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13689 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, c_gt_32_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13690 | TEST_REQUIRES_X86_AVX512F; |
| 13691 | for (uint32_t channels = 33; channels < 64; channels++) { |
| 13692 | DWConvMicrokernelTester() |
| 13693 | .cr(32) |
| 13694 | .kr(4) |
| 13695 | .channels(channels) |
| 13696 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13697 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13698 | } |
| 13699 | } |
| 13700 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13701 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13702 | TEST_REQUIRES_X86_AVX512F; |
| 13703 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13704 | DWConvMicrokernelTester() |
| 13705 | .cr(32) |
| 13706 | .kr(4) |
| 13707 | .channels(channels) |
| 13708 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13709 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13710 | } |
| 13711 | } |
| 13712 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13713 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13714 | TEST_REQUIRES_X86_AVX512F; |
| 13715 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13716 | for (size_t step = 2; step <= 4; step++) { |
| 13717 | DWConvMicrokernelTester() |
| 13718 | .cr(32) |
| 13719 | .kr(4) |
| 13720 | .channels(channels) |
| 13721 | .width(3) |
| 13722 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13723 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13724 | } |
| 13725 | } |
| 13726 | } |
| 13727 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13728 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13729 | TEST_REQUIRES_X86_AVX512F; |
| 13730 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13731 | DWConvMicrokernelTester() |
| 13732 | .cr(32) |
| 13733 | .kr(4) |
| 13734 | .channels(32) |
| 13735 | .width(5) |
| 13736 | .output_stride(163) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13737 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13738 | } |
| 13739 | } |
| 13740 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13741 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13742 | TEST_REQUIRES_X86_AVX512F; |
| 13743 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13744 | DWConvMicrokernelTester() |
| 13745 | .cr(32) |
| 13746 | .kr(4) |
| 13747 | .channels(channels) |
| 13748 | .width(3) |
| 13749 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13750 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13751 | } |
| 13752 | } |
| 13753 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13754 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13755 | TEST_REQUIRES_X86_AVX512F; |
| 13756 | for (size_t channels = 1; channels <= 160; channels += 31) { |
| 13757 | DWConvMicrokernelTester() |
| 13758 | .cr(32) |
| 13759 | .kr(4) |
| 13760 | .channels(channels) |
| 13761 | .width(3) |
| 13762 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13763 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13764 | } |
| 13765 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 13766 | |
| 13767 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, input_offset) { |
| 13768 | TEST_REQUIRES_X86_AVX512F; |
| 13769 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13770 | DWConvMicrokernelTester() |
| 13771 | .cr(32) |
| 13772 | .kr(4) |
| 13773 | .channels(channels) |
| 13774 | .input_offset(592) |
| 13775 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
| 13776 | } |
| 13777 | } |
| 13778 | |
| 13779 | TEST(F32_DWCONV_MINMAX_UP32X4__AVX512F_ACC2, zero) { |
| 13780 | TEST_REQUIRES_X86_AVX512F; |
| 13781 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 13782 | for (uint32_t channels = 64; channels < 512; channels += 96) { |
| 13783 | DWConvMicrokernelTester() |
| 13784 | .cr(32) |
| 13785 | .kr(4) |
| 13786 | .channels(channels) |
| 13787 | .input_offset(592) |
| 13788 | .zero_index(mz) |
| 13789 | .Test(xnn_f32_dwconv_minmax_ukernel_up32x4__avx512f_acc2); |
| 13790 | } |
| 13791 | } |
| 13792 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13793 | #endif // XNN_ARCH_X86 || XNN_ARCH_X86_64 |
| 13794 | |
| 13795 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 13796 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13797 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13798 | TEST_REQUIRES_PSIMD; |
| 13799 | DWConvMicrokernelTester() |
| 13800 | .cr(4) |
| 13801 | .kr(25) |
| 13802 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13803 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13804 | } |
| 13805 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13806 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13807 | TEST_REQUIRES_PSIMD; |
| 13808 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 13809 | DWConvMicrokernelTester() |
| 13810 | .cr(4) |
| 13811 | .kr(25) |
| 13812 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13813 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13814 | } |
| 13815 | } |
| 13816 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13817 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13818 | TEST_REQUIRES_PSIMD; |
| 13819 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 13820 | DWConvMicrokernelTester() |
| 13821 | .cr(4) |
| 13822 | .kr(25) |
| 13823 | .channels(channels) |
| 13824 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13825 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13826 | } |
| 13827 | } |
| 13828 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13829 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13830 | TEST_REQUIRES_PSIMD; |
| 13831 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 13832 | DWConvMicrokernelTester() |
| 13833 | .cr(4) |
| 13834 | .kr(25) |
| 13835 | .channels(channels) |
| 13836 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13837 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13838 | } |
| 13839 | } |
| 13840 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13841 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13842 | TEST_REQUIRES_PSIMD; |
| 13843 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 13844 | DWConvMicrokernelTester() |
| 13845 | .cr(4) |
| 13846 | .kr(25) |
| 13847 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13848 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13849 | } |
| 13850 | } |
| 13851 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13852 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13853 | TEST_REQUIRES_PSIMD; |
| 13854 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 13855 | DWConvMicrokernelTester() |
| 13856 | .cr(4) |
| 13857 | .kr(25) |
| 13858 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13859 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13860 | } |
| 13861 | } |
| 13862 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13863 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13864 | TEST_REQUIRES_PSIMD; |
| 13865 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 13866 | DWConvMicrokernelTester() |
| 13867 | .cr(4) |
| 13868 | .kr(25) |
| 13869 | .channels(channels) |
| 13870 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13871 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13872 | } |
| 13873 | } |
| 13874 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13875 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13876 | TEST_REQUIRES_PSIMD; |
| 13877 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 13878 | DWConvMicrokernelTester() |
| 13879 | .cr(4) |
| 13880 | .kr(25) |
| 13881 | .channels(channels) |
| 13882 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13883 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13884 | } |
| 13885 | } |
| 13886 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13887 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13888 | TEST_REQUIRES_PSIMD; |
| 13889 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 13890 | DWConvMicrokernelTester() |
| 13891 | .cr(4) |
| 13892 | .kr(25) |
| 13893 | .channels(channels) |
| 13894 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13895 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13896 | } |
| 13897 | } |
| 13898 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13899 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13900 | TEST_REQUIRES_PSIMD; |
| 13901 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 13902 | for (size_t step = 2; step <= 25; step++) { |
| 13903 | DWConvMicrokernelTester() |
| 13904 | .cr(4) |
| 13905 | .kr(25) |
| 13906 | .channels(channels) |
| 13907 | .width(3) |
| 13908 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13909 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13910 | } |
| 13911 | } |
| 13912 | } |
| 13913 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13914 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13915 | TEST_REQUIRES_PSIMD; |
| 13916 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 13917 | DWConvMicrokernelTester() |
| 13918 | .cr(4) |
| 13919 | .kr(25) |
| 13920 | .channels(4) |
| 13921 | .width(5) |
| 13922 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13923 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13924 | } |
| 13925 | } |
| 13926 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13927 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13928 | TEST_REQUIRES_PSIMD; |
| 13929 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 13930 | DWConvMicrokernelTester() |
| 13931 | .cr(4) |
| 13932 | .kr(25) |
| 13933 | .channels(channels) |
| 13934 | .width(3) |
| 13935 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13936 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13937 | } |
| 13938 | } |
| 13939 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13940 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13941 | TEST_REQUIRES_PSIMD; |
| 13942 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 13943 | DWConvMicrokernelTester() |
| 13944 | .cr(4) |
| 13945 | .kr(25) |
| 13946 | .channels(channels) |
| 13947 | .width(3) |
| 13948 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13949 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13950 | } |
| 13951 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 13952 | |
| 13953 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, input_offset) { |
| 13954 | TEST_REQUIRES_PSIMD; |
| 13955 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 13956 | DWConvMicrokernelTester() |
| 13957 | .cr(4) |
| 13958 | .kr(25) |
| 13959 | .channels(channels) |
| 13960 | .input_offset(112) |
| 13961 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 13962 | } |
| 13963 | } |
| 13964 | |
| 13965 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD, zero) { |
| 13966 | TEST_REQUIRES_PSIMD; |
| 13967 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 13968 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 13969 | DWConvMicrokernelTester() |
| 13970 | .cr(4) |
| 13971 | .kr(25) |
| 13972 | .channels(channels) |
| 13973 | .input_offset(112) |
| 13974 | .zero_index(mz) |
| 13975 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 13976 | } |
| 13977 | } |
| 13978 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 13979 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13980 | |
| 13981 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 13982 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13983 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13984 | TEST_REQUIRES_PSIMD; |
| 13985 | DWConvMicrokernelTester() |
| 13986 | .cr(4) |
| 13987 | .kr(25) |
| 13988 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13989 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13990 | } |
| 13991 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13992 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 13993 | TEST_REQUIRES_PSIMD; |
| 13994 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 13995 | DWConvMicrokernelTester() |
| 13996 | .cr(4) |
| 13997 | .kr(25) |
| 13998 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 13999 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14000 | } |
| 14001 | } |
| 14002 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14003 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14004 | TEST_REQUIRES_PSIMD; |
| 14005 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14006 | DWConvMicrokernelTester() |
| 14007 | .cr(4) |
| 14008 | .kr(25) |
| 14009 | .channels(channels) |
| 14010 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14011 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14012 | } |
| 14013 | } |
| 14014 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14015 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14016 | TEST_REQUIRES_PSIMD; |
| 14017 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14018 | DWConvMicrokernelTester() |
| 14019 | .cr(4) |
| 14020 | .kr(25) |
| 14021 | .channels(channels) |
| 14022 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14023 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14024 | } |
| 14025 | } |
| 14026 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14027 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14028 | TEST_REQUIRES_PSIMD; |
| 14029 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 14030 | DWConvMicrokernelTester() |
| 14031 | .cr(4) |
| 14032 | .kr(25) |
| 14033 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14034 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14035 | } |
| 14036 | } |
| 14037 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14038 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14039 | TEST_REQUIRES_PSIMD; |
| 14040 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14041 | DWConvMicrokernelTester() |
| 14042 | .cr(4) |
| 14043 | .kr(25) |
| 14044 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14045 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14046 | } |
| 14047 | } |
| 14048 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14049 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14050 | TEST_REQUIRES_PSIMD; |
| 14051 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14052 | DWConvMicrokernelTester() |
| 14053 | .cr(4) |
| 14054 | .kr(25) |
| 14055 | .channels(channels) |
| 14056 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14057 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14058 | } |
| 14059 | } |
| 14060 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14061 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14062 | TEST_REQUIRES_PSIMD; |
| 14063 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14064 | DWConvMicrokernelTester() |
| 14065 | .cr(4) |
| 14066 | .kr(25) |
| 14067 | .channels(channels) |
| 14068 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14069 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14070 | } |
| 14071 | } |
| 14072 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14073 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14074 | TEST_REQUIRES_PSIMD; |
| 14075 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14076 | DWConvMicrokernelTester() |
| 14077 | .cr(4) |
| 14078 | .kr(25) |
| 14079 | .channels(channels) |
| 14080 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14081 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14082 | } |
| 14083 | } |
| 14084 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14085 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14086 | TEST_REQUIRES_PSIMD; |
| 14087 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14088 | for (size_t step = 2; step <= 25; step++) { |
| 14089 | DWConvMicrokernelTester() |
| 14090 | .cr(4) |
| 14091 | .kr(25) |
| 14092 | .channels(channels) |
| 14093 | .width(3) |
| 14094 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14095 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14096 | } |
| 14097 | } |
| 14098 | } |
| 14099 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14100 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14101 | TEST_REQUIRES_PSIMD; |
| 14102 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14103 | DWConvMicrokernelTester() |
| 14104 | .cr(4) |
| 14105 | .kr(25) |
| 14106 | .channels(4) |
| 14107 | .width(5) |
| 14108 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14109 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14110 | } |
| 14111 | } |
| 14112 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14113 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14114 | TEST_REQUIRES_PSIMD; |
| 14115 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14116 | DWConvMicrokernelTester() |
| 14117 | .cr(4) |
| 14118 | .kr(25) |
| 14119 | .channels(channels) |
| 14120 | .width(3) |
| 14121 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14122 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14123 | } |
| 14124 | } |
| 14125 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14126 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14127 | TEST_REQUIRES_PSIMD; |
| 14128 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14129 | DWConvMicrokernelTester() |
| 14130 | .cr(4) |
| 14131 | .kr(25) |
| 14132 | .channels(channels) |
| 14133 | .width(3) |
| 14134 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14135 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14136 | } |
| 14137 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 14138 | |
| 14139 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, input_offset) { |
| 14140 | TEST_REQUIRES_PSIMD; |
| 14141 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14142 | DWConvMicrokernelTester() |
| 14143 | .cr(4) |
| 14144 | .kr(25) |
| 14145 | .channels(channels) |
| 14146 | .input_offset(112) |
| 14147 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 14148 | } |
| 14149 | } |
| 14150 | |
| 14151 | TEST(F32_DWCONV_MINMAX_UP4X25__PSIMD_ACC2, zero) { |
| 14152 | TEST_REQUIRES_PSIMD; |
| 14153 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 14154 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14155 | DWConvMicrokernelTester() |
| 14156 | .cr(4) |
| 14157 | .kr(25) |
| 14158 | .channels(channels) |
| 14159 | .input_offset(112) |
| 14160 | .zero_index(mz) |
| 14161 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 14162 | } |
| 14163 | } |
| 14164 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14165 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14166 | |
| 14167 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14168 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14169 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14170 | TEST_REQUIRES_PSIMD; |
| 14171 | DWConvMicrokernelTester() |
| 14172 | .cr(8) |
| 14173 | .kr(25) |
| 14174 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14175 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14176 | } |
| 14177 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14178 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14179 | TEST_REQUIRES_PSIMD; |
| 14180 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14181 | DWConvMicrokernelTester() |
| 14182 | .cr(8) |
| 14183 | .kr(25) |
| 14184 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14185 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14186 | } |
| 14187 | } |
| 14188 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14189 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14190 | TEST_REQUIRES_PSIMD; |
| 14191 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14192 | DWConvMicrokernelTester() |
| 14193 | .cr(8) |
| 14194 | .kr(25) |
| 14195 | .channels(channels) |
| 14196 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14197 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14198 | } |
| 14199 | } |
| 14200 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14201 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14202 | TEST_REQUIRES_PSIMD; |
| 14203 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14204 | DWConvMicrokernelTester() |
| 14205 | .cr(8) |
| 14206 | .kr(25) |
| 14207 | .channels(channels) |
| 14208 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14209 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14210 | } |
| 14211 | } |
| 14212 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14213 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14214 | TEST_REQUIRES_PSIMD; |
| 14215 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 14216 | DWConvMicrokernelTester() |
| 14217 | .cr(8) |
| 14218 | .kr(25) |
| 14219 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14220 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14221 | } |
| 14222 | } |
| 14223 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14224 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14225 | TEST_REQUIRES_PSIMD; |
| 14226 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14227 | DWConvMicrokernelTester() |
| 14228 | .cr(8) |
| 14229 | .kr(25) |
| 14230 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14231 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14232 | } |
| 14233 | } |
| 14234 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14235 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14236 | TEST_REQUIRES_PSIMD; |
| 14237 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14238 | DWConvMicrokernelTester() |
| 14239 | .cr(8) |
| 14240 | .kr(25) |
| 14241 | .channels(channels) |
| 14242 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14243 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14244 | } |
| 14245 | } |
| 14246 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14247 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14248 | TEST_REQUIRES_PSIMD; |
| 14249 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14250 | DWConvMicrokernelTester() |
| 14251 | .cr(8) |
| 14252 | .kr(25) |
| 14253 | .channels(channels) |
| 14254 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14255 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14256 | } |
| 14257 | } |
| 14258 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14259 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14260 | TEST_REQUIRES_PSIMD; |
| 14261 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14262 | DWConvMicrokernelTester() |
| 14263 | .cr(8) |
| 14264 | .kr(25) |
| 14265 | .channels(channels) |
| 14266 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14267 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14268 | } |
| 14269 | } |
| 14270 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14271 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14272 | TEST_REQUIRES_PSIMD; |
| 14273 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14274 | for (size_t step = 2; step <= 25; step++) { |
| 14275 | DWConvMicrokernelTester() |
| 14276 | .cr(8) |
| 14277 | .kr(25) |
| 14278 | .channels(channels) |
| 14279 | .width(3) |
| 14280 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14281 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14282 | } |
| 14283 | } |
| 14284 | } |
| 14285 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14286 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14287 | TEST_REQUIRES_PSIMD; |
| 14288 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14289 | DWConvMicrokernelTester() |
| 14290 | .cr(8) |
| 14291 | .kr(25) |
| 14292 | .channels(8) |
| 14293 | .width(5) |
| 14294 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14295 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14296 | } |
| 14297 | } |
| 14298 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14299 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14300 | TEST_REQUIRES_PSIMD; |
| 14301 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14302 | DWConvMicrokernelTester() |
| 14303 | .cr(8) |
| 14304 | .kr(25) |
| 14305 | .channels(channels) |
| 14306 | .width(3) |
| 14307 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14308 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14309 | } |
| 14310 | } |
| 14311 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14312 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14313 | TEST_REQUIRES_PSIMD; |
| 14314 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14315 | DWConvMicrokernelTester() |
| 14316 | .cr(8) |
| 14317 | .kr(25) |
| 14318 | .channels(channels) |
| 14319 | .width(3) |
| 14320 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14321 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14322 | } |
| 14323 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 14324 | |
| 14325 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, input_offset) { |
| 14326 | TEST_REQUIRES_PSIMD; |
| 14327 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14328 | DWConvMicrokernelTester() |
| 14329 | .cr(8) |
| 14330 | .kr(25) |
| 14331 | .channels(channels) |
| 14332 | .input_offset(176) |
| 14333 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 14334 | } |
| 14335 | } |
| 14336 | |
| 14337 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD, zero) { |
| 14338 | TEST_REQUIRES_PSIMD; |
| 14339 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 14340 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14341 | DWConvMicrokernelTester() |
| 14342 | .cr(8) |
| 14343 | .kr(25) |
| 14344 | .channels(channels) |
| 14345 | .input_offset(176) |
| 14346 | .zero_index(mz) |
| 14347 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 14348 | } |
| 14349 | } |
| 14350 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14351 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14352 | |
| 14353 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14354 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14355 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14356 | TEST_REQUIRES_PSIMD; |
| 14357 | DWConvMicrokernelTester() |
| 14358 | .cr(8) |
| 14359 | .kr(25) |
| 14360 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14361 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14362 | } |
| 14363 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14364 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14365 | TEST_REQUIRES_PSIMD; |
| 14366 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14367 | DWConvMicrokernelTester() |
| 14368 | .cr(8) |
| 14369 | .kr(25) |
| 14370 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14371 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14372 | } |
| 14373 | } |
| 14374 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14375 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14376 | TEST_REQUIRES_PSIMD; |
| 14377 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14378 | DWConvMicrokernelTester() |
| 14379 | .cr(8) |
| 14380 | .kr(25) |
| 14381 | .channels(channels) |
| 14382 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14383 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14384 | } |
| 14385 | } |
| 14386 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14387 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14388 | TEST_REQUIRES_PSIMD; |
| 14389 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14390 | DWConvMicrokernelTester() |
| 14391 | .cr(8) |
| 14392 | .kr(25) |
| 14393 | .channels(channels) |
| 14394 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14395 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14396 | } |
| 14397 | } |
| 14398 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14399 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14400 | TEST_REQUIRES_PSIMD; |
| 14401 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 14402 | DWConvMicrokernelTester() |
| 14403 | .cr(8) |
| 14404 | .kr(25) |
| 14405 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14406 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14407 | } |
| 14408 | } |
| 14409 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14410 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14411 | TEST_REQUIRES_PSIMD; |
| 14412 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14413 | DWConvMicrokernelTester() |
| 14414 | .cr(8) |
| 14415 | .kr(25) |
| 14416 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14417 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14418 | } |
| 14419 | } |
| 14420 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14421 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14422 | TEST_REQUIRES_PSIMD; |
| 14423 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14424 | DWConvMicrokernelTester() |
| 14425 | .cr(8) |
| 14426 | .kr(25) |
| 14427 | .channels(channels) |
| 14428 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14429 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14430 | } |
| 14431 | } |
| 14432 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14433 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14434 | TEST_REQUIRES_PSIMD; |
| 14435 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14436 | DWConvMicrokernelTester() |
| 14437 | .cr(8) |
| 14438 | .kr(25) |
| 14439 | .channels(channels) |
| 14440 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14441 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14442 | } |
| 14443 | } |
| 14444 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14445 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14446 | TEST_REQUIRES_PSIMD; |
| 14447 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14448 | DWConvMicrokernelTester() |
| 14449 | .cr(8) |
| 14450 | .kr(25) |
| 14451 | .channels(channels) |
| 14452 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14453 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14454 | } |
| 14455 | } |
| 14456 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14457 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14458 | TEST_REQUIRES_PSIMD; |
| 14459 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14460 | for (size_t step = 2; step <= 25; step++) { |
| 14461 | DWConvMicrokernelTester() |
| 14462 | .cr(8) |
| 14463 | .kr(25) |
| 14464 | .channels(channels) |
| 14465 | .width(3) |
| 14466 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14467 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14468 | } |
| 14469 | } |
| 14470 | } |
| 14471 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14472 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14473 | TEST_REQUIRES_PSIMD; |
| 14474 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14475 | DWConvMicrokernelTester() |
| 14476 | .cr(8) |
| 14477 | .kr(25) |
| 14478 | .channels(8) |
| 14479 | .width(5) |
| 14480 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14481 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14482 | } |
| 14483 | } |
| 14484 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14485 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14486 | TEST_REQUIRES_PSIMD; |
| 14487 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14488 | DWConvMicrokernelTester() |
| 14489 | .cr(8) |
| 14490 | .kr(25) |
| 14491 | .channels(channels) |
| 14492 | .width(3) |
| 14493 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14494 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14495 | } |
| 14496 | } |
| 14497 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14498 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14499 | TEST_REQUIRES_PSIMD; |
| 14500 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 14501 | DWConvMicrokernelTester() |
| 14502 | .cr(8) |
| 14503 | .kr(25) |
| 14504 | .channels(channels) |
| 14505 | .width(3) |
| 14506 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14507 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14508 | } |
| 14509 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 14510 | |
| 14511 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, input_offset) { |
| 14512 | TEST_REQUIRES_PSIMD; |
| 14513 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14514 | DWConvMicrokernelTester() |
| 14515 | .cr(8) |
| 14516 | .kr(25) |
| 14517 | .channels(channels) |
| 14518 | .input_offset(176) |
| 14519 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 14520 | } |
| 14521 | } |
| 14522 | |
| 14523 | TEST(F32_DWCONV_MINMAX_UP8X25__PSIMD_ACC2, zero) { |
| 14524 | TEST_REQUIRES_PSIMD; |
| 14525 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 14526 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14527 | DWConvMicrokernelTester() |
| 14528 | .cr(8) |
| 14529 | .kr(25) |
| 14530 | .channels(channels) |
| 14531 | .input_offset(176) |
| 14532 | .zero_index(mz) |
| 14533 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x25__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 14534 | } |
| 14535 | } |
| 14536 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14537 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14538 | |
| 14539 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14540 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14541 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14542 | TEST_REQUIRES_PSIMD; |
| 14543 | DWConvMicrokernelTester() |
| 14544 | .cr(4) |
| 14545 | .kr(9) |
| 14546 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14547 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14548 | } |
| 14549 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14550 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14551 | TEST_REQUIRES_PSIMD; |
| 14552 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14553 | DWConvMicrokernelTester() |
| 14554 | .cr(4) |
| 14555 | .kr(9) |
| 14556 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14557 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14558 | } |
| 14559 | } |
| 14560 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14561 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14562 | TEST_REQUIRES_PSIMD; |
| 14563 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14564 | DWConvMicrokernelTester() |
| 14565 | .cr(4) |
| 14566 | .kr(9) |
| 14567 | .channels(channels) |
| 14568 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14569 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14570 | } |
| 14571 | } |
| 14572 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14573 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14574 | TEST_REQUIRES_PSIMD; |
| 14575 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14576 | DWConvMicrokernelTester() |
| 14577 | .cr(4) |
| 14578 | .kr(9) |
| 14579 | .channels(channels) |
| 14580 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14581 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14582 | } |
| 14583 | } |
| 14584 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14585 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14586 | TEST_REQUIRES_PSIMD; |
| 14587 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 14588 | DWConvMicrokernelTester() |
| 14589 | .cr(4) |
| 14590 | .kr(9) |
| 14591 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14592 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14593 | } |
| 14594 | } |
| 14595 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14596 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14597 | TEST_REQUIRES_PSIMD; |
| 14598 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14599 | DWConvMicrokernelTester() |
| 14600 | .cr(4) |
| 14601 | .kr(9) |
| 14602 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14603 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14604 | } |
| 14605 | } |
| 14606 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14607 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14608 | TEST_REQUIRES_PSIMD; |
| 14609 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14610 | DWConvMicrokernelTester() |
| 14611 | .cr(4) |
| 14612 | .kr(9) |
| 14613 | .channels(channels) |
| 14614 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14615 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14616 | } |
| 14617 | } |
| 14618 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14619 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14620 | TEST_REQUIRES_PSIMD; |
| 14621 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14622 | DWConvMicrokernelTester() |
| 14623 | .cr(4) |
| 14624 | .kr(9) |
| 14625 | .channels(channels) |
| 14626 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14627 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14628 | } |
| 14629 | } |
| 14630 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14631 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14632 | TEST_REQUIRES_PSIMD; |
| 14633 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14634 | DWConvMicrokernelTester() |
| 14635 | .cr(4) |
| 14636 | .kr(9) |
| 14637 | .channels(channels) |
| 14638 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14639 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14640 | } |
| 14641 | } |
| 14642 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14643 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14644 | TEST_REQUIRES_PSIMD; |
| 14645 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14646 | for (size_t step = 2; step <= 9; step++) { |
| 14647 | DWConvMicrokernelTester() |
| 14648 | .cr(4) |
| 14649 | .kr(9) |
| 14650 | .channels(channels) |
| 14651 | .width(3) |
| 14652 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14653 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14654 | } |
| 14655 | } |
| 14656 | } |
| 14657 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14658 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14659 | TEST_REQUIRES_PSIMD; |
| 14660 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14661 | DWConvMicrokernelTester() |
| 14662 | .cr(4) |
| 14663 | .kr(9) |
| 14664 | .channels(4) |
| 14665 | .width(5) |
| 14666 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14667 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14668 | } |
| 14669 | } |
| 14670 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14671 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14672 | TEST_REQUIRES_PSIMD; |
| 14673 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14674 | DWConvMicrokernelTester() |
| 14675 | .cr(4) |
| 14676 | .kr(9) |
| 14677 | .channels(channels) |
| 14678 | .width(3) |
| 14679 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14680 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14681 | } |
| 14682 | } |
| 14683 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14684 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14685 | TEST_REQUIRES_PSIMD; |
| 14686 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14687 | DWConvMicrokernelTester() |
| 14688 | .cr(4) |
| 14689 | .kr(9) |
| 14690 | .channels(channels) |
| 14691 | .width(3) |
| 14692 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14693 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14694 | } |
| 14695 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 14696 | |
| 14697 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, input_offset) { |
| 14698 | TEST_REQUIRES_PSIMD; |
| 14699 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14700 | DWConvMicrokernelTester() |
| 14701 | .cr(4) |
| 14702 | .kr(9) |
| 14703 | .channels(channels) |
| 14704 | .input_offset(112) |
| 14705 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 14706 | } |
| 14707 | } |
| 14708 | |
| 14709 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD, zero) { |
| 14710 | TEST_REQUIRES_PSIMD; |
| 14711 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 14712 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14713 | DWConvMicrokernelTester() |
| 14714 | .cr(4) |
| 14715 | .kr(9) |
| 14716 | .channels(channels) |
| 14717 | .input_offset(112) |
| 14718 | .zero_index(mz) |
| 14719 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 14720 | } |
| 14721 | } |
| 14722 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14723 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14724 | |
| 14725 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14726 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14727 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14728 | TEST_REQUIRES_PSIMD; |
| 14729 | DWConvMicrokernelTester() |
| 14730 | .cr(4) |
| 14731 | .kr(9) |
| 14732 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14733 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14734 | } |
| 14735 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14736 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14737 | TEST_REQUIRES_PSIMD; |
| 14738 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14739 | DWConvMicrokernelTester() |
| 14740 | .cr(4) |
| 14741 | .kr(9) |
| 14742 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14743 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14744 | } |
| 14745 | } |
| 14746 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14747 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14748 | TEST_REQUIRES_PSIMD; |
| 14749 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14750 | DWConvMicrokernelTester() |
| 14751 | .cr(4) |
| 14752 | .kr(9) |
| 14753 | .channels(channels) |
| 14754 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14755 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14756 | } |
| 14757 | } |
| 14758 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14759 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14760 | TEST_REQUIRES_PSIMD; |
| 14761 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14762 | DWConvMicrokernelTester() |
| 14763 | .cr(4) |
| 14764 | .kr(9) |
| 14765 | .channels(channels) |
| 14766 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14767 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14768 | } |
| 14769 | } |
| 14770 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14771 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14772 | TEST_REQUIRES_PSIMD; |
| 14773 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 14774 | DWConvMicrokernelTester() |
| 14775 | .cr(4) |
| 14776 | .kr(9) |
| 14777 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14778 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14779 | } |
| 14780 | } |
| 14781 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14782 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14783 | TEST_REQUIRES_PSIMD; |
| 14784 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14785 | DWConvMicrokernelTester() |
| 14786 | .cr(4) |
| 14787 | .kr(9) |
| 14788 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14789 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14790 | } |
| 14791 | } |
| 14792 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14793 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14794 | TEST_REQUIRES_PSIMD; |
| 14795 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14796 | DWConvMicrokernelTester() |
| 14797 | .cr(4) |
| 14798 | .kr(9) |
| 14799 | .channels(channels) |
| 14800 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14801 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14802 | } |
| 14803 | } |
| 14804 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14805 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14806 | TEST_REQUIRES_PSIMD; |
| 14807 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 14808 | DWConvMicrokernelTester() |
| 14809 | .cr(4) |
| 14810 | .kr(9) |
| 14811 | .channels(channels) |
| 14812 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14813 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14814 | } |
| 14815 | } |
| 14816 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14817 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14818 | TEST_REQUIRES_PSIMD; |
| 14819 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14820 | DWConvMicrokernelTester() |
| 14821 | .cr(4) |
| 14822 | .kr(9) |
| 14823 | .channels(channels) |
| 14824 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14825 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14826 | } |
| 14827 | } |
| 14828 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14829 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14830 | TEST_REQUIRES_PSIMD; |
| 14831 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14832 | for (size_t step = 2; step <= 9; step++) { |
| 14833 | DWConvMicrokernelTester() |
| 14834 | .cr(4) |
| 14835 | .kr(9) |
| 14836 | .channels(channels) |
| 14837 | .width(3) |
| 14838 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14839 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14840 | } |
| 14841 | } |
| 14842 | } |
| 14843 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14844 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14845 | TEST_REQUIRES_PSIMD; |
| 14846 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14847 | DWConvMicrokernelTester() |
| 14848 | .cr(4) |
| 14849 | .kr(9) |
| 14850 | .channels(4) |
| 14851 | .width(5) |
| 14852 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14853 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14854 | } |
| 14855 | } |
| 14856 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14857 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14858 | TEST_REQUIRES_PSIMD; |
| 14859 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14860 | DWConvMicrokernelTester() |
| 14861 | .cr(4) |
| 14862 | .kr(9) |
| 14863 | .channels(channels) |
| 14864 | .width(3) |
| 14865 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14866 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14867 | } |
| 14868 | } |
| 14869 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14870 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14871 | TEST_REQUIRES_PSIMD; |
| 14872 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 14873 | DWConvMicrokernelTester() |
| 14874 | .cr(4) |
| 14875 | .kr(9) |
| 14876 | .channels(channels) |
| 14877 | .width(3) |
| 14878 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14879 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14880 | } |
| 14881 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 14882 | |
| 14883 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, input_offset) { |
| 14884 | TEST_REQUIRES_PSIMD; |
| 14885 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14886 | DWConvMicrokernelTester() |
| 14887 | .cr(4) |
| 14888 | .kr(9) |
| 14889 | .channels(channels) |
| 14890 | .input_offset(112) |
| 14891 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 14892 | } |
| 14893 | } |
| 14894 | |
| 14895 | TEST(F32_DWCONV_MINMAX_UP4X9__PSIMD_ACC2, zero) { |
| 14896 | TEST_REQUIRES_PSIMD; |
| 14897 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 14898 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 14899 | DWConvMicrokernelTester() |
| 14900 | .cr(4) |
| 14901 | .kr(9) |
| 14902 | .channels(channels) |
| 14903 | .input_offset(112) |
| 14904 | .zero_index(mz) |
| 14905 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 14906 | } |
| 14907 | } |
| 14908 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14909 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14910 | |
| 14911 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 14912 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14913 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14914 | TEST_REQUIRES_PSIMD; |
| 14915 | DWConvMicrokernelTester() |
| 14916 | .cr(8) |
| 14917 | .kr(9) |
| 14918 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14919 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14920 | } |
| 14921 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14922 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14923 | TEST_REQUIRES_PSIMD; |
| 14924 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14925 | DWConvMicrokernelTester() |
| 14926 | .cr(8) |
| 14927 | .kr(9) |
| 14928 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14929 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14930 | } |
| 14931 | } |
| 14932 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14933 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14934 | TEST_REQUIRES_PSIMD; |
| 14935 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14936 | DWConvMicrokernelTester() |
| 14937 | .cr(8) |
| 14938 | .kr(9) |
| 14939 | .channels(channels) |
| 14940 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14941 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14942 | } |
| 14943 | } |
| 14944 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14945 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14946 | TEST_REQUIRES_PSIMD; |
| 14947 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 14948 | DWConvMicrokernelTester() |
| 14949 | .cr(8) |
| 14950 | .kr(9) |
| 14951 | .channels(channels) |
| 14952 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14953 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14954 | } |
| 14955 | } |
| 14956 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14957 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14958 | TEST_REQUIRES_PSIMD; |
| 14959 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 14960 | DWConvMicrokernelTester() |
| 14961 | .cr(8) |
| 14962 | .kr(9) |
| 14963 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14964 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14965 | } |
| 14966 | } |
| 14967 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14968 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14969 | TEST_REQUIRES_PSIMD; |
| 14970 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14971 | DWConvMicrokernelTester() |
| 14972 | .cr(8) |
| 14973 | .kr(9) |
| 14974 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14975 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14976 | } |
| 14977 | } |
| 14978 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14979 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14980 | TEST_REQUIRES_PSIMD; |
| 14981 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14982 | DWConvMicrokernelTester() |
| 14983 | .cr(8) |
| 14984 | .kr(9) |
| 14985 | .channels(channels) |
| 14986 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14987 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14988 | } |
| 14989 | } |
| 14990 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14991 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 14992 | TEST_REQUIRES_PSIMD; |
| 14993 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 14994 | DWConvMicrokernelTester() |
| 14995 | .cr(8) |
| 14996 | .kr(9) |
| 14997 | .channels(channels) |
| 14998 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 14999 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15000 | } |
| 15001 | } |
| 15002 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15003 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15004 | TEST_REQUIRES_PSIMD; |
| 15005 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15006 | DWConvMicrokernelTester() |
| 15007 | .cr(8) |
| 15008 | .kr(9) |
| 15009 | .channels(channels) |
| 15010 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15011 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15012 | } |
| 15013 | } |
| 15014 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15015 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15016 | TEST_REQUIRES_PSIMD; |
| 15017 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15018 | for (size_t step = 2; step <= 9; step++) { |
| 15019 | DWConvMicrokernelTester() |
| 15020 | .cr(8) |
| 15021 | .kr(9) |
| 15022 | .channels(channels) |
| 15023 | .width(3) |
| 15024 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15025 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15026 | } |
| 15027 | } |
| 15028 | } |
| 15029 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15030 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15031 | TEST_REQUIRES_PSIMD; |
| 15032 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15033 | DWConvMicrokernelTester() |
| 15034 | .cr(8) |
| 15035 | .kr(9) |
| 15036 | .channels(8) |
| 15037 | .width(5) |
| 15038 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15039 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15040 | } |
| 15041 | } |
| 15042 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15043 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15044 | TEST_REQUIRES_PSIMD; |
| 15045 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15046 | DWConvMicrokernelTester() |
| 15047 | .cr(8) |
| 15048 | .kr(9) |
| 15049 | .channels(channels) |
| 15050 | .width(3) |
| 15051 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15052 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15053 | } |
| 15054 | } |
| 15055 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15056 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15057 | TEST_REQUIRES_PSIMD; |
| 15058 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15059 | DWConvMicrokernelTester() |
| 15060 | .cr(8) |
| 15061 | .kr(9) |
| 15062 | .channels(channels) |
| 15063 | .width(3) |
| 15064 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15065 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15066 | } |
| 15067 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 15068 | |
| 15069 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, input_offset) { |
| 15070 | TEST_REQUIRES_PSIMD; |
| 15071 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15072 | DWConvMicrokernelTester() |
| 15073 | .cr(8) |
| 15074 | .kr(9) |
| 15075 | .channels(channels) |
| 15076 | .input_offset(176) |
| 15077 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 15078 | } |
| 15079 | } |
| 15080 | |
| 15081 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD, zero) { |
| 15082 | TEST_REQUIRES_PSIMD; |
| 15083 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 15084 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15085 | DWConvMicrokernelTester() |
| 15086 | .cr(8) |
| 15087 | .kr(9) |
| 15088 | .channels(channels) |
| 15089 | .input_offset(176) |
| 15090 | .zero_index(mz) |
| 15091 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 15092 | } |
| 15093 | } |
| 15094 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15095 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15096 | |
| 15097 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15098 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15099 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15100 | TEST_REQUIRES_PSIMD; |
| 15101 | DWConvMicrokernelTester() |
| 15102 | .cr(8) |
| 15103 | .kr(9) |
| 15104 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15105 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15106 | } |
| 15107 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15108 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15109 | TEST_REQUIRES_PSIMD; |
| 15110 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15111 | DWConvMicrokernelTester() |
| 15112 | .cr(8) |
| 15113 | .kr(9) |
| 15114 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15115 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15116 | } |
| 15117 | } |
| 15118 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15119 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15120 | TEST_REQUIRES_PSIMD; |
| 15121 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15122 | DWConvMicrokernelTester() |
| 15123 | .cr(8) |
| 15124 | .kr(9) |
| 15125 | .channels(channels) |
| 15126 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15127 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15128 | } |
| 15129 | } |
| 15130 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15131 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15132 | TEST_REQUIRES_PSIMD; |
| 15133 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15134 | DWConvMicrokernelTester() |
| 15135 | .cr(8) |
| 15136 | .kr(9) |
| 15137 | .channels(channels) |
| 15138 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15139 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15140 | } |
| 15141 | } |
| 15142 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15143 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15144 | TEST_REQUIRES_PSIMD; |
| 15145 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 15146 | DWConvMicrokernelTester() |
| 15147 | .cr(8) |
| 15148 | .kr(9) |
| 15149 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15150 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15151 | } |
| 15152 | } |
| 15153 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15154 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15155 | TEST_REQUIRES_PSIMD; |
| 15156 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15157 | DWConvMicrokernelTester() |
| 15158 | .cr(8) |
| 15159 | .kr(9) |
| 15160 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15161 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15162 | } |
| 15163 | } |
| 15164 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15165 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15166 | TEST_REQUIRES_PSIMD; |
| 15167 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15168 | DWConvMicrokernelTester() |
| 15169 | .cr(8) |
| 15170 | .kr(9) |
| 15171 | .channels(channels) |
| 15172 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15173 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15174 | } |
| 15175 | } |
| 15176 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15177 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15178 | TEST_REQUIRES_PSIMD; |
| 15179 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15180 | DWConvMicrokernelTester() |
| 15181 | .cr(8) |
| 15182 | .kr(9) |
| 15183 | .channels(channels) |
| 15184 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15185 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15186 | } |
| 15187 | } |
| 15188 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15189 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15190 | TEST_REQUIRES_PSIMD; |
| 15191 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15192 | DWConvMicrokernelTester() |
| 15193 | .cr(8) |
| 15194 | .kr(9) |
| 15195 | .channels(channels) |
| 15196 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15197 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15198 | } |
| 15199 | } |
| 15200 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15201 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15202 | TEST_REQUIRES_PSIMD; |
| 15203 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15204 | for (size_t step = 2; step <= 9; step++) { |
| 15205 | DWConvMicrokernelTester() |
| 15206 | .cr(8) |
| 15207 | .kr(9) |
| 15208 | .channels(channels) |
| 15209 | .width(3) |
| 15210 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15211 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15212 | } |
| 15213 | } |
| 15214 | } |
| 15215 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15216 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15217 | TEST_REQUIRES_PSIMD; |
| 15218 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15219 | DWConvMicrokernelTester() |
| 15220 | .cr(8) |
| 15221 | .kr(9) |
| 15222 | .channels(8) |
| 15223 | .width(5) |
| 15224 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15225 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15226 | } |
| 15227 | } |
| 15228 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15229 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15230 | TEST_REQUIRES_PSIMD; |
| 15231 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15232 | DWConvMicrokernelTester() |
| 15233 | .cr(8) |
| 15234 | .kr(9) |
| 15235 | .channels(channels) |
| 15236 | .width(3) |
| 15237 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15238 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15239 | } |
| 15240 | } |
| 15241 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15242 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15243 | TEST_REQUIRES_PSIMD; |
| 15244 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15245 | DWConvMicrokernelTester() |
| 15246 | .cr(8) |
| 15247 | .kr(9) |
| 15248 | .channels(channels) |
| 15249 | .width(3) |
| 15250 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15251 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15252 | } |
| 15253 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 15254 | |
| 15255 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, input_offset) { |
| 15256 | TEST_REQUIRES_PSIMD; |
| 15257 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15258 | DWConvMicrokernelTester() |
| 15259 | .cr(8) |
| 15260 | .kr(9) |
| 15261 | .channels(channels) |
| 15262 | .input_offset(176) |
| 15263 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 15264 | } |
| 15265 | } |
| 15266 | |
| 15267 | TEST(F32_DWCONV_MINMAX_UP8X9__PSIMD_ACC2, zero) { |
| 15268 | TEST_REQUIRES_PSIMD; |
| 15269 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 15270 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15271 | DWConvMicrokernelTester() |
| 15272 | .cr(8) |
| 15273 | .kr(9) |
| 15274 | .channels(channels) |
| 15275 | .input_offset(176) |
| 15276 | .zero_index(mz) |
| 15277 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x9__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 15278 | } |
| 15279 | } |
| 15280 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15281 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15282 | |
| 15283 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15284 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15285 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15286 | TEST_REQUIRES_PSIMD; |
| 15287 | DWConvMicrokernelTester() |
| 15288 | .cr(4) |
| 15289 | .kr(4) |
| 15290 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15291 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15292 | } |
| 15293 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15294 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15295 | TEST_REQUIRES_PSIMD; |
| 15296 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15297 | DWConvMicrokernelTester() |
| 15298 | .cr(4) |
| 15299 | .kr(4) |
| 15300 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15301 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15302 | } |
| 15303 | } |
| 15304 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15305 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15306 | TEST_REQUIRES_PSIMD; |
| 15307 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15308 | DWConvMicrokernelTester() |
| 15309 | .cr(4) |
| 15310 | .kr(4) |
| 15311 | .channels(channels) |
| 15312 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15313 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15314 | } |
| 15315 | } |
| 15316 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15317 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15318 | TEST_REQUIRES_PSIMD; |
| 15319 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15320 | DWConvMicrokernelTester() |
| 15321 | .cr(4) |
| 15322 | .kr(4) |
| 15323 | .channels(channels) |
| 15324 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15325 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15326 | } |
| 15327 | } |
| 15328 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15329 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15330 | TEST_REQUIRES_PSIMD; |
| 15331 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 15332 | DWConvMicrokernelTester() |
| 15333 | .cr(4) |
| 15334 | .kr(4) |
| 15335 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15336 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15337 | } |
| 15338 | } |
| 15339 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15340 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15341 | TEST_REQUIRES_PSIMD; |
| 15342 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 15343 | DWConvMicrokernelTester() |
| 15344 | .cr(4) |
| 15345 | .kr(4) |
| 15346 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15347 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15348 | } |
| 15349 | } |
| 15350 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15351 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15352 | TEST_REQUIRES_PSIMD; |
| 15353 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 15354 | DWConvMicrokernelTester() |
| 15355 | .cr(4) |
| 15356 | .kr(4) |
| 15357 | .channels(channels) |
| 15358 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15359 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15360 | } |
| 15361 | } |
| 15362 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15363 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15364 | TEST_REQUIRES_PSIMD; |
| 15365 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 15366 | DWConvMicrokernelTester() |
| 15367 | .cr(4) |
| 15368 | .kr(4) |
| 15369 | .channels(channels) |
| 15370 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15371 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15372 | } |
| 15373 | } |
| 15374 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15375 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15376 | TEST_REQUIRES_PSIMD; |
| 15377 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15378 | DWConvMicrokernelTester() |
| 15379 | .cr(4) |
| 15380 | .kr(4) |
| 15381 | .channels(channels) |
| 15382 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15383 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15384 | } |
| 15385 | } |
| 15386 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15387 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15388 | TEST_REQUIRES_PSIMD; |
| 15389 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15390 | for (size_t step = 2; step <= 4; step++) { |
| 15391 | DWConvMicrokernelTester() |
| 15392 | .cr(4) |
| 15393 | .kr(4) |
| 15394 | .channels(channels) |
| 15395 | .width(3) |
| 15396 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15397 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15398 | } |
| 15399 | } |
| 15400 | } |
| 15401 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15402 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15403 | TEST_REQUIRES_PSIMD; |
| 15404 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15405 | DWConvMicrokernelTester() |
| 15406 | .cr(4) |
| 15407 | .kr(4) |
| 15408 | .channels(4) |
| 15409 | .width(5) |
| 15410 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15411 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15412 | } |
| 15413 | } |
| 15414 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15415 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15416 | TEST_REQUIRES_PSIMD; |
| 15417 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15418 | DWConvMicrokernelTester() |
| 15419 | .cr(4) |
| 15420 | .kr(4) |
| 15421 | .channels(channels) |
| 15422 | .width(3) |
| 15423 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15424 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15425 | } |
| 15426 | } |
| 15427 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15428 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15429 | TEST_REQUIRES_PSIMD; |
| 15430 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15431 | DWConvMicrokernelTester() |
| 15432 | .cr(4) |
| 15433 | .kr(4) |
| 15434 | .channels(channels) |
| 15435 | .width(3) |
| 15436 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15437 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15438 | } |
| 15439 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 15440 | |
| 15441 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, input_offset) { |
| 15442 | TEST_REQUIRES_PSIMD; |
| 15443 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15444 | DWConvMicrokernelTester() |
| 15445 | .cr(4) |
| 15446 | .kr(4) |
| 15447 | .channels(channels) |
| 15448 | .input_offset(112) |
| 15449 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 15450 | } |
| 15451 | } |
| 15452 | |
| 15453 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD, zero) { |
| 15454 | TEST_REQUIRES_PSIMD; |
| 15455 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 15456 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15457 | DWConvMicrokernelTester() |
| 15458 | .cr(4) |
| 15459 | .kr(4) |
| 15460 | .channels(channels) |
| 15461 | .input_offset(112) |
| 15462 | .zero_index(mz) |
| 15463 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 15464 | } |
| 15465 | } |
| 15466 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15467 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15468 | |
| 15469 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15470 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15471 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_eq_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15472 | TEST_REQUIRES_PSIMD; |
| 15473 | DWConvMicrokernelTester() |
| 15474 | .cr(4) |
| 15475 | .kr(4) |
| 15476 | .channels(4) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15477 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15478 | } |
| 15479 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15480 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_div_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15481 | TEST_REQUIRES_PSIMD; |
| 15482 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15483 | DWConvMicrokernelTester() |
| 15484 | .cr(4) |
| 15485 | .kr(4) |
| 15486 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15487 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15488 | } |
| 15489 | } |
| 15490 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15491 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_div_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15492 | TEST_REQUIRES_PSIMD; |
| 15493 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15494 | DWConvMicrokernelTester() |
| 15495 | .cr(4) |
| 15496 | .kr(4) |
| 15497 | .channels(channels) |
| 15498 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15499 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15500 | } |
| 15501 | } |
| 15502 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15503 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_div_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15504 | TEST_REQUIRES_PSIMD; |
| 15505 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15506 | DWConvMicrokernelTester() |
| 15507 | .cr(4) |
| 15508 | .kr(4) |
| 15509 | .channels(channels) |
| 15510 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15511 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15512 | } |
| 15513 | } |
| 15514 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15515 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_lt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15516 | TEST_REQUIRES_PSIMD; |
| 15517 | for (uint32_t channels = 1; channels < 4; channels++) { |
| 15518 | DWConvMicrokernelTester() |
| 15519 | .cr(4) |
| 15520 | .kr(4) |
| 15521 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15522 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15523 | } |
| 15524 | } |
| 15525 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15526 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_gt_4) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15527 | TEST_REQUIRES_PSIMD; |
| 15528 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 15529 | DWConvMicrokernelTester() |
| 15530 | .cr(4) |
| 15531 | .kr(4) |
| 15532 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15533 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15534 | } |
| 15535 | } |
| 15536 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15537 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_gt_4_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15538 | TEST_REQUIRES_PSIMD; |
| 15539 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 15540 | DWConvMicrokernelTester() |
| 15541 | .cr(4) |
| 15542 | .kr(4) |
| 15543 | .channels(channels) |
| 15544 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15545 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15546 | } |
| 15547 | } |
| 15548 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15549 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, c_gt_4_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15550 | TEST_REQUIRES_PSIMD; |
| 15551 | for (uint32_t channels = 5; channels < 8; channels++) { |
| 15552 | DWConvMicrokernelTester() |
| 15553 | .cr(4) |
| 15554 | .kr(4) |
| 15555 | .channels(channels) |
| 15556 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15557 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15558 | } |
| 15559 | } |
| 15560 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15561 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15562 | TEST_REQUIRES_PSIMD; |
| 15563 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15564 | DWConvMicrokernelTester() |
| 15565 | .cr(4) |
| 15566 | .kr(4) |
| 15567 | .channels(channels) |
| 15568 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15569 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15570 | } |
| 15571 | } |
| 15572 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15573 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15574 | TEST_REQUIRES_PSIMD; |
| 15575 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15576 | for (size_t step = 2; step <= 4; step++) { |
| 15577 | DWConvMicrokernelTester() |
| 15578 | .cr(4) |
| 15579 | .kr(4) |
| 15580 | .channels(channels) |
| 15581 | .width(3) |
| 15582 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15583 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15584 | } |
| 15585 | } |
| 15586 | } |
| 15587 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15588 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15589 | TEST_REQUIRES_PSIMD; |
| 15590 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15591 | DWConvMicrokernelTester() |
| 15592 | .cr(4) |
| 15593 | .kr(4) |
| 15594 | .channels(4) |
| 15595 | .width(5) |
| 15596 | .output_stride(23) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15597 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15598 | } |
| 15599 | } |
| 15600 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15601 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15602 | TEST_REQUIRES_PSIMD; |
| 15603 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15604 | DWConvMicrokernelTester() |
| 15605 | .cr(4) |
| 15606 | .kr(4) |
| 15607 | .channels(channels) |
| 15608 | .width(3) |
| 15609 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15610 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15611 | } |
| 15612 | } |
| 15613 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15614 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15615 | TEST_REQUIRES_PSIMD; |
| 15616 | for (size_t channels = 1; channels <= 20; channels += 3) { |
| 15617 | DWConvMicrokernelTester() |
| 15618 | .cr(4) |
| 15619 | .kr(4) |
| 15620 | .channels(channels) |
| 15621 | .width(3) |
| 15622 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15623 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15624 | } |
| 15625 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 15626 | |
| 15627 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, input_offset) { |
| 15628 | TEST_REQUIRES_PSIMD; |
| 15629 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15630 | DWConvMicrokernelTester() |
| 15631 | .cr(4) |
| 15632 | .kr(4) |
| 15633 | .channels(channels) |
| 15634 | .input_offset(112) |
| 15635 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 15636 | } |
| 15637 | } |
| 15638 | |
| 15639 | TEST(F32_DWCONV_MINMAX_UP4X4__PSIMD_ACC2, zero) { |
| 15640 | TEST_REQUIRES_PSIMD; |
| 15641 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 15642 | for (uint32_t channels = 8; channels < 64; channels += 12) { |
| 15643 | DWConvMicrokernelTester() |
| 15644 | .cr(4) |
| 15645 | .kr(4) |
| 15646 | .channels(channels) |
| 15647 | .input_offset(112) |
| 15648 | .zero_index(mz) |
| 15649 | .Test(xnn_f32_dwconv_minmax_ukernel_up4x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 15650 | } |
| 15651 | } |
| 15652 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15653 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15654 | |
| 15655 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15656 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15657 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15658 | TEST_REQUIRES_PSIMD; |
| 15659 | DWConvMicrokernelTester() |
| 15660 | .cr(8) |
| 15661 | .kr(4) |
| 15662 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15663 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15664 | } |
| 15665 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15666 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15667 | TEST_REQUIRES_PSIMD; |
| 15668 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15669 | DWConvMicrokernelTester() |
| 15670 | .cr(8) |
| 15671 | .kr(4) |
| 15672 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15673 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15674 | } |
| 15675 | } |
| 15676 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15677 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15678 | TEST_REQUIRES_PSIMD; |
| 15679 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15680 | DWConvMicrokernelTester() |
| 15681 | .cr(8) |
| 15682 | .kr(4) |
| 15683 | .channels(channels) |
| 15684 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15685 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15686 | } |
| 15687 | } |
| 15688 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15689 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15690 | TEST_REQUIRES_PSIMD; |
| 15691 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15692 | DWConvMicrokernelTester() |
| 15693 | .cr(8) |
| 15694 | .kr(4) |
| 15695 | .channels(channels) |
| 15696 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15697 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15698 | } |
| 15699 | } |
| 15700 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15701 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15702 | TEST_REQUIRES_PSIMD; |
| 15703 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 15704 | DWConvMicrokernelTester() |
| 15705 | .cr(8) |
| 15706 | .kr(4) |
| 15707 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15708 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15709 | } |
| 15710 | } |
| 15711 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15712 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15713 | TEST_REQUIRES_PSIMD; |
| 15714 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15715 | DWConvMicrokernelTester() |
| 15716 | .cr(8) |
| 15717 | .kr(4) |
| 15718 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15719 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15720 | } |
| 15721 | } |
| 15722 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15723 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15724 | TEST_REQUIRES_PSIMD; |
| 15725 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15726 | DWConvMicrokernelTester() |
| 15727 | .cr(8) |
| 15728 | .kr(4) |
| 15729 | .channels(channels) |
| 15730 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15731 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15732 | } |
| 15733 | } |
| 15734 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15735 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15736 | TEST_REQUIRES_PSIMD; |
| 15737 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15738 | DWConvMicrokernelTester() |
| 15739 | .cr(8) |
| 15740 | .kr(4) |
| 15741 | .channels(channels) |
| 15742 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15743 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15744 | } |
| 15745 | } |
| 15746 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15747 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15748 | TEST_REQUIRES_PSIMD; |
| 15749 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15750 | DWConvMicrokernelTester() |
| 15751 | .cr(8) |
| 15752 | .kr(4) |
| 15753 | .channels(channels) |
| 15754 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15755 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15756 | } |
| 15757 | } |
| 15758 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15759 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15760 | TEST_REQUIRES_PSIMD; |
| 15761 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15762 | for (size_t step = 2; step <= 4; step++) { |
| 15763 | DWConvMicrokernelTester() |
| 15764 | .cr(8) |
| 15765 | .kr(4) |
| 15766 | .channels(channels) |
| 15767 | .width(3) |
| 15768 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15769 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15770 | } |
| 15771 | } |
| 15772 | } |
| 15773 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15774 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15775 | TEST_REQUIRES_PSIMD; |
| 15776 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15777 | DWConvMicrokernelTester() |
| 15778 | .cr(8) |
| 15779 | .kr(4) |
| 15780 | .channels(8) |
| 15781 | .width(5) |
| 15782 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15783 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15784 | } |
| 15785 | } |
| 15786 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15787 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15788 | TEST_REQUIRES_PSIMD; |
| 15789 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15790 | DWConvMicrokernelTester() |
| 15791 | .cr(8) |
| 15792 | .kr(4) |
| 15793 | .channels(channels) |
| 15794 | .width(3) |
| 15795 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15796 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15797 | } |
| 15798 | } |
| 15799 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15800 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15801 | TEST_REQUIRES_PSIMD; |
| 15802 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15803 | DWConvMicrokernelTester() |
| 15804 | .cr(8) |
| 15805 | .kr(4) |
| 15806 | .channels(channels) |
| 15807 | .width(3) |
| 15808 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15809 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15810 | } |
| 15811 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 15812 | |
| 15813 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, input_offset) { |
| 15814 | TEST_REQUIRES_PSIMD; |
| 15815 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15816 | DWConvMicrokernelTester() |
| 15817 | .cr(8) |
| 15818 | .kr(4) |
| 15819 | .channels(channels) |
| 15820 | .input_offset(176) |
| 15821 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 15822 | } |
| 15823 | } |
| 15824 | |
| 15825 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD, zero) { |
| 15826 | TEST_REQUIRES_PSIMD; |
| 15827 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 15828 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15829 | DWConvMicrokernelTester() |
| 15830 | .cr(8) |
| 15831 | .kr(4) |
| 15832 | .channels(channels) |
| 15833 | .input_offset(176) |
| 15834 | .zero_index(mz) |
| 15835 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd, DWConvMicrokernelTester::Variant::Scalar); |
| 15836 | } |
| 15837 | } |
| 15838 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15839 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15840 | |
| 15841 | |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 15842 | #if !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15843 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_eq_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15844 | TEST_REQUIRES_PSIMD; |
| 15845 | DWConvMicrokernelTester() |
| 15846 | .cr(8) |
| 15847 | .kr(4) |
| 15848 | .channels(8) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15849 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15850 | } |
| 15851 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15852 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_div_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15853 | TEST_REQUIRES_PSIMD; |
| 15854 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15855 | DWConvMicrokernelTester() |
| 15856 | .cr(8) |
| 15857 | .kr(4) |
| 15858 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15859 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15860 | } |
| 15861 | } |
| 15862 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15863 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_div_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15864 | TEST_REQUIRES_PSIMD; |
| 15865 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15866 | DWConvMicrokernelTester() |
| 15867 | .cr(8) |
| 15868 | .kr(4) |
| 15869 | .channels(channels) |
| 15870 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15871 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15872 | } |
| 15873 | } |
| 15874 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15875 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_div_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15876 | TEST_REQUIRES_PSIMD; |
| 15877 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 15878 | DWConvMicrokernelTester() |
| 15879 | .cr(8) |
| 15880 | .kr(4) |
| 15881 | .channels(channels) |
| 15882 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15883 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15884 | } |
| 15885 | } |
| 15886 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15887 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_lt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15888 | TEST_REQUIRES_PSIMD; |
| 15889 | for (uint32_t channels = 1; channels < 8; channels++) { |
| 15890 | DWConvMicrokernelTester() |
| 15891 | .cr(8) |
| 15892 | .kr(4) |
| 15893 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15894 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15895 | } |
| 15896 | } |
| 15897 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15898 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_gt_8) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15899 | TEST_REQUIRES_PSIMD; |
| 15900 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15901 | DWConvMicrokernelTester() |
| 15902 | .cr(8) |
| 15903 | .kr(4) |
| 15904 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15905 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15906 | } |
| 15907 | } |
| 15908 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15909 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_gt_8_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15910 | TEST_REQUIRES_PSIMD; |
| 15911 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15912 | DWConvMicrokernelTester() |
| 15913 | .cr(8) |
| 15914 | .kr(4) |
| 15915 | .channels(channels) |
| 15916 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15917 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15918 | } |
| 15919 | } |
| 15920 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15921 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, c_gt_8_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15922 | TEST_REQUIRES_PSIMD; |
| 15923 | for (uint32_t channels = 9; channels < 16; channels++) { |
| 15924 | DWConvMicrokernelTester() |
| 15925 | .cr(8) |
| 15926 | .kr(4) |
| 15927 | .channels(channels) |
| 15928 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15929 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15930 | } |
| 15931 | } |
| 15932 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15933 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15934 | TEST_REQUIRES_PSIMD; |
| 15935 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15936 | DWConvMicrokernelTester() |
| 15937 | .cr(8) |
| 15938 | .kr(4) |
| 15939 | .channels(channels) |
| 15940 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15941 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15942 | } |
| 15943 | } |
| 15944 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15945 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15946 | TEST_REQUIRES_PSIMD; |
| 15947 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15948 | for (size_t step = 2; step <= 4; step++) { |
| 15949 | DWConvMicrokernelTester() |
| 15950 | .cr(8) |
| 15951 | .kr(4) |
| 15952 | .channels(channels) |
| 15953 | .width(3) |
| 15954 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15955 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15956 | } |
| 15957 | } |
| 15958 | } |
| 15959 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15960 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15961 | TEST_REQUIRES_PSIMD; |
| 15962 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15963 | DWConvMicrokernelTester() |
| 15964 | .cr(8) |
| 15965 | .kr(4) |
| 15966 | .channels(8) |
| 15967 | .width(5) |
| 15968 | .output_stride(43) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15969 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15970 | } |
| 15971 | } |
| 15972 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15973 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15974 | TEST_REQUIRES_PSIMD; |
| 15975 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15976 | DWConvMicrokernelTester() |
| 15977 | .cr(8) |
| 15978 | .kr(4) |
| 15979 | .channels(channels) |
| 15980 | .width(3) |
| 15981 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15982 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15983 | } |
| 15984 | } |
| 15985 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15986 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15987 | TEST_REQUIRES_PSIMD; |
| 15988 | for (size_t channels = 1; channels <= 40; channels += 7) { |
| 15989 | DWConvMicrokernelTester() |
| 15990 | .cr(8) |
| 15991 | .kr(4) |
| 15992 | .channels(channels) |
| 15993 | .width(3) |
| 15994 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 15995 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 15996 | } |
| 15997 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 15998 | |
| 15999 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, input_offset) { |
| 16000 | TEST_REQUIRES_PSIMD; |
| 16001 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 16002 | DWConvMicrokernelTester() |
| 16003 | .cr(8) |
| 16004 | .kr(4) |
| 16005 | .channels(channels) |
| 16006 | .input_offset(176) |
| 16007 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16008 | } |
| 16009 | } |
| 16010 | |
| 16011 | TEST(F32_DWCONV_MINMAX_UP8X4__PSIMD_ACC2, zero) { |
| 16012 | TEST_REQUIRES_PSIMD; |
| 16013 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 16014 | for (uint32_t channels = 16; channels < 128; channels += 24) { |
| 16015 | DWConvMicrokernelTester() |
| 16016 | .cr(8) |
| 16017 | .kr(4) |
| 16018 | .channels(channels) |
| 16019 | .input_offset(176) |
| 16020 | .zero_index(mz) |
| 16021 | .Test(xnn_f32_dwconv_minmax_ukernel_up8x4__psimd_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16022 | } |
| 16023 | } |
| 16024 | } |
Marat Dukhan | 29c6b26 | 2020-04-14 18:07:56 -0700 | [diff] [blame] | 16025 | #endif // !XNN_ARCH_ASMJS && !XNN_ARCH_WASM && !XNN_COMPILER_MSVC && !XNN_COMPILER_ICC |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16026 | |
| 16027 | |
| 16028 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16029 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16030 | DWConvMicrokernelTester() |
| 16031 | .cr(1) |
| 16032 | .kr(4) |
| 16033 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16034 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16035 | } |
| 16036 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16037 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16038 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16039 | DWConvMicrokernelTester() |
| 16040 | .cr(1) |
| 16041 | .kr(4) |
| 16042 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16043 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16044 | } |
| 16045 | } |
| 16046 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16047 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16048 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16049 | DWConvMicrokernelTester() |
| 16050 | .cr(1) |
| 16051 | .kr(4) |
| 16052 | .channels(channels) |
| 16053 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16054 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16055 | } |
| 16056 | } |
| 16057 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16058 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16059 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16060 | DWConvMicrokernelTester() |
| 16061 | .cr(1) |
| 16062 | .kr(4) |
| 16063 | .channels(channels) |
| 16064 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16065 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16066 | } |
| 16067 | } |
| 16068 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16069 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16070 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16071 | DWConvMicrokernelTester() |
| 16072 | .cr(1) |
| 16073 | .kr(4) |
| 16074 | .channels(channels) |
| 16075 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16076 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16077 | } |
| 16078 | } |
| 16079 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16080 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16081 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16082 | for (size_t step = 2; step <= 4; step++) { |
| 16083 | DWConvMicrokernelTester() |
| 16084 | .cr(1) |
| 16085 | .kr(4) |
| 16086 | .channels(channels) |
| 16087 | .width(3) |
| 16088 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16089 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16090 | } |
| 16091 | } |
| 16092 | } |
| 16093 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16094 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16095 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16096 | DWConvMicrokernelTester() |
| 16097 | .cr(1) |
| 16098 | .kr(4) |
| 16099 | .channels(1) |
| 16100 | .width(5) |
| 16101 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16102 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16103 | } |
| 16104 | } |
| 16105 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16106 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16107 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16108 | DWConvMicrokernelTester() |
| 16109 | .cr(1) |
| 16110 | .kr(4) |
| 16111 | .channels(channels) |
| 16112 | .width(3) |
| 16113 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16114 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16115 | } |
| 16116 | } |
| 16117 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16118 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16119 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16120 | DWConvMicrokernelTester() |
| 16121 | .cr(1) |
| 16122 | .kr(4) |
| 16123 | .channels(channels) |
| 16124 | .width(3) |
| 16125 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16126 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16127 | } |
| 16128 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 16129 | |
| 16130 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, input_offset) { |
| 16131 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16132 | DWConvMicrokernelTester() |
| 16133 | .cr(1) |
| 16134 | .kr(4) |
| 16135 | .channels(channels) |
| 16136 | .input_offset(48) |
| 16137 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 16138 | } |
| 16139 | } |
| 16140 | |
| 16141 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM, zero) { |
| 16142 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 16143 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16144 | DWConvMicrokernelTester() |
| 16145 | .cr(1) |
| 16146 | .kr(4) |
| 16147 | .channels(channels) |
| 16148 | .input_offset(48) |
| 16149 | .zero_index(mz) |
| 16150 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 16151 | } |
| 16152 | } |
| 16153 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16154 | #endif // XNN_ARCH_WASM |
| 16155 | |
| 16156 | |
| 16157 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16158 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16159 | DWConvMicrokernelTester() |
| 16160 | .cr(1) |
| 16161 | .kr(4) |
| 16162 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16163 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16164 | } |
| 16165 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16166 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16167 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16168 | DWConvMicrokernelTester() |
| 16169 | .cr(1) |
| 16170 | .kr(4) |
| 16171 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16172 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16173 | } |
| 16174 | } |
| 16175 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16176 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16177 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16178 | DWConvMicrokernelTester() |
| 16179 | .cr(1) |
| 16180 | .kr(4) |
| 16181 | .channels(channels) |
| 16182 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16183 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16184 | } |
| 16185 | } |
| 16186 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16187 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16188 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16189 | DWConvMicrokernelTester() |
| 16190 | .cr(1) |
| 16191 | .kr(4) |
| 16192 | .channels(channels) |
| 16193 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16194 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16195 | } |
| 16196 | } |
| 16197 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16198 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16199 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16200 | DWConvMicrokernelTester() |
| 16201 | .cr(1) |
| 16202 | .kr(4) |
| 16203 | .channels(channels) |
| 16204 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16205 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16206 | } |
| 16207 | } |
| 16208 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16209 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16210 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16211 | for (size_t step = 2; step <= 4; step++) { |
| 16212 | DWConvMicrokernelTester() |
| 16213 | .cr(1) |
| 16214 | .kr(4) |
| 16215 | .channels(channels) |
| 16216 | .width(3) |
| 16217 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16218 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16219 | } |
| 16220 | } |
| 16221 | } |
| 16222 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16223 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16224 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16225 | DWConvMicrokernelTester() |
| 16226 | .cr(1) |
| 16227 | .kr(4) |
| 16228 | .channels(1) |
| 16229 | .width(5) |
| 16230 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16231 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16232 | } |
| 16233 | } |
| 16234 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16235 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16236 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16237 | DWConvMicrokernelTester() |
| 16238 | .cr(1) |
| 16239 | .kr(4) |
| 16240 | .channels(channels) |
| 16241 | .width(3) |
| 16242 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16243 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16244 | } |
| 16245 | } |
| 16246 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16247 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16248 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16249 | DWConvMicrokernelTester() |
| 16250 | .cr(1) |
| 16251 | .kr(4) |
| 16252 | .channels(channels) |
| 16253 | .width(3) |
| 16254 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16255 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16256 | } |
| 16257 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 16258 | |
| 16259 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, input_offset) { |
| 16260 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16261 | DWConvMicrokernelTester() |
| 16262 | .cr(1) |
| 16263 | .kr(4) |
| 16264 | .channels(channels) |
| 16265 | .input_offset(48) |
| 16266 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16267 | } |
| 16268 | } |
| 16269 | |
| 16270 | TEST(F32_DWCONV_MINMAX_UP1X4__WASM_ACC2, zero) { |
| 16271 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 16272 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16273 | DWConvMicrokernelTester() |
| 16274 | .cr(1) |
| 16275 | .kr(4) |
| 16276 | .channels(channels) |
| 16277 | .input_offset(48) |
| 16278 | .zero_index(mz) |
| 16279 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16280 | } |
| 16281 | } |
| 16282 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16283 | #endif // XNN_ARCH_WASM |
| 16284 | |
| 16285 | |
| 16286 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16287 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16288 | DWConvMicrokernelTester() |
| 16289 | .cr(2) |
| 16290 | .kr(4) |
| 16291 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16292 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16293 | } |
| 16294 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16295 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16296 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16297 | DWConvMicrokernelTester() |
| 16298 | .cr(2) |
| 16299 | .kr(4) |
| 16300 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16301 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16302 | } |
| 16303 | } |
| 16304 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16305 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16306 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16307 | DWConvMicrokernelTester() |
| 16308 | .cr(2) |
| 16309 | .kr(4) |
| 16310 | .channels(channels) |
| 16311 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16312 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16313 | } |
| 16314 | } |
| 16315 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16316 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16317 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16318 | DWConvMicrokernelTester() |
| 16319 | .cr(2) |
| 16320 | .kr(4) |
| 16321 | .channels(channels) |
| 16322 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16323 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16324 | } |
| 16325 | } |
| 16326 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16327 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16328 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 16329 | DWConvMicrokernelTester() |
| 16330 | .cr(2) |
| 16331 | .kr(4) |
| 16332 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16333 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16334 | } |
| 16335 | } |
| 16336 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16337 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16338 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16339 | DWConvMicrokernelTester() |
| 16340 | .cr(2) |
| 16341 | .kr(4) |
| 16342 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16343 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16344 | } |
| 16345 | } |
| 16346 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16347 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16348 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16349 | DWConvMicrokernelTester() |
| 16350 | .cr(2) |
| 16351 | .kr(4) |
| 16352 | .channels(channels) |
| 16353 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16354 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16355 | } |
| 16356 | } |
| 16357 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16358 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16359 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16360 | DWConvMicrokernelTester() |
| 16361 | .cr(2) |
| 16362 | .kr(4) |
| 16363 | .channels(channels) |
| 16364 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16365 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16366 | } |
| 16367 | } |
| 16368 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16369 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16370 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16371 | DWConvMicrokernelTester() |
| 16372 | .cr(2) |
| 16373 | .kr(4) |
| 16374 | .channels(channels) |
| 16375 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16376 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16377 | } |
| 16378 | } |
| 16379 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16380 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16381 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16382 | for (size_t step = 2; step <= 4; step++) { |
| 16383 | DWConvMicrokernelTester() |
| 16384 | .cr(2) |
| 16385 | .kr(4) |
| 16386 | .channels(channels) |
| 16387 | .width(3) |
| 16388 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16389 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16390 | } |
| 16391 | } |
| 16392 | } |
| 16393 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16394 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16395 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16396 | DWConvMicrokernelTester() |
| 16397 | .cr(2) |
| 16398 | .kr(4) |
| 16399 | .channels(2) |
| 16400 | .width(5) |
| 16401 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16402 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16403 | } |
| 16404 | } |
| 16405 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16406 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16407 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16408 | DWConvMicrokernelTester() |
| 16409 | .cr(2) |
| 16410 | .kr(4) |
| 16411 | .channels(channels) |
| 16412 | .width(3) |
| 16413 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16414 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16415 | } |
| 16416 | } |
| 16417 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16418 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16419 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16420 | DWConvMicrokernelTester() |
| 16421 | .cr(2) |
| 16422 | .kr(4) |
| 16423 | .channels(channels) |
| 16424 | .width(3) |
| 16425 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16426 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16427 | } |
| 16428 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 16429 | |
| 16430 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, input_offset) { |
| 16431 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16432 | DWConvMicrokernelTester() |
| 16433 | .cr(2) |
| 16434 | .kr(4) |
| 16435 | .channels(channels) |
| 16436 | .input_offset(80) |
| 16437 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 16438 | } |
| 16439 | } |
| 16440 | |
| 16441 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM, zero) { |
| 16442 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 16443 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16444 | DWConvMicrokernelTester() |
| 16445 | .cr(2) |
| 16446 | .kr(4) |
| 16447 | .channels(channels) |
| 16448 | .input_offset(80) |
| 16449 | .zero_index(mz) |
| 16450 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 16451 | } |
| 16452 | } |
| 16453 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16454 | #endif // XNN_ARCH_WASM |
| 16455 | |
| 16456 | |
| 16457 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16458 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16459 | DWConvMicrokernelTester() |
| 16460 | .cr(2) |
| 16461 | .kr(4) |
| 16462 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16463 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16464 | } |
| 16465 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16466 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16467 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16468 | DWConvMicrokernelTester() |
| 16469 | .cr(2) |
| 16470 | .kr(4) |
| 16471 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16472 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16473 | } |
| 16474 | } |
| 16475 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16476 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16477 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16478 | DWConvMicrokernelTester() |
| 16479 | .cr(2) |
| 16480 | .kr(4) |
| 16481 | .channels(channels) |
| 16482 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16483 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16484 | } |
| 16485 | } |
| 16486 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16487 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16488 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16489 | DWConvMicrokernelTester() |
| 16490 | .cr(2) |
| 16491 | .kr(4) |
| 16492 | .channels(channels) |
| 16493 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16494 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16495 | } |
| 16496 | } |
| 16497 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16498 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16499 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 16500 | DWConvMicrokernelTester() |
| 16501 | .cr(2) |
| 16502 | .kr(4) |
| 16503 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16504 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16505 | } |
| 16506 | } |
| 16507 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16508 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16509 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16510 | DWConvMicrokernelTester() |
| 16511 | .cr(2) |
| 16512 | .kr(4) |
| 16513 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16514 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16515 | } |
| 16516 | } |
| 16517 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16518 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16519 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16520 | DWConvMicrokernelTester() |
| 16521 | .cr(2) |
| 16522 | .kr(4) |
| 16523 | .channels(channels) |
| 16524 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16525 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16526 | } |
| 16527 | } |
| 16528 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16529 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16530 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16531 | DWConvMicrokernelTester() |
| 16532 | .cr(2) |
| 16533 | .kr(4) |
| 16534 | .channels(channels) |
| 16535 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16536 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16537 | } |
| 16538 | } |
| 16539 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16540 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16541 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16542 | DWConvMicrokernelTester() |
| 16543 | .cr(2) |
| 16544 | .kr(4) |
| 16545 | .channels(channels) |
| 16546 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16547 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16548 | } |
| 16549 | } |
| 16550 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16551 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16552 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16553 | for (size_t step = 2; step <= 4; step++) { |
| 16554 | DWConvMicrokernelTester() |
| 16555 | .cr(2) |
| 16556 | .kr(4) |
| 16557 | .channels(channels) |
| 16558 | .width(3) |
| 16559 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16560 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16561 | } |
| 16562 | } |
| 16563 | } |
| 16564 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16565 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16566 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16567 | DWConvMicrokernelTester() |
| 16568 | .cr(2) |
| 16569 | .kr(4) |
| 16570 | .channels(2) |
| 16571 | .width(5) |
| 16572 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16573 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16574 | } |
| 16575 | } |
| 16576 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16577 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16578 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16579 | DWConvMicrokernelTester() |
| 16580 | .cr(2) |
| 16581 | .kr(4) |
| 16582 | .channels(channels) |
| 16583 | .width(3) |
| 16584 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16585 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16586 | } |
| 16587 | } |
| 16588 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16589 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16590 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16591 | DWConvMicrokernelTester() |
| 16592 | .cr(2) |
| 16593 | .kr(4) |
| 16594 | .channels(channels) |
| 16595 | .width(3) |
| 16596 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16597 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16598 | } |
| 16599 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 16600 | |
| 16601 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, input_offset) { |
| 16602 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16603 | DWConvMicrokernelTester() |
| 16604 | .cr(2) |
| 16605 | .kr(4) |
| 16606 | .channels(channels) |
| 16607 | .input_offset(80) |
| 16608 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16609 | } |
| 16610 | } |
| 16611 | |
| 16612 | TEST(F32_DWCONV_MINMAX_UP2X4__WASM_ACC2, zero) { |
| 16613 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 16614 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16615 | DWConvMicrokernelTester() |
| 16616 | .cr(2) |
| 16617 | .kr(4) |
| 16618 | .channels(channels) |
| 16619 | .input_offset(80) |
| 16620 | .zero_index(mz) |
| 16621 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16622 | } |
| 16623 | } |
| 16624 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16625 | #endif // XNN_ARCH_WASM |
| 16626 | |
| 16627 | |
| 16628 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16629 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16630 | DWConvMicrokernelTester() |
| 16631 | .cr(1) |
| 16632 | .kr(9) |
| 16633 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16634 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16635 | } |
| 16636 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16637 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16638 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16639 | DWConvMicrokernelTester() |
| 16640 | .cr(1) |
| 16641 | .kr(9) |
| 16642 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16643 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16644 | } |
| 16645 | } |
| 16646 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16647 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16648 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16649 | DWConvMicrokernelTester() |
| 16650 | .cr(1) |
| 16651 | .kr(9) |
| 16652 | .channels(channels) |
| 16653 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16654 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16655 | } |
| 16656 | } |
| 16657 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16658 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16659 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16660 | DWConvMicrokernelTester() |
| 16661 | .cr(1) |
| 16662 | .kr(9) |
| 16663 | .channels(channels) |
| 16664 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16665 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16666 | } |
| 16667 | } |
| 16668 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16669 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16670 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16671 | DWConvMicrokernelTester() |
| 16672 | .cr(1) |
| 16673 | .kr(9) |
| 16674 | .channels(channels) |
| 16675 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16676 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16677 | } |
| 16678 | } |
| 16679 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16680 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16681 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16682 | for (size_t step = 2; step <= 9; step++) { |
| 16683 | DWConvMicrokernelTester() |
| 16684 | .cr(1) |
| 16685 | .kr(9) |
| 16686 | .channels(channels) |
| 16687 | .width(3) |
| 16688 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16689 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16690 | } |
| 16691 | } |
| 16692 | } |
| 16693 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16694 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16695 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16696 | DWConvMicrokernelTester() |
| 16697 | .cr(1) |
| 16698 | .kr(9) |
| 16699 | .channels(1) |
| 16700 | .width(5) |
| 16701 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16702 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16703 | } |
| 16704 | } |
| 16705 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16706 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16707 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16708 | DWConvMicrokernelTester() |
| 16709 | .cr(1) |
| 16710 | .kr(9) |
| 16711 | .channels(channels) |
| 16712 | .width(3) |
| 16713 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16714 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16715 | } |
| 16716 | } |
| 16717 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16718 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16719 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16720 | DWConvMicrokernelTester() |
| 16721 | .cr(1) |
| 16722 | .kr(9) |
| 16723 | .channels(channels) |
| 16724 | .width(3) |
| 16725 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16726 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16727 | } |
| 16728 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 16729 | |
| 16730 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, input_offset) { |
| 16731 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16732 | DWConvMicrokernelTester() |
| 16733 | .cr(1) |
| 16734 | .kr(9) |
| 16735 | .channels(channels) |
| 16736 | .input_offset(48) |
| 16737 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 16738 | } |
| 16739 | } |
| 16740 | |
| 16741 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM, zero) { |
| 16742 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 16743 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16744 | DWConvMicrokernelTester() |
| 16745 | .cr(1) |
| 16746 | .kr(9) |
| 16747 | .channels(channels) |
| 16748 | .input_offset(48) |
| 16749 | .zero_index(mz) |
| 16750 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 16751 | } |
| 16752 | } |
| 16753 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16754 | #endif // XNN_ARCH_WASM |
| 16755 | |
| 16756 | |
| 16757 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16758 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16759 | DWConvMicrokernelTester() |
| 16760 | .cr(1) |
| 16761 | .kr(9) |
| 16762 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16763 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16764 | } |
| 16765 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16766 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16767 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16768 | DWConvMicrokernelTester() |
| 16769 | .cr(1) |
| 16770 | .kr(9) |
| 16771 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16772 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16773 | } |
| 16774 | } |
| 16775 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16776 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16777 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16778 | DWConvMicrokernelTester() |
| 16779 | .cr(1) |
| 16780 | .kr(9) |
| 16781 | .channels(channels) |
| 16782 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16783 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16784 | } |
| 16785 | } |
| 16786 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16787 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16788 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 16789 | DWConvMicrokernelTester() |
| 16790 | .cr(1) |
| 16791 | .kr(9) |
| 16792 | .channels(channels) |
| 16793 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16794 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16795 | } |
| 16796 | } |
| 16797 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16798 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16799 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16800 | DWConvMicrokernelTester() |
| 16801 | .cr(1) |
| 16802 | .kr(9) |
| 16803 | .channels(channels) |
| 16804 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16805 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16806 | } |
| 16807 | } |
| 16808 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16809 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16810 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16811 | for (size_t step = 2; step <= 9; step++) { |
| 16812 | DWConvMicrokernelTester() |
| 16813 | .cr(1) |
| 16814 | .kr(9) |
| 16815 | .channels(channels) |
| 16816 | .width(3) |
| 16817 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16818 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16819 | } |
| 16820 | } |
| 16821 | } |
| 16822 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16823 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16824 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16825 | DWConvMicrokernelTester() |
| 16826 | .cr(1) |
| 16827 | .kr(9) |
| 16828 | .channels(1) |
| 16829 | .width(5) |
| 16830 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16831 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16832 | } |
| 16833 | } |
| 16834 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16835 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16836 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16837 | DWConvMicrokernelTester() |
| 16838 | .cr(1) |
| 16839 | .kr(9) |
| 16840 | .channels(channels) |
| 16841 | .width(3) |
| 16842 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16843 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16844 | } |
| 16845 | } |
| 16846 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16847 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16848 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 16849 | DWConvMicrokernelTester() |
| 16850 | .cr(1) |
| 16851 | .kr(9) |
| 16852 | .channels(channels) |
| 16853 | .width(3) |
| 16854 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16855 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16856 | } |
| 16857 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 16858 | |
| 16859 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, input_offset) { |
| 16860 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16861 | DWConvMicrokernelTester() |
| 16862 | .cr(1) |
| 16863 | .kr(9) |
| 16864 | .channels(channels) |
| 16865 | .input_offset(48) |
| 16866 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16867 | } |
| 16868 | } |
| 16869 | |
| 16870 | TEST(F32_DWCONV_MINMAX_UP1X9__WASM_ACC2, zero) { |
| 16871 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 16872 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 16873 | DWConvMicrokernelTester() |
| 16874 | .cr(1) |
| 16875 | .kr(9) |
| 16876 | .channels(channels) |
| 16877 | .input_offset(48) |
| 16878 | .zero_index(mz) |
| 16879 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 16880 | } |
| 16881 | } |
| 16882 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16883 | #endif // XNN_ARCH_WASM |
| 16884 | |
| 16885 | |
| 16886 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16887 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16888 | DWConvMicrokernelTester() |
| 16889 | .cr(2) |
| 16890 | .kr(9) |
| 16891 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16892 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16893 | } |
| 16894 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16895 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16896 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16897 | DWConvMicrokernelTester() |
| 16898 | .cr(2) |
| 16899 | .kr(9) |
| 16900 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16901 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16902 | } |
| 16903 | } |
| 16904 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16905 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16906 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16907 | DWConvMicrokernelTester() |
| 16908 | .cr(2) |
| 16909 | .kr(9) |
| 16910 | .channels(channels) |
| 16911 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16912 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16913 | } |
| 16914 | } |
| 16915 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16916 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16917 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 16918 | DWConvMicrokernelTester() |
| 16919 | .cr(2) |
| 16920 | .kr(9) |
| 16921 | .channels(channels) |
| 16922 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16923 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16924 | } |
| 16925 | } |
| 16926 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16927 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16928 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 16929 | DWConvMicrokernelTester() |
| 16930 | .cr(2) |
| 16931 | .kr(9) |
| 16932 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16933 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16934 | } |
| 16935 | } |
| 16936 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16937 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16938 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16939 | DWConvMicrokernelTester() |
| 16940 | .cr(2) |
| 16941 | .kr(9) |
| 16942 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16943 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16944 | } |
| 16945 | } |
| 16946 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16947 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16948 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16949 | DWConvMicrokernelTester() |
| 16950 | .cr(2) |
| 16951 | .kr(9) |
| 16952 | .channels(channels) |
| 16953 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16954 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16955 | } |
| 16956 | } |
| 16957 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16958 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16959 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 16960 | DWConvMicrokernelTester() |
| 16961 | .cr(2) |
| 16962 | .kr(9) |
| 16963 | .channels(channels) |
| 16964 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16965 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16966 | } |
| 16967 | } |
| 16968 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16969 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16970 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16971 | DWConvMicrokernelTester() |
| 16972 | .cr(2) |
| 16973 | .kr(9) |
| 16974 | .channels(channels) |
| 16975 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16976 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16977 | } |
| 16978 | } |
| 16979 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16980 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16981 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16982 | for (size_t step = 2; step <= 9; step++) { |
| 16983 | DWConvMicrokernelTester() |
| 16984 | .cr(2) |
| 16985 | .kr(9) |
| 16986 | .channels(channels) |
| 16987 | .width(3) |
| 16988 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16989 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16990 | } |
| 16991 | } |
| 16992 | } |
| 16993 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 16994 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 16995 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 16996 | DWConvMicrokernelTester() |
| 16997 | .cr(2) |
| 16998 | .kr(9) |
| 16999 | .channels(2) |
| 17000 | .width(5) |
| 17001 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17002 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17003 | } |
| 17004 | } |
| 17005 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17006 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17007 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17008 | DWConvMicrokernelTester() |
| 17009 | .cr(2) |
| 17010 | .kr(9) |
| 17011 | .channels(channels) |
| 17012 | .width(3) |
| 17013 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17014 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17015 | } |
| 17016 | } |
| 17017 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17018 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17019 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17020 | DWConvMicrokernelTester() |
| 17021 | .cr(2) |
| 17022 | .kr(9) |
| 17023 | .channels(channels) |
| 17024 | .width(3) |
| 17025 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17026 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17027 | } |
| 17028 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 17029 | |
| 17030 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, input_offset) { |
| 17031 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17032 | DWConvMicrokernelTester() |
| 17033 | .cr(2) |
| 17034 | .kr(9) |
| 17035 | .channels(channels) |
| 17036 | .input_offset(80) |
| 17037 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 17038 | } |
| 17039 | } |
| 17040 | |
| 17041 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM, zero) { |
| 17042 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 17043 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17044 | DWConvMicrokernelTester() |
| 17045 | .cr(2) |
| 17046 | .kr(9) |
| 17047 | .channels(channels) |
| 17048 | .input_offset(80) |
| 17049 | .zero_index(mz) |
| 17050 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 17051 | } |
| 17052 | } |
| 17053 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17054 | #endif // XNN_ARCH_WASM |
| 17055 | |
| 17056 | |
| 17057 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17058 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17059 | DWConvMicrokernelTester() |
| 17060 | .cr(2) |
| 17061 | .kr(9) |
| 17062 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17063 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17064 | } |
| 17065 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17066 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17067 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17068 | DWConvMicrokernelTester() |
| 17069 | .cr(2) |
| 17070 | .kr(9) |
| 17071 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17072 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17073 | } |
| 17074 | } |
| 17075 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17076 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17077 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17078 | DWConvMicrokernelTester() |
| 17079 | .cr(2) |
| 17080 | .kr(9) |
| 17081 | .channels(channels) |
| 17082 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17083 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17084 | } |
| 17085 | } |
| 17086 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17087 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17088 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17089 | DWConvMicrokernelTester() |
| 17090 | .cr(2) |
| 17091 | .kr(9) |
| 17092 | .channels(channels) |
| 17093 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17094 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17095 | } |
| 17096 | } |
| 17097 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17098 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17099 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 17100 | DWConvMicrokernelTester() |
| 17101 | .cr(2) |
| 17102 | .kr(9) |
| 17103 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17104 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17105 | } |
| 17106 | } |
| 17107 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17108 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17109 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17110 | DWConvMicrokernelTester() |
| 17111 | .cr(2) |
| 17112 | .kr(9) |
| 17113 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17114 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17115 | } |
| 17116 | } |
| 17117 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17118 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17119 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17120 | DWConvMicrokernelTester() |
| 17121 | .cr(2) |
| 17122 | .kr(9) |
| 17123 | .channels(channels) |
| 17124 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17125 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17126 | } |
| 17127 | } |
| 17128 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17129 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17130 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17131 | DWConvMicrokernelTester() |
| 17132 | .cr(2) |
| 17133 | .kr(9) |
| 17134 | .channels(channels) |
| 17135 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17136 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17137 | } |
| 17138 | } |
| 17139 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17140 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17141 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17142 | DWConvMicrokernelTester() |
| 17143 | .cr(2) |
| 17144 | .kr(9) |
| 17145 | .channels(channels) |
| 17146 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17147 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17148 | } |
| 17149 | } |
| 17150 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17151 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17152 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17153 | for (size_t step = 2; step <= 9; step++) { |
| 17154 | DWConvMicrokernelTester() |
| 17155 | .cr(2) |
| 17156 | .kr(9) |
| 17157 | .channels(channels) |
| 17158 | .width(3) |
| 17159 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17160 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17161 | } |
| 17162 | } |
| 17163 | } |
| 17164 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17165 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17166 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17167 | DWConvMicrokernelTester() |
| 17168 | .cr(2) |
| 17169 | .kr(9) |
| 17170 | .channels(2) |
| 17171 | .width(5) |
| 17172 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17173 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17174 | } |
| 17175 | } |
| 17176 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17177 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17178 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17179 | DWConvMicrokernelTester() |
| 17180 | .cr(2) |
| 17181 | .kr(9) |
| 17182 | .channels(channels) |
| 17183 | .width(3) |
| 17184 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17185 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17186 | } |
| 17187 | } |
| 17188 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17189 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17190 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17191 | DWConvMicrokernelTester() |
| 17192 | .cr(2) |
| 17193 | .kr(9) |
| 17194 | .channels(channels) |
| 17195 | .width(3) |
| 17196 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17197 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17198 | } |
| 17199 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 17200 | |
| 17201 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, input_offset) { |
| 17202 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17203 | DWConvMicrokernelTester() |
| 17204 | .cr(2) |
| 17205 | .kr(9) |
| 17206 | .channels(channels) |
| 17207 | .input_offset(80) |
| 17208 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 17209 | } |
| 17210 | } |
| 17211 | |
| 17212 | TEST(F32_DWCONV_MINMAX_UP2X9__WASM_ACC2, zero) { |
| 17213 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 17214 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17215 | DWConvMicrokernelTester() |
| 17216 | .cr(2) |
| 17217 | .kr(9) |
| 17218 | .channels(channels) |
| 17219 | .input_offset(80) |
| 17220 | .zero_index(mz) |
| 17221 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 17222 | } |
| 17223 | } |
| 17224 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17225 | #endif // XNN_ARCH_WASM |
| 17226 | |
| 17227 | |
| 17228 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17229 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17230 | DWConvMicrokernelTester() |
| 17231 | .cr(1) |
| 17232 | .kr(25) |
| 17233 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17234 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17235 | } |
| 17236 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17237 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17238 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17239 | DWConvMicrokernelTester() |
| 17240 | .cr(1) |
| 17241 | .kr(25) |
| 17242 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17243 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17244 | } |
| 17245 | } |
| 17246 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17247 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17248 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17249 | DWConvMicrokernelTester() |
| 17250 | .cr(1) |
| 17251 | .kr(25) |
| 17252 | .channels(channels) |
| 17253 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17254 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17255 | } |
| 17256 | } |
| 17257 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17258 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17259 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17260 | DWConvMicrokernelTester() |
| 17261 | .cr(1) |
| 17262 | .kr(25) |
| 17263 | .channels(channels) |
| 17264 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17265 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17266 | } |
| 17267 | } |
| 17268 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17269 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17270 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17271 | DWConvMicrokernelTester() |
| 17272 | .cr(1) |
| 17273 | .kr(25) |
| 17274 | .channels(channels) |
| 17275 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17276 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17277 | } |
| 17278 | } |
| 17279 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17280 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17281 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17282 | for (size_t step = 2; step <= 25; step++) { |
| 17283 | DWConvMicrokernelTester() |
| 17284 | .cr(1) |
| 17285 | .kr(25) |
| 17286 | .channels(channels) |
| 17287 | .width(3) |
| 17288 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17289 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17290 | } |
| 17291 | } |
| 17292 | } |
| 17293 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17294 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17295 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17296 | DWConvMicrokernelTester() |
| 17297 | .cr(1) |
| 17298 | .kr(25) |
| 17299 | .channels(1) |
| 17300 | .width(5) |
| 17301 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17302 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17303 | } |
| 17304 | } |
| 17305 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17306 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17307 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17308 | DWConvMicrokernelTester() |
| 17309 | .cr(1) |
| 17310 | .kr(25) |
| 17311 | .channels(channels) |
| 17312 | .width(3) |
| 17313 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17314 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17315 | } |
| 17316 | } |
| 17317 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17318 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17319 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17320 | DWConvMicrokernelTester() |
| 17321 | .cr(1) |
| 17322 | .kr(25) |
| 17323 | .channels(channels) |
| 17324 | .width(3) |
| 17325 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17326 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17327 | } |
| 17328 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 17329 | |
| 17330 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, input_offset) { |
| 17331 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 17332 | DWConvMicrokernelTester() |
| 17333 | .cr(1) |
| 17334 | .kr(25) |
| 17335 | .channels(channels) |
| 17336 | .input_offset(48) |
| 17337 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 17338 | } |
| 17339 | } |
| 17340 | |
| 17341 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM, zero) { |
| 17342 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 17343 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 17344 | DWConvMicrokernelTester() |
| 17345 | .cr(1) |
| 17346 | .kr(25) |
| 17347 | .channels(channels) |
| 17348 | .input_offset(48) |
| 17349 | .zero_index(mz) |
| 17350 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 17351 | } |
| 17352 | } |
| 17353 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17354 | #endif // XNN_ARCH_WASM |
| 17355 | |
| 17356 | |
| 17357 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17358 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17359 | DWConvMicrokernelTester() |
| 17360 | .cr(1) |
| 17361 | .kr(25) |
| 17362 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17363 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17364 | } |
| 17365 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17366 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17367 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17368 | DWConvMicrokernelTester() |
| 17369 | .cr(1) |
| 17370 | .kr(25) |
| 17371 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17372 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17373 | } |
| 17374 | } |
| 17375 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17376 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17377 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17378 | DWConvMicrokernelTester() |
| 17379 | .cr(1) |
| 17380 | .kr(25) |
| 17381 | .channels(channels) |
| 17382 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17383 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17384 | } |
| 17385 | } |
| 17386 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17387 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17388 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17389 | DWConvMicrokernelTester() |
| 17390 | .cr(1) |
| 17391 | .kr(25) |
| 17392 | .channels(channels) |
| 17393 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17394 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17395 | } |
| 17396 | } |
| 17397 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17398 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17399 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17400 | DWConvMicrokernelTester() |
| 17401 | .cr(1) |
| 17402 | .kr(25) |
| 17403 | .channels(channels) |
| 17404 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17405 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17406 | } |
| 17407 | } |
| 17408 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17409 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17410 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17411 | for (size_t step = 2; step <= 25; step++) { |
| 17412 | DWConvMicrokernelTester() |
| 17413 | .cr(1) |
| 17414 | .kr(25) |
| 17415 | .channels(channels) |
| 17416 | .width(3) |
| 17417 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17418 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17419 | } |
| 17420 | } |
| 17421 | } |
| 17422 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17423 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17424 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17425 | DWConvMicrokernelTester() |
| 17426 | .cr(1) |
| 17427 | .kr(25) |
| 17428 | .channels(1) |
| 17429 | .width(5) |
| 17430 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17431 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17432 | } |
| 17433 | } |
| 17434 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17435 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17436 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17437 | DWConvMicrokernelTester() |
| 17438 | .cr(1) |
| 17439 | .kr(25) |
| 17440 | .channels(channels) |
| 17441 | .width(3) |
| 17442 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17443 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17444 | } |
| 17445 | } |
| 17446 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17447 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17448 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17449 | DWConvMicrokernelTester() |
| 17450 | .cr(1) |
| 17451 | .kr(25) |
| 17452 | .channels(channels) |
| 17453 | .width(3) |
| 17454 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17455 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17456 | } |
| 17457 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 17458 | |
| 17459 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, input_offset) { |
| 17460 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 17461 | DWConvMicrokernelTester() |
| 17462 | .cr(1) |
| 17463 | .kr(25) |
| 17464 | .channels(channels) |
| 17465 | .input_offset(48) |
| 17466 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 17467 | } |
| 17468 | } |
| 17469 | |
| 17470 | TEST(F32_DWCONV_MINMAX_UP1X25__WASM_ACC2, zero) { |
| 17471 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 17472 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 17473 | DWConvMicrokernelTester() |
| 17474 | .cr(1) |
| 17475 | .kr(25) |
| 17476 | .channels(channels) |
| 17477 | .input_offset(48) |
| 17478 | .zero_index(mz) |
| 17479 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 17480 | } |
| 17481 | } |
| 17482 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17483 | #endif // XNN_ARCH_WASM |
| 17484 | |
| 17485 | |
| 17486 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17487 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17488 | DWConvMicrokernelTester() |
| 17489 | .cr(2) |
| 17490 | .kr(25) |
| 17491 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17492 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17493 | } |
| 17494 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17495 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17496 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17497 | DWConvMicrokernelTester() |
| 17498 | .cr(2) |
| 17499 | .kr(25) |
| 17500 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17501 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17502 | } |
| 17503 | } |
| 17504 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17505 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17506 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17507 | DWConvMicrokernelTester() |
| 17508 | .cr(2) |
| 17509 | .kr(25) |
| 17510 | .channels(channels) |
| 17511 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17512 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17513 | } |
| 17514 | } |
| 17515 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17516 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17517 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17518 | DWConvMicrokernelTester() |
| 17519 | .cr(2) |
| 17520 | .kr(25) |
| 17521 | .channels(channels) |
| 17522 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17523 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17524 | } |
| 17525 | } |
| 17526 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17527 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17528 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 17529 | DWConvMicrokernelTester() |
| 17530 | .cr(2) |
| 17531 | .kr(25) |
| 17532 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17533 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17534 | } |
| 17535 | } |
| 17536 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17537 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17538 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17539 | DWConvMicrokernelTester() |
| 17540 | .cr(2) |
| 17541 | .kr(25) |
| 17542 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17543 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17544 | } |
| 17545 | } |
| 17546 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17547 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17548 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17549 | DWConvMicrokernelTester() |
| 17550 | .cr(2) |
| 17551 | .kr(25) |
| 17552 | .channels(channels) |
| 17553 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17554 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17555 | } |
| 17556 | } |
| 17557 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17558 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17559 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17560 | DWConvMicrokernelTester() |
| 17561 | .cr(2) |
| 17562 | .kr(25) |
| 17563 | .channels(channels) |
| 17564 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17565 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17566 | } |
| 17567 | } |
| 17568 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17569 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17570 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17571 | DWConvMicrokernelTester() |
| 17572 | .cr(2) |
| 17573 | .kr(25) |
| 17574 | .channels(channels) |
| 17575 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17576 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17577 | } |
| 17578 | } |
| 17579 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17580 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17581 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17582 | for (size_t step = 2; step <= 25; step++) { |
| 17583 | DWConvMicrokernelTester() |
| 17584 | .cr(2) |
| 17585 | .kr(25) |
| 17586 | .channels(channels) |
| 17587 | .width(3) |
| 17588 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17589 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17590 | } |
| 17591 | } |
| 17592 | } |
| 17593 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17594 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17595 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17596 | DWConvMicrokernelTester() |
| 17597 | .cr(2) |
| 17598 | .kr(25) |
| 17599 | .channels(2) |
| 17600 | .width(5) |
| 17601 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17602 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17603 | } |
| 17604 | } |
| 17605 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17606 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17607 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17608 | DWConvMicrokernelTester() |
| 17609 | .cr(2) |
| 17610 | .kr(25) |
| 17611 | .channels(channels) |
| 17612 | .width(3) |
| 17613 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17614 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17615 | } |
| 17616 | } |
| 17617 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17618 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17619 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17620 | DWConvMicrokernelTester() |
| 17621 | .cr(2) |
| 17622 | .kr(25) |
| 17623 | .channels(channels) |
| 17624 | .width(3) |
| 17625 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17626 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17627 | } |
| 17628 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 17629 | |
| 17630 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, input_offset) { |
| 17631 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17632 | DWConvMicrokernelTester() |
| 17633 | .cr(2) |
| 17634 | .kr(25) |
| 17635 | .channels(channels) |
| 17636 | .input_offset(80) |
| 17637 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 17638 | } |
| 17639 | } |
| 17640 | |
| 17641 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM, zero) { |
| 17642 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 17643 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17644 | DWConvMicrokernelTester() |
| 17645 | .cr(2) |
| 17646 | .kr(25) |
| 17647 | .channels(channels) |
| 17648 | .input_offset(80) |
| 17649 | .zero_index(mz) |
| 17650 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm, DWConvMicrokernelTester::Variant::Scalar); |
| 17651 | } |
| 17652 | } |
| 17653 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17654 | #endif // XNN_ARCH_WASM |
| 17655 | |
| 17656 | |
| 17657 | #if XNN_ARCH_WASM |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17658 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17659 | DWConvMicrokernelTester() |
| 17660 | .cr(2) |
| 17661 | .kr(25) |
| 17662 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17663 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17664 | } |
| 17665 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17666 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17667 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17668 | DWConvMicrokernelTester() |
| 17669 | .cr(2) |
| 17670 | .kr(25) |
| 17671 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17672 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17673 | } |
| 17674 | } |
| 17675 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17676 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17677 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17678 | DWConvMicrokernelTester() |
| 17679 | .cr(2) |
| 17680 | .kr(25) |
| 17681 | .channels(channels) |
| 17682 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17683 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17684 | } |
| 17685 | } |
| 17686 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17687 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17688 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17689 | DWConvMicrokernelTester() |
| 17690 | .cr(2) |
| 17691 | .kr(25) |
| 17692 | .channels(channels) |
| 17693 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17694 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17695 | } |
| 17696 | } |
| 17697 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17698 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17699 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 17700 | DWConvMicrokernelTester() |
| 17701 | .cr(2) |
| 17702 | .kr(25) |
| 17703 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17704 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17705 | } |
| 17706 | } |
| 17707 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17708 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17709 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17710 | DWConvMicrokernelTester() |
| 17711 | .cr(2) |
| 17712 | .kr(25) |
| 17713 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17714 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17715 | } |
| 17716 | } |
| 17717 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17718 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17719 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17720 | DWConvMicrokernelTester() |
| 17721 | .cr(2) |
| 17722 | .kr(25) |
| 17723 | .channels(channels) |
| 17724 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17725 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17726 | } |
| 17727 | } |
| 17728 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17729 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17730 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 17731 | DWConvMicrokernelTester() |
| 17732 | .cr(2) |
| 17733 | .kr(25) |
| 17734 | .channels(channels) |
| 17735 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17736 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17737 | } |
| 17738 | } |
| 17739 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17740 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17741 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17742 | DWConvMicrokernelTester() |
| 17743 | .cr(2) |
| 17744 | .kr(25) |
| 17745 | .channels(channels) |
| 17746 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17747 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17748 | } |
| 17749 | } |
| 17750 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17751 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17752 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17753 | for (size_t step = 2; step <= 25; step++) { |
| 17754 | DWConvMicrokernelTester() |
| 17755 | .cr(2) |
| 17756 | .kr(25) |
| 17757 | .channels(channels) |
| 17758 | .width(3) |
| 17759 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17760 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17761 | } |
| 17762 | } |
| 17763 | } |
| 17764 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17765 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17766 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17767 | DWConvMicrokernelTester() |
| 17768 | .cr(2) |
| 17769 | .kr(25) |
| 17770 | .channels(2) |
| 17771 | .width(5) |
| 17772 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17773 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17774 | } |
| 17775 | } |
| 17776 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17777 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17778 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17779 | DWConvMicrokernelTester() |
| 17780 | .cr(2) |
| 17781 | .kr(25) |
| 17782 | .channels(channels) |
| 17783 | .width(3) |
| 17784 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17785 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17786 | } |
| 17787 | } |
| 17788 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17789 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17790 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 17791 | DWConvMicrokernelTester() |
| 17792 | .cr(2) |
| 17793 | .kr(25) |
| 17794 | .channels(channels) |
| 17795 | .width(3) |
| 17796 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17797 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17798 | } |
| 17799 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 17800 | |
| 17801 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, input_offset) { |
| 17802 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17803 | DWConvMicrokernelTester() |
| 17804 | .cr(2) |
| 17805 | .kr(25) |
| 17806 | .channels(channels) |
| 17807 | .input_offset(80) |
| 17808 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 17809 | } |
| 17810 | } |
| 17811 | |
| 17812 | TEST(F32_DWCONV_MINMAX_UP2X25__WASM_ACC2, zero) { |
| 17813 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 17814 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 17815 | DWConvMicrokernelTester() |
| 17816 | .cr(2) |
| 17817 | .kr(25) |
| 17818 | .channels(channels) |
| 17819 | .input_offset(80) |
| 17820 | .zero_index(mz) |
| 17821 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__wasm_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 17822 | } |
| 17823 | } |
| 17824 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17825 | #endif // XNN_ARCH_WASM |
| 17826 | |
| 17827 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17828 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17829 | DWConvMicrokernelTester() |
| 17830 | .cr(1) |
| 17831 | .kr(4) |
| 17832 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17833 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17834 | } |
| 17835 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17836 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17837 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17838 | DWConvMicrokernelTester() |
| 17839 | .cr(1) |
| 17840 | .kr(4) |
| 17841 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17842 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17843 | } |
| 17844 | } |
| 17845 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17846 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17847 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17848 | DWConvMicrokernelTester() |
| 17849 | .cr(1) |
| 17850 | .kr(4) |
| 17851 | .channels(channels) |
| 17852 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17853 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17854 | } |
| 17855 | } |
| 17856 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17857 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17858 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17859 | DWConvMicrokernelTester() |
| 17860 | .cr(1) |
| 17861 | .kr(4) |
| 17862 | .channels(channels) |
| 17863 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17864 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17865 | } |
| 17866 | } |
| 17867 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17868 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17869 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17870 | DWConvMicrokernelTester() |
| 17871 | .cr(1) |
| 17872 | .kr(4) |
| 17873 | .channels(channels) |
| 17874 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17875 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17876 | } |
| 17877 | } |
| 17878 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17879 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17880 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17881 | for (size_t step = 2; step <= 4; step++) { |
| 17882 | DWConvMicrokernelTester() |
| 17883 | .cr(1) |
| 17884 | .kr(4) |
| 17885 | .channels(channels) |
| 17886 | .width(3) |
| 17887 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17888 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17889 | } |
| 17890 | } |
| 17891 | } |
| 17892 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17893 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17894 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17895 | DWConvMicrokernelTester() |
| 17896 | .cr(1) |
| 17897 | .kr(4) |
| 17898 | .channels(1) |
| 17899 | .width(5) |
| 17900 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17901 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17902 | } |
| 17903 | } |
| 17904 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17905 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17906 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17907 | DWConvMicrokernelTester() |
| 17908 | .cr(1) |
| 17909 | .kr(4) |
| 17910 | .channels(channels) |
| 17911 | .width(3) |
| 17912 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17913 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17914 | } |
| 17915 | } |
| 17916 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17917 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17918 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17919 | DWConvMicrokernelTester() |
| 17920 | .cr(1) |
| 17921 | .kr(4) |
| 17922 | .channels(channels) |
| 17923 | .width(3) |
| 17924 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17925 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17926 | } |
| 17927 | } |
| 17928 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 17929 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, input_offset) { |
| 17930 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 17931 | DWConvMicrokernelTester() |
| 17932 | .cr(1) |
| 17933 | .kr(4) |
| 17934 | .channels(channels) |
| 17935 | .input_offset(48) |
| 17936 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 17937 | } |
| 17938 | } |
| 17939 | |
| 17940 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR, zero) { |
| 17941 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 17942 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 17943 | DWConvMicrokernelTester() |
| 17944 | .cr(1) |
| 17945 | .kr(4) |
| 17946 | .channels(channels) |
| 17947 | .input_offset(48) |
| 17948 | .zero_index(mz) |
| 17949 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 17950 | } |
| 17951 | } |
| 17952 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17953 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17954 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17955 | DWConvMicrokernelTester() |
| 17956 | .cr(1) |
| 17957 | .kr(4) |
| 17958 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17959 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17960 | } |
| 17961 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17962 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17963 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17964 | DWConvMicrokernelTester() |
| 17965 | .cr(1) |
| 17966 | .kr(4) |
| 17967 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17968 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17969 | } |
| 17970 | } |
| 17971 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17972 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17973 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17974 | DWConvMicrokernelTester() |
| 17975 | .cr(1) |
| 17976 | .kr(4) |
| 17977 | .channels(channels) |
| 17978 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17979 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17980 | } |
| 17981 | } |
| 17982 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17983 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17984 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 17985 | DWConvMicrokernelTester() |
| 17986 | .cr(1) |
| 17987 | .kr(4) |
| 17988 | .channels(channels) |
| 17989 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17990 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17991 | } |
| 17992 | } |
| 17993 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 17994 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 17995 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 17996 | DWConvMicrokernelTester() |
| 17997 | .cr(1) |
| 17998 | .kr(4) |
| 17999 | .channels(channels) |
| 18000 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18001 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18002 | } |
| 18003 | } |
| 18004 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18005 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18006 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18007 | for (size_t step = 2; step <= 4; step++) { |
| 18008 | DWConvMicrokernelTester() |
| 18009 | .cr(1) |
| 18010 | .kr(4) |
| 18011 | .channels(channels) |
| 18012 | .width(3) |
| 18013 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18014 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18015 | } |
| 18016 | } |
| 18017 | } |
| 18018 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18019 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18020 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18021 | DWConvMicrokernelTester() |
| 18022 | .cr(1) |
| 18023 | .kr(4) |
| 18024 | .channels(1) |
| 18025 | .width(5) |
| 18026 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18027 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18028 | } |
| 18029 | } |
| 18030 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18031 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18032 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18033 | DWConvMicrokernelTester() |
| 18034 | .cr(1) |
| 18035 | .kr(4) |
| 18036 | .channels(channels) |
| 18037 | .width(3) |
| 18038 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18039 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18040 | } |
| 18041 | } |
| 18042 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18043 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18044 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18045 | DWConvMicrokernelTester() |
| 18046 | .cr(1) |
| 18047 | .kr(4) |
| 18048 | .channels(channels) |
| 18049 | .width(3) |
| 18050 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18051 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18052 | } |
| 18053 | } |
| 18054 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 18055 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, input_offset) { |
| 18056 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 18057 | DWConvMicrokernelTester() |
| 18058 | .cr(1) |
| 18059 | .kr(4) |
| 18060 | .channels(channels) |
| 18061 | .input_offset(48) |
| 18062 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 18063 | } |
| 18064 | } |
| 18065 | |
| 18066 | TEST(F32_DWCONV_MINMAX_UP1X4__SCALAR_ACC2, zero) { |
| 18067 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 18068 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 18069 | DWConvMicrokernelTester() |
| 18070 | .cr(1) |
| 18071 | .kr(4) |
| 18072 | .channels(channels) |
| 18073 | .input_offset(48) |
| 18074 | .zero_index(mz) |
| 18075 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 18076 | } |
| 18077 | } |
| 18078 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18079 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18080 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18081 | DWConvMicrokernelTester() |
| 18082 | .cr(2) |
| 18083 | .kr(4) |
| 18084 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18085 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18086 | } |
| 18087 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18088 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18089 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18090 | DWConvMicrokernelTester() |
| 18091 | .cr(2) |
| 18092 | .kr(4) |
| 18093 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18094 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18095 | } |
| 18096 | } |
| 18097 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18098 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18099 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18100 | DWConvMicrokernelTester() |
| 18101 | .cr(2) |
| 18102 | .kr(4) |
| 18103 | .channels(channels) |
| 18104 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18105 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18106 | } |
| 18107 | } |
| 18108 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18109 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18110 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18111 | DWConvMicrokernelTester() |
| 18112 | .cr(2) |
| 18113 | .kr(4) |
| 18114 | .channels(channels) |
| 18115 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18116 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18117 | } |
| 18118 | } |
| 18119 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18120 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18121 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 18122 | DWConvMicrokernelTester() |
| 18123 | .cr(2) |
| 18124 | .kr(4) |
| 18125 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18126 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18127 | } |
| 18128 | } |
| 18129 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18130 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18131 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18132 | DWConvMicrokernelTester() |
| 18133 | .cr(2) |
| 18134 | .kr(4) |
| 18135 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18136 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18137 | } |
| 18138 | } |
| 18139 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18140 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18141 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18142 | DWConvMicrokernelTester() |
| 18143 | .cr(2) |
| 18144 | .kr(4) |
| 18145 | .channels(channels) |
| 18146 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18147 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18148 | } |
| 18149 | } |
| 18150 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18151 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18152 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18153 | DWConvMicrokernelTester() |
| 18154 | .cr(2) |
| 18155 | .kr(4) |
| 18156 | .channels(channels) |
| 18157 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18158 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18159 | } |
| 18160 | } |
| 18161 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18162 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18163 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18164 | DWConvMicrokernelTester() |
| 18165 | .cr(2) |
| 18166 | .kr(4) |
| 18167 | .channels(channels) |
| 18168 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18169 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18170 | } |
| 18171 | } |
| 18172 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18173 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18174 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18175 | for (size_t step = 2; step <= 4; step++) { |
| 18176 | DWConvMicrokernelTester() |
| 18177 | .cr(2) |
| 18178 | .kr(4) |
| 18179 | .channels(channels) |
| 18180 | .width(3) |
| 18181 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18182 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18183 | } |
| 18184 | } |
| 18185 | } |
| 18186 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18187 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18188 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18189 | DWConvMicrokernelTester() |
| 18190 | .cr(2) |
| 18191 | .kr(4) |
| 18192 | .channels(2) |
| 18193 | .width(5) |
| 18194 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18195 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18196 | } |
| 18197 | } |
| 18198 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18199 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18200 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18201 | DWConvMicrokernelTester() |
| 18202 | .cr(2) |
| 18203 | .kr(4) |
| 18204 | .channels(channels) |
| 18205 | .width(3) |
| 18206 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18207 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18208 | } |
| 18209 | } |
| 18210 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18211 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18212 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18213 | DWConvMicrokernelTester() |
| 18214 | .cr(2) |
| 18215 | .kr(4) |
| 18216 | .channels(channels) |
| 18217 | .width(3) |
| 18218 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18219 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18220 | } |
| 18221 | } |
| 18222 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 18223 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, input_offset) { |
| 18224 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18225 | DWConvMicrokernelTester() |
| 18226 | .cr(2) |
| 18227 | .kr(4) |
| 18228 | .channels(channels) |
| 18229 | .input_offset(80) |
| 18230 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 18231 | } |
| 18232 | } |
| 18233 | |
| 18234 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR, zero) { |
| 18235 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 18236 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18237 | DWConvMicrokernelTester() |
| 18238 | .cr(2) |
| 18239 | .kr(4) |
| 18240 | .channels(channels) |
| 18241 | .input_offset(80) |
| 18242 | .zero_index(mz) |
| 18243 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 18244 | } |
| 18245 | } |
| 18246 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18247 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18248 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18249 | DWConvMicrokernelTester() |
| 18250 | .cr(2) |
| 18251 | .kr(4) |
| 18252 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18253 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18254 | } |
| 18255 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18256 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18257 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18258 | DWConvMicrokernelTester() |
| 18259 | .cr(2) |
| 18260 | .kr(4) |
| 18261 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18262 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18263 | } |
| 18264 | } |
| 18265 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18266 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18267 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18268 | DWConvMicrokernelTester() |
| 18269 | .cr(2) |
| 18270 | .kr(4) |
| 18271 | .channels(channels) |
| 18272 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18273 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18274 | } |
| 18275 | } |
| 18276 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18277 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18278 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18279 | DWConvMicrokernelTester() |
| 18280 | .cr(2) |
| 18281 | .kr(4) |
| 18282 | .channels(channels) |
| 18283 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18284 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18285 | } |
| 18286 | } |
| 18287 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18288 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18289 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 18290 | DWConvMicrokernelTester() |
| 18291 | .cr(2) |
| 18292 | .kr(4) |
| 18293 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18294 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18295 | } |
| 18296 | } |
| 18297 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18298 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18299 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18300 | DWConvMicrokernelTester() |
| 18301 | .cr(2) |
| 18302 | .kr(4) |
| 18303 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18304 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18305 | } |
| 18306 | } |
| 18307 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18308 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18309 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18310 | DWConvMicrokernelTester() |
| 18311 | .cr(2) |
| 18312 | .kr(4) |
| 18313 | .channels(channels) |
| 18314 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18315 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18316 | } |
| 18317 | } |
| 18318 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18319 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18320 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18321 | DWConvMicrokernelTester() |
| 18322 | .cr(2) |
| 18323 | .kr(4) |
| 18324 | .channels(channels) |
| 18325 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18326 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18327 | } |
| 18328 | } |
| 18329 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18330 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18331 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18332 | DWConvMicrokernelTester() |
| 18333 | .cr(2) |
| 18334 | .kr(4) |
| 18335 | .channels(channels) |
| 18336 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18337 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18338 | } |
| 18339 | } |
| 18340 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18341 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18342 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18343 | for (size_t step = 2; step <= 4; step++) { |
| 18344 | DWConvMicrokernelTester() |
| 18345 | .cr(2) |
| 18346 | .kr(4) |
| 18347 | .channels(channels) |
| 18348 | .width(3) |
| 18349 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18350 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18351 | } |
| 18352 | } |
| 18353 | } |
| 18354 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18355 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18356 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18357 | DWConvMicrokernelTester() |
| 18358 | .cr(2) |
| 18359 | .kr(4) |
| 18360 | .channels(2) |
| 18361 | .width(5) |
| 18362 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18363 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18364 | } |
| 18365 | } |
| 18366 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18367 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18368 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18369 | DWConvMicrokernelTester() |
| 18370 | .cr(2) |
| 18371 | .kr(4) |
| 18372 | .channels(channels) |
| 18373 | .width(3) |
| 18374 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18375 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18376 | } |
| 18377 | } |
| 18378 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18379 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18380 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18381 | DWConvMicrokernelTester() |
| 18382 | .cr(2) |
| 18383 | .kr(4) |
| 18384 | .channels(channels) |
| 18385 | .width(3) |
| 18386 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18387 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18388 | } |
| 18389 | } |
| 18390 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 18391 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, input_offset) { |
| 18392 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18393 | DWConvMicrokernelTester() |
| 18394 | .cr(2) |
| 18395 | .kr(4) |
| 18396 | .channels(channels) |
| 18397 | .input_offset(80) |
| 18398 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 18399 | } |
| 18400 | } |
| 18401 | |
| 18402 | TEST(F32_DWCONV_MINMAX_UP2X4__SCALAR_ACC2, zero) { |
| 18403 | for (uint32_t mz = 0; mz < 4; mz++) { |
| 18404 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18405 | DWConvMicrokernelTester() |
| 18406 | .cr(2) |
| 18407 | .kr(4) |
| 18408 | .channels(channels) |
| 18409 | .input_offset(80) |
| 18410 | .zero_index(mz) |
| 18411 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x4__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 18412 | } |
| 18413 | } |
| 18414 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18415 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18416 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18417 | DWConvMicrokernelTester() |
| 18418 | .cr(1) |
| 18419 | .kr(9) |
| 18420 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18421 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18422 | } |
| 18423 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18424 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18425 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 18426 | DWConvMicrokernelTester() |
| 18427 | .cr(1) |
| 18428 | .kr(9) |
| 18429 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18430 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18431 | } |
| 18432 | } |
| 18433 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18434 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18435 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 18436 | DWConvMicrokernelTester() |
| 18437 | .cr(1) |
| 18438 | .kr(9) |
| 18439 | .channels(channels) |
| 18440 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18441 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18442 | } |
| 18443 | } |
| 18444 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18445 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18446 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 18447 | DWConvMicrokernelTester() |
| 18448 | .cr(1) |
| 18449 | .kr(9) |
| 18450 | .channels(channels) |
| 18451 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18452 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18453 | } |
| 18454 | } |
| 18455 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18456 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18457 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18458 | DWConvMicrokernelTester() |
| 18459 | .cr(1) |
| 18460 | .kr(9) |
| 18461 | .channels(channels) |
| 18462 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18463 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18464 | } |
| 18465 | } |
| 18466 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18467 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18468 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18469 | for (size_t step = 2; step <= 9; step++) { |
| 18470 | DWConvMicrokernelTester() |
| 18471 | .cr(1) |
| 18472 | .kr(9) |
| 18473 | .channels(channels) |
| 18474 | .width(3) |
| 18475 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18476 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18477 | } |
| 18478 | } |
| 18479 | } |
| 18480 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18481 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18482 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18483 | DWConvMicrokernelTester() |
| 18484 | .cr(1) |
| 18485 | .kr(9) |
| 18486 | .channels(1) |
| 18487 | .width(5) |
| 18488 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18489 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18490 | } |
| 18491 | } |
| 18492 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18493 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18494 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18495 | DWConvMicrokernelTester() |
| 18496 | .cr(1) |
| 18497 | .kr(9) |
| 18498 | .channels(channels) |
| 18499 | .width(3) |
| 18500 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18501 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18502 | } |
| 18503 | } |
| 18504 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18505 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18506 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18507 | DWConvMicrokernelTester() |
| 18508 | .cr(1) |
| 18509 | .kr(9) |
| 18510 | .channels(channels) |
| 18511 | .width(3) |
| 18512 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18513 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18514 | } |
| 18515 | } |
| 18516 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 18517 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, input_offset) { |
| 18518 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 18519 | DWConvMicrokernelTester() |
| 18520 | .cr(1) |
| 18521 | .kr(9) |
| 18522 | .channels(channels) |
| 18523 | .input_offset(48) |
| 18524 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 18525 | } |
| 18526 | } |
| 18527 | |
| 18528 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR, zero) { |
| 18529 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 18530 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 18531 | DWConvMicrokernelTester() |
| 18532 | .cr(1) |
| 18533 | .kr(9) |
| 18534 | .channels(channels) |
| 18535 | .input_offset(48) |
| 18536 | .zero_index(mz) |
| 18537 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 18538 | } |
| 18539 | } |
| 18540 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18541 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18542 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18543 | DWConvMicrokernelTester() |
| 18544 | .cr(1) |
| 18545 | .kr(9) |
| 18546 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18547 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18548 | } |
| 18549 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18550 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18551 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 18552 | DWConvMicrokernelTester() |
| 18553 | .cr(1) |
| 18554 | .kr(9) |
| 18555 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18556 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18557 | } |
| 18558 | } |
| 18559 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18560 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18561 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 18562 | DWConvMicrokernelTester() |
| 18563 | .cr(1) |
| 18564 | .kr(9) |
| 18565 | .channels(channels) |
| 18566 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18567 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18568 | } |
| 18569 | } |
| 18570 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18571 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18572 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 18573 | DWConvMicrokernelTester() |
| 18574 | .cr(1) |
| 18575 | .kr(9) |
| 18576 | .channels(channels) |
| 18577 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18578 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18579 | } |
| 18580 | } |
| 18581 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18582 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18583 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18584 | DWConvMicrokernelTester() |
| 18585 | .cr(1) |
| 18586 | .kr(9) |
| 18587 | .channels(channels) |
| 18588 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18589 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18590 | } |
| 18591 | } |
| 18592 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18593 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18594 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18595 | for (size_t step = 2; step <= 9; step++) { |
| 18596 | DWConvMicrokernelTester() |
| 18597 | .cr(1) |
| 18598 | .kr(9) |
| 18599 | .channels(channels) |
| 18600 | .width(3) |
| 18601 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18602 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18603 | } |
| 18604 | } |
| 18605 | } |
| 18606 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18607 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18608 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18609 | DWConvMicrokernelTester() |
| 18610 | .cr(1) |
| 18611 | .kr(9) |
| 18612 | .channels(1) |
| 18613 | .width(5) |
| 18614 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18615 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18616 | } |
| 18617 | } |
| 18618 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18619 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18620 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18621 | DWConvMicrokernelTester() |
| 18622 | .cr(1) |
| 18623 | .kr(9) |
| 18624 | .channels(channels) |
| 18625 | .width(3) |
| 18626 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18627 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18628 | } |
| 18629 | } |
| 18630 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18631 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18632 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 18633 | DWConvMicrokernelTester() |
| 18634 | .cr(1) |
| 18635 | .kr(9) |
| 18636 | .channels(channels) |
| 18637 | .width(3) |
| 18638 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18639 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18640 | } |
| 18641 | } |
| 18642 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 18643 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, input_offset) { |
| 18644 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 18645 | DWConvMicrokernelTester() |
| 18646 | .cr(1) |
| 18647 | .kr(9) |
| 18648 | .channels(channels) |
| 18649 | .input_offset(48) |
| 18650 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 18651 | } |
| 18652 | } |
| 18653 | |
| 18654 | TEST(F32_DWCONV_MINMAX_UP1X9__SCALAR_ACC2, zero) { |
| 18655 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 18656 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 18657 | DWConvMicrokernelTester() |
| 18658 | .cr(1) |
| 18659 | .kr(9) |
| 18660 | .channels(channels) |
| 18661 | .input_offset(48) |
| 18662 | .zero_index(mz) |
| 18663 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 18664 | } |
| 18665 | } |
| 18666 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18667 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18668 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18669 | DWConvMicrokernelTester() |
| 18670 | .cr(2) |
| 18671 | .kr(9) |
| 18672 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18673 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18674 | } |
| 18675 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18676 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18677 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18678 | DWConvMicrokernelTester() |
| 18679 | .cr(2) |
| 18680 | .kr(9) |
| 18681 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18682 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18683 | } |
| 18684 | } |
| 18685 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18686 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18687 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18688 | DWConvMicrokernelTester() |
| 18689 | .cr(2) |
| 18690 | .kr(9) |
| 18691 | .channels(channels) |
| 18692 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18693 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18694 | } |
| 18695 | } |
| 18696 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18697 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18698 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18699 | DWConvMicrokernelTester() |
| 18700 | .cr(2) |
| 18701 | .kr(9) |
| 18702 | .channels(channels) |
| 18703 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18704 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18705 | } |
| 18706 | } |
| 18707 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18708 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18709 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 18710 | DWConvMicrokernelTester() |
| 18711 | .cr(2) |
| 18712 | .kr(9) |
| 18713 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18714 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18715 | } |
| 18716 | } |
| 18717 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18718 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18719 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18720 | DWConvMicrokernelTester() |
| 18721 | .cr(2) |
| 18722 | .kr(9) |
| 18723 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18724 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18725 | } |
| 18726 | } |
| 18727 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18728 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18729 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18730 | DWConvMicrokernelTester() |
| 18731 | .cr(2) |
| 18732 | .kr(9) |
| 18733 | .channels(channels) |
| 18734 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18735 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18736 | } |
| 18737 | } |
| 18738 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18739 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18740 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18741 | DWConvMicrokernelTester() |
| 18742 | .cr(2) |
| 18743 | .kr(9) |
| 18744 | .channels(channels) |
| 18745 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18746 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18747 | } |
| 18748 | } |
| 18749 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18750 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18751 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18752 | DWConvMicrokernelTester() |
| 18753 | .cr(2) |
| 18754 | .kr(9) |
| 18755 | .channels(channels) |
| 18756 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18757 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18758 | } |
| 18759 | } |
| 18760 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18761 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18762 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18763 | for (size_t step = 2; step <= 9; step++) { |
| 18764 | DWConvMicrokernelTester() |
| 18765 | .cr(2) |
| 18766 | .kr(9) |
| 18767 | .channels(channels) |
| 18768 | .width(3) |
| 18769 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18770 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18771 | } |
| 18772 | } |
| 18773 | } |
| 18774 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18775 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18776 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18777 | DWConvMicrokernelTester() |
| 18778 | .cr(2) |
| 18779 | .kr(9) |
| 18780 | .channels(2) |
| 18781 | .width(5) |
| 18782 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18783 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18784 | } |
| 18785 | } |
| 18786 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18787 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18788 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18789 | DWConvMicrokernelTester() |
| 18790 | .cr(2) |
| 18791 | .kr(9) |
| 18792 | .channels(channels) |
| 18793 | .width(3) |
| 18794 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18795 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18796 | } |
| 18797 | } |
| 18798 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18799 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18800 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18801 | DWConvMicrokernelTester() |
| 18802 | .cr(2) |
| 18803 | .kr(9) |
| 18804 | .channels(channels) |
| 18805 | .width(3) |
| 18806 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18807 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18808 | } |
| 18809 | } |
| 18810 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 18811 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, input_offset) { |
| 18812 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18813 | DWConvMicrokernelTester() |
| 18814 | .cr(2) |
| 18815 | .kr(9) |
| 18816 | .channels(channels) |
| 18817 | .input_offset(80) |
| 18818 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 18819 | } |
| 18820 | } |
| 18821 | |
| 18822 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR, zero) { |
| 18823 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 18824 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18825 | DWConvMicrokernelTester() |
| 18826 | .cr(2) |
| 18827 | .kr(9) |
| 18828 | .channels(channels) |
| 18829 | .input_offset(80) |
| 18830 | .zero_index(mz) |
| 18831 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 18832 | } |
| 18833 | } |
| 18834 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18835 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18836 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18837 | DWConvMicrokernelTester() |
| 18838 | .cr(2) |
| 18839 | .kr(9) |
| 18840 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18841 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18842 | } |
| 18843 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18844 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18845 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18846 | DWConvMicrokernelTester() |
| 18847 | .cr(2) |
| 18848 | .kr(9) |
| 18849 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18850 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18851 | } |
| 18852 | } |
| 18853 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18854 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18855 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18856 | DWConvMicrokernelTester() |
| 18857 | .cr(2) |
| 18858 | .kr(9) |
| 18859 | .channels(channels) |
| 18860 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18861 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18862 | } |
| 18863 | } |
| 18864 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18865 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18866 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18867 | DWConvMicrokernelTester() |
| 18868 | .cr(2) |
| 18869 | .kr(9) |
| 18870 | .channels(channels) |
| 18871 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18872 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18873 | } |
| 18874 | } |
| 18875 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18876 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18877 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 18878 | DWConvMicrokernelTester() |
| 18879 | .cr(2) |
| 18880 | .kr(9) |
| 18881 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18882 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18883 | } |
| 18884 | } |
| 18885 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18886 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18887 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18888 | DWConvMicrokernelTester() |
| 18889 | .cr(2) |
| 18890 | .kr(9) |
| 18891 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18892 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18893 | } |
| 18894 | } |
| 18895 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18896 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18897 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18898 | DWConvMicrokernelTester() |
| 18899 | .cr(2) |
| 18900 | .kr(9) |
| 18901 | .channels(channels) |
| 18902 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18903 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18904 | } |
| 18905 | } |
| 18906 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18907 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18908 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 18909 | DWConvMicrokernelTester() |
| 18910 | .cr(2) |
| 18911 | .kr(9) |
| 18912 | .channels(channels) |
| 18913 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18914 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18915 | } |
| 18916 | } |
| 18917 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18918 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18919 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18920 | DWConvMicrokernelTester() |
| 18921 | .cr(2) |
| 18922 | .kr(9) |
| 18923 | .channels(channels) |
| 18924 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18925 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18926 | } |
| 18927 | } |
| 18928 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18929 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18930 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18931 | for (size_t step = 2; step <= 9; step++) { |
| 18932 | DWConvMicrokernelTester() |
| 18933 | .cr(2) |
| 18934 | .kr(9) |
| 18935 | .channels(channels) |
| 18936 | .width(3) |
| 18937 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18938 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18939 | } |
| 18940 | } |
| 18941 | } |
| 18942 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18943 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18944 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18945 | DWConvMicrokernelTester() |
| 18946 | .cr(2) |
| 18947 | .kr(9) |
| 18948 | .channels(2) |
| 18949 | .width(5) |
| 18950 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18951 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18952 | } |
| 18953 | } |
| 18954 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18955 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18956 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18957 | DWConvMicrokernelTester() |
| 18958 | .cr(2) |
| 18959 | .kr(9) |
| 18960 | .channels(channels) |
| 18961 | .width(3) |
| 18962 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18963 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18964 | } |
| 18965 | } |
| 18966 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18967 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18968 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 18969 | DWConvMicrokernelTester() |
| 18970 | .cr(2) |
| 18971 | .kr(9) |
| 18972 | .channels(channels) |
| 18973 | .width(3) |
| 18974 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 18975 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 18976 | } |
| 18977 | } |
| 18978 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 18979 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, input_offset) { |
| 18980 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18981 | DWConvMicrokernelTester() |
| 18982 | .cr(2) |
| 18983 | .kr(9) |
| 18984 | .channels(channels) |
| 18985 | .input_offset(80) |
| 18986 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 18987 | } |
| 18988 | } |
| 18989 | |
| 18990 | TEST(F32_DWCONV_MINMAX_UP2X9__SCALAR_ACC2, zero) { |
| 18991 | for (uint32_t mz = 0; mz < 9; mz++) { |
| 18992 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 18993 | DWConvMicrokernelTester() |
| 18994 | .cr(2) |
| 18995 | .kr(9) |
| 18996 | .channels(channels) |
| 18997 | .input_offset(80) |
| 18998 | .zero_index(mz) |
| 18999 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x9__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 19000 | } |
| 19001 | } |
| 19002 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19003 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19004 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19005 | DWConvMicrokernelTester() |
| 19006 | .cr(1) |
| 19007 | .kr(25) |
| 19008 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19009 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19010 | } |
| 19011 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19012 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19013 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 19014 | DWConvMicrokernelTester() |
| 19015 | .cr(1) |
| 19016 | .kr(25) |
| 19017 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19018 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19019 | } |
| 19020 | } |
| 19021 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19022 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19023 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 19024 | DWConvMicrokernelTester() |
| 19025 | .cr(1) |
| 19026 | .kr(25) |
| 19027 | .channels(channels) |
| 19028 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19029 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19030 | } |
| 19031 | } |
| 19032 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19033 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19034 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 19035 | DWConvMicrokernelTester() |
| 19036 | .cr(1) |
| 19037 | .kr(25) |
| 19038 | .channels(channels) |
| 19039 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19040 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19041 | } |
| 19042 | } |
| 19043 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19044 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19045 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19046 | DWConvMicrokernelTester() |
| 19047 | .cr(1) |
| 19048 | .kr(25) |
| 19049 | .channels(channels) |
| 19050 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19051 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19052 | } |
| 19053 | } |
| 19054 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19055 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19056 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19057 | for (size_t step = 2; step <= 25; step++) { |
| 19058 | DWConvMicrokernelTester() |
| 19059 | .cr(1) |
| 19060 | .kr(25) |
| 19061 | .channels(channels) |
| 19062 | .width(3) |
| 19063 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19064 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19065 | } |
| 19066 | } |
| 19067 | } |
| 19068 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19069 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19070 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19071 | DWConvMicrokernelTester() |
| 19072 | .cr(1) |
| 19073 | .kr(25) |
| 19074 | .channels(1) |
| 19075 | .width(5) |
| 19076 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19077 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19078 | } |
| 19079 | } |
| 19080 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19081 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19082 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19083 | DWConvMicrokernelTester() |
| 19084 | .cr(1) |
| 19085 | .kr(25) |
| 19086 | .channels(channels) |
| 19087 | .width(3) |
| 19088 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19089 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19090 | } |
| 19091 | } |
| 19092 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19093 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19094 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19095 | DWConvMicrokernelTester() |
| 19096 | .cr(1) |
| 19097 | .kr(25) |
| 19098 | .channels(channels) |
| 19099 | .width(3) |
| 19100 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19101 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19102 | } |
| 19103 | } |
| 19104 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 19105 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, input_offset) { |
| 19106 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 19107 | DWConvMicrokernelTester() |
| 19108 | .cr(1) |
| 19109 | .kr(25) |
| 19110 | .channels(channels) |
| 19111 | .input_offset(48) |
| 19112 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 19113 | } |
| 19114 | } |
| 19115 | |
| 19116 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR, zero) { |
| 19117 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 19118 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 19119 | DWConvMicrokernelTester() |
| 19120 | .cr(1) |
| 19121 | .kr(25) |
| 19122 | .channels(channels) |
| 19123 | .input_offset(48) |
| 19124 | .zero_index(mz) |
| 19125 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 19126 | } |
| 19127 | } |
| 19128 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19129 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19130 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, c_eq_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19131 | DWConvMicrokernelTester() |
| 19132 | .cr(1) |
| 19133 | .kr(25) |
| 19134 | .channels(1) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19135 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19136 | } |
| 19137 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19138 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, c_gt_1) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19139 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 19140 | DWConvMicrokernelTester() |
| 19141 | .cr(1) |
| 19142 | .kr(25) |
| 19143 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19144 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19145 | } |
| 19146 | } |
| 19147 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19148 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, c_gt_1_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19149 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 19150 | DWConvMicrokernelTester() |
| 19151 | .cr(1) |
| 19152 | .kr(25) |
| 19153 | .channels(channels) |
| 19154 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19155 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19156 | } |
| 19157 | } |
| 19158 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19159 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, c_gt_1_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19160 | for (uint32_t channels = 2; channels < 10; channels++) { |
| 19161 | DWConvMicrokernelTester() |
| 19162 | .cr(1) |
| 19163 | .kr(25) |
| 19164 | .channels(channels) |
| 19165 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19166 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19167 | } |
| 19168 | } |
| 19169 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19170 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19171 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19172 | DWConvMicrokernelTester() |
| 19173 | .cr(1) |
| 19174 | .kr(25) |
| 19175 | .channels(channels) |
| 19176 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19177 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19178 | } |
| 19179 | } |
| 19180 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19181 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19182 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19183 | for (size_t step = 2; step <= 25; step++) { |
| 19184 | DWConvMicrokernelTester() |
| 19185 | .cr(1) |
| 19186 | .kr(25) |
| 19187 | .channels(channels) |
| 19188 | .width(3) |
| 19189 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19190 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19191 | } |
| 19192 | } |
| 19193 | } |
| 19194 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19195 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19196 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19197 | DWConvMicrokernelTester() |
| 19198 | .cr(1) |
| 19199 | .kr(25) |
| 19200 | .channels(1) |
| 19201 | .width(5) |
| 19202 | .output_stride(7) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19203 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19204 | } |
| 19205 | } |
| 19206 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19207 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19208 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19209 | DWConvMicrokernelTester() |
| 19210 | .cr(1) |
| 19211 | .kr(25) |
| 19212 | .channels(channels) |
| 19213 | .width(3) |
| 19214 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19215 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19216 | } |
| 19217 | } |
| 19218 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19219 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19220 | for (size_t channels = 1; channels <= 5; channels += 1) { |
| 19221 | DWConvMicrokernelTester() |
| 19222 | .cr(1) |
| 19223 | .kr(25) |
| 19224 | .channels(channels) |
| 19225 | .width(3) |
| 19226 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19227 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19228 | } |
| 19229 | } |
| 19230 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 19231 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, input_offset) { |
| 19232 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 19233 | DWConvMicrokernelTester() |
| 19234 | .cr(1) |
| 19235 | .kr(25) |
| 19236 | .channels(channels) |
| 19237 | .input_offset(48) |
| 19238 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 19239 | } |
| 19240 | } |
| 19241 | |
| 19242 | TEST(F32_DWCONV_MINMAX_UP1X25__SCALAR_ACC2, zero) { |
| 19243 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 19244 | for (uint32_t channels = 2; channels < 16; channels += 3) { |
| 19245 | DWConvMicrokernelTester() |
| 19246 | .cr(1) |
| 19247 | .kr(25) |
| 19248 | .channels(channels) |
| 19249 | .input_offset(48) |
| 19250 | .zero_index(mz) |
| 19251 | .Test(xnn_f32_dwconv_minmax_ukernel_up1x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 19252 | } |
| 19253 | } |
| 19254 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19255 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19256 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19257 | DWConvMicrokernelTester() |
| 19258 | .cr(2) |
| 19259 | .kr(25) |
| 19260 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19261 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19262 | } |
| 19263 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19264 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19265 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19266 | DWConvMicrokernelTester() |
| 19267 | .cr(2) |
| 19268 | .kr(25) |
| 19269 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19270 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19271 | } |
| 19272 | } |
| 19273 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19274 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19275 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19276 | DWConvMicrokernelTester() |
| 19277 | .cr(2) |
| 19278 | .kr(25) |
| 19279 | .channels(channels) |
| 19280 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19281 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19282 | } |
| 19283 | } |
| 19284 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19285 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19286 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19287 | DWConvMicrokernelTester() |
| 19288 | .cr(2) |
| 19289 | .kr(25) |
| 19290 | .channels(channels) |
| 19291 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19292 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19293 | } |
| 19294 | } |
| 19295 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19296 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19297 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 19298 | DWConvMicrokernelTester() |
| 19299 | .cr(2) |
| 19300 | .kr(25) |
| 19301 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19302 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19303 | } |
| 19304 | } |
| 19305 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19306 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19307 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 19308 | DWConvMicrokernelTester() |
| 19309 | .cr(2) |
| 19310 | .kr(25) |
| 19311 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19312 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19313 | } |
| 19314 | } |
| 19315 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19316 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19317 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 19318 | DWConvMicrokernelTester() |
| 19319 | .cr(2) |
| 19320 | .kr(25) |
| 19321 | .channels(channels) |
| 19322 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19323 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19324 | } |
| 19325 | } |
| 19326 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19327 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19328 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 19329 | DWConvMicrokernelTester() |
| 19330 | .cr(2) |
| 19331 | .kr(25) |
| 19332 | .channels(channels) |
| 19333 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19334 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19335 | } |
| 19336 | } |
| 19337 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19338 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19339 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19340 | DWConvMicrokernelTester() |
| 19341 | .cr(2) |
| 19342 | .kr(25) |
| 19343 | .channels(channels) |
| 19344 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19345 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19346 | } |
| 19347 | } |
| 19348 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19349 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19350 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19351 | for (size_t step = 2; step <= 25; step++) { |
| 19352 | DWConvMicrokernelTester() |
| 19353 | .cr(2) |
| 19354 | .kr(25) |
| 19355 | .channels(channels) |
| 19356 | .width(3) |
| 19357 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19358 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19359 | } |
| 19360 | } |
| 19361 | } |
| 19362 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19363 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19364 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19365 | DWConvMicrokernelTester() |
| 19366 | .cr(2) |
| 19367 | .kr(25) |
| 19368 | .channels(2) |
| 19369 | .width(5) |
| 19370 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19371 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19372 | } |
| 19373 | } |
| 19374 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19375 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19376 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19377 | DWConvMicrokernelTester() |
| 19378 | .cr(2) |
| 19379 | .kr(25) |
| 19380 | .channels(channels) |
| 19381 | .width(3) |
| 19382 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19383 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19384 | } |
| 19385 | } |
| 19386 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19387 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19388 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19389 | DWConvMicrokernelTester() |
| 19390 | .cr(2) |
| 19391 | .kr(25) |
| 19392 | .channels(channels) |
| 19393 | .width(3) |
| 19394 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19395 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19396 | } |
| 19397 | } |
| 19398 | |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 19399 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, input_offset) { |
| 19400 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19401 | DWConvMicrokernelTester() |
| 19402 | .cr(2) |
| 19403 | .kr(25) |
| 19404 | .channels(channels) |
| 19405 | .input_offset(80) |
| 19406 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 19407 | } |
| 19408 | } |
| 19409 | |
| 19410 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR, zero) { |
| 19411 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 19412 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19413 | DWConvMicrokernelTester() |
| 19414 | .cr(2) |
| 19415 | .kr(25) |
| 19416 | .channels(channels) |
| 19417 | .input_offset(80) |
| 19418 | .zero_index(mz) |
| 19419 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar, DWConvMicrokernelTester::Variant::Scalar); |
| 19420 | } |
| 19421 | } |
| 19422 | } |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19423 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19424 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_eq_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19425 | DWConvMicrokernelTester() |
| 19426 | .cr(2) |
| 19427 | .kr(25) |
| 19428 | .channels(2) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19429 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19430 | } |
| 19431 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19432 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_div_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19433 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19434 | DWConvMicrokernelTester() |
| 19435 | .cr(2) |
| 19436 | .kr(25) |
| 19437 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19438 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19439 | } |
| 19440 | } |
| 19441 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19442 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_div_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19443 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19444 | DWConvMicrokernelTester() |
| 19445 | .cr(2) |
| 19446 | .kr(25) |
| 19447 | .channels(channels) |
| 19448 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19449 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19450 | } |
| 19451 | } |
| 19452 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19453 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_div_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19454 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19455 | DWConvMicrokernelTester() |
| 19456 | .cr(2) |
| 19457 | .kr(25) |
| 19458 | .channels(channels) |
| 19459 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19460 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19461 | } |
| 19462 | } |
| 19463 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19464 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_lt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19465 | for (uint32_t channels = 1; channels < 2; channels++) { |
| 19466 | DWConvMicrokernelTester() |
| 19467 | .cr(2) |
| 19468 | .kr(25) |
| 19469 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19470 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19471 | } |
| 19472 | } |
| 19473 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19474 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_gt_2) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19475 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 19476 | DWConvMicrokernelTester() |
| 19477 | .cr(2) |
| 19478 | .kr(25) |
| 19479 | .channels(channels) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19480 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19481 | } |
| 19482 | } |
| 19483 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19484 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_gt_2_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19485 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 19486 | DWConvMicrokernelTester() |
| 19487 | .cr(2) |
| 19488 | .kr(25) |
| 19489 | .channels(channels) |
| 19490 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19491 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19492 | } |
| 19493 | } |
| 19494 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19495 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, c_gt_2_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19496 | for (uint32_t channels = 3; channels < 4; channels++) { |
| 19497 | DWConvMicrokernelTester() |
| 19498 | .cr(2) |
| 19499 | .kr(25) |
| 19500 | .channels(channels) |
| 19501 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19502 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19503 | } |
| 19504 | } |
| 19505 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19506 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, multipixel) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19507 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19508 | DWConvMicrokernelTester() |
| 19509 | .cr(2) |
| 19510 | .kr(25) |
| 19511 | .channels(channels) |
| 19512 | .width(3) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19513 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19514 | } |
| 19515 | } |
| 19516 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19517 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, multipixel_with_step) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19518 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19519 | for (size_t step = 2; step <= 25; step++) { |
| 19520 | DWConvMicrokernelTester() |
| 19521 | .cr(2) |
| 19522 | .kr(25) |
| 19523 | .channels(channels) |
| 19524 | .width(3) |
| 19525 | .step(step) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19526 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19527 | } |
| 19528 | } |
| 19529 | } |
| 19530 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19531 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, multipixel_with_output_stride) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19532 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19533 | DWConvMicrokernelTester() |
| 19534 | .cr(2) |
| 19535 | .kr(25) |
| 19536 | .channels(2) |
| 19537 | .width(5) |
| 19538 | .output_stride(13) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19539 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19540 | } |
| 19541 | } |
| 19542 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19543 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, multipixel_with_qmin) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19544 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19545 | DWConvMicrokernelTester() |
| 19546 | .cr(2) |
| 19547 | .kr(25) |
| 19548 | .channels(channels) |
| 19549 | .width(3) |
| 19550 | .qmin(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19551 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19552 | } |
| 19553 | } |
| 19554 | |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19555 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, multipixel_with_qmax) { |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19556 | for (size_t channels = 1; channels <= 10; channels += 1) { |
| 19557 | DWConvMicrokernelTester() |
| 19558 | .cr(2) |
| 19559 | .kr(25) |
| 19560 | .channels(channels) |
| 19561 | .width(3) |
| 19562 | .qmax(128) |
Marat Dukhan | de06f49 | 2020-04-09 00:19:31 -0700 | [diff] [blame] | 19563 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
Marat Dukhan | 1c58711 | 2020-04-08 20:04:28 -0700 | [diff] [blame] | 19564 | } |
| 19565 | } |
Frank Barchard | d536072 | 2020-05-17 16:10:36 -0700 | [diff] [blame] | 19566 | |
| 19567 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, input_offset) { |
| 19568 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19569 | DWConvMicrokernelTester() |
| 19570 | .cr(2) |
| 19571 | .kr(25) |
| 19572 | .channels(channels) |
| 19573 | .input_offset(80) |
| 19574 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 19575 | } |
| 19576 | } |
| 19577 | |
| 19578 | TEST(F32_DWCONV_MINMAX_UP2X25__SCALAR_ACC2, zero) { |
| 19579 | for (uint32_t mz = 0; mz < 25; mz++) { |
| 19580 | for (uint32_t channels = 4; channels < 32; channels += 6) { |
| 19581 | DWConvMicrokernelTester() |
| 19582 | .cr(2) |
| 19583 | .kr(25) |
| 19584 | .channels(channels) |
| 19585 | .input_offset(80) |
| 19586 | .zero_index(mz) |
| 19587 | .Test(xnn_f32_dwconv_minmax_ukernel_up2x25__scalar_acc2, DWConvMicrokernelTester::Variant::Scalar); |
| 19588 | } |
| 19589 | } |
| 19590 | } |