Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 1 | // Auto-generated file. Do not edit! |
| 2 | // Template: src/f32-dwconv/up-neon.c.in |
| 3 | // Generator: tools/xngen |
| 4 | // |
| 5 | // Copyright 2019 Google LLC |
| 6 | // |
| 7 | // This source code is licensed under the BSD-style license found in the |
| 8 | // LICENSE file in the root directory of this source tree. |
| 9 | |
| 10 | #include <assert.h> |
| 11 | |
| 12 | #include <arm_neon.h> |
| 13 | |
| 14 | #include <xnnpack/dwconv.h> |
| 15 | |
| 16 | |
| 17 | void xnn_f32_dwconv_ukernel_up4x9__neonfma_acc2( |
| 18 | size_t channels, |
| 19 | size_t output_width, |
| 20 | const float** input, |
| 21 | const float* weights, |
| 22 | float* output, |
| 23 | size_t input_stride, |
| 24 | size_t output_increment, |
Marat Dukhan | eb09a6b | 2020-04-08 17:34:32 -0700 | [diff] [blame] | 25 | const union xnn_f32_minmax_params params[restrict static 1]) |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 26 | { |
| 27 | assert(channels != 0); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 28 | assert(output_width != 0); |
| 29 | |
| 30 | const float32x4_t vmax = vld1q_dup_f32(¶ms->scalar.max); |
| 31 | const float32x4_t vmin = vld1q_dup_f32(¶ms->scalar.min); |
| 32 | do { |
| 33 | const float* i0 = input[0]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 34 | assert(i0 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 35 | const float* i1 = input[1]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 36 | assert(i1 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 37 | const float* i2 = input[2]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 38 | assert(i2 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 39 | const float* i3 = input[3]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 40 | assert(i3 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 41 | const float* i4 = input[4]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 42 | assert(i4 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 43 | const float* i5 = input[5]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 44 | assert(i5 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 45 | const float* i6 = input[6]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 46 | assert(i6 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 47 | const float* i7 = input[7]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 48 | assert(i7 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 49 | const float* i8 = input[8]; |
Marat Dukhan | 6866099 | 2020-02-03 13:31:12 -0800 | [diff] [blame] | 50 | assert(i8 != NULL); |
Marat Dukhan | 5098c3e | 2019-11-07 12:01:19 -0800 | [diff] [blame] | 51 | input = (const float**) ((uintptr_t) input + input_stride); |
| 52 | |
| 53 | size_t c = channels; |
| 54 | const float* w = weights; |
| 55 | for (; c >= 4; c -= 4) { |
| 56 | float32x4_t vacc0123p0 = vld1q_f32(w); w += 4; |
| 57 | |
| 58 | |
| 59 | const float32x4_t vi0x0123 = vld1q_f32(i0); i0 += 4; |
| 60 | const float32x4_t vk0x0123 = vld1q_f32(w); w += 4; |
| 61 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi0x0123, vk0x0123); |
| 62 | |
| 63 | const float32x4_t vi1x0123 = vld1q_f32(i1); i1 += 4; |
| 64 | const float32x4_t vk1x0123 = vld1q_f32(w); w += 4; |
| 65 | float32x4_t vacc0123p1 = vmulq_f32(vi1x0123, vk1x0123); |
| 66 | |
| 67 | const float32x4_t vi2x0123 = vld1q_f32(i2); i2 += 4; |
| 68 | const float32x4_t vk2x0123 = vld1q_f32(w); w += 4; |
| 69 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi2x0123, vk2x0123); |
| 70 | |
| 71 | const float32x4_t vi3x0123 = vld1q_f32(i3); i3 += 4; |
| 72 | const float32x4_t vk3x0123 = vld1q_f32(w); w += 4; |
| 73 | vacc0123p1 = vfmaq_f32(vacc0123p1, vi3x0123, vk3x0123); |
| 74 | |
| 75 | const float32x4_t vi4x0123 = vld1q_f32(i4); i4 += 4; |
| 76 | const float32x4_t vk4x0123 = vld1q_f32(w); w += 4; |
| 77 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi4x0123, vk4x0123); |
| 78 | |
| 79 | const float32x4_t vi5x0123 = vld1q_f32(i5); i5 += 4; |
| 80 | const float32x4_t vk5x0123 = vld1q_f32(w); w += 4; |
| 81 | vacc0123p1 = vfmaq_f32(vacc0123p1, vi5x0123, vk5x0123); |
| 82 | |
| 83 | const float32x4_t vi6x0123 = vld1q_f32(i6); i6 += 4; |
| 84 | const float32x4_t vk6x0123 = vld1q_f32(w); w += 4; |
| 85 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi6x0123, vk6x0123); |
| 86 | |
| 87 | const float32x4_t vi7x0123 = vld1q_f32(i7); i7 += 4; |
| 88 | const float32x4_t vk7x0123 = vld1q_f32(w); w += 4; |
| 89 | vacc0123p1 = vfmaq_f32(vacc0123p1, vi7x0123, vk7x0123); |
| 90 | |
| 91 | const float32x4_t vi8x0123 = vld1q_f32(i8); i8 += 4; |
| 92 | const float32x4_t vk8x0123 = vld1q_f32(w); w += 4; |
| 93 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi8x0123, vk8x0123); |
| 94 | |
| 95 | // Add up all accumulators to vacc0123p0 |
| 96 | vacc0123p0 = vaddq_f32(vacc0123p0, vacc0123p1); |
| 97 | |
| 98 | float32x4_t vacc0123 = vmaxq_f32(vacc0123p0, vmin); |
| 99 | vacc0123 = vminq_f32(vacc0123, vmax); |
| 100 | |
| 101 | vst1q_f32(output, vacc0123); output += 4; |
| 102 | } |
| 103 | if XNN_UNLIKELY(c != 0) { |
| 104 | float32x4_t vacc0123p0 = vld1q_f32(w); w += 4; |
| 105 | |
| 106 | |
| 107 | const float32x4_t vi0x0123 = vld1q_f32(i0); |
| 108 | const float32x4_t vk0x0123 = vld1q_f32(w); w += 4; |
| 109 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi0x0123, vk0x0123); |
| 110 | |
| 111 | const float32x4_t vi1x0123 = vld1q_f32(i1); |
| 112 | const float32x4_t vk1x0123 = vld1q_f32(w); w += 4; |
| 113 | float32x4_t vacc0123p1 = vmulq_f32(vi1x0123, vk1x0123); |
| 114 | |
| 115 | const float32x4_t vi2x0123 = vld1q_f32(i2); |
| 116 | const float32x4_t vk2x0123 = vld1q_f32(w); w += 4; |
| 117 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi2x0123, vk2x0123); |
| 118 | |
| 119 | const float32x4_t vi3x0123 = vld1q_f32(i3); |
| 120 | const float32x4_t vk3x0123 = vld1q_f32(w); w += 4; |
| 121 | vacc0123p1 = vfmaq_f32(vacc0123p1, vi3x0123, vk3x0123); |
| 122 | |
| 123 | const float32x4_t vi4x0123 = vld1q_f32(i4); |
| 124 | const float32x4_t vk4x0123 = vld1q_f32(w); w += 4; |
| 125 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi4x0123, vk4x0123); |
| 126 | |
| 127 | const float32x4_t vi5x0123 = vld1q_f32(i5); |
| 128 | const float32x4_t vk5x0123 = vld1q_f32(w); w += 4; |
| 129 | vacc0123p1 = vfmaq_f32(vacc0123p1, vi5x0123, vk5x0123); |
| 130 | |
| 131 | const float32x4_t vi6x0123 = vld1q_f32(i6); |
| 132 | const float32x4_t vk6x0123 = vld1q_f32(w); w += 4; |
| 133 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi6x0123, vk6x0123); |
| 134 | |
| 135 | const float32x4_t vi7x0123 = vld1q_f32(i7); |
| 136 | const float32x4_t vk7x0123 = vld1q_f32(w); w += 4; |
| 137 | vacc0123p1 = vfmaq_f32(vacc0123p1, vi7x0123, vk7x0123); |
| 138 | |
| 139 | const float32x4_t vi8x0123 = vld1q_f32(i8); |
| 140 | const float32x4_t vk8x0123 = vld1q_f32(w); w += 4; |
| 141 | vacc0123p0 = vfmaq_f32(vacc0123p0, vi8x0123, vk8x0123); |
| 142 | |
| 143 | // Add up all accumulators to vacc0123p0 |
| 144 | vacc0123p0 = vaddq_f32(vacc0123p0, vacc0123p1); |
| 145 | |
| 146 | float32x4_t vacc0123 = vmaxq_f32(vacc0123p0, vmin); |
| 147 | vacc0123 = vminq_f32(vacc0123, vmax); |
| 148 | |
| 149 | float32x2_t vacc01 = vget_low_f32(vacc0123); |
| 150 | if (c & 2) { |
| 151 | vst1_f32(output, vacc01); output += 2; |
| 152 | vacc01 = vget_high_f32(vacc0123); |
| 153 | } |
| 154 | if (c & 1) { |
| 155 | vst1_lane_f32(output, vacc01, 0); output += 1; |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | output = (float*) ((uintptr_t) output + output_increment); |
| 160 | } while (--output_width != 0); |
| 161 | } |