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Marat Dukhan17ec5f32019-11-22 13:34:16 -08001// Auto-generated file. Do not edit!
2// Template: src/f32-dwconv/up-avx.c.in
3// Generator: tools/xngen
4//
5// Copyright 2019 Google LLC
6//
7// This source code is licensed under the BSD-style license found in the
8// LICENSE file in the root directory of this source tree.
9
10#include <assert.h>
11
12#include <immintrin.h>
13
14#include <xnnpack/dwconv.h>
15
16
17static const int32_t mask_table[14] = {-1, -1, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0};
18
19void xnn_f32_dwconv_ukernel_up8x4__avx_acc2(
20 size_t channels,
21 size_t output_width,
22 const float** input,
23 const float* weights,
24 float* output,
25 size_t input_stride,
26 size_t output_increment,
Marat Dukhaneb09a6b2020-04-08 17:34:32 -070027 const union xnn_f32_minmax_params params[restrict static 1])
Marat Dukhan17ec5f32019-11-22 13:34:16 -080028{
29 assert(channels != 0);
30 assert(output_width != 0);
31
32 const __m256 vmax = _mm256_broadcast_ps((const __m128*) params->sse.max);
33 const __m256 vmin = _mm256_broadcast_ps((const __m128*) params->sse.min);
34 do {
35 const float* i0 = input[0];
Marat Dukhan68660992020-02-03 13:31:12 -080036 assert(i0 != NULL);
Marat Dukhan17ec5f32019-11-22 13:34:16 -080037 const float* i1 = input[1];
Marat Dukhan68660992020-02-03 13:31:12 -080038 assert(i1 != NULL);
Marat Dukhan17ec5f32019-11-22 13:34:16 -080039 const float* i2 = input[2];
Marat Dukhan68660992020-02-03 13:31:12 -080040 assert(i2 != NULL);
Marat Dukhan17ec5f32019-11-22 13:34:16 -080041 const float* i3 = input[3];
Marat Dukhan68660992020-02-03 13:31:12 -080042 assert(i3 != NULL);
Marat Dukhan17ec5f32019-11-22 13:34:16 -080043 input = (const float**) ((uintptr_t) input + input_stride);
44
45 size_t c = channels;
46 const float* w = weights;
47 for (; c >= 8; c -= 8) {
48 __m256 vacc01234567p0 = _mm256_load_ps(w);
49
50
51 const __m256 vi0x01234567 = _mm256_loadu_ps(i0);
52 i0 += 8;
53
54 const __m256 vk0x01234567 = _mm256_load_ps(w + 8);
55 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi0x01234567, vk0x01234567));
56
57 const __m256 vi1x01234567 = _mm256_loadu_ps(i1);
58 i1 += 8;
59
60 const __m256 vk1x01234567 = _mm256_load_ps(w + 16);
61 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
62
63 const __m256 vi2x01234567 = _mm256_loadu_ps(i2);
64 i2 += 8;
65
66 const __m256 vk2x01234567 = _mm256_load_ps(w + 24);
67 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi2x01234567, vk2x01234567));
68
69 const __m256 vi3x01234567 = _mm256_loadu_ps(i3);
70 i3 += 8;
71
72 const __m256 vk3x01234567 = _mm256_load_ps(w + 32);
73 vacc01234567p1 = _mm256_add_ps(vacc01234567p1, _mm256_mul_ps(vi3x01234567, vk3x01234567));
74
75 w += 40;
76
77 // Add up all accumulators to vacc01234567p0
78 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
79
80 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
81 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
82
83 _mm256_storeu_ps(output, vacc01234567);
84 output += 8;
85 }
86 if XNN_UNLIKELY(c != 0) {
87 assert(c >= 1);
88 assert(c <= 7);
89 __m256i vmask = _mm256_loadu_si256((const __m256i*) &mask_table[7 - c]);
90
91 __m256 vacc01234567p0 = _mm256_load_ps(w);
92
93 const __m256 vi0x01234567 = _mm256_maskload_ps(i0, vmask);
94 const __m256 vk0x01234567 = _mm256_load_ps(w + 8);
95 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi0x01234567, vk0x01234567));
96
97 const __m256 vi1x01234567 = _mm256_maskload_ps(i1, vmask);
98 const __m256 vk1x01234567 = _mm256_load_ps(w + 16);
99 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
100
101 const __m256 vi2x01234567 = _mm256_maskload_ps(i2, vmask);
102 const __m256 vk2x01234567 = _mm256_load_ps(w + 24);
103 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi2x01234567, vk2x01234567));
104
105 const __m256 vi3x01234567 = _mm256_maskload_ps(i3, vmask);
106 const __m256 vk3x01234567 = _mm256_load_ps(w + 32);
107 vacc01234567p1 = _mm256_add_ps(vacc01234567p1, _mm256_mul_ps(vi3x01234567, vk3x01234567));
108
109 // Add up all accumulators to vacc01234567p0
110 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
111
112 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
113 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
114
Marat Dukhand16d0f02020-02-05 21:33:05 -0800115 // _mm256_maskstore_ps(output, vmask, vacc01234567); output += c; could be used here, but triggers msan failures (probably an msan bug).
116 __m128 vacc0123 = _mm256_castps256_ps128(vacc01234567);
117 if (c & 4) {
118 _mm_storeu_ps(output, vacc0123);
119 vacc0123 = _mm256_extractf128_ps(vacc01234567, 1);
120 output += 4;
121 }
122 if (c & 2) {
123 _mm_storel_pi((__m64*) output, vacc0123);
124 vacc0123 = _mm_movehl_ps(vacc0123, vacc0123);
125 output += 2;
126 }
127 if (c & 1) {
128 _mm_store_ss(output, vacc0123);
129 output += 1;
130 }
Marat Dukhan17ec5f32019-11-22 13:34:16 -0800131 }
132
133 output = (float*) ((uintptr_t) output + output_increment);
134 } while (--output_width != 0);
135}