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gerrit-public.fairphone.software / platform / external / XNNPACK / 1f29b806ebd61c56d9ad9b4dd36ea387d0c46cc7 / . / test / f32-dwconv-chw.cc
blob: c7434d4336ab6e468a14a414fe8ce2558f40413c [file] [log] [blame]
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1// Copyright 2019 Google LLC
2//
3// This source code is licensed under the BSD-style license found in the
4// LICENSE file in the root directory of this source tree.
5
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]6#include <gtest/gtest.h>
7
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]8#include <xnnpack/common.h>
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]9#include <xnnpack/isa-checks.h>
10
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]11#include <xnnpack/dwconv.h>
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]12#include "dwconv-chw-microkernel-tester.h"
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]13
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]14#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]15 TEST(F32_DWCONV_CHW_3X3P1__SSE, input_width_eq_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]16 TEST_REQUIRES_X86_SSE;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]17 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]18 .input_tuple_size(4)
19 .output_tuple_size(4)
20 .input_width(4)
21 .padding_left(1)
22 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]23 .padding_top(1)
24 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]25 .kernel_height(3)
26 .kernel_width(3)
27 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]28 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]29 }
30
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]31 TEST(F32_DWCONV_CHW_3X3P1__SSE, input_width_lt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]32 TEST_REQUIRES_X86_SSE;
33 for (size_t input_width = 1; input_width < 4; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]34 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]35 .input_tuple_size(4)
36 .output_tuple_size(4)
37 .input_width(input_width)
38 .padding_left(1)
39 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]40 .padding_top(1)
41 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]42 .kernel_height(3)
43 .kernel_width(3)
44 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]45 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]46 }
47 }
48
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]49 TEST(F32_DWCONV_CHW_3X3P1__SSE, input_width_gt_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]50 TEST_REQUIRES_X86_SSE;
51 for (size_t input_width = 5; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]52 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]53 .input_tuple_size(4)
54 .output_tuple_size(4)
55 .input_width(input_width)
56 .padding_left(1)
57 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]58 .padding_top(1)
59 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]60 .kernel_height(3)
61 .kernel_width(3)
62 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]63 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]64 }
65 }
66
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]67 TEST(F32_DWCONV_CHW_3X3P1__SSE, input_width_div_4) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]68 TEST_REQUIRES_X86_SSE;
69 for (size_t input_width = 8; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]70 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]71 .input_tuple_size(4)
72 .output_tuple_size(4)
73 .input_width(input_width)
74 .padding_left(1)
75 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]76 .padding_top(1)
77 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]78 .kernel_height(3)
79 .kernel_width(3)
80 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]81 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]82 }
83 }
84
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]85 TEST(F32_DWCONV_CHW_3X3P1__SSE, input_width_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]86 TEST_REQUIRES_X86_SSE;
87 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]88 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]89 .input_tuple_size(4)
90 .output_tuple_size(4)
91 .input_width(input_width)
92 .input_width_stride(36)
93 .padding_left(1)
94 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]95 .padding_top(1)
96 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]97 .kernel_height(3)
98 .kernel_width(3)
99 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]100 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]101 }
102 }
103
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]104 TEST(F32_DWCONV_CHW_3X3P1__SSE, input_tuple_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]105 TEST_REQUIRES_X86_SSE;
106 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]107 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]108 .input_tuple_size(4)
109 .output_tuple_size(4)
110 .input_width(input_width)
111 .input_width_stride(4)
112 .input_tuple_stride(3 * 4)
113 .padding_left(1)
114 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]115 .padding_top(1)
116 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]117 .kernel_height(3)
118 .kernel_width(3)
119 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]120 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]121 }
122 }
123
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]124 TEST(F32_DWCONV_CHW_3X3P1__SSE, output_height_gt_1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]125 TEST_REQUIRES_X86_SSE;
126 for (size_t output_height = 2; output_height < 5; output_height++) {
127 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]128 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]129 .input_tuple_size(4)
130 .output_tuple_size(4)
131 .input_width(input_width)
132 .padding_left(1)
133 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]134 .padding_top(1)
135 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]136 .kernel_height(3)
137 .kernel_width(3)
138 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]139 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]140 }
141 }
142 }
143
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]144 TEST(F32_DWCONV_CHW_3X3P1__SSE, output_width_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]145 TEST_REQUIRES_X86_SSE;
146 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]147 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]148 .input_tuple_size(4)
149 .output_tuple_size(4)
150 .input_width(input_width)
151 .padding_left(1)
152 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]153 .padding_top(1)
154 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]155 .kernel_height(3)
156 .kernel_width(3)
157 .output_height(5)
158 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]159 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]160 }
161 }
162
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]163 TEST(F32_DWCONV_CHW_3X3P1__SSE, output_tuple_stride) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]164 TEST_REQUIRES_X86_SSE;
165 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]166 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]167 .input_tuple_size(4)
168 .output_tuple_size(4)
169 .input_width(input_width)
170 .padding_left(1)
171 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]172 .padding_top(1)
173 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]174 .kernel_height(3)
175 .kernel_width(3)
176 .output_height(5)
177 .output_width_stride(4)
178 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]179 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]180 }
181 }
182
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]183 TEST(F32_DWCONV_CHW_3X3P1__SSE, chw_layout) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]184 TEST_REQUIRES_X86_SSE;
185 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]186 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]187 .input_tuple_size(4)
188 .output_tuple_size(4)
189 .input_width(input_width)
190 .input_width_stride(input_width)
191 .padding_left(1)
192 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]193 .padding_top(1)
194 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]195 .kernel_height(3)
196 .kernel_width(3)
197 .output_height(5)
198 .output_width_stride(input_width)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]199 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]200 }
201 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]202#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]203
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]204#if XNN_ARCH_X86 || XNN_ARCH_X86_64
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]205 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_eq_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]206 TEST_REQUIRES_X86_SSE;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]207 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]208 .input_tuple_size(4)
209 .output_tuple_size(4)
210 .input_width(4)
211 .padding_left(1)
212 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]213 .padding_top(0)
214 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]215 .kernel_height(3)
216 .kernel_width(3)
217 .subsampling(2)
218 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]219 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]220 }
221
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]222 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_lt_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]223 TEST_REQUIRES_X86_SSE;
224 for (size_t input_width = 1; input_width < 4; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]225 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]226 .input_tuple_size(4)
227 .output_tuple_size(4)
228 .input_width(input_width)
229 .padding_left(1)
230 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]231 .padding_top(0)
232 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]233 .kernel_height(3)
234 .kernel_width(3)
235 .subsampling(2)
236 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]237 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]238 }
239 }
240
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]241 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_gt_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]242 TEST_REQUIRES_X86_SSE;
243 for (size_t input_width = 5; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]244 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]245 .input_tuple_size(4)
246 .output_tuple_size(4)
247 .input_width(input_width)
248 .padding_left(1)
249 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]250 .padding_top(0)
251 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]252 .kernel_height(3)
253 .kernel_width(3)
254 .subsampling(2)
255 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]256 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]257 }
258 }
259
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]260 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_div_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]261 TEST_REQUIRES_X86_SSE;
262 for (size_t input_width = 8; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]263 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]264 .input_tuple_size(4)
265 .output_tuple_size(4)
266 .input_width(input_width)
267 .padding_left(1)
268 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]269 .padding_top(0)
270 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]271 .kernel_height(3)
272 .kernel_width(3)
273 .subsampling(2)
274 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]275 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]276 }
277 }
278
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]279 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_stride_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]280 TEST_REQUIRES_X86_SSE;
281 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]282 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]283 .input_tuple_size(4)
284 .output_tuple_size(4)
285 .input_width(input_width)
286 .input_width_stride(36)
287 .padding_left(1)
288 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]289 .padding_top(0)
290 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]291 .kernel_height(3)
292 .kernel_width(3)
293 .subsampling(2)
294 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]295 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]296 }
297 }
298
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]299 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_tuple_stride_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]300 TEST_REQUIRES_X86_SSE;
301 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]302 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]303 .input_tuple_size(4)
304 .output_tuple_size(4)
305 .input_width(input_width)
306 .input_width_stride(4)
307 .input_tuple_stride(3 * 4)
308 .padding_left(1)
309 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]310 .padding_top(0)
311 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]312 .kernel_height(3)
313 .kernel_width(3)
314 .subsampling(2)
315 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]316 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]317 }
318 }
319
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]320 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, output_height_gt_1_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]321 TEST_REQUIRES_X86_SSE;
322 for (size_t output_height = 2; output_height < 5; output_height++) {
323 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]324 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]325 .input_tuple_size(4)
326 .output_tuple_size(4)
327 .input_width(input_width)
328 .padding_left(1)
329 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]330 .padding_top(0)
331 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]332 .kernel_height(3)
333 .kernel_width(3)
334 .subsampling(2)
335 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]336 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]337 }
338 }
339 }
340
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]341 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, output_width_stride_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]342 TEST_REQUIRES_X86_SSE;
343 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]344 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]345 .input_tuple_size(4)
346 .output_tuple_size(4)
347 .input_width(input_width)
348 .padding_left(1)
349 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]350 .padding_top(0)
351 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]352 .kernel_height(3)
353 .kernel_width(3)
354 .subsampling(2)
355 .output_height(5)
356 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]357 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]358 }
359 }
360
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]361 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, output_tuple_stride_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]362 TEST_REQUIRES_X86_SSE;
363 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]364 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]365 .input_tuple_size(4)
366 .output_tuple_size(4)
367 .input_width(input_width)
368 .padding_left(1)
369 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]370 .padding_top(0)
371 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]372 .kernel_height(3)
373 .kernel_width(3)
374 .subsampling(2)
375 .output_height(5)
376 .output_width_stride(4)
377 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]378 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]379 }
380 }
381
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]382 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, chw_layout_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]383 TEST_REQUIRES_X86_SSE;
384 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]385 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]386 .input_tuple_size(4)
387 .output_tuple_size(4)
388 .input_width(input_width)
389 .input_width_stride(input_width)
390 .padding_left(1)
391 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]392 .padding_top(0)
393 .padding_bottom(1)
394 .kernel_height(3)
395 .kernel_width(3)
396 .subsampling(2)
397 .output_height(5)
398 .output_width_stride((input_width - 1) / 2 + 1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]399 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]400 }
401 }
402
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]403 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_eq_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]404 TEST_REQUIRES_X86_SSE;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]405 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]406 .input_tuple_size(4)
407 .output_tuple_size(4)
408 .input_width(4)
409 .padding_left(1)
410 .padding_right(1)
411 .padding_top(1)
412 .padding_bottom(1)
413 .kernel_height(3)
414 .kernel_width(3)
415 .subsampling(2)
416 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]417 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]418 }
419
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]420 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_lt_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]421 TEST_REQUIRES_X86_SSE;
422 for (size_t input_width = 1; input_width < 4; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]423 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]424 .input_tuple_size(4)
425 .output_tuple_size(4)
426 .input_width(input_width)
427 .padding_left(1)
428 .padding_right(1)
429 .padding_top(1)
430 .padding_bottom(1)
431 .kernel_height(3)
432 .kernel_width(3)
433 .subsampling(2)
434 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]435 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]436 }
437 }
438
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]439 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_gt_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]440 TEST_REQUIRES_X86_SSE;
441 for (size_t input_width = 5; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]442 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]443 .input_tuple_size(4)
444 .output_tuple_size(4)
445 .input_width(input_width)
446 .padding_left(1)
447 .padding_right(1)
448 .padding_top(1)
449 .padding_bottom(1)
450 .kernel_height(3)
451 .kernel_width(3)
452 .subsampling(2)
453 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]454 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]455 }
456 }
457
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]458 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_div_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]459 TEST_REQUIRES_X86_SSE;
460 for (size_t input_width = 8; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]461 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]462 .input_tuple_size(4)
463 .output_tuple_size(4)
464 .input_width(input_width)
465 .padding_left(1)
466 .padding_right(1)
467 .padding_top(1)
468 .padding_bottom(1)
469 .kernel_height(3)
470 .kernel_width(3)
471 .subsampling(2)
472 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]473 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]474 }
475 }
476
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]477 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_width_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]478 TEST_REQUIRES_X86_SSE;
479 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]480 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]481 .input_tuple_size(4)
482 .output_tuple_size(4)
483 .input_width(input_width)
484 .input_width_stride(36)
485 .padding_left(1)
486 .padding_right(1)
487 .padding_top(1)
488 .padding_bottom(1)
489 .kernel_height(3)
490 .kernel_width(3)
491 .subsampling(2)
492 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]493 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]494 }
495 }
496
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]497 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, input_tuple_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]498 TEST_REQUIRES_X86_SSE;
499 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]500 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]501 .input_tuple_size(4)
502 .output_tuple_size(4)
503 .input_width(input_width)
504 .input_width_stride(4)
505 .input_tuple_stride(3 * 4)
506 .padding_left(1)
507 .padding_right(1)
508 .padding_top(1)
509 .padding_bottom(1)
510 .kernel_height(3)
511 .kernel_width(3)
512 .subsampling(2)
513 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]514 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]515 }
516 }
517
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]518 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, output_height_gt_1_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]519 TEST_REQUIRES_X86_SSE;
520 for (size_t output_height = 2; output_height < 5; output_height++) {
521 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]522 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]523 .input_tuple_size(4)
524 .output_tuple_size(4)
525 .input_width(input_width)
526 .padding_left(1)
527 .padding_right(1)
528 .padding_top(1)
529 .padding_bottom(1)
530 .kernel_height(3)
531 .kernel_width(3)
532 .subsampling(2)
533 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]534 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]535 }
536 }
537 }
538
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]539 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, output_width_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]540 TEST_REQUIRES_X86_SSE;
541 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]542 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]543 .input_tuple_size(4)
544 .output_tuple_size(4)
545 .input_width(input_width)
546 .padding_left(1)
547 .padding_right(1)
548 .padding_top(1)
549 .padding_bottom(1)
550 .kernel_height(3)
551 .kernel_width(3)
552 .subsampling(2)
553 .output_height(5)
554 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]555 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]556 }
557 }
558
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]559 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, output_tuple_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]560 TEST_REQUIRES_X86_SSE;
561 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]562 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]563 .input_tuple_size(4)
564 .output_tuple_size(4)
565 .input_width(input_width)
566 .padding_left(1)
567 .padding_right(1)
568 .padding_top(1)
569 .padding_bottom(1)
570 .kernel_height(3)
571 .kernel_width(3)
572 .subsampling(2)
573 .output_height(5)
574 .output_width_stride(4)
575 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]576 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]577 }
578 }
579
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]580 TEST(F32_DWCONV_CHW_3X3S2P1__SSE, chw_layout_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]581 TEST_REQUIRES_X86_SSE;
582 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]583 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]584 .input_tuple_size(4)
585 .output_tuple_size(4)
586 .input_width(input_width)
587 .input_width_stride(input_width)
588 .padding_left(1)
589 .padding_right(1)
590 .padding_top(1)
591 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]592 .kernel_height(3)
593 .kernel_width(3)
594 .subsampling(2)
595 .output_height(5)
596 .output_width_stride((input_width - 1) / 2 + 1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]597 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__sse);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]598 }
599 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]600#endif // XNN_ARCH_X86 || XNN_ARCH_X86_64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]601
602
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]603#if XNN_ARCH_ARM64
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]604 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, input_width_eq_4_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]605 TEST_REQUIRES_ARM_NEON_FMA;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]606 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]607 .input_tuple_size(4)
608 .output_tuple_size(4)
609 .input_width(4)
610 .padding_left(1)
611 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]612 .padding_top(1)
613 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]614 .kernel_height(3)
615 .kernel_width(3)
616 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]617 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]618 }
619
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]620 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, input_width_lt_4_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]621 TEST_REQUIRES_ARM_NEON_FMA;
622 for (size_t input_width = 1; input_width < 4; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]623 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]624 .input_tuple_size(4)
625 .output_tuple_size(4)
626 .input_width(input_width)
627 .padding_left(1)
628 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]629 .padding_top(1)
630 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]631 .kernel_height(3)
632 .kernel_width(3)
633 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]634 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]635 }
636 }
637
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]638 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, input_width_gt_4_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]639 TEST_REQUIRES_ARM_NEON_FMA;
640 for (size_t input_width = 5; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]641 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]642 .input_tuple_size(4)
643 .output_tuple_size(4)
644 .input_width(input_width)
645 .padding_left(1)
646 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]647 .padding_top(1)
648 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]649 .kernel_height(3)
650 .kernel_width(3)
651 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]652 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]653 }
654 }
655
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]656 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, input_width_div_4_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]657 TEST_REQUIRES_ARM_NEON_FMA;
658 for (size_t input_width = 8; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]659 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]660 .input_tuple_size(4)
661 .output_tuple_size(4)
662 .input_width(input_width)
663 .padding_left(1)
664 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]665 .padding_top(1)
666 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]667 .kernel_height(3)
668 .kernel_width(3)
669 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]670 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]671 }
672 }
673
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]674 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, input_width_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]675 TEST_REQUIRES_ARM_NEON_FMA;
676 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]677 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]678 .input_tuple_size(4)
679 .output_tuple_size(4)
680 .input_width(input_width)
681 .input_width_stride(36)
682 .padding_left(1)
683 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]684 .padding_top(1)
685 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]686 .kernel_height(3)
687 .kernel_width(3)
688 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]689 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]690 }
691 }
692
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]693 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, input_tuple_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]694 TEST_REQUIRES_ARM_NEON_FMA;
695 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]696 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]697 .input_tuple_size(4)
698 .output_tuple_size(4)
699 .input_width(input_width)
700 .input_width_stride(4)
701 .input_tuple_stride(3 * 4)
702 .padding_left(1)
703 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]704 .padding_top(1)
705 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]706 .kernel_height(3)
707 .kernel_width(3)
708 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]709 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]710 }
711 }
712
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]713 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, output_height_gt_1_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]714 TEST_REQUIRES_ARM_NEON_FMA;
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]715 for (size_t output_height = 2; output_height <= 5; output_height++) {
716 for (size_t input_width = 8; input_width < 9; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]717 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]718 .input_tuple_size(4)
719 .output_tuple_size(4)
720 .input_width(input_width)
721 .padding_left(1)
722 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]723 .padding_top(1)
724 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]725 .kernel_height(3)
726 .kernel_width(3)
727 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]728 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]729 }
730 }
731 }
732
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]733 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, output_width_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]734 TEST_REQUIRES_ARM_NEON_FMA;
735 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]736 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]737 .input_tuple_size(4)
738 .output_tuple_size(4)
739 .input_width(input_width)
740 .padding_left(1)
741 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]742 .padding_top(1)
743 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]744 .kernel_height(3)
745 .kernel_width(3)
746 .output_height(5)
747 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]748 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]749 }
750 }
751
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]752 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, output_tuple_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]753 TEST_REQUIRES_ARM_NEON_FMA;
754 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]755 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]756 .input_tuple_size(4)
757 .output_tuple_size(4)
758 .input_width(input_width)
759 .padding_left(1)
760 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]761 .padding_top(1)
762 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]763 .kernel_height(3)
764 .kernel_width(3)
765 .output_height(5)
766 .output_width_stride(4)
767 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]768 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]769 }
770 }
771
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]772 TEST(F32_DWCONV_CHW_3X3P1__NEONFMA, chw_layout_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]773 TEST_REQUIRES_ARM_NEON_FMA;
774 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]775 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]776 .input_tuple_size(4)
777 .output_tuple_size(4)
778 .input_width(input_width)
779 .input_width_stride(input_width)
780 .padding_left(1)
781 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]782 .padding_top(1)
783 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]784 .kernel_height(3)
785 .kernel_width(3)
786 .output_height(5)
787 .output_width_stride(input_width)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]788 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]789 }
790 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]791#endif // XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]792
793
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]794#if XNN_ARCH_ARM64
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]795 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_eq_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]796 TEST_REQUIRES_ARM_NEON_FMA;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]797 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]798 .input_tuple_size(4)
799 .output_tuple_size(4)
800 .input_width(4)
801 .padding_left(1)
802 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]803 .padding_top(0)
804 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]805 .kernel_height(3)
806 .kernel_width(3)
807 .subsampling(2)
808 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]809 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]810 }
811
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]812 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_eq_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]813 TEST_REQUIRES_ARM_NEON_FMA;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]814 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]815 .input_tuple_size(4)
816 .output_tuple_size(4)
817 .input_width(4)
818 .padding_left(1)
819 .padding_right(1)
820 .padding_top(1)
821 .padding_bottom(1)
822 .kernel_height(3)
823 .kernel_width(3)
824 .subsampling(2)
825 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]826 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]827 }
828
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]829 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_lt_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]830 TEST_REQUIRES_ARM_NEON_FMA;
831 for (size_t input_width = 1; input_width < 4; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]832 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]833 .input_tuple_size(4)
834 .output_tuple_size(4)
835 .input_width(input_width)
836 .padding_left(1)
837 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]838 .padding_top(0)
839 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]840 .kernel_height(3)
841 .kernel_width(3)
842 .subsampling(2)
843 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]844 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]845 }
846 }
847
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]848 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_lt_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]849 TEST_REQUIRES_ARM_NEON_FMA;
850 for (size_t input_width = 1; input_width < 4; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]851 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]852 .input_tuple_size(4)
853 .output_tuple_size(4)
854 .input_width(input_width)
855 .padding_left(1)
856 .padding_right(1)
857 .padding_top(1)
858 .padding_bottom(1)
859 .kernel_height(3)
860 .kernel_width(3)
861 .subsampling(2)
862 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]863 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]864 }
865 }
866
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]867 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_gt_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]868 TEST_REQUIRES_ARM_NEON_FMA;
869 for (size_t input_width = 5; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]870 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]871 .input_tuple_size(4)
872 .output_tuple_size(4)
873 .input_width(input_width)
874 .padding_left(1)
875 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]876 .padding_top(0)
877 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]878 .kernel_height(3)
879 .kernel_width(3)
880 .subsampling(2)
881 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]882 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]883 }
884 }
885
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]886 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_gt_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]887 TEST_REQUIRES_ARM_NEON_FMA;
888 for (size_t input_width = 5; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]889 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]890 .input_tuple_size(4)
891 .output_tuple_size(4)
892 .input_width(input_width)
893 .padding_left(1)
894 .padding_right(1)
895 .padding_top(1)
896 .padding_bottom(1)
897 .kernel_height(3)
898 .kernel_width(3)
899 .subsampling(2)
900 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]901 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]902 }
903 }
904
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]905 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_div_4_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]906 TEST_REQUIRES_ARM_NEON_FMA;
907 for (size_t input_width = 8; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]908 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]909 .input_tuple_size(4)
910 .output_tuple_size(4)
911 .input_width(input_width)
912 .padding_left(1)
913 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]914 .padding_top(0)
915 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]916 .kernel_height(3)
917 .kernel_width(3)
918 .subsampling(2)
919 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]920 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]921 }
922 }
923
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]924 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_div_4_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]925 TEST_REQUIRES_ARM_NEON_FMA;
926 for (size_t input_width = 8; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]927 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]928 .input_tuple_size(4)
929 .output_tuple_size(4)
930 .input_width(input_width)
931 .padding_left(1)
932 .padding_right(1)
933 .padding_top(1)
934 .padding_bottom(1)
935 .kernel_height(3)
936 .kernel_width(3)
937 .subsampling(2)
938 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]939 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]940 }
941 }
942
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]943 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_stride_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]944 TEST_REQUIRES_ARM_NEON_FMA;
945 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]946 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]947 .input_tuple_size(4)
948 .output_tuple_size(4)
949 .input_width(input_width)
950 .input_width_stride(36)
951 .padding_left(1)
952 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]953 .padding_top(0)
954 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]955 .kernel_height(3)
956 .kernel_width(3)
957 .subsampling(2)
958 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]959 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]960 }
961 }
962
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]963 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_width_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]964 TEST_REQUIRES_ARM_NEON_FMA;
965 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]966 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]967 .input_tuple_size(4)
968 .output_tuple_size(4)
969 .input_width(input_width)
970 .input_width_stride(36)
971 .padding_left(1)
972 .padding_right(1)
973 .padding_top(1)
974 .padding_bottom(1)
975 .kernel_height(3)
976 .kernel_width(3)
977 .subsampling(2)
978 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]979 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]980 }
981 }
982
983
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]984 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_tuple_stride_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]985 TEST_REQUIRES_ARM_NEON_FMA;
986 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]987 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]988 .input_tuple_size(4)
989 .output_tuple_size(4)
990 .input_width(input_width)
991 .input_width_stride(4)
992 .input_tuple_stride(3 * 4)
993 .padding_left(1)
994 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]995 .padding_top(0)
996 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]997 .kernel_height(3)
998 .kernel_width(3)
999 .subsampling(2)
1000 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1001 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1002 }
1003 }
1004
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1005 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, input_tuple_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1006 TEST_REQUIRES_ARM_NEON_FMA;
1007 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1008 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1009 .input_tuple_size(4)
1010 .output_tuple_size(4)
1011 .input_width(input_width)
1012 .input_width_stride(4)
1013 .input_tuple_stride(3 * 4)
1014 .padding_left(1)
1015 .padding_right(1)
1016 .padding_top(1)
1017 .padding_bottom(1)
1018 .kernel_height(3)
1019 .kernel_width(3)
1020 .subsampling(2)
1021 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1022 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1023 }
1024 }
1025
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1026 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, output_height_gt_1_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1027 TEST_REQUIRES_ARM_NEON_FMA;
1028 for (size_t output_height = 2; output_height < 5; output_height++) {
1029 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1030 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1031 .input_tuple_size(4)
1032 .output_tuple_size(4)
1033 .input_width(input_width)
1034 .padding_left(1)
1035 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1036 .padding_top(0)
1037 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1038 .kernel_height(3)
1039 .kernel_width(3)
1040 .subsampling(2)
1041 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1042 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1043 }
1044 }
1045 }
1046
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1047 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, output_height_gt_1_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1048 TEST_REQUIRES_ARM_NEON_FMA;
1049 for (size_t output_height = 2; output_height < 5; output_height++) {
1050 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1051 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1052 .input_tuple_size(4)
1053 .output_tuple_size(4)
1054 .input_width(input_width)
1055 .padding_left(1)
1056 .padding_right(1)
1057 .padding_top(1)
1058 .padding_bottom(1)
1059 .kernel_height(3)
1060 .kernel_width(3)
1061 .subsampling(2)
1062 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1063 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1064 }
1065 }
1066 }
1067
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1068 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, output_width_stride_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1069 TEST_REQUIRES_ARM_NEON_FMA;
1070 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1071 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1072 .input_tuple_size(4)
1073 .output_tuple_size(4)
1074 .input_width(input_width)
1075 .padding_left(1)
1076 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1077 .padding_top(0)
1078 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1079 .kernel_height(3)
1080 .kernel_width(3)
1081 .subsampling(2)
1082 .output_height(5)
1083 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1084 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1085 }
1086 }
1087
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1088 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, output_width_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1089 TEST_REQUIRES_ARM_NEON_FMA;
1090 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1091 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1092 .input_tuple_size(4)
1093 .output_tuple_size(4)
1094 .input_width(input_width)
1095 .padding_left(1)
1096 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1097 .padding_top(1)
1098 .padding_bottom(1)
1099 .kernel_height(3)
1100 .kernel_width(3)
1101 .subsampling(2)
1102 .output_height(5)
1103 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1104 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1105 }
1106 }
1107
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1108 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, output_tuple_stride_pad0) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1109 TEST_REQUIRES_ARM_NEON_FMA;
1110 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1111 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1112 .input_tuple_size(4)
1113 .output_tuple_size(4)
1114 .input_width(input_width)
1115 .padding_left(1)
1116 .padding_right(1)
1117 .padding_top(0)
1118 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1119 .kernel_height(3)
1120 .kernel_width(3)
1121 .subsampling(2)
1122 .output_height(5)
1123 .output_width_stride(4)
1124 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1125 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1126 }
1127 }
1128
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1129 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, output_tuple_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1130 TEST_REQUIRES_ARM_NEON_FMA;
1131 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1132 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1133 .input_tuple_size(4)
1134 .output_tuple_size(4)
1135 .input_width(input_width)
1136 .padding_left(1)
1137 .padding_right(1)
1138 .padding_top(1)
1139 .padding_bottom(1)
1140 .kernel_height(3)
1141 .kernel_width(3)
1142 .subsampling(2)
1143 .output_height(5)
1144 .output_width_stride(4)
1145 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1146 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1147 }
1148 }
1149
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1150 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, chw_layout_pad0) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1151 TEST_REQUIRES_ARM_NEON_FMA;
1152 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1153 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1154 .input_tuple_size(4)
1155 .output_tuple_size(4)
1156 .input_width(input_width)
1157 .input_width_stride(input_width)
1158 .padding_left(1)
1159 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1160 .padding_top(0)
1161 .padding_bottom(1)
1162 .kernel_height(3)
1163 .kernel_width(3)
1164 .subsampling(2)
1165 .output_height(5)
1166 .output_width_stride((input_width - 1) / 2 + 1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1167 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1168 }
1169 }
1170
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1171 TEST(F32_DWCONV_CHW_3X3S2P1__NEONFMA, chw_layout_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1172 TEST_REQUIRES_ARM_NEON_FMA;
1173 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1174 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1175 .input_tuple_size(4)
1176 .output_tuple_size(4)
1177 .input_width(input_width)
1178 .input_width_stride(input_width)
1179 .padding_left(1)
1180 .padding_right(1)
1181 .padding_top(1)
1182 .padding_bottom(1)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1183 .kernel_height(3)
1184 .kernel_width(3)
1185 .subsampling(2)
1186 .output_height(5)
1187 .output_width_stride((input_width - 1) / 2 + 1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1188 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1189 }
1190 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]1191#endif // XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1192
1193
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]1194#if XNN_ARCH_ARM64
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1195 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, input_width_eq_4_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1196 TEST_REQUIRES_ARM_NEON_FMA;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1197 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1198 .input_tuple_size(4)
1199 .output_tuple_size(4)
1200 .input_width(4)
1201 .padding_left(2)
1202 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1203 .padding_top(2)
1204 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1205 .kernel_height(5)
1206 .kernel_width(5)
1207 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1208 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1209 }
1210
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1211 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, input_width_lt_4_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1212 TEST_REQUIRES_ARM_NEON_FMA;
1213 for (size_t input_width = 1; input_width < 4; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1214 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1215 .input_tuple_size(4)
1216 .output_tuple_size(4)
1217 .input_width(input_width)
1218 .padding_left(2)
1219 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1220 .padding_top(2)
1221 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1222 .kernel_height(5)
1223 .kernel_width(5)
1224 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1225 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1226 }
1227 }
1228
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1229 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, input_width_gt_4_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1230 TEST_REQUIRES_ARM_NEON_FMA;
1231 for (size_t input_width = 5; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1232 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1233 .input_tuple_size(4)
1234 .output_tuple_size(4)
1235 .input_width(input_width)
1236 .padding_left(2)
1237 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1238 .padding_top(2)
1239 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1240 .kernel_height(5)
1241 .kernel_width(5)
1242 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1243 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1244 }
1245 }
1246
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1247 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, input_width_div_4_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1248 TEST_REQUIRES_ARM_NEON_FMA;
1249 for (size_t input_width = 8; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1250 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1251 .input_tuple_size(4)
1252 .output_tuple_size(4)
1253 .input_width(input_width)
1254 .padding_left(2)
1255 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1256 .padding_top(2)
1257 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1258 .kernel_height(5)
1259 .kernel_width(5)
1260 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1261 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1262 }
1263 }
1264
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1265 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, input_width_stride_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1266 TEST_REQUIRES_ARM_NEON_FMA;
1267 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1268 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1269 .input_tuple_size(4)
1270 .output_tuple_size(4)
1271 .input_width(input_width)
1272 .input_width_stride(36)
1273 .padding_left(2)
1274 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1275 .padding_top(2)
1276 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1277 .kernel_height(5)
1278 .kernel_width(5)
1279 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1280 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1281 }
1282 }
1283
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1284 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, input_tuple_stride_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1285 TEST_REQUIRES_ARM_NEON_FMA;
1286 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1287 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1288 .input_tuple_size(4)
1289 .output_tuple_size(4)
1290 .input_width(input_width)
1291 .input_width_stride(4)
1292 .input_tuple_stride(3 * 4)
1293 .padding_left(2)
1294 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1295 .padding_top(2)
1296 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1297 .kernel_height(5)
1298 .kernel_width(5)
1299 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1300 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1301 }
1302 }
1303
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1304 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, output_height_eq_2_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1305 TEST_REQUIRES_ARM_NEON_FMA;
Erich Elsen4ad51152019-11-19 13:11:53 -0800[diff] [blame]1306 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1307 DWConvCHWMicrokernelTester()
Erich Elsen4ad51152019-11-19 13:11:53 -0800[diff] [blame]1308 .input_tuple_size(4)
1309 .output_tuple_size(4)
1310 .input_width(input_width)
1311 .padding_left(2)
1312 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1313 .padding_top(2)
1314 .padding_bottom(2)
Erich Elsen4ad51152019-11-19 13:11:53 -0800[diff] [blame]1315 .kernel_height(5)
1316 .kernel_width(5)
1317 .output_height(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1318 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
Erich Elsen4ad51152019-11-19 13:11:53 -0800[diff] [blame]1319 }
1320 }
1321
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1322 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, output_height_gt_2_pad2) {
Erich Elsen4ad51152019-11-19 13:11:53 -0800[diff] [blame]1323 TEST_REQUIRES_ARM_NEON_FMA;
1324 for (size_t output_height = 3; output_height < 5; output_height++) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1325 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1326 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1327 .input_tuple_size(4)
1328 .output_tuple_size(4)
1329 .input_width(input_width)
1330 .padding_left(2)
1331 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1332 .padding_top(2)
1333 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1334 .kernel_height(5)
1335 .kernel_width(5)
1336 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1337 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1338 }
1339 }
1340 }
1341
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1342 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, output_width_stride_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1343 TEST_REQUIRES_ARM_NEON_FMA;
1344 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1345 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1346 .input_tuple_size(4)
1347 .output_tuple_size(4)
1348 .input_width(input_width)
1349 .padding_left(2)
1350 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1351 .padding_top(2)
1352 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1353 .kernel_height(5)
1354 .kernel_width(5)
1355 .output_height(5)
1356 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1357 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1358 }
1359 }
1360
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1361 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, output_tuple_stride_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1362 TEST_REQUIRES_ARM_NEON_FMA;
1363 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1364 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1365 .input_tuple_size(4)
1366 .output_tuple_size(4)
1367 .input_width(input_width)
1368 .padding_left(2)
1369 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1370 .padding_top(2)
1371 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1372 .kernel_height(5)
1373 .kernel_width(5)
1374 .output_height(5)
1375 .output_width_stride(4)
1376 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1377 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1378 }
1379 }
1380
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1381 TEST(F32_DWCONV_CHW_5X5P2__NEONFMA, chw_layout_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1382 TEST_REQUIRES_ARM_NEON_FMA;
1383 for (size_t input_width = 1; input_width < 32; input_width += 3) {
1384 for (size_t output_height = 1; output_height < 32; output_height += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1385 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1386 .input_tuple_size(4)
1387 .output_tuple_size(4)
1388 .input_width(input_width)
1389 .input_width_stride(input_width)
1390 .padding_left(2)
1391 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1392 .padding_top(2)
1393 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1394 .kernel_height(5)
1395 .kernel_width(5)
1396 .output_height(5)
1397 .output_width_stride(input_width)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1398 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1399 }
1400 }
1401 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]1402#endif // XNN_ARCH_ARM64
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1403
1404
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]1405#if XNN_ARCH_ARM64
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1406 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_eq_8_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1407 TEST_REQUIRES_ARM_NEON_FMA;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1408 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1409 .input_tuple_size(4)
1410 .output_tuple_size(4)
1411 .input_width(8)
1412 .padding_left(2)
1413 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1414 .padding_top(2)
1415 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1416 .kernel_height(5)
1417 .kernel_width(5)
1418 .subsampling(2)
1419 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1420 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1421 }
1422
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1423 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_eq_8_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1424 TEST_REQUIRES_ARM_NEON_FMA;
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1425 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1426 .input_tuple_size(4)
1427 .output_tuple_size(4)
1428 .input_width(8)
1429 .padding_left(2)
1430 .padding_right(2)
1431 .padding_top(1)
1432 .padding_bottom(2)
1433 .kernel_height(5)
1434 .kernel_width(5)
1435 .subsampling(2)
1436 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1437 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1438 }
1439
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1440 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_lt_8_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1441 TEST_REQUIRES_ARM_NEON_FMA;
1442 for (size_t input_width = 1; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1443 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1444 .input_tuple_size(4)
1445 .output_tuple_size(4)
1446 .input_width(input_width)
1447 .padding_left(2)
1448 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1449 .padding_top(1)
1450 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1451 .kernel_height(5)
1452 .kernel_width(5)
1453 .subsampling(2)
1454 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1455 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1456 }
1457 }
1458
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1459 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_lt_8_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1460 TEST_REQUIRES_ARM_NEON_FMA;
1461 for (size_t input_width = 1; input_width < 8; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1462 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1463 .input_tuple_size(4)
1464 .output_tuple_size(4)
1465 .input_width(input_width)
1466 .padding_left(2)
1467 .padding_right(2)
1468 .padding_top(2)
1469 .padding_bottom(2)
1470 .kernel_height(5)
1471 .kernel_width(5)
1472 .subsampling(2)
1473 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1474 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1475 }
1476 }
1477
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1478 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_gt_8_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1479 TEST_REQUIRES_ARM_NEON_FMA;
1480 for (size_t input_width = 8; input_width < 16; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1481 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1482 .input_tuple_size(4)
1483 .output_tuple_size(4)
1484 .input_width(input_width)
1485 .padding_left(2)
1486 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1487 .padding_top(1)
1488 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1489 .kernel_height(5)
1490 .kernel_width(5)
1491 .subsampling(2)
1492 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1493 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1494 }
1495 }
1496
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1497 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_gt_8_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1498 TEST_REQUIRES_ARM_NEON_FMA;
1499 for (size_t input_width = 8; input_width < 16; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1500 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1501 .input_tuple_size(4)
1502 .output_tuple_size(4)
1503 .input_width(input_width)
1504 .padding_left(2)
1505 .padding_right(2)
1506 .padding_top(2)
1507 .padding_bottom(2)
1508 .kernel_height(5)
1509 .kernel_width(5)
1510 .subsampling(2)
1511 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1512 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1513 }
1514 }
1515
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1516 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_div_4_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1517 TEST_REQUIRES_ARM_NEON_FMA;
1518 for (size_t input_width = 16; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1519 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1520 .input_tuple_size(4)
1521 .output_tuple_size(4)
1522 .input_width(input_width)
1523 .padding_left(2)
1524 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1525 .padding_top(1)
1526 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1527 .kernel_height(5)
1528 .kernel_width(5)
1529 .subsampling(2)
1530 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1531 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1532 }
1533 }
1534
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1535 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_div_4_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1536 TEST_REQUIRES_ARM_NEON_FMA;
1537 for (size_t input_width = 16; input_width < 32; input_width += 4) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1538 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1539 .input_tuple_size(4)
1540 .output_tuple_size(4)
1541 .input_width(input_width)
1542 .padding_left(2)
1543 .padding_right(2)
1544 .padding_top(2)
1545 .padding_bottom(2)
1546 .kernel_height(5)
1547 .kernel_width(5)
1548 .subsampling(2)
1549 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1550 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1551 }
1552 }
1553
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1554 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1555 TEST_REQUIRES_ARM_NEON_FMA;
1556 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1557 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1558 .input_tuple_size(4)
1559 .output_tuple_size(4)
1560 .input_width(input_width)
1561 .input_width_stride(36)
1562 .padding_left(2)
1563 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1564 .padding_top(1)
1565 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1566 .kernel_height(5)
1567 .kernel_width(5)
1568 .subsampling(2)
1569 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1570 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1571 }
1572 }
1573
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1574 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_width_stride_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1575 TEST_REQUIRES_ARM_NEON_FMA;
1576 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1577 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1578 .input_tuple_size(4)
1579 .output_tuple_size(4)
1580 .input_width(input_width)
1581 .input_width_stride(36)
1582 .padding_left(2)
1583 .padding_right(2)
1584 .padding_top(2)
1585 .padding_bottom(2)
1586 .kernel_height(5)
1587 .kernel_width(5)
1588 .subsampling(2)
1589 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1590 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1591 }
1592 }
1593
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1594 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_tuple_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1595 TEST_REQUIRES_ARM_NEON_FMA;
1596 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1597 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1598 .input_tuple_size(4)
1599 .output_tuple_size(4)
1600 .input_width(input_width)
1601 .input_width_stride(4)
1602 .input_tuple_stride(3 * 4)
1603 .padding_left(2)
1604 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1605 .padding_top(1)
1606 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1607 .kernel_height(5)
1608 .kernel_width(5)
1609 .subsampling(2)
1610 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1611 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1612 }
1613 }
1614
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1615 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, input_tuple_stride_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1616 TEST_REQUIRES_ARM_NEON_FMA;
1617 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1618 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1619 .input_tuple_size(4)
1620 .output_tuple_size(4)
1621 .input_width(input_width)
1622 .input_width_stride(4)
1623 .input_tuple_stride(3 * 4)
1624 .padding_left(2)
1625 .padding_right(2)
1626 .padding_top(2)
1627 .padding_bottom(2)
1628 .kernel_height(5)
1629 .kernel_width(5)
1630 .subsampling(2)
1631 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1632 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1633 }
1634 }
1635
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1636 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, output_height_gt_1_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1637 TEST_REQUIRES_ARM_NEON_FMA;
1638 for (size_t output_height = 3; output_height < 4; output_height++) {
1639 for (size_t input_width = 4; input_width < 5; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1640 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1641 .input_tuple_size(4)
1642 .output_tuple_size(4)
1643 .input_width(input_width)
1644 .padding_left(2)
1645 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1646 .padding_top(1)
1647 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1648 .kernel_height(5)
1649 .kernel_width(5)
1650 .subsampling(2)
1651 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1652 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1653 }
1654 }
1655 }
1656
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1657 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, output_height_gt_1_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1658 TEST_REQUIRES_ARM_NEON_FMA;
1659 for (size_t output_height = 3; output_height < 4; output_height++) {
1660 for (size_t input_width = 4; input_width < 5; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1661 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1662 .input_tuple_size(4)
1663 .output_tuple_size(4)
1664 .input_width(input_width)
1665 .padding_left(2)
1666 .padding_right(2)
1667 .padding_top(2)
1668 .padding_bottom(2)
1669 .kernel_height(5)
1670 .kernel_width(5)
1671 .subsampling(2)
1672 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1673 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1674 }
1675 }
1676 }
1677
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1678 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, output_width_stride_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1679 TEST_REQUIRES_ARM_NEON_FMA;
1680 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1681 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1682 .input_tuple_size(4)
1683 .output_tuple_size(4)
1684 .input_width(input_width)
1685 .padding_left(2)
1686 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1687 .padding_top(1)
1688 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1689 .kernel_height(5)
1690 .kernel_width(5)
1691 .subsampling(2)
1692 .output_height(5)
1693 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1694 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1695 }
1696 }
1697
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1698 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, output_width_stride_pad2) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1699 TEST_REQUIRES_ARM_NEON_FMA;
1700 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1701 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1702 .input_tuple_size(4)
1703 .output_tuple_size(4)
1704 .input_width(input_width)
1705 .padding_left(2)
1706 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1707 .padding_top(2)
1708 .padding_bottom(2)
1709 .kernel_height(5)
1710 .kernel_width(5)
1711 .subsampling(2)
1712 .output_height(5)
1713 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1714 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1715 }
1716 }
1717
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1718 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, output_tuple_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1719 TEST_REQUIRES_ARM_NEON_FMA;
1720 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1721 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1722 .input_tuple_size(4)
1723 .output_tuple_size(4)
1724 .input_width(input_width)
1725 .padding_left(2)
1726 .padding_right(2)
1727 .padding_top(1)
1728 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1729 .kernel_height(5)
1730 .kernel_width(5)
1731 .subsampling(2)
1732 .output_height(5)
1733 .output_width_stride(4)
1734 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1735 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1736 }
1737 }
1738
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1739 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, output_tuple_stride_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1740 TEST_REQUIRES_ARM_NEON_FMA;
1741 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1742 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1743 .input_tuple_size(4)
1744 .output_tuple_size(4)
1745 .input_width(input_width)
1746 .padding_left(2)
1747 .padding_right(2)
1748 .padding_top(2)
1749 .padding_bottom(2)
1750 .kernel_height(5)
1751 .kernel_width(5)
1752 .subsampling(2)
1753 .output_height(5)
1754 .output_width_stride(4)
1755 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1756 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1757 }
1758 }
1759
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1760 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, chw_layout_pad1) {
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1761 TEST_REQUIRES_ARM_NEON_FMA;
1762 for (size_t input_width = 1; input_width < 32; input_width += 1) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1763 DWConvCHWMicrokernelTester()
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1764 .input_tuple_size(4)
1765 .output_tuple_size(4)
1766 .input_width(input_width)
1767 .input_width_stride(input_width)
1768 .padding_left(2)
1769 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1770 .padding_top(1)
1771 .padding_bottom(2)
1772 .kernel_height(5)
1773 .kernel_width(5)
1774 .subsampling(2)
1775 .output_height(5)
1776 .output_width_stride((input_width - 1) / 2 + 1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1777 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1778 }
1779 }
1780
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1781 TEST(F32_DWCONV_CHW_5X5S2P2__NEONFMA, chw_layout_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1782 TEST_REQUIRES_ARM_NEON_FMA;
1783 for (size_t input_width = 1; input_width < 32; input_width += 1) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1784 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1785 .input_tuple_size(4)
1786 .output_tuple_size(4)
1787 .input_width(input_width)
1788 .input_width_stride(input_width)
1789 .padding_left(2)
1790 .padding_right(2)
1791 .padding_top(2)
1792 .padding_bottom(2)
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1793 .kernel_height(5)
1794 .kernel_width(5)
1795 .subsampling(2)
1796 .output_height(5)
1797 .output_width_stride((input_width - 1) / 2 + 1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1798 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__neonfma);
XNNPACK Teamb455b122019-09-27 18:10:33 -0700[diff] [blame]1799 }
1800 }
Marat Dukhan1dadbf72019-10-01 10:46:20 -0700[diff] [blame]1801#endif // XNN_ARCH_ARM64
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1802
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1803
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1804TEST(F32_DWCONV_CHW_3X3P1__SCALAR, input_width_eq_1) {
1805 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1806 .input_tuple_size(1)
1807 .output_tuple_size(1)
1808 .input_width(1)
1809 .padding_left(1)
1810 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1811 .padding_top(1)
1812 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1813 .kernel_height(3)
1814 .kernel_width(3)
1815 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1816 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1817}
1818
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1819TEST(F32_DWCONV_CHW_3X3P1__SCALAR, input_width_gt_1) {
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1820 for (size_t input_width = 2; input_width < 32; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1821 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1822 .input_tuple_size(1)
1823 .output_tuple_size(1)
1824 .input_width(input_width)
1825 .padding_left(1)
1826 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1827 .padding_top(1)
1828 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1829 .kernel_height(3)
1830 .kernel_width(3)
1831 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1832 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1833 }
1834}
1835
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1836TEST(F32_DWCONV_CHW_3X3P1__SCALAR, input_width_stride) {
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1837 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1838 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1839 .input_tuple_size(1)
1840 .output_tuple_size(1)
1841 .input_width(input_width)
1842 .input_width_stride(36)
1843 .padding_left(1)
1844 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1845 .padding_top(1)
1846 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1847 .kernel_height(3)
1848 .kernel_width(3)
1849 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1850 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1851 }
1852}
1853
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1854TEST(F32_DWCONV_CHW_3X3P1__SCALAR, input_tuple_stride) {
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1855 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1856 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1857 .input_tuple_size(1)
1858 .output_tuple_size(1)
1859 .input_width(input_width)
1860 .input_width_stride(4)
1861 .input_tuple_stride(3 * 4)
1862 .padding_left(1)
1863 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1864 .padding_top(1)
1865 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1866 .kernel_height(3)
1867 .kernel_width(3)
1868 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1869 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1870 }
1871}
1872
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1873TEST(F32_DWCONV_CHW_3X3P1__SCALAR, output_height_gt_1) {
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1874 for (size_t output_height = 2; output_height < 5; output_height++) {
1875 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1876 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1877 .input_tuple_size(1)
1878 .output_tuple_size(1)
1879 .input_width(input_width)
1880 .padding_left(1)
1881 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1882 .padding_top(1)
1883 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1884 .kernel_height(3)
1885 .kernel_width(3)
1886 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1887 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1888 }
1889 }
1890}
1891
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1892TEST(F32_DWCONV_CHW_3X3P1__SCALAR, output_width_stride) {
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1893 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1894 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1895 .input_tuple_size(1)
1896 .output_tuple_size(1)
1897 .input_width(input_width)
1898 .padding_left(1)
1899 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1900 .padding_top(1)
1901 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1902 .kernel_height(3)
1903 .kernel_width(3)
1904 .output_height(5)
1905 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1906 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1907 }
1908}
1909
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1910TEST(F32_DWCONV_CHW_3X3P1__SCALAR, output_tuple_stride) {
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1911 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1912 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1913 .input_tuple_size(1)
1914 .output_tuple_size(1)
1915 .input_width(input_width)
1916 .padding_left(1)
1917 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1918 .padding_top(1)
1919 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1920 .kernel_height(3)
1921 .kernel_width(3)
1922 .output_height(5)
1923 .output_width_stride(4)
1924 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1925 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1926 }
1927}
1928
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1929TEST(F32_DWCONV_CHW_3X3P1__SCALAR, chw_layout) {
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1930 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1931 DWConvCHWMicrokernelTester()
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1932 .input_tuple_size(1)
1933 .output_tuple_size(1)
1934 .input_width(input_width)
1935 .input_width_stride(input_width)
1936 .padding_left(1)
1937 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1938 .padding_top(1)
1939 .padding_bottom(1)
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1940 .kernel_height(3)
1941 .kernel_width(3)
1942 .output_height(5)
1943 .output_width_stride(input_width)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1944 .Test(xnn_f32_dwconv_chw_ukernel_3x3p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen0cc2c532019-10-15 04:44:18 -0700[diff] [blame]1945 }
1946}
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1947
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1948TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_width_eq_1_pad0) {
1949 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1950 .input_tuple_size(1)
1951 .output_tuple_size(1)
1952 .input_width(1)
1953 .padding_left(1)
1954 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1955 .padding_top(0)
1956 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1957 .kernel_height(3)
1958 .kernel_width(3)
1959 .subsampling(2)
1960 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1961 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1962}
1963
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1964TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_width_gt_1_pad0) {
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1965 for (size_t input_width = 2; input_width < 32; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1966 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1967 .input_tuple_size(1)
1968 .output_tuple_size(1)
1969 .input_width(input_width)
1970 .padding_left(1)
1971 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1972 .padding_top(0)
1973 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1974 .kernel_height(3)
1975 .kernel_width(3)
1976 .subsampling(2)
1977 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1978 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1979 }
1980}
1981
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1982TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_width_stride_pad0) {
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1983 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1984 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1985 .input_tuple_size(1)
1986 .output_tuple_size(1)
1987 .input_width(input_width)
1988 .input_width_stride(36)
1989 .padding_left(1)
1990 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]1991 .padding_top(0)
1992 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1993 .kernel_height(3)
1994 .kernel_width(3)
1995 .subsampling(2)
1996 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]1997 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]1998 }
1999}
2000
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2001TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_tuple_stride_pad0) {
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2002 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2003 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2004 .input_tuple_size(1)
2005 .output_tuple_size(1)
2006 .input_width(input_width)
2007 .input_width_stride(4)
2008 .input_tuple_stride(3 * 4)
2009 .padding_left(1)
2010 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2011 .padding_top(0)
2012 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2013 .kernel_height(3)
2014 .kernel_width(3)
2015 .subsampling(2)
2016 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2017 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2018 }
2019}
2020
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2021TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, output_height_gt_1_pad0) {
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2022 for (size_t output_height = 2; output_height < 5; output_height++) {
2023 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2024 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2025 .input_tuple_size(1)
2026 .output_tuple_size(1)
2027 .input_width(input_width)
2028 .padding_left(1)
2029 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2030 .padding_top(0)
2031 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2032 .kernel_height(3)
2033 .kernel_width(3)
2034 .subsampling(2)
2035 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2036 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2037 }
2038 }
2039}
2040
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2041TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, output_width_stride_pad0) {
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2042 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2043 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2044 .input_tuple_size(1)
2045 .output_tuple_size(1)
2046 .input_width(input_width)
2047 .padding_left(1)
2048 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2049 .padding_top(0)
2050 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2051 .kernel_height(3)
2052 .kernel_width(3)
2053 .subsampling(2)
2054 .output_height(5)
2055 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2056 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2057 }
2058}
2059
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2060TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, output_tuple_stride_pad0) {
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2061 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2062 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2063 .input_tuple_size(1)
2064 .output_tuple_size(1)
2065 .input_width(input_width)
2066 .padding_left(1)
2067 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2068 .padding_top(0)
2069 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2070 .kernel_height(3)
2071 .kernel_width(3)
2072 .subsampling(2)
2073 .output_height(5)
2074 .output_width_stride(4)
2075 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2076 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2077 }
2078}
2079
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2080TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, chw_layout_pad0) {
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2081 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2082 DWConvCHWMicrokernelTester()
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2083 .input_tuple_size(1)
2084 .output_tuple_size(1)
2085 .input_width(input_width)
2086 .input_width_stride(input_width)
2087 .padding_left(1)
2088 .padding_right(1)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2089 .padding_top(0)
2090 .padding_bottom(1)
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2091 .kernel_height(3)
2092 .kernel_width(3)
2093 .subsampling(2)
2094 .output_height(5)
2095 .output_width_stride(input_width)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2096 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsenac4de802019-10-16 04:35:30 -0700[diff] [blame]2097 }
2098}
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2099
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2100TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_width_eq_1_pad1) {
2101 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2102 .input_tuple_size(1)
2103 .output_tuple_size(1)
2104 .input_width(1)
2105 .padding_left(1)
2106 .padding_right(1)
2107 .padding_top(1)
2108 .padding_bottom(1)
2109 .kernel_height(3)
2110 .kernel_width(3)
2111 .subsampling(2)
2112 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2113 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2114}
2115
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2116TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_width_gt_1_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2117 for (size_t input_width = 2; input_width < 32; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2118 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2119 .input_tuple_size(1)
2120 .output_tuple_size(1)
2121 .input_width(input_width)
2122 .padding_left(1)
2123 .padding_right(1)
2124 .padding_top(1)
2125 .padding_bottom(1)
2126 .kernel_height(3)
2127 .kernel_width(3)
2128 .subsampling(2)
2129 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2130 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2131 }
2132}
2133
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2134TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_width_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2135 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2136 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2137 .input_tuple_size(1)
2138 .output_tuple_size(1)
2139 .input_width(input_width)
2140 .input_width_stride(36)
2141 .padding_left(1)
2142 .padding_right(1)
2143 .padding_top(1)
2144 .padding_bottom(1)
2145 .kernel_height(3)
2146 .kernel_width(3)
2147 .subsampling(2)
2148 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2149 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2150 }
2151}
2152
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2153TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, input_tuple_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2154 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2155 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2156 .input_tuple_size(1)
2157 .output_tuple_size(1)
2158 .input_width(input_width)
2159 .input_width_stride(4)
2160 .input_tuple_stride(3 * 4)
2161 .padding_left(1)
2162 .padding_right(1)
2163 .padding_top(1)
2164 .padding_bottom(1)
2165 .kernel_height(3)
2166 .kernel_width(3)
2167 .subsampling(2)
2168 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2169 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2170 }
2171}
2172
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2173TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, output_height_gt_1_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2174 for (size_t output_height = 2; output_height < 5; output_height++) {
2175 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2176 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2177 .input_tuple_size(1)
2178 .output_tuple_size(1)
2179 .input_width(input_width)
2180 .padding_left(1)
2181 .padding_right(1)
2182 .padding_top(1)
2183 .padding_bottom(1)
2184 .kernel_height(3)
2185 .kernel_width(3)
2186 .subsampling(2)
2187 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2188 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2189 }
2190 }
2191}
2192
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2193TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, output_width_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2194 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2195 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2196 .input_tuple_size(1)
2197 .output_tuple_size(1)
2198 .input_width(input_width)
2199 .padding_left(1)
2200 .padding_right(1)
2201 .padding_top(1)
2202 .padding_bottom(1)
2203 .kernel_height(3)
2204 .kernel_width(3)
2205 .subsampling(2)
2206 .output_height(5)
2207 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2208 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2209 }
2210}
2211
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2212TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, output_tuple_stride_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2213 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2214 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2215 .input_tuple_size(1)
2216 .output_tuple_size(1)
2217 .input_width(input_width)
2218 .padding_left(1)
2219 .padding_right(1)
2220 .padding_top(1)
2221 .padding_bottom(1)
2222 .kernel_height(3)
2223 .kernel_width(3)
2224 .subsampling(2)
2225 .output_height(5)
2226 .output_width_stride(4)
2227 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2228 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2229 }
2230}
2231
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2232TEST(F32_DWCONV_CHW_3X3S2P1__SCALAR, chw_layout_pad1) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2233 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2234 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2235 .input_tuple_size(1)
2236 .output_tuple_size(1)
2237 .input_width(input_width)
2238 .input_width_stride(input_width)
2239 .padding_left(1)
2240 .padding_right(1)
2241 .padding_top(1)
2242 .padding_bottom(1)
2243 .kernel_height(3)
2244 .kernel_width(3)
2245 .subsampling(2)
2246 .output_height(5)
2247 .output_width_stride(input_width)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2248 .Test(xnn_f32_dwconv_chw_ukernel_3x3s2p1__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2249 }
2250}
2251
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2252TEST(F32_DWCONV_CHW_5X5P2__SCALAR, input_width_eq_1_pad2) {
2253 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2254 .input_tuple_size(1)
2255 .output_tuple_size(1)
2256 .input_width(1)
2257 .padding_left(2)
2258 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2259 .padding_top(2)
2260 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2261 .kernel_height(5)
2262 .kernel_width(5)
2263 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2264 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2265}
2266
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2267TEST(F32_DWCONV_CHW_5X5P2__SCALAR, input_width_gt_1_pad2) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2268 for (size_t input_width = 2; input_width < 32; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2269 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2270 .input_tuple_size(1)
2271 .output_tuple_size(1)
2272 .input_width(input_width)
2273 .padding_left(2)
2274 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2275 .padding_top(2)
2276 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2277 .kernel_height(5)
2278 .kernel_width(5)
2279 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2280 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2281 }
2282}
2283
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2284TEST(F32_DWCONV_CHW_5X5P2__SCALAR, input_width_stride_pad2) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2285 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2286 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2287 .input_tuple_size(1)
2288 .output_tuple_size(1)
2289 .input_width(input_width)
2290 .input_width_stride(36)
2291 .padding_left(2)
2292 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2293 .padding_top(2)
2294 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2295 .kernel_height(5)
2296 .kernel_width(5)
2297 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2298 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2299 }
2300}
2301
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2302TEST(F32_DWCONV_CHW_5X5P2__SCALAR, input_tuple_stride_pad2) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2303 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2304 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2305 .input_tuple_size(1)
2306 .output_tuple_size(1)
2307 .input_width(input_width)
2308 .input_width_stride(4)
2309 .input_tuple_stride(3 * 4)
2310 .padding_left(2)
2311 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2312 .padding_top(2)
2313 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2314 .kernel_height(5)
2315 .kernel_width(5)
2316 .output_height(1)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2317 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2318 }
2319}
2320
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2321TEST(F32_DWCONV_CHW_5X5P2__SCALAR, output_height_gt_1_pad2) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2322 for (size_t output_height = 2; output_height < 5; output_height++) {
2323 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2324 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2325 .input_tuple_size(1)
2326 .output_tuple_size(1)
2327 .input_width(input_width)
2328 .padding_left(2)
2329 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2330 .padding_top(2)
2331 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2332 .kernel_height(5)
2333 .kernel_width(5)
2334 .output_height(output_height)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2335 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2336 }
2337 }
2338}
2339
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2340TEST(F32_DWCONV_CHW_5X5P2__SCALAR, output_width_stride_pad2) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2341 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2342 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2343 .input_tuple_size(1)
2344 .output_tuple_size(1)
2345 .input_width(input_width)
2346 .padding_left(2)
2347 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2348 .padding_top(2)
2349 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2350 .kernel_height(5)
2351 .kernel_width(5)
2352 .output_height(5)
2353 .output_width_stride(36)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2354 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2355 }
2356}
2357
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2358TEST(F32_DWCONV_CHW_5X5P2__SCALAR, output_tuple_stride_pad2) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2359 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2360 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2361 .input_tuple_size(1)
2362 .output_tuple_size(1)
2363 .input_width(input_width)
2364 .padding_left(2)
2365 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2366 .padding_top(2)
2367 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2368 .kernel_height(5)
2369 .kernel_width(5)
2370 .output_height(5)
2371 .output_width_stride(4)
2372 .output_tuple_stride(5 * 4)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2373 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2374 }
2375}
2376
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2377TEST(F32_DWCONV_CHW_5X5P2__SCALAR, chw_layout_pad2) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2378 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2379 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2380 .input_tuple_size(1)
2381 .output_tuple_size(1)
2382 .input_width(input_width)
2383 .input_width_stride(input_width)
2384 .padding_left(2)
2385 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2386 .padding_top(2)
2387 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2388 .kernel_height(5)
2389 .kernel_width(5)
2390 .output_height(5)
2391 .output_width_stride(input_width)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2392 .Test(xnn_f32_dwconv_chw_ukernel_5x5p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2393 }
2394}
2395
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2396TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_width_eq_1_pad1) {
2397 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2398 .input_tuple_size(1)
2399 .output_tuple_size(1)
2400 .input_width(1)
2401 .padding_left(2)
2402 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2403 .padding_top(2)
2404 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2405 .kernel_height(5)
2406 .kernel_width(5)
2407 .output_height(1)
2408 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2409 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2410}
2411
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2412TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_width_gt_1_pad1) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2413 for (size_t input_width = 2; input_width < 32; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2414 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2415 .input_tuple_size(1)
2416 .output_tuple_size(1)
2417 .input_width(input_width)
2418 .padding_left(2)
2419 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2420 .padding_top(2)
2421 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2422 .kernel_height(5)
2423 .kernel_width(5)
2424 .output_height(1)
2425 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2426 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2427 }
2428}
2429
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2430TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_width_stride_pad1) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2431 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2432 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2433 .input_tuple_size(1)
2434 .output_tuple_size(1)
2435 .input_width(input_width)
2436 .input_width_stride(36)
2437 .padding_left(2)
2438 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2439 .padding_top(2)
2440 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2441 .kernel_height(5)
2442 .kernel_width(5)
2443 .output_height(1)
2444 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2445 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2446 }
2447}
2448
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2449TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_tuple_stride_pad1) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2450 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2451 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2452 .input_tuple_size(1)
2453 .output_tuple_size(1)
2454 .input_width(input_width)
2455 .input_width_stride(4)
2456 .input_tuple_stride(3 * 4)
2457 .padding_left(2)
2458 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2459 .padding_top(2)
2460 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2461 .kernel_height(5)
2462 .kernel_width(5)
2463 .output_height(1)
2464 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2465 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2466 }
2467}
2468
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2469TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, output_height_gt_1_pad1) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2470 for (size_t output_height = 2; output_height < 5; output_height++) {
2471 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2472 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2473 .input_tuple_size(1)
2474 .output_tuple_size(1)
2475 .input_width(input_width)
2476 .padding_left(2)
2477 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2478 .padding_top(2)
2479 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2480 .kernel_height(5)
2481 .kernel_width(5)
2482 .output_height(output_height)
2483 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2484 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2485 }
2486 }
2487}
2488
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2489TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, output_width_stride_pad1) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2490 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2491 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2492 .input_tuple_size(1)
2493 .output_tuple_size(1)
2494 .input_width(input_width)
2495 .padding_left(2)
2496 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2497 .padding_top(2)
2498 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2499 .kernel_height(5)
2500 .kernel_width(5)
2501 .output_height(5)
2502 .output_width_stride(36)
2503 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2504 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2505 }
2506}
2507
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2508TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, output_tuple_stride_pad1) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2509 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2510 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2511 .input_tuple_size(1)
2512 .output_tuple_size(1)
2513 .input_width(input_width)
2514 .padding_left(2)
2515 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2516 .padding_top(2)
2517 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2518 .kernel_height(5)
2519 .kernel_width(5)
2520 .output_height(5)
2521 .output_width_stride(4)
2522 .output_tuple_stride(5 * 4)
2523 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2524 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2525 }
2526}
2527
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2528TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, chw_layout_pad1) {
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2529 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2530 DWConvCHWMicrokernelTester()
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2531 .input_tuple_size(1)
2532 .output_tuple_size(1)
2533 .input_width(input_width)
2534 .input_width_stride(input_width)
2535 .padding_left(2)
2536 .padding_right(2)
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2537 .padding_top(2)
2538 .padding_bottom(2)
2539 .kernel_height(5)
2540 .kernel_width(5)
2541 .output_height(5)
2542 .output_width_stride(input_width)
2543 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2544 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2545 }
2546}
2547
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2548TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_width_eq_1_pad2) {
2549 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2550 .input_tuple_size(1)
2551 .output_tuple_size(1)
2552 .input_width(1)
2553 .padding_left(2)
2554 .padding_right(2)
2555 .padding_top(2)
2556 .padding_bottom(2)
2557 .kernel_height(5)
2558 .kernel_width(5)
2559 .output_height(1)
2560 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2561 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2562}
2563
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2564TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_width_gt_1_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2565 for (size_t input_width = 2; input_width < 32; input_width++) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2566 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2567 .input_tuple_size(1)
2568 .output_tuple_size(1)
2569 .input_width(input_width)
2570 .padding_left(2)
2571 .padding_right(2)
2572 .padding_top(2)
2573 .padding_bottom(2)
2574 .kernel_height(5)
2575 .kernel_width(5)
2576 .output_height(1)
2577 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2578 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2579 }
2580}
2581
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2582TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_width_stride_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2583 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2584 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2585 .input_tuple_size(1)
2586 .output_tuple_size(1)
2587 .input_width(input_width)
2588 .input_width_stride(36)
2589 .padding_left(2)
2590 .padding_right(2)
2591 .padding_top(2)
2592 .padding_bottom(2)
2593 .kernel_height(5)
2594 .kernel_width(5)
2595 .output_height(1)
2596 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2597 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2598 }
2599}
2600
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2601TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, input_tuple_stride_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2602 for (size_t input_width = 1; input_width < 32; input_width += 5) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2603 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2604 .input_tuple_size(1)
2605 .output_tuple_size(1)
2606 .input_width(input_width)
2607 .input_width_stride(4)
2608 .input_tuple_stride(3 * 4)
2609 .padding_left(2)
2610 .padding_right(2)
2611 .padding_top(2)
2612 .padding_bottom(2)
2613 .kernel_height(5)
2614 .kernel_width(5)
2615 .output_height(1)
2616 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2617 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2618 }
2619}
2620
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2621TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, output_height_gt_1_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2622 for (size_t output_height = 2; output_height < 5; output_height++) {
2623 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2624 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2625 .input_tuple_size(1)
2626 .output_tuple_size(1)
2627 .input_width(input_width)
2628 .padding_left(2)
2629 .padding_right(2)
2630 .padding_top(2)
2631 .padding_bottom(2)
2632 .kernel_height(5)
2633 .kernel_width(5)
2634 .output_height(output_height)
2635 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2636 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2637 }
2638 }
2639}
2640
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2641TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, output_width_stride_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2642 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2643 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2644 .input_tuple_size(1)
2645 .output_tuple_size(1)
2646 .input_width(input_width)
2647 .padding_left(2)
2648 .padding_right(2)
2649 .padding_top(2)
2650 .padding_bottom(2)
2651 .kernel_height(5)
2652 .kernel_width(5)
2653 .output_height(5)
2654 .output_width_stride(36)
2655 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2656 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2657 }
2658}
2659
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2660TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, output_tuple_stride_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2661 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2662 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2663 .input_tuple_size(1)
2664 .output_tuple_size(1)
2665 .input_width(input_width)
2666 .padding_left(2)
2667 .padding_right(2)
2668 .padding_top(2)
2669 .padding_bottom(2)
2670 .kernel_height(5)
2671 .kernel_width(5)
2672 .output_height(5)
2673 .output_width_stride(4)
2674 .output_tuple_stride(5 * 4)
2675 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2676 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2677 }
2678}
2679
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2680TEST(F32_DWCONV_CHW_5X5S2P2__SCALAR, chw_layout_pad2) {
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2681 for (size_t input_width = 1; input_width < 32; input_width += 3) {
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2682 DWConvCHWMicrokernelTester()
Erich Elsen4e5db3d2020-05-07 08:57:47 -0700[diff] [blame]2683 .input_tuple_size(1)
2684 .output_tuple_size(1)
2685 .input_width(input_width)
2686 .input_width_stride(input_width)
2687 .padding_left(2)
2688 .padding_right(2)
2689 .padding_top(2)
2690 .padding_bottom(2)
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2691 .kernel_height(5)
2692 .kernel_width(5)
2693 .output_height(5)
2694 .output_width_stride(input_width)
2695 .subsampling(2)
Marat Dukhan1f29b802020-05-15 23:46:39 -0700[diff] [blame^]2696 .Test(xnn_f32_dwconv_chw_ukernel_5x5s2p2__scalar, DWConvCHWMicrokernelTester::Variant::Scalar);
Erich Elsen38709a62019-11-08 11:58:45 -0800[diff] [blame]2697 }
2698}