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Marat Dukhan4741e412021-06-30 13:38:06 -07001// Auto-generated file. Do not edit!
Marat Dukhandfc2db02021-08-08 21:19:07 -07002// Template: src/qs8-igemm/MRx4c8-wasmsimd-mul16.c.in
Marat Dukhan4741e412021-06-30 13:38:06 -07003// Generator: tools/xngen
4//
5// Copyright 2020 Google LLC
6//
7// This source code is licensed under the BSD-style license found in the
8// LICENSE file in the root directory of this source tree.
9
10#include <assert.h>
11
12#include <wasm_simd128.h>
13
14#include <xnnpack/gemm.h>
15#include <xnnpack/math.h>
16
17
Marat Dukhandfc2db02021-08-08 21:19:07 -070018void xnn_qs8_igemm_minmax_fp32_ukernel_3x4c8__wasmsimd_mul16_ld128(
Marat Dukhan4741e412021-06-30 13:38:06 -070019 size_t mr,
20 size_t nc,
21 size_t kc,
22 size_t ks,
23 const int8_t** restrict a,
24 const void* restrict w,
25 int8_t* restrict c,
26 size_t cm_stride,
27 size_t cn_stride,
28 size_t a_offset,
29 const int8_t* zero,
30 const union xnn_qs8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_DISABLE_TSAN XNN_DISABLE_MSAN
31{
32 assert(mr != 0);
33 assert(mr <= 3);
34 assert(nc != 0);
35 assert(kc != 0);
36 assert(ks != 0);
37 assert(ks % (3 * sizeof(void*)) == 0);
38 assert(a_offset % sizeof(int8_t) == 0);
39 assert(a != NULL);
40 assert(w != NULL);
41 assert(c != NULL);
42
43 kc = round_up_po2(kc, 8);
44 int8_t* c0 = c;
45 int8_t* c1 = (int8_t*) ((uintptr_t) c0 + cm_stride);
46 if XNN_UNPREDICTABLE(mr < 2) {
47 c1 = c0;
48 }
49 int8_t* c2 = (int8_t*) ((uintptr_t) c1 + cm_stride);
50 if XNN_UNPREDICTABLE(mr <= 2) {
51 c2 = c1;
52 }
53
Marat Dukhan4741e412021-06-30 13:38:06 -070054 do {
Marat Dukhan48109052021-08-31 17:31:57 -070055 v128_t vacc0x0 = wasm_f32x4_replace_lane(wasm_f32x4_const_splat(0.0f), 0, ((const float*) w)[0]);
56 v128_t vacc0x1 = wasm_f32x4_replace_lane(wasm_f32x4_const_splat(0.0f), 0, ((const float*) w)[1]);
57 v128_t vacc0x2 = wasm_f32x4_replace_lane(wasm_f32x4_const_splat(0.0f), 0, ((const float*) w)[2]);
58 v128_t vacc0x3 = wasm_f32x4_replace_lane(wasm_f32x4_const_splat(0.0f), 0, ((const float*) w)[3]);
Marat Dukhan4741e412021-06-30 13:38:06 -070059 v128_t vacc1x0 = vacc0x0;
60 v128_t vacc1x1 = vacc0x1;
61 v128_t vacc1x2 = vacc0x2;
62 v128_t vacc1x3 = vacc0x3;
63 v128_t vacc2x0 = vacc0x0;
64 v128_t vacc2x1 = vacc0x1;
65 v128_t vacc2x2 = vacc0x2;
66 v128_t vacc2x3 = vacc0x3;
Marat Dukhan43bee052021-07-14 20:57:18 -070067 w = (const void*) ((const int32_t*) w + 4);
Marat Dukhan4741e412021-06-30 13:38:06 -070068
69 size_t p = ks;
70 do {
71 const int8_t* restrict a0 = a[0];
72 if XNN_UNPREDICTABLE(a0 != zero) {
73 a0 = (const int8_t*) ((uintptr_t) a0 + a_offset);
74 }
75 const int8_t* restrict a1 = a[1];
76 if XNN_UNPREDICTABLE(a1 != zero) {
77 a1 = (const int8_t*) ((uintptr_t) a1 + a_offset);
78 }
79 const int8_t* restrict a2 = a[2];
80 if XNN_UNPREDICTABLE(a2 != zero) {
81 a2 = (const int8_t*) ((uintptr_t) a2 + a_offset);
82 }
83 a += 3;
84
85 size_t k = 0;
86 while (k < kc) {
87 const v128_t vxa0 = wasm_i16x8_load8x8(a0);
88 a0 += 8;
89 const v128_t vxa1 = wasm_i16x8_load8x8(a1);
90 a1 += 8;
91 const v128_t vxa2 = wasm_i16x8_load8x8(a2);
92 a2 += 8;
93
94 const v128_t vb01 = wasm_v128_load(w);
95 const v128_t vxb0 = wasm_i16x8_extend_low_i8x16(vb01);
96 const v128_t vxb1 = wasm_i16x8_extend_high_i8x16(vb01);
97
98 const v128_t vprod0x0 = wasm_i16x8_mul(vxb0, vxa0);
99 vacc0x0 = wasm_i32x4_add(vacc0x0, wasm_i32x4_extend_low_i16x8(vprod0x0));
100 const v128_t vprod1x0 = wasm_i16x8_mul(vxb0, vxa1);
101 vacc1x0 = wasm_i32x4_add(vacc1x0, wasm_i32x4_extend_low_i16x8(vprod1x0));
102 const v128_t vprod2x0 = wasm_i16x8_mul(vxb0, vxa2);
103 vacc2x0 = wasm_i32x4_add(vacc2x0, wasm_i32x4_extend_low_i16x8(vprod2x0));
104
105 const v128_t vprod0x1 = wasm_i16x8_mul(vxb1, vxa0);
106 vacc0x1 = wasm_i32x4_add(vacc0x1, wasm_i32x4_extend_low_i16x8(vprod0x1));
107 vacc0x0 = wasm_i32x4_add(vacc0x0, wasm_i32x4_extend_high_i16x8(vprod0x0));
108 const v128_t vprod1x1 = wasm_i16x8_mul(vxb1, vxa1);
109 vacc1x1 = wasm_i32x4_add(vacc1x1, wasm_i32x4_extend_low_i16x8(vprod1x1));
110 vacc1x0 = wasm_i32x4_add(vacc1x0, wasm_i32x4_extend_high_i16x8(vprod1x0));
111 const v128_t vprod2x1 = wasm_i16x8_mul(vxb1, vxa2);
112 vacc2x1 = wasm_i32x4_add(vacc2x1, wasm_i32x4_extend_low_i16x8(vprod2x1));
113 vacc2x0 = wasm_i32x4_add(vacc2x0, wasm_i32x4_extend_high_i16x8(vprod2x0));
114
115 vacc0x1 = wasm_i32x4_add(vacc0x1, wasm_i32x4_extend_high_i16x8(vprod0x1));
116 vacc1x1 = wasm_i32x4_add(vacc1x1, wasm_i32x4_extend_high_i16x8(vprod1x1));
117 vacc2x1 = wasm_i32x4_add(vacc2x1, wasm_i32x4_extend_high_i16x8(vprod2x1));
Marat Dukhan43bee052021-07-14 20:57:18 -0700118 const v128_t vb23 = wasm_v128_load((const int8_t*) w + 16);
Marat Dukhan4741e412021-06-30 13:38:06 -0700119 const v128_t vxb2 = wasm_i16x8_extend_low_i8x16(vb23);
120 const v128_t vxb3 = wasm_i16x8_extend_high_i8x16(vb23);
121
122 const v128_t vprod0x2 = wasm_i16x8_mul(vxb2, vxa0);
123 vacc0x2 = wasm_i32x4_add(vacc0x2, wasm_i32x4_extend_low_i16x8(vprod0x2));
124 const v128_t vprod1x2 = wasm_i16x8_mul(vxb2, vxa1);
125 vacc1x2 = wasm_i32x4_add(vacc1x2, wasm_i32x4_extend_low_i16x8(vprod1x2));
126 const v128_t vprod2x2 = wasm_i16x8_mul(vxb2, vxa2);
127 vacc2x2 = wasm_i32x4_add(vacc2x2, wasm_i32x4_extend_low_i16x8(vprod2x2));
128
129 const v128_t vprod0x3 = wasm_i16x8_mul(vxb3, vxa0);
130 vacc0x3 = wasm_i32x4_add(vacc0x3, wasm_i32x4_extend_low_i16x8(vprod0x3));
131 vacc0x2 = wasm_i32x4_add(vacc0x2, wasm_i32x4_extend_high_i16x8(vprod0x2));
132 const v128_t vprod1x3 = wasm_i16x8_mul(vxb3, vxa1);
133 vacc1x3 = wasm_i32x4_add(vacc1x3, wasm_i32x4_extend_low_i16x8(vprod1x3));
134 vacc1x2 = wasm_i32x4_add(vacc1x2, wasm_i32x4_extend_high_i16x8(vprod1x2));
135 const v128_t vprod2x3 = wasm_i16x8_mul(vxb3, vxa2);
136 vacc2x3 = wasm_i32x4_add(vacc2x3, wasm_i32x4_extend_low_i16x8(vprod2x3));
137 vacc2x2 = wasm_i32x4_add(vacc2x2, wasm_i32x4_extend_high_i16x8(vprod2x2));
138
139 vacc0x3 = wasm_i32x4_add(vacc0x3, wasm_i32x4_extend_high_i16x8(vprod0x3));
140 vacc1x3 = wasm_i32x4_add(vacc1x3, wasm_i32x4_extend_high_i16x8(vprod1x3));
141 vacc2x3 = wasm_i32x4_add(vacc2x3, wasm_i32x4_extend_high_i16x8(vprod2x3));
142
Marat Dukhan43bee052021-07-14 20:57:18 -0700143 w = (const void*) ((const int8_t*) w + 32);
Marat Dukhan4741e412021-06-30 13:38:06 -0700144 k += 8 * sizeof(int8_t);
145 }
146 p -= 3 * sizeof(void*);
147 } while (p != 0);
148
149 const v128_t vacc0x02 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc0x0, vacc0x2, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc0x0, vacc0x2, 2, 6, 3, 7));
150 const v128_t vacc0x13 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc0x1, vacc0x3, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc0x1, vacc0x3, 2, 6, 3, 7));
151 const v128_t vacc1x02 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc1x0, vacc1x2, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc1x0, vacc1x2, 2, 6, 3, 7));
152 const v128_t vacc1x13 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc1x1, vacc1x3, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc1x1, vacc1x3, 2, 6, 3, 7));
153 const v128_t vacc2x02 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc2x0, vacc2x2, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc2x0, vacc2x2, 2, 6, 3, 7));
154 const v128_t vacc2x13 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc2x1, vacc2x3, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc2x1, vacc2x3, 2, 6, 3, 7));
155
156 v128_t vacc0x0123 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc0x02, vacc0x13, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc0x02, vacc0x13, 2, 6, 3, 7));
157 v128_t vacc1x0123 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc1x02, vacc1x13, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc1x02, vacc1x13, 2, 6, 3, 7));
158 v128_t vacc2x0123 = wasm_i32x4_add(wasm_v32x4_shuffle(vacc2x02, vacc2x13, 0, 4, 1, 5), wasm_v32x4_shuffle(vacc2x02, vacc2x13, 2, 6, 3, 7));
159
160 vacc0x0123 = wasm_f32x4_convert_i32x4(vacc0x0123);
161 vacc1x0123 = wasm_f32x4_convert_i32x4(vacc1x0123);
162 vacc2x0123 = wasm_f32x4_convert_i32x4(vacc2x0123);
163
164 const v128_t vscale = wasm_v128_load(params->fp32_wasmsimd.scale);
165 vacc0x0123 = wasm_f32x4_mul(vacc0x0123, vscale);
166 vacc1x0123 = wasm_f32x4_mul(vacc1x0123, vscale);
167 vacc2x0123 = wasm_f32x4_mul(vacc2x0123, vscale);
168
169 const v128_t voutput_min_less_zero_point = wasm_v128_load(params->fp32_wasmsimd.output_min_less_zero_point);
Marat Dukhan0bf8afa2021-09-20 10:02:18 -0700170 vacc0x0123 = wasm_f32x4_pmax(voutput_min_less_zero_point, vacc0x0123);
171 vacc1x0123 = wasm_f32x4_pmax(voutput_min_less_zero_point, vacc1x0123);
172 vacc2x0123 = wasm_f32x4_pmax(voutput_min_less_zero_point, vacc2x0123);
Marat Dukhan4741e412021-06-30 13:38:06 -0700173
174 const v128_t voutput_max_less_zero_point = wasm_v128_load(params->fp32_wasmsimd.output_max_less_zero_point);
Marat Dukhan0bf8afa2021-09-20 10:02:18 -0700175 vacc0x0123 = wasm_f32x4_pmin(voutput_max_less_zero_point, vacc0x0123);
176 vacc1x0123 = wasm_f32x4_pmin(voutput_max_less_zero_point, vacc1x0123);
177 vacc2x0123 = wasm_f32x4_pmin(voutput_max_less_zero_point, vacc2x0123);
Marat Dukhan4741e412021-06-30 13:38:06 -0700178
179 const v128_t vmagic_bias = wasm_v128_load(params->fp32_wasmsimd.magic_bias);
180 vacc0x0123 = wasm_f32x4_add(vacc0x0123, vmagic_bias);
181 vacc1x0123 = wasm_f32x4_add(vacc1x0123, vmagic_bias);
182 vacc2x0123 = wasm_f32x4_add(vacc2x0123, vmagic_bias);
183
184 const v128_t vmagic_bias_less_output_zero_point = wasm_v128_load(params->fp32_wasmsimd.magic_bias_less_output_zero_point);
185 vacc0x0123 = wasm_i32x4_sub(vacc0x0123, vmagic_bias_less_output_zero_point);
186 vacc1x0123 = wasm_i32x4_sub(vacc1x0123, vmagic_bias_less_output_zero_point);
187 vacc2x0123 = wasm_i32x4_sub(vacc2x0123, vmagic_bias_less_output_zero_point);
188
Marat Dukhan07706f62021-08-08 23:48:40 -0700189 v128_t vacc01x0123 = wasm_i16x8_narrow_i32x4(vacc0x0123, vacc1x0123);
190 v128_t vacc22x0123 = wasm_i16x8_narrow_i32x4(vacc2x0123, vacc2x0123);
Marat Dukhan4741e412021-06-30 13:38:06 -0700191
Marat Dukhan07706f62021-08-08 23:48:40 -0700192 v128_t vout = wasm_i8x16_narrow_i16x8(vacc01x0123, vacc22x0123);
Marat Dukhan4741e412021-06-30 13:38:06 -0700193
194 if (nc >= 4) {
195 *((float*) c2) = (float) wasm_f32x4_extract_lane(vout, 2);
196 *((float*) c1) = (float) wasm_f32x4_extract_lane(vout, 1);
197 *((float*) c0) = (float) wasm_f32x4_extract_lane(vout, 0);
198
199 c2 = (int8_t*) ((uintptr_t) c2 + cn_stride);
200 c1 = (int8_t*) ((uintptr_t) c1 + cn_stride);
201 c0 = (int8_t*) ((uintptr_t) c0 + cn_stride);
202
203 a = (const int8_t**restrict) ((uintptr_t) a - ks);
204
205 nc -= 4;
206 } else {
Marat Dukhan7a8dd872021-08-19 02:39:13 -0700207 uint32_t vout2 = wasm_i32x4_extract_lane(vout, 2);
208 uint32_t vout1 = wasm_i32x4_extract_lane(vout, 1);
209 uint32_t vout0 = wasm_i32x4_extract_lane(vout, 0);
Marat Dukhan4741e412021-06-30 13:38:06 -0700210 if (nc & 2) {
Marat Dukhan7a8dd872021-08-19 02:39:13 -0700211 *((uint16_t*) c2) = (uint16_t) vout2;
212 vout2 >>= 16;
Marat Dukhan4741e412021-06-30 13:38:06 -0700213 c2 += 2;
Marat Dukhan7a8dd872021-08-19 02:39:13 -0700214 *((uint16_t*) c1) = (uint16_t) vout1;
215 vout1 >>= 16;
Marat Dukhan4741e412021-06-30 13:38:06 -0700216 c1 += 2;
Marat Dukhan7a8dd872021-08-19 02:39:13 -0700217 *((uint16_t*) c0) = (uint16_t) vout0;
218 vout0 >>= 16;
Marat Dukhan4741e412021-06-30 13:38:06 -0700219 c0 += 2;
Marat Dukhan4741e412021-06-30 13:38:06 -0700220 }
221 if (nc & 1) {
Marat Dukhan7a8dd872021-08-19 02:39:13 -0700222 *c2 = (int8_t) vout2;
223 *c1 = (int8_t) vout1;
224 *c0 = (int8_t) vout0;
Marat Dukhan4741e412021-06-30 13:38:06 -0700225 }
226
227 nc = 0;
228 }
229 } while (nc != 0);
230}